2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/stop_machine.h>
42 #include <linux/swap.h>
43 #include <linux/pci.h>
44 #include <linux/dma-buf.h>
46 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
47 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
48 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(to_i915(dev
)) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
61 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
64 return obj
->pin_display
;
68 insert_mappable_node(struct i915_ggtt
*ggtt
,
69 struct drm_mm_node
*node
, u32 size
)
71 memset(node
, 0, sizeof(*node
));
72 return drm_mm_insert_node_in_range(&ggtt
->base
.mm
, node
,
73 size
, 0, I915_COLOR_UNEVICTABLE
,
74 0, ggtt
->mappable_end
,
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
110 if (!i915_reset_in_progress(error
))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 !i915_reset_in_progress(error
),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret
< 0) {
131 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
136 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
148 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
152 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
153 struct drm_i915_gem_get_aperture
*args
= data
;
154 struct i915_vma
*vma
;
158 mutex_lock(&dev
->struct_mutex
);
159 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 if (i915_vma_is_pinned(vma
))
161 pinned
+= vma
->node
.size
;
162 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 if (i915_vma_is_pinned(vma
))
164 pinned
+= vma
->node
.size
;
165 mutex_unlock(&dev
->struct_mutex
);
167 args
->aper_size
= ggtt
->base
.total
;
168 args
->aper_available_size
= args
->aper_size
- pinned
;
173 static struct sg_table
*
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
176 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
177 drm_dma_handle_t
*phys
;
179 struct scatterlist
*sg
;
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 return ERR_PTR(-EINVAL
);
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
190 phys
= drm_pci_alloc(obj
->base
.dev
,
192 roundup_pow_of_two(obj
->base
.size
));
194 return ERR_PTR(-ENOMEM
);
197 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
201 page
= shmem_read_mapping_page(mapping
, i
);
207 src
= kmap_atomic(page
);
208 memcpy(vaddr
, src
, PAGE_SIZE
);
209 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
216 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
220 st
= ERR_PTR(-ENOMEM
);
224 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
226 st
= ERR_PTR(-ENOMEM
);
232 sg
->length
= obj
->base
.size
;
234 sg_dma_address(sg
) = phys
->busaddr
;
235 sg_dma_len(sg
) = obj
->base
.size
;
237 obj
->phys_handle
= phys
;
241 drm_pci_free(obj
->base
.dev
, phys
);
246 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
247 struct sg_table
*pages
,
250 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
252 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
253 obj
->mm
.dirty
= false;
256 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
257 !cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
258 drm_clflush_sg(pages
);
260 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
261 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
265 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
266 struct sg_table
*pages
)
268 __i915_gem_object_release_shmem(obj
, pages
, false);
271 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
272 char *vaddr
= obj
->phys_handle
->vaddr
;
275 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
279 page
= shmem_read_mapping_page(mapping
, i
);
283 dst
= kmap_atomic(page
);
284 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
285 memcpy(dst
, vaddr
, PAGE_SIZE
);
288 set_page_dirty(page
);
289 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
290 mark_page_accessed(page
);
294 obj
->mm
.dirty
= false;
297 sg_free_table(pages
);
300 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
304 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
306 i915_gem_object_unpin_pages(obj
);
309 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
310 .get_pages
= i915_gem_object_get_pages_phys
,
311 .put_pages
= i915_gem_object_put_pages_phys
,
312 .release
= i915_gem_object_release_phys
,
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
->i915
, rps
, rq
->emitted_jiffies
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
402 if (rps
&& rq
->global_seqno
== intel_engine_last_submit(rq
->engine
)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
413 spin_lock(&rq
->i915
->rps
.client_lock
);
414 list_del_init(&rps
->link
);
415 spin_unlock(&rq
->i915
->rps
.client_lock
);
422 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
425 struct intel_rps_client
*rps
)
427 struct dma_fence
*excl
;
429 if (flags
& I915_WAIT_ALL
) {
430 struct dma_fence
**shared
;
431 unsigned int count
, i
;
434 ret
= reservation_object_get_fences_rcu(resv
,
435 &excl
, &count
, &shared
);
439 for (i
= 0; i
< count
; i
++) {
440 timeout
= i915_gem_object_wait_fence(shared
[i
],
446 dma_fence_put(shared
[i
]);
449 for (; i
< count
; i
++)
450 dma_fence_put(shared
[i
]);
453 excl
= reservation_object_get_excl_rcu(resv
);
456 if (excl
&& timeout
> 0)
457 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
464 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
466 struct drm_i915_gem_request
*rq
;
467 struct intel_engine_cs
*engine
;
469 if (!dma_fence_is_i915(fence
))
472 rq
= to_request(fence
);
474 if (!engine
->schedule
)
477 engine
->schedule(rq
, prio
);
480 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence
)) {
484 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
487 for (i
= 0; i
< array
->num_fences
; i
++)
488 __fence_set_priority(array
->fences
[i
], prio
);
490 __fence_set_priority(fence
, prio
);
495 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
499 struct dma_fence
*excl
;
501 if (flags
& I915_WAIT_ALL
) {
502 struct dma_fence
**shared
;
503 unsigned int count
, i
;
506 ret
= reservation_object_get_fences_rcu(obj
->resv
,
507 &excl
, &count
, &shared
);
511 for (i
= 0; i
< count
; i
++) {
512 fence_set_priority(shared
[i
], prio
);
513 dma_fence_put(shared
[i
]);
518 excl
= reservation_object_get_excl_rcu(obj
->resv
);
522 fence_set_priority(excl
, prio
);
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
536 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
539 struct intel_rps_client
*rps
)
542 #if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks
&&
544 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
545 !!(flags
& I915_WAIT_LOCKED
));
547 GEM_BUG_ON(timeout
< 0);
549 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
552 return timeout
< 0 ? timeout
: 0;
555 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
557 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
563 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
568 if (align
> obj
->base
.size
)
571 if (obj
->ops
== &i915_gem_phys_ops
)
574 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
577 if (obj
->base
.filp
== NULL
)
580 ret
= i915_gem_object_unbind(obj
);
584 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
588 obj
->ops
= &i915_gem_phys_ops
;
590 return i915_gem_object_pin_pages(obj
);
594 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
599 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
604 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
605 if (copy_from_user(vaddr
, user_data
, args
->size
))
608 drm_clflush_virt_range(vaddr
, args
->size
);
609 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
611 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
615 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
)
617 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
620 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
622 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
623 kmem_cache_free(dev_priv
->objects
, obj
);
627 i915_gem_create(struct drm_file
*file
,
628 struct drm_i915_private
*dev_priv
,
632 struct drm_i915_gem_object
*obj
;
636 size
= roundup(size
, PAGE_SIZE
);
640 /* Allocate the new object */
641 obj
= i915_gem_object_create(dev_priv
, size
);
645 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
646 /* drop reference from allocate - handle holds it now */
647 i915_gem_object_put(obj
);
656 i915_gem_dumb_create(struct drm_file
*file
,
657 struct drm_device
*dev
,
658 struct drm_mode_create_dumb
*args
)
660 /* have to work out size/pitch and return them */
661 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
662 args
->size
= args
->pitch
* args
->height
;
663 return i915_gem_create(file
, to_i915(dev
),
664 args
->size
, &args
->handle
);
668 * Creates a new mm object and returns a handle to it.
669 * @dev: drm device pointer
670 * @data: ioctl data blob
671 * @file: drm file pointer
674 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
675 struct drm_file
*file
)
677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
678 struct drm_i915_gem_create
*args
= data
;
680 i915_gem_flush_free_objects(dev_priv
);
682 return i915_gem_create(file
, dev_priv
,
683 args
->size
, &args
->handle
);
687 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
688 const char *gpu_vaddr
, int gpu_offset
,
691 int ret
, cpu_offset
= 0;
694 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
695 int this_length
= min(cacheline_end
- gpu_offset
, length
);
696 int swizzled_gpu_offset
= gpu_offset
^ 64;
698 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
699 gpu_vaddr
+ swizzled_gpu_offset
,
704 cpu_offset
+= this_length
;
705 gpu_offset
+= this_length
;
706 length
-= this_length
;
713 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
714 const char __user
*cpu_vaddr
,
717 int ret
, cpu_offset
= 0;
720 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
721 int this_length
= min(cacheline_end
- gpu_offset
, length
);
722 int swizzled_gpu_offset
= gpu_offset
^ 64;
724 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
725 cpu_vaddr
+ cpu_offset
,
730 cpu_offset
+= this_length
;
731 gpu_offset
+= this_length
;
732 length
-= this_length
;
739 * Pins the specified object's pages and synchronizes the object with
740 * GPU accesses. Sets needs_clflush to non-zero if the caller should
741 * flush the object from the CPU cache.
743 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
744 unsigned int *needs_clflush
)
748 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
751 if (!i915_gem_object_has_struct_page(obj
))
754 ret
= i915_gem_object_wait(obj
,
755 I915_WAIT_INTERRUPTIBLE
|
757 MAX_SCHEDULE_TIMEOUT
,
762 ret
= i915_gem_object_pin_pages(obj
);
766 i915_gem_object_flush_gtt_write_domain(obj
);
768 /* If we're not in the cpu read domain, set ourself into the gtt
769 * read domain and manually flush cachelines (if required). This
770 * optimizes for the case when the gpu will dirty the data
771 * anyway again before the next pread happens.
773 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
774 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
777 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
778 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
785 /* return with the pages pinned */
789 i915_gem_object_unpin_pages(obj
);
793 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
794 unsigned int *needs_clflush
)
798 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
801 if (!i915_gem_object_has_struct_page(obj
))
804 ret
= i915_gem_object_wait(obj
,
805 I915_WAIT_INTERRUPTIBLE
|
808 MAX_SCHEDULE_TIMEOUT
,
813 ret
= i915_gem_object_pin_pages(obj
);
817 i915_gem_object_flush_gtt_write_domain(obj
);
819 /* If we're not in the cpu write domain, set ourself into the
820 * gtt write domain and manually flush cachelines (as required).
821 * This optimizes for the case when the gpu will use the data
822 * right away and we therefore have to clflush anyway.
824 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
825 *needs_clflush
|= cpu_write_needs_clflush(obj
) << 1;
827 /* Same trick applies to invalidate partially written cachelines read
830 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
831 *needs_clflush
|= !cpu_cache_is_coherent(obj
->base
.dev
,
834 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
835 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
842 if ((*needs_clflush
& CLFLUSH_AFTER
) == 0)
843 obj
->cache_dirty
= true;
845 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
846 obj
->mm
.dirty
= true;
847 /* return with the pages pinned */
851 i915_gem_object_unpin_pages(obj
);
856 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
859 if (unlikely(swizzled
)) {
860 unsigned long start
= (unsigned long) addr
;
861 unsigned long end
= (unsigned long) addr
+ length
;
863 /* For swizzling simply ensure that we always flush both
864 * channels. Lame, but simple and it works. Swizzled
865 * pwrite/pread is far from a hotpath - current userspace
866 * doesn't use it at all. */
867 start
= round_down(start
, 128);
868 end
= round_up(end
, 128);
870 drm_clflush_virt_range((void *)start
, end
- start
);
872 drm_clflush_virt_range(addr
, length
);
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pread_slow(struct page
*page
, int offset
, int length
,
881 char __user
*user_data
,
882 bool page_do_bit17_swizzling
, bool needs_clflush
)
889 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
890 page_do_bit17_swizzling
);
892 if (page_do_bit17_swizzling
)
893 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
895 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
898 return ret
? - EFAULT
: 0;
902 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
903 bool page_do_bit17_swizzling
, bool needs_clflush
)
908 if (!page_do_bit17_swizzling
) {
909 char *vaddr
= kmap_atomic(page
);
912 drm_clflush_virt_range(vaddr
+ offset
, length
);
913 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
914 kunmap_atomic(vaddr
);
919 return shmem_pread_slow(page
, offset
, length
, user_data
,
920 page_do_bit17_swizzling
, needs_clflush
);
924 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
925 struct drm_i915_gem_pread
*args
)
927 char __user
*user_data
;
929 unsigned int obj_do_bit17_swizzling
;
930 unsigned int needs_clflush
;
931 unsigned int idx
, offset
;
934 obj_do_bit17_swizzling
= 0;
935 if (i915_gem_object_needs_bit17_swizzle(obj
))
936 obj_do_bit17_swizzling
= BIT(17);
938 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
942 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
943 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
948 user_data
= u64_to_user_ptr(args
->data_ptr
);
949 offset
= offset_in_page(args
->offset
);
950 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
951 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
955 if (offset
+ length
> PAGE_SIZE
)
956 length
= PAGE_SIZE
- offset
;
958 ret
= shmem_pread(page
, offset
, length
, user_data
,
959 page_to_phys(page
) & obj_do_bit17_swizzling
,
969 i915_gem_obj_finish_shmem_access(obj
);
974 gtt_user_read(struct io_mapping
*mapping
,
975 loff_t base
, int offset
,
976 char __user
*user_data
, int length
)
979 unsigned long unwritten
;
981 /* We can use the cpu mem copy function because this is X86. */
982 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
983 unwritten
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
984 io_mapping_unmap_atomic(vaddr
);
986 vaddr
= (void __force
*)
987 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
988 unwritten
= copy_to_user(user_data
, vaddr
+ offset
, length
);
989 io_mapping_unmap(vaddr
);
995 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
996 const struct drm_i915_gem_pread
*args
)
998 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
999 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1000 struct drm_mm_node node
;
1001 struct i915_vma
*vma
;
1002 void __user
*user_data
;
1006 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1010 intel_runtime_pm_get(i915
);
1011 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1012 PIN_MAPPABLE
| PIN_NONBLOCK
);
1014 node
.start
= i915_ggtt_offset(vma
);
1015 node
.allocated
= false;
1016 ret
= i915_vma_put_fence(vma
);
1018 i915_vma_unpin(vma
);
1023 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1026 GEM_BUG_ON(!node
.allocated
);
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 mutex_unlock(&i915
->drm
.struct_mutex
);
1035 user_data
= u64_to_user_ptr(args
->data_ptr
);
1036 remain
= args
->size
;
1037 offset
= args
->offset
;
1039 while (remain
> 0) {
1040 /* Operation in this page
1042 * page_base = page offset within aperture
1043 * page_offset = offset within page
1044 * page_length = bytes to copy for this page
1046 u32 page_base
= node
.start
;
1047 unsigned page_offset
= offset_in_page(offset
);
1048 unsigned page_length
= PAGE_SIZE
- page_offset
;
1049 page_length
= remain
< page_length
? remain
: page_length
;
1050 if (node
.allocated
) {
1052 ggtt
->base
.insert_page(&ggtt
->base
,
1053 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1054 node
.start
, I915_CACHE_NONE
, 0);
1057 page_base
+= offset
& PAGE_MASK
;
1060 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1061 user_data
, page_length
)) {
1066 remain
-= page_length
;
1067 user_data
+= page_length
;
1068 offset
+= page_length
;
1071 mutex_lock(&i915
->drm
.struct_mutex
);
1073 if (node
.allocated
) {
1075 ggtt
->base
.clear_range(&ggtt
->base
,
1076 node
.start
, node
.size
);
1077 remove_mappable_node(&node
);
1079 i915_vma_unpin(vma
);
1082 intel_runtime_pm_put(i915
);
1083 mutex_unlock(&i915
->drm
.struct_mutex
);
1089 * Reads data from the object referenced by handle.
1090 * @dev: drm device pointer
1091 * @data: ioctl data blob
1092 * @file: drm file pointer
1094 * On error, the contents of *data are undefined.
1097 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1098 struct drm_file
*file
)
1100 struct drm_i915_gem_pread
*args
= data
;
1101 struct drm_i915_gem_object
*obj
;
1104 if (args
->size
== 0)
1107 if (!access_ok(VERIFY_WRITE
,
1108 u64_to_user_ptr(args
->data_ptr
),
1112 obj
= i915_gem_object_lookup(file
, args
->handle
);
1116 /* Bounds check source. */
1117 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1122 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1124 ret
= i915_gem_object_wait(obj
,
1125 I915_WAIT_INTERRUPTIBLE
,
1126 MAX_SCHEDULE_TIMEOUT
,
1127 to_rps_client(file
));
1131 ret
= i915_gem_object_pin_pages(obj
);
1135 ret
= i915_gem_shmem_pread(obj
, args
);
1136 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1137 ret
= i915_gem_gtt_pread(obj
, args
);
1139 i915_gem_object_unpin_pages(obj
);
1141 i915_gem_object_put(obj
);
1145 /* This is the fast write path which cannot handle
1146 * page faults in the source data
1150 ggtt_write(struct io_mapping
*mapping
,
1151 loff_t base
, int offset
,
1152 char __user
*user_data
, int length
)
1155 unsigned long unwritten
;
1157 /* We can use the cpu mem copy function because this is X86. */
1158 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1159 unwritten
= __copy_from_user_inatomic_nocache(vaddr
+ offset
,
1161 io_mapping_unmap_atomic(vaddr
);
1163 vaddr
= (void __force
*)
1164 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1165 unwritten
= copy_from_user(vaddr
+ offset
, user_data
, length
);
1166 io_mapping_unmap(vaddr
);
1173 * This is the fast pwrite path, where we copy the data directly from the
1174 * user into the GTT, uncached.
1175 * @obj: i915 GEM object
1176 * @args: pwrite arguments structure
1179 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1180 const struct drm_i915_gem_pwrite
*args
)
1182 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1183 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1184 struct drm_mm_node node
;
1185 struct i915_vma
*vma
;
1187 void __user
*user_data
;
1190 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1194 intel_runtime_pm_get(i915
);
1195 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1196 PIN_MAPPABLE
| PIN_NONBLOCK
);
1198 node
.start
= i915_ggtt_offset(vma
);
1199 node
.allocated
= false;
1200 ret
= i915_vma_put_fence(vma
);
1202 i915_vma_unpin(vma
);
1207 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1210 GEM_BUG_ON(!node
.allocated
);
1213 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1217 mutex_unlock(&i915
->drm
.struct_mutex
);
1219 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1221 user_data
= u64_to_user_ptr(args
->data_ptr
);
1222 offset
= args
->offset
;
1223 remain
= args
->size
;
1225 /* Operation in this page
1227 * page_base = page offset within aperture
1228 * page_offset = offset within page
1229 * page_length = bytes to copy for this page
1231 u32 page_base
= node
.start
;
1232 unsigned int page_offset
= offset_in_page(offset
);
1233 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1234 page_length
= remain
< page_length
? remain
: page_length
;
1235 if (node
.allocated
) {
1236 wmb(); /* flush the write before we modify the GGTT */
1237 ggtt
->base
.insert_page(&ggtt
->base
,
1238 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1239 node
.start
, I915_CACHE_NONE
, 0);
1240 wmb(); /* flush modifications to the GGTT (insert_page) */
1242 page_base
+= offset
& PAGE_MASK
;
1244 /* If we get a fault while copying data, then (presumably) our
1245 * source page isn't available. Return the error and we'll
1246 * retry in the slow path.
1247 * If the object is non-shmem backed, we retry again with the
1248 * path that handles page fault.
1250 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1251 user_data
, page_length
)) {
1256 remain
-= page_length
;
1257 user_data
+= page_length
;
1258 offset
+= page_length
;
1260 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1262 mutex_lock(&i915
->drm
.struct_mutex
);
1264 if (node
.allocated
) {
1266 ggtt
->base
.clear_range(&ggtt
->base
,
1267 node
.start
, node
.size
);
1268 remove_mappable_node(&node
);
1270 i915_vma_unpin(vma
);
1273 intel_runtime_pm_put(i915
);
1274 mutex_unlock(&i915
->drm
.struct_mutex
);
1279 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1280 char __user
*user_data
,
1281 bool page_do_bit17_swizzling
,
1282 bool needs_clflush_before
,
1283 bool needs_clflush_after
)
1289 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1290 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1291 page_do_bit17_swizzling
);
1292 if (page_do_bit17_swizzling
)
1293 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1296 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1297 if (needs_clflush_after
)
1298 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1299 page_do_bit17_swizzling
);
1302 return ret
? -EFAULT
: 0;
1305 /* Per-page copy function for the shmem pwrite fastpath.
1306 * Flushes invalid cachelines before writing to the target if
1307 * needs_clflush_before is set and flushes out any written cachelines after
1308 * writing if needs_clflush is set.
1311 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1312 bool page_do_bit17_swizzling
,
1313 bool needs_clflush_before
,
1314 bool needs_clflush_after
)
1319 if (!page_do_bit17_swizzling
) {
1320 char *vaddr
= kmap_atomic(page
);
1322 if (needs_clflush_before
)
1323 drm_clflush_virt_range(vaddr
+ offset
, len
);
1324 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1325 if (needs_clflush_after
)
1326 drm_clflush_virt_range(vaddr
+ offset
, len
);
1328 kunmap_atomic(vaddr
);
1333 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1334 page_do_bit17_swizzling
,
1335 needs_clflush_before
,
1336 needs_clflush_after
);
1340 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1341 const struct drm_i915_gem_pwrite
*args
)
1343 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1344 void __user
*user_data
;
1346 unsigned int obj_do_bit17_swizzling
;
1347 unsigned int partial_cacheline_write
;
1348 unsigned int needs_clflush
;
1349 unsigned int offset
, idx
;
1352 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1356 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1357 mutex_unlock(&i915
->drm
.struct_mutex
);
1361 obj_do_bit17_swizzling
= 0;
1362 if (i915_gem_object_needs_bit17_swizzle(obj
))
1363 obj_do_bit17_swizzling
= BIT(17);
1365 /* If we don't overwrite a cacheline completely we need to be
1366 * careful to have up-to-date data by first clflushing. Don't
1367 * overcomplicate things and flush the entire patch.
1369 partial_cacheline_write
= 0;
1370 if (needs_clflush
& CLFLUSH_BEFORE
)
1371 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1373 user_data
= u64_to_user_ptr(args
->data_ptr
);
1374 remain
= args
->size
;
1375 offset
= offset_in_page(args
->offset
);
1376 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1377 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1381 if (offset
+ length
> PAGE_SIZE
)
1382 length
= PAGE_SIZE
- offset
;
1384 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1385 page_to_phys(page
) & obj_do_bit17_swizzling
,
1386 (offset
| length
) & partial_cacheline_write
,
1387 needs_clflush
& CLFLUSH_AFTER
);
1392 user_data
+= length
;
1396 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1397 i915_gem_obj_finish_shmem_access(obj
);
1402 * Writes data to the object referenced by handle.
1404 * @data: ioctl data blob
1407 * On error, the contents of the buffer that were to be modified are undefined.
1410 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1411 struct drm_file
*file
)
1413 struct drm_i915_gem_pwrite
*args
= data
;
1414 struct drm_i915_gem_object
*obj
;
1417 if (args
->size
== 0)
1420 if (!access_ok(VERIFY_READ
,
1421 u64_to_user_ptr(args
->data_ptr
),
1425 obj
= i915_gem_object_lookup(file
, args
->handle
);
1429 /* Bounds check destination. */
1430 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1435 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1437 ret
= i915_gem_object_wait(obj
,
1438 I915_WAIT_INTERRUPTIBLE
|
1440 MAX_SCHEDULE_TIMEOUT
,
1441 to_rps_client(file
));
1445 ret
= i915_gem_object_pin_pages(obj
);
1450 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1451 * it would end up going through the fenced access, and we'll get
1452 * different detiling behavior between reading and writing.
1453 * pread/pwrite currently are reading and writing from the CPU
1454 * perspective, requiring manual detiling by the client.
1456 if (!i915_gem_object_has_struct_page(obj
) ||
1457 cpu_write_needs_clflush(obj
))
1458 /* Note that the gtt paths might fail with non-page-backed user
1459 * pointers (e.g. gtt mappings when moving data between
1460 * textures). Fallback to the shmem path in that case.
1462 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1464 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1465 if (obj
->phys_handle
)
1466 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1468 ret
= i915_gem_shmem_pwrite(obj
, args
);
1471 i915_gem_object_unpin_pages(obj
);
1473 i915_gem_object_put(obj
);
1477 static inline enum fb_op_origin
1478 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1480 return (domain
== I915_GEM_DOMAIN_GTT
?
1481 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
1484 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1486 struct drm_i915_private
*i915
;
1487 struct list_head
*list
;
1488 struct i915_vma
*vma
;
1490 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1491 if (!i915_vma_is_ggtt(vma
))
1494 if (i915_vma_is_active(vma
))
1497 if (!drm_mm_node_allocated(&vma
->node
))
1500 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1503 i915
= to_i915(obj
->base
.dev
);
1504 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1505 list_move_tail(&obj
->global_link
, list
);
1509 * Called when user space prepares to use an object with the CPU, either
1510 * through the mmap ioctl's mapping or a GTT mapping.
1512 * @data: ioctl data blob
1516 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1517 struct drm_file
*file
)
1519 struct drm_i915_gem_set_domain
*args
= data
;
1520 struct drm_i915_gem_object
*obj
;
1521 uint32_t read_domains
= args
->read_domains
;
1522 uint32_t write_domain
= args
->write_domain
;
1525 /* Only handle setting domains to types used by the CPU. */
1526 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1529 /* Having something in the write domain implies it's in the read
1530 * domain, and only that read domain. Enforce that in the request.
1532 if (write_domain
!= 0 && read_domains
!= write_domain
)
1535 obj
= i915_gem_object_lookup(file
, args
->handle
);
1539 /* Try to flush the object off the GPU without holding the lock.
1540 * We will repeat the flush holding the lock in the normal manner
1541 * to catch cases where we are gazumped.
1543 err
= i915_gem_object_wait(obj
,
1544 I915_WAIT_INTERRUPTIBLE
|
1545 (write_domain
? I915_WAIT_ALL
: 0),
1546 MAX_SCHEDULE_TIMEOUT
,
1547 to_rps_client(file
));
1551 /* Flush and acquire obj->pages so that we are coherent through
1552 * direct access in memory with previous cached writes through
1553 * shmemfs and that our cache domain tracking remains valid.
1554 * For example, if the obj->filp was moved to swap without us
1555 * being notified and releasing the pages, we would mistakenly
1556 * continue to assume that the obj remained out of the CPU cached
1559 err
= i915_gem_object_pin_pages(obj
);
1563 err
= i915_mutex_lock_interruptible(dev
);
1567 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1568 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1570 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1572 /* And bump the LRU for this access */
1573 i915_gem_object_bump_inactive_ggtt(obj
);
1575 mutex_unlock(&dev
->struct_mutex
);
1577 if (write_domain
!= 0)
1578 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1581 i915_gem_object_unpin_pages(obj
);
1583 i915_gem_object_put(obj
);
1588 * Called when user space has done writes to this buffer
1590 * @data: ioctl data blob
1594 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1595 struct drm_file
*file
)
1597 struct drm_i915_gem_sw_finish
*args
= data
;
1598 struct drm_i915_gem_object
*obj
;
1601 obj
= i915_gem_object_lookup(file
, args
->handle
);
1605 /* Pinned buffers may be scanout, so flush the cache */
1606 if (READ_ONCE(obj
->pin_display
)) {
1607 err
= i915_mutex_lock_interruptible(dev
);
1609 i915_gem_object_flush_cpu_write_domain(obj
);
1610 mutex_unlock(&dev
->struct_mutex
);
1614 i915_gem_object_put(obj
);
1619 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1622 * @data: ioctl data blob
1625 * While the mapping holds a reference on the contents of the object, it doesn't
1626 * imply a ref on the object itself.
1630 * DRM driver writers who look a this function as an example for how to do GEM
1631 * mmap support, please don't implement mmap support like here. The modern way
1632 * to implement DRM mmap support is with an mmap offset ioctl (like
1633 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1634 * That way debug tooling like valgrind will understand what's going on, hiding
1635 * the mmap call in a driver private ioctl will break that. The i915 driver only
1636 * does cpu mmaps this way because we didn't know better.
1639 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1640 struct drm_file
*file
)
1642 struct drm_i915_gem_mmap
*args
= data
;
1643 struct drm_i915_gem_object
*obj
;
1646 if (args
->flags
& ~(I915_MMAP_WC
))
1649 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1652 obj
= i915_gem_object_lookup(file
, args
->handle
);
1656 /* prime objects have no backing filp to GEM mmap
1659 if (!obj
->base
.filp
) {
1660 i915_gem_object_put(obj
);
1664 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1665 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1667 if (args
->flags
& I915_MMAP_WC
) {
1668 struct mm_struct
*mm
= current
->mm
;
1669 struct vm_area_struct
*vma
;
1671 if (down_write_killable(&mm
->mmap_sem
)) {
1672 i915_gem_object_put(obj
);
1675 vma
= find_vma(mm
, addr
);
1678 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1681 up_write(&mm
->mmap_sem
);
1683 /* This may race, but that's ok, it only gets set */
1684 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1686 i915_gem_object_put(obj
);
1687 if (IS_ERR((void *)addr
))
1690 args
->addr_ptr
= (uint64_t) addr
;
1695 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1697 return i915_gem_object_get_tile_row_size(obj
) >> PAGE_SHIFT
;
1701 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1703 * A history of the GTT mmap interface:
1705 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1706 * aligned and suitable for fencing, and still fit into the available
1707 * mappable space left by the pinned display objects. A classic problem
1708 * we called the page-fault-of-doom where we would ping-pong between
1709 * two objects that could not fit inside the GTT and so the memcpy
1710 * would page one object in at the expense of the other between every
1713 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1714 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1715 * object is too large for the available space (or simply too large
1716 * for the mappable aperture!), a view is created instead and faulted
1717 * into userspace. (This view is aligned and sized appropriately for
1722 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1723 * hangs on some architectures, corruption on others. An attempt to service
1724 * a GTT page fault from a snoopable object will generate a SIGBUS.
1726 * * the object must be able to fit into RAM (physical memory, though no
1727 * limited to the mappable aperture).
1732 * * a new GTT page fault will synchronize rendering from the GPU and flush
1733 * all data to system memory. Subsequent access will not be synchronized.
1735 * * all mappings are revoked on runtime device suspend.
1737 * * there are only 8, 16 or 32 fence registers to share between all users
1738 * (older machines require fence register for display and blitter access
1739 * as well). Contention of the fence registers will cause the previous users
1740 * to be unmapped and any new access will generate new page faults.
1742 * * running out of memory while servicing a fault may generate a SIGBUS,
1743 * rather than the expected SIGSEGV.
1745 int i915_gem_mmap_gtt_version(void)
1750 static inline struct i915_ggtt_view
1751 compute_partial_view(struct drm_i915_gem_object
*obj
,
1752 pgoff_t page_offset
,
1755 struct i915_ggtt_view view
;
1757 if (i915_gem_object_is_tiled(obj
))
1758 chunk
= roundup(chunk
, tile_row_pages(obj
));
1760 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1761 view
.partial
.offset
= rounddown(page_offset
, chunk
);
1763 min_t(unsigned int, chunk
,
1764 (obj
->base
.size
>> PAGE_SHIFT
) - view
.partial
.offset
);
1766 /* If the partial covers the entire object, just create a normal VMA. */
1767 if (chunk
>= obj
->base
.size
>> PAGE_SHIFT
)
1768 view
.type
= I915_GGTT_VIEW_NORMAL
;
1774 * i915_gem_fault - fault a page into the GTT
1775 * @area: CPU VMA in question
1778 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1779 * from userspace. The fault handler takes care of binding the object to
1780 * the GTT (if needed), allocating and programming a fence register (again,
1781 * only if needed based on whether the old reg is still valid or the object
1782 * is tiled) and inserting a new PTE into the faulting process.
1784 * Note that the faulting process may involve evicting existing objects
1785 * from the GTT and/or fence registers to make room. So performance may
1786 * suffer if the GTT working set is large or there are few fence registers
1789 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1790 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1792 int i915_gem_fault(struct vm_area_struct
*area
, struct vm_fault
*vmf
)
1794 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1795 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1796 struct drm_device
*dev
= obj
->base
.dev
;
1797 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1798 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1799 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1800 struct i915_vma
*vma
;
1801 pgoff_t page_offset
;
1805 /* We don't use vmf->pgoff since that has the fake offset */
1806 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1808 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1810 /* Try to flush the object off the GPU first without holding the lock.
1811 * Upon acquiring the lock, we will perform our sanity checks and then
1812 * repeat the flush holding the lock in the normal manner to catch cases
1813 * where we are gazumped.
1815 ret
= i915_gem_object_wait(obj
,
1816 I915_WAIT_INTERRUPTIBLE
,
1817 MAX_SCHEDULE_TIMEOUT
,
1822 ret
= i915_gem_object_pin_pages(obj
);
1826 intel_runtime_pm_get(dev_priv
);
1828 ret
= i915_mutex_lock_interruptible(dev
);
1832 /* Access to snoopable pages through the GTT is incoherent. */
1833 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1838 /* If the object is smaller than a couple of partial vma, it is
1839 * not worth only creating a single partial vma - we may as well
1840 * clear enough space for the full object.
1842 flags
= PIN_MAPPABLE
;
1843 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1844 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1846 /* Now pin it into the GTT as needed */
1847 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1849 /* Use a partial view if it is bigger than available space */
1850 struct i915_ggtt_view view
=
1851 compute_partial_view(obj
, page_offset
, MIN_CHUNK_PAGES
);
1853 /* Userspace is now writing through an untracked VMA, abandon
1854 * all hope that the hardware is able to track future writes.
1856 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1858 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1865 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1869 ret
= i915_vma_get_fence(vma
);
1873 /* Mark as being mmapped into userspace for later revocation */
1874 assert_rpm_wakelock_held(dev_priv
);
1875 if (list_empty(&obj
->userfault_link
))
1876 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1878 /* Finally, remap it using the new GTT offset */
1879 ret
= remap_io_mapping(area
,
1880 area
->vm_start
+ (vma
->ggtt_view
.partial
.offset
<< PAGE_SHIFT
),
1881 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1882 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1886 __i915_vma_unpin(vma
);
1888 mutex_unlock(&dev
->struct_mutex
);
1890 intel_runtime_pm_put(dev_priv
);
1891 i915_gem_object_unpin_pages(obj
);
1896 * We eat errors when the gpu is terminally wedged to avoid
1897 * userspace unduly crashing (gl has no provisions for mmaps to
1898 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1899 * and so needs to be reported.
1901 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1902 ret
= VM_FAULT_SIGBUS
;
1907 * EAGAIN means the gpu is hung and we'll wait for the error
1908 * handler to reset everything when re-faulting in
1909 * i915_mutex_lock_interruptible.
1916 * EBUSY is ok: this just means that another thread
1917 * already did the job.
1919 ret
= VM_FAULT_NOPAGE
;
1926 ret
= VM_FAULT_SIGBUS
;
1929 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1930 ret
= VM_FAULT_SIGBUS
;
1937 * i915_gem_release_mmap - remove physical page mappings
1938 * @obj: obj in question
1940 * Preserve the reservation of the mmapping with the DRM core code, but
1941 * relinquish ownership of the pages back to the system.
1943 * It is vital that we remove the page mapping if we have mapped a tiled
1944 * object through the GTT and then lose the fence register due to
1945 * resource pressure. Similarly if the object has been moved out of the
1946 * aperture, than pages mapped into userspace must be revoked. Removing the
1947 * mapping will then trigger a page fault on the next user access, allowing
1948 * fixup by i915_gem_fault().
1951 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1953 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1955 /* Serialisation between user GTT access and our code depends upon
1956 * revoking the CPU's PTE whilst the mutex is held. The next user
1957 * pagefault then has to wait until we release the mutex.
1959 * Note that RPM complicates somewhat by adding an additional
1960 * requirement that operations to the GGTT be made holding the RPM
1963 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1964 intel_runtime_pm_get(i915
);
1966 if (list_empty(&obj
->userfault_link
))
1969 list_del_init(&obj
->userfault_link
);
1970 drm_vma_node_unmap(&obj
->base
.vma_node
,
1971 obj
->base
.dev
->anon_inode
->i_mapping
);
1973 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1974 * memory transactions from userspace before we return. The TLB
1975 * flushing implied above by changing the PTE above *should* be
1976 * sufficient, an extra barrier here just provides us with a bit
1977 * of paranoid documentation about our requirement to serialise
1978 * memory writes before touching registers / GSM.
1983 intel_runtime_pm_put(i915
);
1986 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
1988 struct drm_i915_gem_object
*obj
, *on
;
1992 * Only called during RPM suspend. All users of the userfault_list
1993 * must be holding an RPM wakeref to ensure that this can not
1994 * run concurrently with themselves (and use the struct_mutex for
1995 * protection between themselves).
1998 list_for_each_entry_safe(obj
, on
,
1999 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2000 list_del_init(&obj
->userfault_link
);
2001 drm_vma_node_unmap(&obj
->base
.vma_node
,
2002 obj
->base
.dev
->anon_inode
->i_mapping
);
2005 /* The fence will be lost when the device powers down. If any were
2006 * in use by hardware (i.e. they are pinned), we should not be powering
2007 * down! All other fences will be reacquired by the user upon waking.
2009 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2010 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2012 if (WARN_ON(reg
->pin_count
))
2018 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2023 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2025 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2028 err
= drm_gem_create_mmap_offset(&obj
->base
);
2032 /* Attempt to reap some mmap space from dead objects */
2034 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2038 i915_gem_drain_freed_objects(dev_priv
);
2039 err
= drm_gem_create_mmap_offset(&obj
->base
);
2043 } while (flush_delayed_work(&dev_priv
->gt
.retire_work
));
2048 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2050 drm_gem_free_mmap_offset(&obj
->base
);
2054 i915_gem_mmap_gtt(struct drm_file
*file
,
2055 struct drm_device
*dev
,
2059 struct drm_i915_gem_object
*obj
;
2062 obj
= i915_gem_object_lookup(file
, handle
);
2066 ret
= i915_gem_object_create_mmap_offset(obj
);
2068 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2070 i915_gem_object_put(obj
);
2075 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2077 * @data: GTT mapping ioctl data
2078 * @file: GEM object info
2080 * Simply returns the fake offset to userspace so it can mmap it.
2081 * The mmap call will end up in drm_gem_mmap(), which will set things
2082 * up so we can get faults in the handler above.
2084 * The fault handler will take care of binding the object into the GTT
2085 * (since it may have been evicted to make room for something), allocating
2086 * a fence register, and mapping the appropriate aperture address into
2090 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2091 struct drm_file
*file
)
2093 struct drm_i915_gem_mmap_gtt
*args
= data
;
2095 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2098 /* Immediately discard the backing storage */
2100 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2102 i915_gem_object_free_mmap_offset(obj
);
2104 if (obj
->base
.filp
== NULL
)
2107 /* Our goal here is to return as much of the memory as
2108 * is possible back to the system as we are called from OOM.
2109 * To do this we must instruct the shmfs to drop all of its
2110 * backing pages, *now*.
2112 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2113 obj
->mm
.madv
= __I915_MADV_PURGED
;
2116 /* Try to discard unwanted pages */
2117 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2119 struct address_space
*mapping
;
2121 lockdep_assert_held(&obj
->mm
.lock
);
2122 GEM_BUG_ON(obj
->mm
.pages
);
2124 switch (obj
->mm
.madv
) {
2125 case I915_MADV_DONTNEED
:
2126 i915_gem_object_truncate(obj
);
2127 case __I915_MADV_PURGED
:
2131 if (obj
->base
.filp
== NULL
)
2134 mapping
= obj
->base
.filp
->f_mapping
,
2135 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2139 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2140 struct sg_table
*pages
)
2142 struct sgt_iter sgt_iter
;
2145 __i915_gem_object_release_shmem(obj
, pages
, true);
2147 i915_gem_gtt_finish_pages(obj
, pages
);
2149 if (i915_gem_object_needs_bit17_swizzle(obj
))
2150 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2152 for_each_sgt_page(page
, sgt_iter
, pages
) {
2154 set_page_dirty(page
);
2156 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2157 mark_page_accessed(page
);
2161 obj
->mm
.dirty
= false;
2163 sg_free_table(pages
);
2167 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2169 struct radix_tree_iter iter
;
2172 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2173 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2176 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2177 enum i915_mm_subclass subclass
)
2179 struct sg_table
*pages
;
2181 if (i915_gem_object_has_pinned_pages(obj
))
2184 GEM_BUG_ON(obj
->bind_count
);
2185 if (!READ_ONCE(obj
->mm
.pages
))
2188 /* May be called by shrinker from within get_pages() (on another bo) */
2189 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2190 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2193 /* ->put_pages might need to allocate memory for the bit17 swizzle
2194 * array, hence protect them from being reaped by removing them from gtt
2196 pages
= fetch_and_zero(&obj
->mm
.pages
);
2199 if (obj
->mm
.mapping
) {
2202 ptr
= ptr_mask_bits(obj
->mm
.mapping
);
2203 if (is_vmalloc_addr(ptr
))
2206 kunmap(kmap_to_page(ptr
));
2208 obj
->mm
.mapping
= NULL
;
2211 __i915_gem_object_reset_page_iter(obj
);
2213 obj
->ops
->put_pages(obj
, pages
);
2215 mutex_unlock(&obj
->mm
.lock
);
2218 static void i915_sg_trim(struct sg_table
*orig_st
)
2220 struct sg_table new_st
;
2221 struct scatterlist
*sg
, *new_sg
;
2224 if (orig_st
->nents
== orig_st
->orig_nents
)
2227 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2230 new_sg
= new_st
.sgl
;
2231 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2232 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2233 /* called before being DMA mapped, no need to copy sg->dma_* */
2234 new_sg
= sg_next(new_sg
);
2236 GEM_BUG_ON(new_sg
); /* Should walk exactly nents and hit the end */
2238 sg_free_table(orig_st
);
2243 static struct sg_table
*
2244 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2246 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2247 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2249 struct address_space
*mapping
;
2250 struct sg_table
*st
;
2251 struct scatterlist
*sg
;
2252 struct sgt_iter sgt_iter
;
2254 unsigned long last_pfn
= 0; /* suppress gcc warning */
2255 unsigned int max_segment
;
2259 /* Assert that the object is not currently in any GPU domain. As it
2260 * wasn't in the GTT, there shouldn't be any way it could have been in
2263 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2264 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2266 max_segment
= swiotlb_max_segment();
2268 max_segment
= rounddown(UINT_MAX
, PAGE_SIZE
);
2270 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2272 return ERR_PTR(-ENOMEM
);
2275 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2277 return ERR_PTR(-ENOMEM
);
2280 /* Get the list of pages out of our struct file. They'll be pinned
2281 * at this point until we release them.
2283 * Fail silently without starting the shrinker
2285 mapping
= obj
->base
.filp
->f_mapping
;
2286 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2287 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2290 for (i
= 0; i
< page_count
; i
++) {
2291 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2293 i915_gem_shrink(dev_priv
,
2296 I915_SHRINK_UNBOUND
|
2297 I915_SHRINK_PURGEABLE
);
2298 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2301 /* We've tried hard to allocate the memory by reaping
2302 * our own buffer, now let the real VM do its job and
2303 * go down in flames if truly OOM.
2305 page
= shmem_read_mapping_page(mapping
, i
);
2307 ret
= PTR_ERR(page
);
2312 sg
->length
>= max_segment
||
2313 page_to_pfn(page
) != last_pfn
+ 1) {
2317 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2319 sg
->length
+= PAGE_SIZE
;
2321 last_pfn
= page_to_pfn(page
);
2323 /* Check that the i965g/gm workaround works. */
2324 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2326 if (sg
) /* loop terminated early; short sg table */
2329 /* Trim unused sg entries to avoid wasting memory. */
2332 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2334 /* DMA remapping failed? One possible cause is that
2335 * it could not reserve enough large entries, asking
2336 * for PAGE_SIZE chunks instead may be helpful.
2338 if (max_segment
> PAGE_SIZE
) {
2339 for_each_sgt_page(page
, sgt_iter
, st
)
2343 max_segment
= PAGE_SIZE
;
2346 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2347 "Failed to DMA remap %lu pages\n",
2353 if (i915_gem_object_needs_bit17_swizzle(obj
))
2354 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2361 for_each_sgt_page(page
, sgt_iter
, st
)
2366 /* shmemfs first checks if there is enough memory to allocate the page
2367 * and reports ENOSPC should there be insufficient, along with the usual
2368 * ENOMEM for a genuine allocation failure.
2370 * We use ENOSPC in our driver to mean that we have run out of aperture
2371 * space and so want to translate the error from shmemfs back to our
2372 * usual understanding of ENOMEM.
2377 return ERR_PTR(ret
);
2380 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2381 struct sg_table
*pages
)
2383 lockdep_assert_held(&obj
->mm
.lock
);
2385 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2386 obj
->mm
.get_page
.sg_idx
= 0;
2388 obj
->mm
.pages
= pages
;
2390 if (i915_gem_object_is_tiled(obj
) &&
2391 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2392 GEM_BUG_ON(obj
->mm
.quirked
);
2393 __i915_gem_object_pin_pages(obj
);
2394 obj
->mm
.quirked
= true;
2398 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2400 struct sg_table
*pages
;
2402 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2404 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2405 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2409 pages
= obj
->ops
->get_pages(obj
);
2410 if (unlikely(IS_ERR(pages
)))
2411 return PTR_ERR(pages
);
2413 __i915_gem_object_set_pages(obj
, pages
);
2417 /* Ensure that the associated pages are gathered from the backing storage
2418 * and pinned into our object. i915_gem_object_pin_pages() may be called
2419 * multiple times before they are released by a single call to
2420 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2421 * either as a result of memory pressure (reaping pages under the shrinker)
2422 * or as the object is itself released.
2424 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2428 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2432 if (unlikely(!obj
->mm
.pages
)) {
2433 err
= ____i915_gem_object_get_pages(obj
);
2437 smp_mb__before_atomic();
2439 atomic_inc(&obj
->mm
.pages_pin_count
);
2442 mutex_unlock(&obj
->mm
.lock
);
2446 /* The 'mapping' part of i915_gem_object_pin_map() below */
2447 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2448 enum i915_map_type type
)
2450 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2451 struct sg_table
*sgt
= obj
->mm
.pages
;
2452 struct sgt_iter sgt_iter
;
2454 struct page
*stack_pages
[32];
2455 struct page
**pages
= stack_pages
;
2456 unsigned long i
= 0;
2460 /* A single page can always be kmapped */
2461 if (n_pages
== 1 && type
== I915_MAP_WB
)
2462 return kmap(sg_page(sgt
->sgl
));
2464 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2465 /* Too big for stack -- allocate temporary array instead */
2466 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2471 for_each_sgt_page(page
, sgt_iter
, sgt
)
2474 /* Check that we have the expected number of pages */
2475 GEM_BUG_ON(i
!= n_pages
);
2479 pgprot
= PAGE_KERNEL
;
2482 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2485 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2487 if (pages
!= stack_pages
)
2488 drm_free_large(pages
);
2493 /* get, pin, and map the pages of the object into kernel space */
2494 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2495 enum i915_map_type type
)
2497 enum i915_map_type has_type
;
2502 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2504 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2506 return ERR_PTR(ret
);
2509 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2510 if (unlikely(!obj
->mm
.pages
)) {
2511 ret
= ____i915_gem_object_get_pages(obj
);
2515 smp_mb__before_atomic();
2517 atomic_inc(&obj
->mm
.pages_pin_count
);
2520 GEM_BUG_ON(!obj
->mm
.pages
);
2522 ptr
= ptr_unpack_bits(obj
->mm
.mapping
, has_type
);
2523 if (ptr
&& has_type
!= type
) {
2529 if (is_vmalloc_addr(ptr
))
2532 kunmap(kmap_to_page(ptr
));
2534 ptr
= obj
->mm
.mapping
= NULL
;
2538 ptr
= i915_gem_object_map(obj
, type
);
2544 obj
->mm
.mapping
= ptr_pack_bits(ptr
, type
);
2548 mutex_unlock(&obj
->mm
.lock
);
2552 atomic_dec(&obj
->mm
.pages_pin_count
);
2558 static bool ban_context(const struct i915_gem_context
*ctx
)
2560 return (i915_gem_context_is_bannable(ctx
) &&
2561 ctx
->ban_score
>= CONTEXT_SCORE_BAN_THRESHOLD
);
2564 static void i915_gem_context_mark_guilty(struct i915_gem_context
*ctx
)
2566 ctx
->guilty_count
++;
2567 ctx
->ban_score
+= CONTEXT_SCORE_GUILTY
;
2568 if (ban_context(ctx
))
2569 i915_gem_context_set_banned(ctx
);
2571 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2572 ctx
->name
, ctx
->ban_score
,
2573 yesno(i915_gem_context_is_banned(ctx
)));
2575 if (!i915_gem_context_is_banned(ctx
) || IS_ERR_OR_NULL(ctx
->file_priv
))
2578 ctx
->file_priv
->context_bans
++;
2579 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2580 ctx
->name
, ctx
->file_priv
->context_bans
);
2583 static void i915_gem_context_mark_innocent(struct i915_gem_context
*ctx
)
2585 ctx
->active_count
++;
2588 struct drm_i915_gem_request
*
2589 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2591 struct drm_i915_gem_request
*request
;
2593 /* We are called by the error capture and reset at a random
2594 * point in time. In particular, note that neither is crucially
2595 * ordered with an interrupt. After a hang, the GPU is dead and we
2596 * assume that no more writes can happen (we waited long enough for
2597 * all writes that were in transaction to be flushed) - adding an
2598 * extra delay for a recent interrupt is pointless. Hence, we do
2599 * not need an engine->irq_seqno_barrier() before the seqno reads.
2601 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2602 if (__i915_gem_request_completed(request
))
2605 GEM_BUG_ON(request
->engine
!= engine
);
2612 static bool engine_stalled(struct intel_engine_cs
*engine
)
2614 if (!engine
->hangcheck
.stalled
)
2617 /* Check for possible seqno movement after hang declaration */
2618 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
)) {
2619 DRM_DEBUG_DRIVER("%s pardoned\n", engine
->name
);
2626 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
)
2628 struct intel_engine_cs
*engine
;
2629 enum intel_engine_id id
;
2632 /* Ensure irq handler finishes, and not run again. */
2633 for_each_engine(engine
, dev_priv
, id
) {
2634 struct drm_i915_gem_request
*request
;
2636 tasklet_kill(&engine
->irq_tasklet
);
2638 if (engine_stalled(engine
)) {
2639 request
= i915_gem_find_active_request(engine
);
2640 if (request
&& request
->fence
.error
== -EIO
)
2641 err
= -EIO
; /* Previous reset failed! */
2645 i915_gem_revoke_fences(dev_priv
);
2650 static void skip_request(struct drm_i915_gem_request
*request
)
2652 void *vaddr
= request
->ring
->vaddr
;
2655 /* As this request likely depends on state from the lost
2656 * context, clear out all the user operations leaving the
2657 * breadcrumb at the end (so we get the fence notifications).
2659 head
= request
->head
;
2660 if (request
->postfix
< head
) {
2661 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2664 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2666 dma_fence_set_error(&request
->fence
, -EIO
);
2669 static void engine_skip_context(struct drm_i915_gem_request
*request
)
2671 struct intel_engine_cs
*engine
= request
->engine
;
2672 struct i915_gem_context
*hung_ctx
= request
->ctx
;
2673 struct intel_timeline
*timeline
;
2674 unsigned long flags
;
2676 timeline
= i915_gem_context_lookup_timeline(hung_ctx
, engine
);
2678 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2679 spin_lock(&timeline
->lock
);
2681 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2682 if (request
->ctx
== hung_ctx
)
2683 skip_request(request
);
2685 list_for_each_entry(request
, &timeline
->requests
, link
)
2686 skip_request(request
);
2688 spin_unlock(&timeline
->lock
);
2689 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2692 /* Returns true if the request was guilty of hang */
2693 static bool i915_gem_reset_request(struct drm_i915_gem_request
*request
)
2695 /* Read once and return the resolution */
2696 const bool guilty
= engine_stalled(request
->engine
);
2698 /* The guilty request will get skipped on a hung engine.
2700 * Users of client default contexts do not rely on logical
2701 * state preserved between batches so it is safe to execute
2702 * queued requests following the hang. Non default contexts
2703 * rely on preserved state, so skipping a batch loses the
2704 * evolution of the state and it needs to be considered corrupted.
2705 * Executing more queued batches on top of corrupted state is
2706 * risky. But we take the risk by trying to advance through
2707 * the queued requests in order to make the client behaviour
2708 * more predictable around resets, by not throwing away random
2709 * amount of batches it has prepared for execution. Sophisticated
2710 * clients can use gem_reset_stats_ioctl and dma fence status
2711 * (exported via sync_file info ioctl on explicit fences) to observe
2712 * when it loses the context state and should rebuild accordingly.
2714 * The context ban, and ultimately the client ban, mechanism are safety
2715 * valves if client submission ends up resulting in nothing more than
2720 i915_gem_context_mark_guilty(request
->ctx
);
2721 skip_request(request
);
2723 i915_gem_context_mark_innocent(request
->ctx
);
2724 dma_fence_set_error(&request
->fence
, -EAGAIN
);
2730 static void i915_gem_reset_engine(struct intel_engine_cs
*engine
)
2732 struct drm_i915_gem_request
*request
;
2734 if (engine
->irq_seqno_barrier
)
2735 engine
->irq_seqno_barrier(engine
);
2737 request
= i915_gem_find_active_request(engine
);
2741 if (!i915_gem_reset_request(request
))
2744 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2745 engine
->name
, request
->global_seqno
);
2747 /* Setup the CS to resume from the breadcrumb of the hung request */
2748 engine
->reset_hw(engine
, request
);
2750 /* If this context is now banned, skip all of its pending requests. */
2751 if (i915_gem_context_is_banned(request
->ctx
))
2752 engine_skip_context(request
);
2755 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
)
2757 struct intel_engine_cs
*engine
;
2758 enum intel_engine_id id
;
2760 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2762 i915_gem_retire_requests(dev_priv
);
2764 for_each_engine(engine
, dev_priv
, id
)
2765 i915_gem_reset_engine(engine
);
2767 i915_gem_restore_fences(dev_priv
);
2769 if (dev_priv
->gt
.awake
) {
2770 intel_sanitize_gt_powersave(dev_priv
);
2771 intel_enable_gt_powersave(dev_priv
);
2772 if (INTEL_GEN(dev_priv
) >= 6)
2773 gen6_rps_busy(dev_priv
);
2777 static void nop_submit_request(struct drm_i915_gem_request
*request
)
2779 dma_fence_set_error(&request
->fence
, -EIO
);
2780 i915_gem_request_submit(request
);
2781 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
2784 static void engine_set_wedged(struct intel_engine_cs
*engine
)
2786 struct drm_i915_gem_request
*request
;
2787 unsigned long flags
;
2789 /* We need to be sure that no thread is running the old callback as
2790 * we install the nop handler (otherwise we would submit a request
2791 * to hardware that will never complete). In order to prevent this
2792 * race, we wait until the machine is idle before making the swap
2793 * (using stop_machine()).
2795 engine
->submit_request
= nop_submit_request
;
2797 /* Mark all executing requests as skipped */
2798 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2799 list_for_each_entry(request
, &engine
->timeline
->requests
, link
)
2800 dma_fence_set_error(&request
->fence
, -EIO
);
2801 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2803 /* Mark all pending requests as complete so that any concurrent
2804 * (lockless) lookup doesn't try and wait upon the request as we
2807 intel_engine_init_global_seqno(engine
,
2808 intel_engine_last_submit(engine
));
2811 * Clear the execlists queue up before freeing the requests, as those
2812 * are the ones that keep the context and ringbuffer backing objects
2816 if (i915
.enable_execlists
) {
2817 unsigned long flags
;
2819 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2821 i915_gem_request_put(engine
->execlist_port
[0].request
);
2822 i915_gem_request_put(engine
->execlist_port
[1].request
);
2823 memset(engine
->execlist_port
, 0, sizeof(engine
->execlist_port
));
2824 engine
->execlist_queue
= RB_ROOT
;
2825 engine
->execlist_first
= NULL
;
2827 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2831 static int __i915_gem_set_wedged_BKL(void *data
)
2833 struct drm_i915_private
*i915
= data
;
2834 struct intel_engine_cs
*engine
;
2835 enum intel_engine_id id
;
2837 for_each_engine(engine
, i915
, id
)
2838 engine_set_wedged(engine
);
2843 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
2845 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2846 set_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
);
2848 stop_machine(__i915_gem_set_wedged_BKL
, dev_priv
, NULL
);
2850 i915_gem_context_lost(dev_priv
);
2851 i915_gem_retire_requests(dev_priv
);
2853 mod_delayed_work(dev_priv
->wq
, &dev_priv
->gt
.idle_work
, 0);
2857 i915_gem_retire_work_handler(struct work_struct
*work
)
2859 struct drm_i915_private
*dev_priv
=
2860 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
2861 struct drm_device
*dev
= &dev_priv
->drm
;
2863 /* Come back later if the device is busy... */
2864 if (mutex_trylock(&dev
->struct_mutex
)) {
2865 i915_gem_retire_requests(dev_priv
);
2866 mutex_unlock(&dev
->struct_mutex
);
2869 /* Keep the retire handler running until we are finally idle.
2870 * We do not need to do this test under locking as in the worst-case
2871 * we queue the retire worker once too often.
2873 if (READ_ONCE(dev_priv
->gt
.awake
)) {
2874 i915_queue_hangcheck(dev_priv
);
2875 queue_delayed_work(dev_priv
->wq
,
2876 &dev_priv
->gt
.retire_work
,
2877 round_jiffies_up_relative(HZ
));
2882 i915_gem_idle_work_handler(struct work_struct
*work
)
2884 struct drm_i915_private
*dev_priv
=
2885 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
2886 struct drm_device
*dev
= &dev_priv
->drm
;
2887 struct intel_engine_cs
*engine
;
2888 enum intel_engine_id id
;
2889 bool rearm_hangcheck
;
2891 if (!READ_ONCE(dev_priv
->gt
.awake
))
2895 * Wait for last execlists context complete, but bail out in case a
2896 * new request is submitted.
2898 wait_for(READ_ONCE(dev_priv
->gt
.active_requests
) ||
2899 intel_execlists_idle(dev_priv
), 10);
2901 if (READ_ONCE(dev_priv
->gt
.active_requests
))
2905 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
2907 if (!mutex_trylock(&dev
->struct_mutex
)) {
2908 /* Currently busy, come back later */
2909 mod_delayed_work(dev_priv
->wq
,
2910 &dev_priv
->gt
.idle_work
,
2911 msecs_to_jiffies(50));
2916 * New request retired after this work handler started, extend active
2917 * period until next instance of the work.
2919 if (work_pending(work
))
2922 if (dev_priv
->gt
.active_requests
)
2925 if (wait_for(intel_execlists_idle(dev_priv
), 10))
2926 DRM_ERROR("Timeout waiting for engines to idle\n");
2928 for_each_engine(engine
, dev_priv
, id
)
2929 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2931 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2932 dev_priv
->gt
.awake
= false;
2933 rearm_hangcheck
= false;
2935 if (INTEL_GEN(dev_priv
) >= 6)
2936 gen6_rps_idle(dev_priv
);
2937 intel_runtime_pm_put(dev_priv
);
2939 mutex_unlock(&dev
->struct_mutex
);
2942 if (rearm_hangcheck
) {
2943 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2944 i915_queue_hangcheck(dev_priv
);
2948 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
2950 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
2951 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
2952 struct i915_vma
*vma
, *vn
;
2954 mutex_lock(&obj
->base
.dev
->struct_mutex
);
2955 list_for_each_entry_safe(vma
, vn
, &obj
->vma_list
, obj_link
)
2956 if (vma
->vm
->file
== fpriv
)
2957 i915_vma_close(vma
);
2959 if (i915_gem_object_is_active(obj
) &&
2960 !i915_gem_object_has_active_reference(obj
)) {
2961 i915_gem_object_set_active_reference(obj
);
2962 i915_gem_object_get(obj
);
2964 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
2967 static unsigned long to_wait_timeout(s64 timeout_ns
)
2970 return MAX_SCHEDULE_TIMEOUT
;
2972 if (timeout_ns
== 0)
2975 return nsecs_to_jiffies_timeout(timeout_ns
);
2979 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2980 * @dev: drm device pointer
2981 * @data: ioctl data blob
2982 * @file: drm file pointer
2984 * Returns 0 if successful, else an error is returned with the remaining time in
2985 * the timeout parameter.
2986 * -ETIME: object is still busy after timeout
2987 * -ERESTARTSYS: signal interrupted the wait
2988 * -ENONENT: object doesn't exist
2989 * Also possible, but rare:
2990 * -EAGAIN: GPU wedged
2992 * -ENODEV: Internal IRQ fail
2993 * -E?: The add request failed
2995 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2996 * non-zero timeout parameter the wait ioctl will wait for the given number of
2997 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2998 * without holding struct_mutex the object may become re-busied before this
2999 * function completes. A similar but shorter * race condition exists in the busy
3003 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3005 struct drm_i915_gem_wait
*args
= data
;
3006 struct drm_i915_gem_object
*obj
;
3010 if (args
->flags
!= 0)
3013 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
3017 start
= ktime_get();
3019 ret
= i915_gem_object_wait(obj
,
3020 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3021 to_wait_timeout(args
->timeout_ns
),
3022 to_rps_client(file
));
3024 if (args
->timeout_ns
> 0) {
3025 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3026 if (args
->timeout_ns
< 0)
3027 args
->timeout_ns
= 0;
3030 i915_gem_object_put(obj
);
3034 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3038 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3039 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3047 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3051 if (flags
& I915_WAIT_LOCKED
) {
3052 struct i915_gem_timeline
*tl
;
3054 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3056 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3057 ret
= wait_for_timeline(tl
, flags
);
3062 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3070 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3073 /* If we don't have a page list set up, then we're not pinned
3074 * to GPU, and we can ignore the cache flush because it'll happen
3075 * again at bind time.
3081 * Stolen memory is always coherent with the GPU as it is explicitly
3082 * marked as wc by the system, or the system is cache-coherent.
3084 if (obj
->stolen
|| obj
->phys_handle
)
3087 /* If the GPU is snooping the contents of the CPU cache,
3088 * we do not need to manually clear the CPU cache lines. However,
3089 * the caches are only snooped when the render cache is
3090 * flushed/invalidated. As we always have to emit invalidations
3091 * and flushes when moving into and out of the RENDER domain, correct
3092 * snooping behaviour occurs naturally as the result of our domain
3095 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3096 obj
->cache_dirty
= true;
3100 trace_i915_gem_object_clflush(obj
);
3101 drm_clflush_sg(obj
->mm
.pages
);
3102 obj
->cache_dirty
= false;
3105 /** Flushes the GTT write domain for the object if it's dirty. */
3107 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3109 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3111 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3114 /* No actual flushing is required for the GTT write domain. Writes
3115 * to it "immediately" go to main memory as far as we know, so there's
3116 * no chipset flush. It also doesn't land in render cache.
3118 * However, we do have to enforce the order so that all writes through
3119 * the GTT land before any writes to the device, such as updates to
3122 * We also have to wait a bit for the writes to land from the GTT.
3123 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3124 * timing. This issue has only been observed when switching quickly
3125 * between GTT writes and CPU reads from inside the kernel on recent hw,
3126 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3127 * system agents we cannot reproduce this behaviour).
3130 if (INTEL_GEN(dev_priv
) >= 6 && !HAS_LLC(dev_priv
))
3131 POSTING_READ(RING_ACTHD(dev_priv
->engine
[RCS
]->mmio_base
));
3133 intel_fb_obj_flush(obj
, false, write_origin(obj
, I915_GEM_DOMAIN_GTT
));
3135 obj
->base
.write_domain
= 0;
3136 trace_i915_gem_object_change_domain(obj
,
3137 obj
->base
.read_domains
,
3138 I915_GEM_DOMAIN_GTT
);
3141 /** Flushes the CPU write domain for the object if it's dirty. */
3143 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3145 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3148 i915_gem_clflush_object(obj
, obj
->pin_display
);
3149 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3151 obj
->base
.write_domain
= 0;
3152 trace_i915_gem_object_change_domain(obj
,
3153 obj
->base
.read_domains
,
3154 I915_GEM_DOMAIN_CPU
);
3158 * Moves a single object to the GTT read, and possibly write domain.
3159 * @obj: object to act on
3160 * @write: ask for write access or read only
3162 * This function returns when the move is complete, including waiting on
3166 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3168 uint32_t old_write_domain
, old_read_domains
;
3171 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3173 ret
= i915_gem_object_wait(obj
,
3174 I915_WAIT_INTERRUPTIBLE
|
3176 (write
? I915_WAIT_ALL
: 0),
3177 MAX_SCHEDULE_TIMEOUT
,
3182 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3185 /* Flush and acquire obj->pages so that we are coherent through
3186 * direct access in memory with previous cached writes through
3187 * shmemfs and that our cache domain tracking remains valid.
3188 * For example, if the obj->filp was moved to swap without us
3189 * being notified and releasing the pages, we would mistakenly
3190 * continue to assume that the obj remained out of the CPU cached
3193 ret
= i915_gem_object_pin_pages(obj
);
3197 i915_gem_object_flush_cpu_write_domain(obj
);
3199 /* Serialise direct access to this object with the barriers for
3200 * coherent writes from the GPU, by effectively invalidating the
3201 * GTT domain upon first access.
3203 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3206 old_write_domain
= obj
->base
.write_domain
;
3207 old_read_domains
= obj
->base
.read_domains
;
3209 /* It should now be out of any other write domains, and we can update
3210 * the domain values for our changes.
3212 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3213 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3215 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3216 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3217 obj
->mm
.dirty
= true;
3220 trace_i915_gem_object_change_domain(obj
,
3224 i915_gem_object_unpin_pages(obj
);
3229 * Changes the cache-level of an object across all VMA.
3230 * @obj: object to act on
3231 * @cache_level: new cache level to set for the object
3233 * After this function returns, the object will be in the new cache-level
3234 * across all GTT and the contents of the backing storage will be coherent,
3235 * with respect to the new cache-level. In order to keep the backing storage
3236 * coherent for all users, we only allow a single cache level to be set
3237 * globally on the object and prevent it from being changed whilst the
3238 * hardware is reading from the object. That is if the object is currently
3239 * on the scanout it will be set to uncached (or equivalent display
3240 * cache coherency) and all non-MOCS GPU access will also be uncached so
3241 * that all direct access to the scanout remains coherent.
3243 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3244 enum i915_cache_level cache_level
)
3246 struct i915_vma
*vma
;
3249 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3251 if (obj
->cache_level
== cache_level
)
3254 /* Inspect the list of currently bound VMA and unbind any that would
3255 * be invalid given the new cache-level. This is principally to
3256 * catch the issue of the CS prefetch crossing page boundaries and
3257 * reading an invalid PTE on older architectures.
3260 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3261 if (!drm_mm_node_allocated(&vma
->node
))
3264 if (i915_vma_is_pinned(vma
)) {
3265 DRM_DEBUG("can not change the cache level of pinned objects\n");
3269 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3272 ret
= i915_vma_unbind(vma
);
3276 /* As unbinding may affect other elements in the
3277 * obj->vma_list (due to side-effects from retiring
3278 * an active vma), play safe and restart the iterator.
3283 /* We can reuse the existing drm_mm nodes but need to change the
3284 * cache-level on the PTE. We could simply unbind them all and
3285 * rebind with the correct cache-level on next use. However since
3286 * we already have a valid slot, dma mapping, pages etc, we may as
3287 * rewrite the PTE in the belief that doing so tramples upon less
3288 * state and so involves less work.
3290 if (obj
->bind_count
) {
3291 /* Before we change the PTE, the GPU must not be accessing it.
3292 * If we wait upon the object, we know that all the bound
3293 * VMA are no longer active.
3295 ret
= i915_gem_object_wait(obj
,
3296 I915_WAIT_INTERRUPTIBLE
|
3299 MAX_SCHEDULE_TIMEOUT
,
3304 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3305 cache_level
!= I915_CACHE_NONE
) {
3306 /* Access to snoopable pages through the GTT is
3307 * incoherent and on some machines causes a hard
3308 * lockup. Relinquish the CPU mmaping to force
3309 * userspace to refault in the pages and we can
3310 * then double check if the GTT mapping is still
3311 * valid for that pointer access.
3313 i915_gem_release_mmap(obj
);
3315 /* As we no longer need a fence for GTT access,
3316 * we can relinquish it now (and so prevent having
3317 * to steal a fence from someone else on the next
3318 * fence request). Note GPU activity would have
3319 * dropped the fence as all snoopable access is
3320 * supposed to be linear.
3322 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3323 ret
= i915_vma_put_fence(vma
);
3328 /* We either have incoherent backing store and
3329 * so no GTT access or the architecture is fully
3330 * coherent. In such cases, existing GTT mmaps
3331 * ignore the cache bit in the PTE and we can
3332 * rewrite it without confusing the GPU or having
3333 * to force userspace to fault back in its mmaps.
3337 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3338 if (!drm_mm_node_allocated(&vma
->node
))
3341 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3347 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
&&
3348 cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3349 obj
->cache_dirty
= true;
3351 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3352 vma
->node
.color
= cache_level
;
3353 obj
->cache_level
= cache_level
;
3358 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3359 struct drm_file
*file
)
3361 struct drm_i915_gem_caching
*args
= data
;
3362 struct drm_i915_gem_object
*obj
;
3366 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3372 switch (obj
->cache_level
) {
3373 case I915_CACHE_LLC
:
3374 case I915_CACHE_L3_LLC
:
3375 args
->caching
= I915_CACHING_CACHED
;
3379 args
->caching
= I915_CACHING_DISPLAY
;
3383 args
->caching
= I915_CACHING_NONE
;
3391 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3392 struct drm_file
*file
)
3394 struct drm_i915_private
*i915
= to_i915(dev
);
3395 struct drm_i915_gem_caching
*args
= data
;
3396 struct drm_i915_gem_object
*obj
;
3397 enum i915_cache_level level
;
3400 switch (args
->caching
) {
3401 case I915_CACHING_NONE
:
3402 level
= I915_CACHE_NONE
;
3404 case I915_CACHING_CACHED
:
3406 * Due to a HW issue on BXT A stepping, GPU stores via a
3407 * snooped mapping may leave stale data in a corresponding CPU
3408 * cacheline, whereas normally such cachelines would get
3411 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3414 level
= I915_CACHE_LLC
;
3416 case I915_CACHING_DISPLAY
:
3417 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3423 obj
= i915_gem_object_lookup(file
, args
->handle
);
3427 if (obj
->cache_level
== level
)
3430 ret
= i915_gem_object_wait(obj
,
3431 I915_WAIT_INTERRUPTIBLE
,
3432 MAX_SCHEDULE_TIMEOUT
,
3433 to_rps_client(file
));
3437 ret
= i915_mutex_lock_interruptible(dev
);
3441 ret
= i915_gem_object_set_cache_level(obj
, level
);
3442 mutex_unlock(&dev
->struct_mutex
);
3445 i915_gem_object_put(obj
);
3450 * Prepare buffer for display plane (scanout, cursors, etc).
3451 * Can be called from an uninterruptible phase (modesetting) and allows
3452 * any flushes to be pipelined (for pageflips).
3455 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3457 const struct i915_ggtt_view
*view
)
3459 struct i915_vma
*vma
;
3460 u32 old_read_domains
, old_write_domain
;
3463 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3465 /* Mark the pin_display early so that we account for the
3466 * display coherency whilst setting up the cache domains.
3470 /* The display engine is not coherent with the LLC cache on gen6. As
3471 * a result, we make sure that the pinning that is about to occur is
3472 * done with uncached PTEs. This is lowest common denominator for all
3475 * However for gen6+, we could do better by using the GFDT bit instead
3476 * of uncaching, which would allow us to flush all the LLC-cached data
3477 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3479 ret
= i915_gem_object_set_cache_level(obj
,
3480 HAS_WT(to_i915(obj
->base
.dev
)) ?
3481 I915_CACHE_WT
: I915_CACHE_NONE
);
3484 goto err_unpin_display
;
3487 /* As the user may map the buffer once pinned in the display plane
3488 * (e.g. libkms for the bootup splash), we have to ensure that we
3489 * always use map_and_fenceable for all scanout buffers. However,
3490 * it may simply be too big to fit into mappable, in which case
3491 * put it anyway and hope that userspace can cope (but always first
3492 * try to preserve the existing ABI).
3494 vma
= ERR_PTR(-ENOSPC
);
3495 if (!view
|| view
->type
== I915_GGTT_VIEW_NORMAL
)
3496 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3497 PIN_MAPPABLE
| PIN_NONBLOCK
);
3499 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3502 /* Valleyview is definitely limited to scanning out the first
3503 * 512MiB. Lets presume this behaviour was inherited from the
3504 * g4x display engine and that all earlier gen are similarly
3505 * limited. Testing suggests that it is a little more
3506 * complicated than this. For example, Cherryview appears quite
3507 * happy to scanout from anywhere within its global aperture.
3510 if (HAS_GMCH_DISPLAY(i915
))
3511 flags
= PIN_MAPPABLE
;
3512 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3515 goto err_unpin_display
;
3517 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3519 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3520 if (obj
->cache_dirty
) {
3521 i915_gem_clflush_object(obj
, true);
3522 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
3525 old_write_domain
= obj
->base
.write_domain
;
3526 old_read_domains
= obj
->base
.read_domains
;
3528 /* It should now be out of any other write domains, and we can update
3529 * the domain values for our changes.
3531 obj
->base
.write_domain
= 0;
3532 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3534 trace_i915_gem_object_change_domain(obj
,
3546 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3548 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
3550 if (WARN_ON(vma
->obj
->pin_display
== 0))
3553 if (--vma
->obj
->pin_display
== 0)
3554 vma
->display_alignment
= I915_GTT_MIN_ALIGNMENT
;
3556 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3557 i915_gem_object_bump_inactive_ggtt(vma
->obj
);
3559 i915_vma_unpin(vma
);
3563 * Moves a single object to the CPU read, and possibly write domain.
3564 * @obj: object to act on
3565 * @write: requesting write or read-only access
3567 * This function returns when the move is complete, including waiting on
3571 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3573 uint32_t old_write_domain
, old_read_domains
;
3576 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3578 ret
= i915_gem_object_wait(obj
,
3579 I915_WAIT_INTERRUPTIBLE
|
3581 (write
? I915_WAIT_ALL
: 0),
3582 MAX_SCHEDULE_TIMEOUT
,
3587 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3590 i915_gem_object_flush_gtt_write_domain(obj
);
3592 old_write_domain
= obj
->base
.write_domain
;
3593 old_read_domains
= obj
->base
.read_domains
;
3595 /* Flush the CPU cache if it's still invalid. */
3596 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3597 i915_gem_clflush_object(obj
, false);
3599 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3602 /* It should now be out of any other write domains, and we can update
3603 * the domain values for our changes.
3605 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3607 /* If we're writing through the CPU, then the GPU read domains will
3608 * need to be invalidated at next use.
3611 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3612 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3615 trace_i915_gem_object_change_domain(obj
,
3622 /* Throttle our rendering by waiting until the ring has completed our requests
3623 * emitted over 20 msec ago.
3625 * Note that if we were to use the current jiffies each time around the loop,
3626 * we wouldn't escape the function with any frames outstanding if the time to
3627 * render a frame was over 20ms.
3629 * This should get us reasonable parallelism between CPU and GPU but also
3630 * relatively low latency when blocking on a particular request to finish.
3633 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3635 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3636 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3637 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3638 struct drm_i915_gem_request
*request
, *target
= NULL
;
3641 /* ABI: return -EIO if already wedged */
3642 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3645 spin_lock(&file_priv
->mm
.lock
);
3646 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3647 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3651 * Note that the request might not have been submitted yet.
3652 * In which case emitted_jiffies will be zero.
3654 if (!request
->emitted_jiffies
)
3660 i915_gem_request_get(target
);
3661 spin_unlock(&file_priv
->mm
.lock
);
3666 ret
= i915_wait_request(target
,
3667 I915_WAIT_INTERRUPTIBLE
,
3668 MAX_SCHEDULE_TIMEOUT
);
3669 i915_gem_request_put(target
);
3671 return ret
< 0 ? ret
: 0;
3675 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3676 const struct i915_ggtt_view
*view
,
3681 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3682 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
3683 struct i915_vma
*vma
;
3686 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3688 vma
= i915_vma_instance(obj
, vm
, view
);
3689 if (unlikely(IS_ERR(vma
)))
3692 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
3693 if (flags
& PIN_NONBLOCK
&&
3694 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
3695 return ERR_PTR(-ENOSPC
);
3697 if (flags
& PIN_MAPPABLE
) {
3698 /* If the required space is larger than the available
3699 * aperture, we will not able to find a slot for the
3700 * object and unbinding the object now will be in
3701 * vain. Worse, doing so may cause us to ping-pong
3702 * the object in and out of the Global GTT and
3703 * waste a lot of cycles under the mutex.
3705 if (vma
->fence_size
> dev_priv
->ggtt
.mappable_end
)
3706 return ERR_PTR(-E2BIG
);
3708 /* If NONBLOCK is set the caller is optimistically
3709 * trying to cache the full object within the mappable
3710 * aperture, and *must* have a fallback in place for
3711 * situations where we cannot bind the object. We
3712 * can be a little more lax here and use the fallback
3713 * more often to avoid costly migrations of ourselves
3714 * and other objects within the aperture.
3716 * Half-the-aperture is used as a simple heuristic.
3717 * More interesting would to do search for a free
3718 * block prior to making the commitment to unbind.
3719 * That caters for the self-harm case, and with a
3720 * little more heuristics (e.g. NOFAULT, NOEVICT)
3721 * we could try to minimise harm to others.
3723 if (flags
& PIN_NONBLOCK
&&
3724 vma
->fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
3725 return ERR_PTR(-ENOSPC
);
3728 WARN(i915_vma_is_pinned(vma
),
3729 "bo is already pinned in ggtt with incorrect alignment:"
3730 " offset=%08x, req.alignment=%llx,"
3731 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3732 i915_ggtt_offset(vma
), alignment
,
3733 !!(flags
& PIN_MAPPABLE
),
3734 i915_vma_is_map_and_fenceable(vma
));
3735 ret
= i915_vma_unbind(vma
);
3737 return ERR_PTR(ret
);
3740 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
3742 return ERR_PTR(ret
);
3747 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
3749 /* Note that we could alias engines in the execbuf API, but
3750 * that would be very unwise as it prevents userspace from
3751 * fine control over engine selection. Ahem.
3753 * This should be something like EXEC_MAX_ENGINE instead of
3756 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
3757 return 0x10000 << id
;
3760 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
3762 /* The uABI guarantees an active writer is also amongst the read
3763 * engines. This would be true if we accessed the activity tracking
3764 * under the lock, but as we perform the lookup of the object and
3765 * its activity locklessly we can not guarantee that the last_write
3766 * being active implies that we have set the same engine flag from
3767 * last_read - hence we always set both read and write busy for
3770 return id
| __busy_read_flag(id
);
3773 static __always_inline
unsigned int
3774 __busy_set_if_active(const struct dma_fence
*fence
,
3775 unsigned int (*flag
)(unsigned int id
))
3777 struct drm_i915_gem_request
*rq
;
3779 /* We have to check the current hw status of the fence as the uABI
3780 * guarantees forward progress. We could rely on the idle worker
3781 * to eventually flush us, but to minimise latency just ask the
3784 * Note we only report on the status of native fences.
3786 if (!dma_fence_is_i915(fence
))
3789 /* opencode to_request() in order to avoid const warnings */
3790 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
3791 if (i915_gem_request_completed(rq
))
3794 return flag(rq
->engine
->exec_id
);
3797 static __always_inline
unsigned int
3798 busy_check_reader(const struct dma_fence
*fence
)
3800 return __busy_set_if_active(fence
, __busy_read_flag
);
3803 static __always_inline
unsigned int
3804 busy_check_writer(const struct dma_fence
*fence
)
3809 return __busy_set_if_active(fence
, __busy_write_id
);
3813 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3814 struct drm_file
*file
)
3816 struct drm_i915_gem_busy
*args
= data
;
3817 struct drm_i915_gem_object
*obj
;
3818 struct reservation_object_list
*list
;
3824 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3828 /* A discrepancy here is that we do not report the status of
3829 * non-i915 fences, i.e. even though we may report the object as idle,
3830 * a call to set-domain may still stall waiting for foreign rendering.
3831 * This also means that wait-ioctl may report an object as busy,
3832 * where busy-ioctl considers it idle.
3834 * We trade the ability to warn of foreign fences to report on which
3835 * i915 engines are active for the object.
3837 * Alternatively, we can trade that extra information on read/write
3840 * !reservation_object_test_signaled_rcu(obj->resv, true);
3841 * to report the overall busyness. This is what the wait-ioctl does.
3845 seq
= raw_read_seqcount(&obj
->resv
->seq
);
3847 /* Translate the exclusive fence to the READ *and* WRITE engine */
3848 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
3850 /* Translate shared fences to READ set of engines */
3851 list
= rcu_dereference(obj
->resv
->fence
);
3853 unsigned int shared_count
= list
->shared_count
, i
;
3855 for (i
= 0; i
< shared_count
; ++i
) {
3856 struct dma_fence
*fence
=
3857 rcu_dereference(list
->shared
[i
]);
3859 args
->busy
|= busy_check_reader(fence
);
3863 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
3873 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3874 struct drm_file
*file_priv
)
3876 return i915_gem_ring_throttle(dev
, file_priv
);
3880 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3881 struct drm_file
*file_priv
)
3883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3884 struct drm_i915_gem_madvise
*args
= data
;
3885 struct drm_i915_gem_object
*obj
;
3888 switch (args
->madv
) {
3889 case I915_MADV_DONTNEED
:
3890 case I915_MADV_WILLNEED
:
3896 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
3900 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
3904 if (obj
->mm
.pages
&&
3905 i915_gem_object_is_tiled(obj
) &&
3906 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
3907 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
3908 GEM_BUG_ON(!obj
->mm
.quirked
);
3909 __i915_gem_object_unpin_pages(obj
);
3910 obj
->mm
.quirked
= false;
3912 if (args
->madv
== I915_MADV_WILLNEED
) {
3913 GEM_BUG_ON(obj
->mm
.quirked
);
3914 __i915_gem_object_pin_pages(obj
);
3915 obj
->mm
.quirked
= true;
3919 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
3920 obj
->mm
.madv
= args
->madv
;
3922 /* if the object is no longer attached, discard its backing storage */
3923 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
3924 i915_gem_object_truncate(obj
);
3926 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
3927 mutex_unlock(&obj
->mm
.lock
);
3930 i915_gem_object_put(obj
);
3935 frontbuffer_retire(struct i915_gem_active
*active
,
3936 struct drm_i915_gem_request
*request
)
3938 struct drm_i915_gem_object
*obj
=
3939 container_of(active
, typeof(*obj
), frontbuffer_write
);
3941 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
3944 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3945 const struct drm_i915_gem_object_ops
*ops
)
3947 mutex_init(&obj
->mm
.lock
);
3949 INIT_LIST_HEAD(&obj
->global_link
);
3950 INIT_LIST_HEAD(&obj
->userfault_link
);
3951 INIT_LIST_HEAD(&obj
->obj_exec_link
);
3952 INIT_LIST_HEAD(&obj
->vma_list
);
3953 INIT_LIST_HEAD(&obj
->batch_pool_link
);
3957 reservation_object_init(&obj
->__builtin_resv
);
3958 obj
->resv
= &obj
->__builtin_resv
;
3960 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
3961 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
3963 obj
->mm
.madv
= I915_MADV_WILLNEED
;
3964 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
3965 mutex_init(&obj
->mm
.get_page
.lock
);
3967 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
3970 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3971 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
3972 I915_GEM_OBJECT_IS_SHRINKABLE
,
3973 .get_pages
= i915_gem_object_get_pages_gtt
,
3974 .put_pages
= i915_gem_object_put_pages_gtt
,
3977 struct drm_i915_gem_object
*
3978 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
)
3980 struct drm_i915_gem_object
*obj
;
3981 struct address_space
*mapping
;
3985 /* There is a prevalence of the assumption that we fit the object's
3986 * page count inside a 32bit _signed_ variable. Let's document this and
3987 * catch if we ever need to fix it. In the meantime, if you do spot
3988 * such a local variable, please consider fixing!
3990 if (WARN_ON(size
>> PAGE_SHIFT
> INT_MAX
))
3991 return ERR_PTR(-E2BIG
);
3993 if (overflows_type(size
, obj
->base
.size
))
3994 return ERR_PTR(-E2BIG
);
3996 obj
= i915_gem_object_alloc(dev_priv
);
3998 return ERR_PTR(-ENOMEM
);
4000 ret
= drm_gem_object_init(&dev_priv
->drm
, &obj
->base
, size
);
4004 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4005 if (IS_I965GM(dev_priv
) || IS_I965G(dev_priv
)) {
4006 /* 965gm cannot relocate objects above 4GiB. */
4007 mask
&= ~__GFP_HIGHMEM
;
4008 mask
|= __GFP_DMA32
;
4011 mapping
= obj
->base
.filp
->f_mapping
;
4012 mapping_set_gfp_mask(mapping
, mask
);
4014 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4016 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4017 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4019 if (HAS_LLC(dev_priv
)) {
4020 /* On some devices, we can have the GPU use the LLC (the CPU
4021 * cache) for about a 10% performance improvement
4022 * compared to uncached. Graphics requests other than
4023 * display scanout are coherent with the CPU in
4024 * accessing this cache. This means in this mode we
4025 * don't need to clflush on the CPU side, and on the
4026 * GPU side we only need to flush internal caches to
4027 * get data visible to the CPU.
4029 * However, we maintain the display planes as UC, and so
4030 * need to rebind when first used as such.
4032 obj
->cache_level
= I915_CACHE_LLC
;
4034 obj
->cache_level
= I915_CACHE_NONE
;
4036 trace_i915_gem_object_create(obj
);
4041 i915_gem_object_free(obj
);
4042 return ERR_PTR(ret
);
4045 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4047 /* If we are the last user of the backing storage (be it shmemfs
4048 * pages or stolen etc), we know that the pages are going to be
4049 * immediately released. In this case, we can then skip copying
4050 * back the contents from the GPU.
4053 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4056 if (obj
->base
.filp
== NULL
)
4059 /* At first glance, this looks racy, but then again so would be
4060 * userspace racing mmap against close. However, the first external
4061 * reference to the filp can only be obtained through the
4062 * i915_gem_mmap_ioctl() which safeguards us against the user
4063 * acquiring such a reference whilst we are in the middle of
4064 * freeing the object.
4066 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4069 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4070 struct llist_node
*freed
)
4072 struct drm_i915_gem_object
*obj
, *on
;
4074 mutex_lock(&i915
->drm
.struct_mutex
);
4075 intel_runtime_pm_get(i915
);
4076 llist_for_each_entry(obj
, freed
, freed
) {
4077 struct i915_vma
*vma
, *vn
;
4079 trace_i915_gem_object_destroy(obj
);
4081 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4082 list_for_each_entry_safe(vma
, vn
,
4083 &obj
->vma_list
, obj_link
) {
4084 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
4085 GEM_BUG_ON(i915_vma_is_active(vma
));
4086 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4087 i915_vma_close(vma
);
4089 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4090 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4092 list_del(&obj
->global_link
);
4094 intel_runtime_pm_put(i915
);
4095 mutex_unlock(&i915
->drm
.struct_mutex
);
4097 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4098 GEM_BUG_ON(obj
->bind_count
);
4099 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4101 if (obj
->ops
->release
)
4102 obj
->ops
->release(obj
);
4104 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4105 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4106 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4107 GEM_BUG_ON(obj
->mm
.pages
);
4109 if (obj
->base
.import_attach
)
4110 drm_prime_gem_destroy(&obj
->base
, NULL
);
4112 reservation_object_fini(&obj
->__builtin_resv
);
4113 drm_gem_object_release(&obj
->base
);
4114 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4117 i915_gem_object_free(obj
);
4121 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4123 struct llist_node
*freed
;
4125 freed
= llist_del_all(&i915
->mm
.free_list
);
4126 if (unlikely(freed
))
4127 __i915_gem_free_objects(i915
, freed
);
4130 static void __i915_gem_free_work(struct work_struct
*work
)
4132 struct drm_i915_private
*i915
=
4133 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4134 struct llist_node
*freed
;
4136 /* All file-owned VMA should have been released by this point through
4137 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4138 * However, the object may also be bound into the global GTT (e.g.
4139 * older GPUs without per-process support, or for direct access through
4140 * the GTT either for the user or for scanout). Those VMA still need to
4144 while ((freed
= llist_del_all(&i915
->mm
.free_list
)))
4145 __i915_gem_free_objects(i915
, freed
);
4148 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4150 struct drm_i915_gem_object
*obj
=
4151 container_of(head
, typeof(*obj
), rcu
);
4152 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4154 /* We can't simply use call_rcu() from i915_gem_free_object()
4155 * as we need to block whilst unbinding, and the call_rcu
4156 * task may be called from softirq context. So we take a
4157 * detour through a worker.
4159 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4160 schedule_work(&i915
->mm
.free_work
);
4163 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4165 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4167 if (obj
->mm
.quirked
)
4168 __i915_gem_object_unpin_pages(obj
);
4170 if (discard_backing_storage(obj
))
4171 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4173 /* Before we free the object, make sure any pure RCU-only
4174 * read-side critical sections are complete, e.g.
4175 * i915_gem_busy_ioctl(). For the corresponding synchronized
4176 * lookup see i915_gem_object_lookup_rcu().
4178 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4181 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4183 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4185 GEM_BUG_ON(i915_gem_object_has_active_reference(obj
));
4186 if (i915_gem_object_is_active(obj
))
4187 i915_gem_object_set_active_reference(obj
);
4189 i915_gem_object_put(obj
);
4192 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4194 struct intel_engine_cs
*engine
;
4195 enum intel_engine_id id
;
4197 for_each_engine(engine
, dev_priv
, id
)
4198 GEM_BUG_ON(engine
->last_retired_context
&&
4199 !i915_gem_context_is_kernel(engine
->last_retired_context
));
4202 int i915_gem_suspend(struct drm_i915_private
*dev_priv
)
4204 struct drm_device
*dev
= &dev_priv
->drm
;
4207 intel_suspend_gt_powersave(dev_priv
);
4209 mutex_lock(&dev
->struct_mutex
);
4211 /* We have to flush all the executing contexts to main memory so
4212 * that they can saved in the hibernation image. To ensure the last
4213 * context image is coherent, we have to switch away from it. That
4214 * leaves the dev_priv->kernel_context still active when
4215 * we actually suspend, and its image in memory may not match the GPU
4216 * state. Fortunately, the kernel_context is disposable and we do
4217 * not rely on its state.
4219 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4223 ret
= i915_gem_wait_for_idle(dev_priv
,
4224 I915_WAIT_INTERRUPTIBLE
|
4229 i915_gem_retire_requests(dev_priv
);
4230 GEM_BUG_ON(dev_priv
->gt
.active_requests
);
4232 assert_kernel_context_is_current(dev_priv
);
4233 i915_gem_context_lost(dev_priv
);
4234 mutex_unlock(&dev
->struct_mutex
);
4236 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4237 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4239 /* As the idle_work is rearming if it detects a race, play safe and
4240 * repeat the flush until it is definitely idle.
4242 while (flush_delayed_work(&dev_priv
->gt
.idle_work
))
4245 i915_gem_drain_freed_objects(dev_priv
);
4247 /* Assert that we sucessfully flushed all the work and
4248 * reset the GPU back to its idle, low power state.
4250 WARN_ON(dev_priv
->gt
.awake
);
4251 WARN_ON(!intel_execlists_idle(dev_priv
));
4254 * Neither the BIOS, ourselves or any other kernel
4255 * expects the system to be in execlists mode on startup,
4256 * so we need to reset the GPU back to legacy mode. And the only
4257 * known way to disable logical contexts is through a GPU reset.
4259 * So in order to leave the system in a known default configuration,
4260 * always reset the GPU upon unload and suspend. Afterwards we then
4261 * clean up the GEM state tracking, flushing off the requests and
4262 * leaving the system in a known idle state.
4264 * Note that is of the upmost importance that the GPU is idle and
4265 * all stray writes are flushed *before* we dismantle the backing
4266 * storage for the pinned objects.
4268 * However, since we are uncertain that resetting the GPU on older
4269 * machines is a good idea, we don't - just in case it leaves the
4270 * machine in an unusable condition.
4272 if (HAS_HW_CONTEXTS(dev_priv
)) {
4273 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
4274 WARN_ON(reset
&& reset
!= -ENODEV
);
4280 mutex_unlock(&dev
->struct_mutex
);
4284 void i915_gem_resume(struct drm_i915_private
*dev_priv
)
4286 struct drm_device
*dev
= &dev_priv
->drm
;
4288 WARN_ON(dev_priv
->gt
.awake
);
4290 mutex_lock(&dev
->struct_mutex
);
4291 i915_gem_restore_gtt_mappings(dev_priv
);
4293 /* As we didn't flush the kernel context before suspend, we cannot
4294 * guarantee that the context image is complete. So let's just reset
4295 * it and start again.
4297 dev_priv
->gt
.resume(dev_priv
);
4299 mutex_unlock(&dev
->struct_mutex
);
4302 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4304 if (INTEL_GEN(dev_priv
) < 5 ||
4305 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4308 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4309 DISP_TILE_SURFACE_SWIZZLING
);
4311 if (IS_GEN5(dev_priv
))
4314 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4315 if (IS_GEN6(dev_priv
))
4316 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4317 else if (IS_GEN7(dev_priv
))
4318 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4319 else if (IS_GEN8(dev_priv
))
4320 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4325 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4327 I915_WRITE(RING_CTL(base
), 0);
4328 I915_WRITE(RING_HEAD(base
), 0);
4329 I915_WRITE(RING_TAIL(base
), 0);
4330 I915_WRITE(RING_START(base
), 0);
4333 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4335 if (IS_I830(dev_priv
)) {
4336 init_unused_ring(dev_priv
, PRB1_BASE
);
4337 init_unused_ring(dev_priv
, SRB0_BASE
);
4338 init_unused_ring(dev_priv
, SRB1_BASE
);
4339 init_unused_ring(dev_priv
, SRB2_BASE
);
4340 init_unused_ring(dev_priv
, SRB3_BASE
);
4341 } else if (IS_GEN2(dev_priv
)) {
4342 init_unused_ring(dev_priv
, SRB0_BASE
);
4343 init_unused_ring(dev_priv
, SRB1_BASE
);
4344 } else if (IS_GEN3(dev_priv
)) {
4345 init_unused_ring(dev_priv
, PRB1_BASE
);
4346 init_unused_ring(dev_priv
, PRB2_BASE
);
4351 i915_gem_init_hw(struct drm_i915_private
*dev_priv
)
4353 struct intel_engine_cs
*engine
;
4354 enum intel_engine_id id
;
4357 dev_priv
->gt
.last_init_time
= ktime_get();
4359 /* Double layer security blanket, see i915_gem_init() */
4360 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4362 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4363 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4365 if (IS_HASWELL(dev_priv
))
4366 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4367 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4369 if (HAS_PCH_NOP(dev_priv
)) {
4370 if (IS_IVYBRIDGE(dev_priv
)) {
4371 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4372 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4373 I915_WRITE(GEN7_MSG_CTL
, temp
);
4374 } else if (INTEL_GEN(dev_priv
) >= 7) {
4375 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4376 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4377 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4381 i915_gem_init_swizzling(dev_priv
);
4384 * At least 830 can leave some of the unused rings
4385 * "active" (ie. head != tail) after resume which
4386 * will prevent c3 entry. Makes sure all unused rings
4389 init_unused_rings(dev_priv
);
4391 BUG_ON(!dev_priv
->kernel_context
);
4393 ret
= i915_ppgtt_init_hw(dev_priv
);
4395 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4399 /* Need to do basic initialisation of all rings first: */
4400 for_each_engine(engine
, dev_priv
, id
) {
4401 ret
= engine
->init_hw(engine
);
4406 intel_mocs_init_l3cc_table(dev_priv
);
4408 /* We can't enable contexts until all firmware is loaded */
4409 ret
= intel_guc_setup(dev_priv
);
4414 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4418 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4420 if (INTEL_INFO(dev_priv
)->gen
< 6)
4423 /* TODO: make semaphores and Execlists play nicely together */
4424 if (i915
.enable_execlists
)
4430 #ifdef CONFIG_INTEL_IOMMU
4431 /* Enable semaphores on SNB when IO remapping is off */
4432 if (INTEL_INFO(dev_priv
)->gen
== 6 && intel_iommu_gfx_mapped
)
4439 int i915_gem_init(struct drm_i915_private
*dev_priv
)
4443 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4445 if (!i915
.enable_execlists
) {
4446 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4447 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4449 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4450 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4453 /* This is just a security blanket to placate dragons.
4454 * On some systems, we very sporadically observe that the first TLBs
4455 * used by the CS may be stale, despite us poking the TLB reset. If
4456 * we hold the forcewake during initialisation these problems
4457 * just magically go away.
4459 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4461 i915_gem_init_userptr(dev_priv
);
4463 ret
= i915_gem_init_ggtt(dev_priv
);
4467 ret
= i915_gem_context_init(dev_priv
);
4471 ret
= intel_engines_init(dev_priv
);
4475 ret
= i915_gem_init_hw(dev_priv
);
4477 /* Allow engine initialisation to fail by marking the GPU as
4478 * wedged. But we only want to do this where the GPU is angry,
4479 * for all other failure, such as an allocation failure, bail.
4481 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4482 i915_gem_set_wedged(dev_priv
);
4487 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4488 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4494 i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
)
4496 struct intel_engine_cs
*engine
;
4497 enum intel_engine_id id
;
4499 for_each_engine(engine
, dev_priv
, id
)
4500 dev_priv
->gt
.cleanup_engine(engine
);
4504 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4508 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4509 !IS_CHERRYVIEW(dev_priv
))
4510 dev_priv
->num_fence_regs
= 32;
4511 else if (INTEL_INFO(dev_priv
)->gen
>= 4 ||
4512 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
4513 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
))
4514 dev_priv
->num_fence_regs
= 16;
4516 dev_priv
->num_fence_regs
= 8;
4518 if (intel_vgpu_active(dev_priv
))
4519 dev_priv
->num_fence_regs
=
4520 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4522 /* Initialize fence registers to zero */
4523 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4524 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4526 fence
->i915
= dev_priv
;
4528 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4530 i915_gem_restore_fences(dev_priv
);
4532 i915_gem_detect_bit_6_swizzle(dev_priv
);
4536 i915_gem_load_init(struct drm_i915_private
*dev_priv
)
4540 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4541 if (!dev_priv
->objects
)
4544 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4545 if (!dev_priv
->vmas
)
4548 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4549 SLAB_HWCACHE_ALIGN
|
4550 SLAB_RECLAIM_ACCOUNT
|
4551 SLAB_DESTROY_BY_RCU
);
4552 if (!dev_priv
->requests
)
4555 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4556 SLAB_HWCACHE_ALIGN
|
4557 SLAB_RECLAIM_ACCOUNT
);
4558 if (!dev_priv
->dependencies
)
4561 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4562 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4563 err
= i915_gem_timeline_init__global(dev_priv
);
4564 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4566 goto err_dependencies
;
4568 INIT_LIST_HEAD(&dev_priv
->context_list
);
4569 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4570 init_llist_head(&dev_priv
->mm
.free_list
);
4571 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4572 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4573 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4574 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4575 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4576 i915_gem_retire_work_handler
);
4577 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4578 i915_gem_idle_work_handler
);
4579 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4580 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4582 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4584 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4586 dev_priv
->mm
.interruptible
= true;
4588 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4590 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4595 kmem_cache_destroy(dev_priv
->dependencies
);
4597 kmem_cache_destroy(dev_priv
->requests
);
4599 kmem_cache_destroy(dev_priv
->vmas
);
4601 kmem_cache_destroy(dev_priv
->objects
);
4606 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
)
4608 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4610 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4611 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4612 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4613 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4615 kmem_cache_destroy(dev_priv
->dependencies
);
4616 kmem_cache_destroy(dev_priv
->requests
);
4617 kmem_cache_destroy(dev_priv
->vmas
);
4618 kmem_cache_destroy(dev_priv
->objects
);
4620 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4624 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
4626 intel_runtime_pm_get(dev_priv
);
4628 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4629 i915_gem_shrink_all(dev_priv
);
4630 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4632 intel_runtime_pm_put(dev_priv
);
4637 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
4639 struct drm_i915_gem_object
*obj
;
4640 struct list_head
*phases
[] = {
4641 &dev_priv
->mm
.unbound_list
,
4642 &dev_priv
->mm
.bound_list
,
4646 /* Called just before we write the hibernation image.
4648 * We need to update the domain tracking to reflect that the CPU
4649 * will be accessing all the pages to create and restore from the
4650 * hibernation, and so upon restoration those pages will be in the
4653 * To make sure the hibernation image contains the latest state,
4654 * we update that state just before writing out the image.
4656 * To try and reduce the hibernation image, we manually shrink
4657 * the objects as well.
4660 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4661 i915_gem_shrink(dev_priv
, -1UL, I915_SHRINK_UNBOUND
);
4663 for (p
= phases
; *p
; p
++) {
4664 list_for_each_entry(obj
, *p
, global_link
) {
4665 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4666 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4669 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4674 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4676 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4677 struct drm_i915_gem_request
*request
;
4679 /* Clean up our request list when the client is going away, so that
4680 * later retire_requests won't dereference our soon-to-be-gone
4683 spin_lock(&file_priv
->mm
.lock
);
4684 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
)
4685 request
->file_priv
= NULL
;
4686 spin_unlock(&file_priv
->mm
.lock
);
4688 if (!list_empty(&file_priv
->rps
.link
)) {
4689 spin_lock(&to_i915(dev
)->rps
.client_lock
);
4690 list_del(&file_priv
->rps
.link
);
4691 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
4695 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4697 struct drm_i915_file_private
*file_priv
;
4702 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4706 file
->driver_priv
= file_priv
;
4707 file_priv
->dev_priv
= to_i915(dev
);
4708 file_priv
->file
= file
;
4709 INIT_LIST_HEAD(&file_priv
->rps
.link
);
4711 spin_lock_init(&file_priv
->mm
.lock
);
4712 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4714 file_priv
->bsd_engine
= -1;
4716 ret
= i915_gem_context_open(dev
, file
);
4724 * i915_gem_track_fb - update frontbuffer tracking
4725 * @old: current GEM buffer for the frontbuffer slots
4726 * @new: new GEM buffer for the frontbuffer slots
4727 * @frontbuffer_bits: bitmask of frontbuffer slots
4729 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4730 * from @old and setting them in @new. Both @old and @new can be NULL.
4732 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
4733 struct drm_i915_gem_object
*new,
4734 unsigned frontbuffer_bits
)
4736 /* Control of individual bits within the mask are guarded by
4737 * the owning plane->mutex, i.e. we can never see concurrent
4738 * manipulation of individual bits. But since the bitfield as a whole
4739 * is updated using RMW, we need to use atomics in order to update
4742 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
4743 sizeof(atomic_t
) * BITS_PER_BYTE
);
4746 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
4747 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
4751 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
4752 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
4756 /* Allocate a new GEM object and fill it with the supplied data */
4757 struct drm_i915_gem_object
*
4758 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
4759 const void *data
, size_t size
)
4761 struct drm_i915_gem_object
*obj
;
4762 struct sg_table
*sg
;
4766 obj
= i915_gem_object_create(dev_priv
, round_up(size
, PAGE_SIZE
));
4770 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
4774 ret
= i915_gem_object_pin_pages(obj
);
4779 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
4780 obj
->mm
.dirty
= true; /* Backing store is now out of date */
4781 i915_gem_object_unpin_pages(obj
);
4783 if (WARN_ON(bytes
!= size
)) {
4784 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
4792 i915_gem_object_put(obj
);
4793 return ERR_PTR(ret
);
4796 struct scatterlist
*
4797 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
4799 unsigned int *offset
)
4801 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
4802 struct scatterlist
*sg
;
4803 unsigned int idx
, count
;
4806 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
4807 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
4809 /* As we iterate forward through the sg, we record each entry in a
4810 * radixtree for quick repeated (backwards) lookups. If we have seen
4811 * this index previously, we will have an entry for it.
4813 * Initial lookup is O(N), but this is amortized to O(1) for
4814 * sequential page access (where each new request is consecutive
4815 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4816 * i.e. O(1) with a large constant!
4818 if (n
< READ_ONCE(iter
->sg_idx
))
4821 mutex_lock(&iter
->lock
);
4823 /* We prefer to reuse the last sg so that repeated lookup of this
4824 * (or the subsequent) sg are fast - comparing against the last
4825 * sg is faster than going through the radixtree.
4830 count
= __sg_page_count(sg
);
4832 while (idx
+ count
<= n
) {
4833 unsigned long exception
, i
;
4836 /* If we cannot allocate and insert this entry, or the
4837 * individual pages from this range, cancel updating the
4838 * sg_idx so that on this lookup we are forced to linearly
4839 * scan onwards, but on future lookups we will try the
4840 * insertion again (in which case we need to be careful of
4841 * the error return reporting that we have already inserted
4844 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
4845 if (ret
&& ret
!= -EEXIST
)
4849 RADIX_TREE_EXCEPTIONAL_ENTRY
|
4850 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
4851 for (i
= 1; i
< count
; i
++) {
4852 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
4854 if (ret
&& ret
!= -EEXIST
)
4859 sg
= ____sg_next(sg
);
4860 count
= __sg_page_count(sg
);
4867 mutex_unlock(&iter
->lock
);
4869 if (unlikely(n
< idx
)) /* insertion completed by another thread */
4872 /* In case we failed to insert the entry into the radixtree, we need
4873 * to look beyond the current sg.
4875 while (idx
+ count
<= n
) {
4877 sg
= ____sg_next(sg
);
4878 count
= __sg_page_count(sg
);
4887 sg
= radix_tree_lookup(&iter
->radix
, n
);
4890 /* If this index is in the middle of multi-page sg entry,
4891 * the radixtree will contain an exceptional entry that points
4892 * to the start of that range. We will return the pointer to
4893 * the base page and the offset of this page within the
4897 if (unlikely(radix_tree_exception(sg
))) {
4898 unsigned long base
=
4899 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
4901 sg
= radix_tree_lookup(&iter
->radix
, base
);
4913 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
4915 struct scatterlist
*sg
;
4916 unsigned int offset
;
4918 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
4920 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4921 return nth_page(sg_page(sg
), offset
);
4924 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4926 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
4931 page
= i915_gem_object_get_page(obj
, n
);
4933 set_page_dirty(page
);
4939 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
4942 struct scatterlist
*sg
;
4943 unsigned int offset
;
4945 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4946 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);