2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct i915_gtt
*ggtt
= &dev_priv
->gtt
;
153 struct i915_vma
*vma
;
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(vma
, &ggtt
->base
.active_list
, mm_list
)
160 pinned
+= vma
->node
.size
;
161 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, mm_list
)
163 pinned
+= vma
->node
.size
;
164 mutex_unlock(&dev
->struct_mutex
);
166 args
->aper_size
= dev_priv
->gtt
.base
.total
;
167 args
->aper_available_size
= args
->aper_size
- pinned
;
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
175 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
176 char *vaddr
= obj
->phys_handle
->vaddr
;
178 struct scatterlist
*sg
;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
188 page
= shmem_read_mapping_page(mapping
, i
);
190 return PTR_ERR(page
);
192 src
= kmap_atomic(page
);
193 memcpy(vaddr
, src
, PAGE_SIZE
);
194 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
197 page_cache_release(page
);
201 i915_gem_chipset_flush(obj
->base
.dev
);
203 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
207 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
214 sg
->length
= obj
->base
.size
;
216 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
217 sg_dma_len(sg
) = obj
->base
.size
;
224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
228 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
230 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
232 /* In the event of a disaster, abandon all caches and
235 WARN_ON(ret
!= -EIO
);
236 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
239 if (obj
->madv
== I915_MADV_DONTNEED
)
243 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
244 char *vaddr
= obj
->phys_handle
->vaddr
;
247 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
251 page
= shmem_read_mapping_page(mapping
, i
);
255 dst
= kmap_atomic(page
);
256 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
257 memcpy(dst
, vaddr
, PAGE_SIZE
);
260 set_page_dirty(page
);
261 if (obj
->madv
== I915_MADV_WILLNEED
)
262 mark_page_accessed(page
);
263 page_cache_release(page
);
269 sg_free_table(obj
->pages
);
274 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
276 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
279 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
280 .get_pages
= i915_gem_object_get_pages_phys
,
281 .put_pages
= i915_gem_object_put_pages_phys
,
282 .release
= i915_gem_object_release_phys
,
286 drop_pages(struct drm_i915_gem_object
*obj
)
288 struct i915_vma
*vma
, *next
;
291 drm_gem_object_reference(&obj
->base
);
292 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
293 if (i915_vma_unbind(vma
))
296 ret
= i915_gem_object_put_pages(obj
);
297 drm_gem_object_unreference(&obj
->base
);
303 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
306 drm_dma_handle_t
*phys
;
309 if (obj
->phys_handle
) {
310 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
316 if (obj
->madv
!= I915_MADV_WILLNEED
)
319 if (obj
->base
.filp
== NULL
)
322 ret
= drop_pages(obj
);
326 /* create a new object */
327 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
331 obj
->phys_handle
= phys
;
332 obj
->ops
= &i915_gem_phys_ops
;
334 return i915_gem_object_get_pages(obj
);
338 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
339 struct drm_i915_gem_pwrite
*args
,
340 struct drm_file
*file_priv
)
342 struct drm_device
*dev
= obj
->base
.dev
;
343 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
344 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
347 /* We manually control the domain here and pretend that it
348 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
350 ret
= i915_gem_object_wait_rendering(obj
, false);
354 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
355 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
356 unsigned long unwritten
;
358 /* The physical object once assigned is fixed for the lifetime
359 * of the obj, so we can safely drop the lock and continue
362 mutex_unlock(&dev
->struct_mutex
);
363 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
364 mutex_lock(&dev
->struct_mutex
);
371 drm_clflush_virt_range(vaddr
, args
->size
);
372 i915_gem_chipset_flush(dev
);
375 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
379 void *i915_gem_object_alloc(struct drm_device
*dev
)
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
382 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
385 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
387 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
388 kmem_cache_free(dev_priv
->objects
, obj
);
392 i915_gem_create(struct drm_file
*file
,
393 struct drm_device
*dev
,
397 struct drm_i915_gem_object
*obj
;
401 size
= roundup(size
, PAGE_SIZE
);
405 /* Allocate the new object */
406 obj
= i915_gem_alloc_object(dev
, size
);
410 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
411 /* drop reference from allocate - handle holds it now */
412 drm_gem_object_unreference_unlocked(&obj
->base
);
421 i915_gem_dumb_create(struct drm_file
*file
,
422 struct drm_device
*dev
,
423 struct drm_mode_create_dumb
*args
)
425 /* have to work out size/pitch and return them */
426 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
427 args
->size
= args
->pitch
* args
->height
;
428 return i915_gem_create(file
, dev
,
429 args
->size
, &args
->handle
);
433 * Creates a new mm object and returns a handle to it.
436 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
437 struct drm_file
*file
)
439 struct drm_i915_gem_create
*args
= data
;
441 return i915_gem_create(file
, dev
,
442 args
->size
, &args
->handle
);
446 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
447 const char *gpu_vaddr
, int gpu_offset
,
450 int ret
, cpu_offset
= 0;
453 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
454 int this_length
= min(cacheline_end
- gpu_offset
, length
);
455 int swizzled_gpu_offset
= gpu_offset
^ 64;
457 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
458 gpu_vaddr
+ swizzled_gpu_offset
,
463 cpu_offset
+= this_length
;
464 gpu_offset
+= this_length
;
465 length
-= this_length
;
472 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
473 const char __user
*cpu_vaddr
,
476 int ret
, cpu_offset
= 0;
479 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
480 int this_length
= min(cacheline_end
- gpu_offset
, length
);
481 int swizzled_gpu_offset
= gpu_offset
^ 64;
483 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
484 cpu_vaddr
+ cpu_offset
,
489 cpu_offset
+= this_length
;
490 gpu_offset
+= this_length
;
491 length
-= this_length
;
498 * Pins the specified object's pages and synchronizes the object with
499 * GPU accesses. Sets needs_clflush to non-zero if the caller should
500 * flush the object from the CPU cache.
502 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
512 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
513 /* If we're not in the cpu read domain, set ourself into the gtt
514 * read domain and manually flush cachelines (if required). This
515 * optimizes for the case when the gpu will dirty the data
516 * anyway again before the next pread happens. */
517 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
519 ret
= i915_gem_object_wait_rendering(obj
, true);
524 ret
= i915_gem_object_get_pages(obj
);
528 i915_gem_object_pin_pages(obj
);
533 /* Per-page copy function for the shmem pread fastpath.
534 * Flushes invalid cachelines before reading the target if
535 * needs_clflush is set. */
537 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
538 char __user
*user_data
,
539 bool page_do_bit17_swizzling
, bool needs_clflush
)
544 if (unlikely(page_do_bit17_swizzling
))
547 vaddr
= kmap_atomic(page
);
549 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
551 ret
= __copy_to_user_inatomic(user_data
,
552 vaddr
+ shmem_page_offset
,
554 kunmap_atomic(vaddr
);
556 return ret
? -EFAULT
: 0;
560 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
563 if (unlikely(swizzled
)) {
564 unsigned long start
= (unsigned long) addr
;
565 unsigned long end
= (unsigned long) addr
+ length
;
567 /* For swizzling simply ensure that we always flush both
568 * channels. Lame, but simple and it works. Swizzled
569 * pwrite/pread is far from a hotpath - current userspace
570 * doesn't use it at all. */
571 start
= round_down(start
, 128);
572 end
= round_up(end
, 128);
574 drm_clflush_virt_range((void *)start
, end
- start
);
576 drm_clflush_virt_range(addr
, length
);
581 /* Only difference to the fast-path function is that this can handle bit17
582 * and uses non-atomic copy and kmap functions. */
584 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
585 char __user
*user_data
,
586 bool page_do_bit17_swizzling
, bool needs_clflush
)
593 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
595 page_do_bit17_swizzling
);
597 if (page_do_bit17_swizzling
)
598 ret
= __copy_to_user_swizzled(user_data
,
599 vaddr
, shmem_page_offset
,
602 ret
= __copy_to_user(user_data
,
603 vaddr
+ shmem_page_offset
,
607 return ret
? - EFAULT
: 0;
611 i915_gem_shmem_pread(struct drm_device
*dev
,
612 struct drm_i915_gem_object
*obj
,
613 struct drm_i915_gem_pread
*args
,
614 struct drm_file
*file
)
616 char __user
*user_data
;
619 int shmem_page_offset
, page_length
, ret
= 0;
620 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
622 int needs_clflush
= 0;
623 struct sg_page_iter sg_iter
;
625 user_data
= to_user_ptr(args
->data_ptr
);
628 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
630 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
634 offset
= args
->offset
;
636 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
637 offset
>> PAGE_SHIFT
) {
638 struct page
*page
= sg_page_iter_page(&sg_iter
);
643 /* Operation in this page
645 * shmem_page_offset = offset within page in shmem file
646 * page_length = bytes to copy for this page
648 shmem_page_offset
= offset_in_page(offset
);
649 page_length
= remain
;
650 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
651 page_length
= PAGE_SIZE
- shmem_page_offset
;
653 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
654 (page_to_phys(page
) & (1 << 17)) != 0;
656 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
657 user_data
, page_do_bit17_swizzling
,
662 mutex_unlock(&dev
->struct_mutex
);
664 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
665 ret
= fault_in_multipages_writeable(user_data
, remain
);
666 /* Userspace is tricking us, but we've already clobbered
667 * its pages with the prefault and promised to write the
668 * data up to the first fault. Hence ignore any errors
669 * and just continue. */
674 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
675 user_data
, page_do_bit17_swizzling
,
678 mutex_lock(&dev
->struct_mutex
);
684 remain
-= page_length
;
685 user_data
+= page_length
;
686 offset
+= page_length
;
690 i915_gem_object_unpin_pages(obj
);
696 * Reads data from the object referenced by handle.
698 * On error, the contents of *data are undefined.
701 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
702 struct drm_file
*file
)
704 struct drm_i915_gem_pread
*args
= data
;
705 struct drm_i915_gem_object
*obj
;
711 if (!access_ok(VERIFY_WRITE
,
712 to_user_ptr(args
->data_ptr
),
716 ret
= i915_mutex_lock_interruptible(dev
);
720 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
721 if (&obj
->base
== NULL
) {
726 /* Bounds check source. */
727 if (args
->offset
> obj
->base
.size
||
728 args
->size
> obj
->base
.size
- args
->offset
) {
733 /* prime objects have no backing filp to GEM pread/pwrite
736 if (!obj
->base
.filp
) {
741 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
743 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
746 drm_gem_object_unreference(&obj
->base
);
748 mutex_unlock(&dev
->struct_mutex
);
752 /* This is the fast write path which cannot handle
753 * page faults in the source data
757 fast_user_write(struct io_mapping
*mapping
,
758 loff_t page_base
, int page_offset
,
759 char __user
*user_data
,
762 void __iomem
*vaddr_atomic
;
764 unsigned long unwritten
;
766 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
767 /* We can use the cpu mem copy function because this is X86. */
768 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
769 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
771 io_mapping_unmap_atomic(vaddr_atomic
);
776 * This is the fast pwrite path, where we copy the data directly from the
777 * user into the GTT, uncached.
780 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
781 struct drm_i915_gem_object
*obj
,
782 struct drm_i915_gem_pwrite
*args
,
783 struct drm_file
*file
)
785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
787 loff_t offset
, page_base
;
788 char __user
*user_data
;
789 int page_offset
, page_length
, ret
;
791 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
795 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
799 ret
= i915_gem_object_put_fence(obj
);
803 user_data
= to_user_ptr(args
->data_ptr
);
806 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
808 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
811 /* Operation in this page
813 * page_base = page offset within aperture
814 * page_offset = offset within page
815 * page_length = bytes to copy for this page
817 page_base
= offset
& PAGE_MASK
;
818 page_offset
= offset_in_page(offset
);
819 page_length
= remain
;
820 if ((page_offset
+ remain
) > PAGE_SIZE
)
821 page_length
= PAGE_SIZE
- page_offset
;
823 /* If we get a fault while copying data, then (presumably) our
824 * source page isn't available. Return the error and we'll
825 * retry in the slow path.
827 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
828 page_offset
, user_data
, page_length
)) {
833 remain
-= page_length
;
834 user_data
+= page_length
;
835 offset
+= page_length
;
839 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
841 i915_gem_object_ggtt_unpin(obj
);
846 /* Per-page copy function for the shmem pwrite fastpath.
847 * Flushes invalid cachelines before writing to the target if
848 * needs_clflush_before is set and flushes out any written cachelines after
849 * writing if needs_clflush is set. */
851 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
852 char __user
*user_data
,
853 bool page_do_bit17_swizzling
,
854 bool needs_clflush_before
,
855 bool needs_clflush_after
)
860 if (unlikely(page_do_bit17_swizzling
))
863 vaddr
= kmap_atomic(page
);
864 if (needs_clflush_before
)
865 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
867 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
868 user_data
, page_length
);
869 if (needs_clflush_after
)
870 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
872 kunmap_atomic(vaddr
);
874 return ret
? -EFAULT
: 0;
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
881 char __user
*user_data
,
882 bool page_do_bit17_swizzling
,
883 bool needs_clflush_before
,
884 bool needs_clflush_after
)
890 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
891 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
893 page_do_bit17_swizzling
);
894 if (page_do_bit17_swizzling
)
895 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
899 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
902 if (needs_clflush_after
)
903 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
905 page_do_bit17_swizzling
);
908 return ret
? -EFAULT
: 0;
912 i915_gem_shmem_pwrite(struct drm_device
*dev
,
913 struct drm_i915_gem_object
*obj
,
914 struct drm_i915_gem_pwrite
*args
,
915 struct drm_file
*file
)
919 char __user
*user_data
;
920 int shmem_page_offset
, page_length
, ret
= 0;
921 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
922 int hit_slowpath
= 0;
923 int needs_clflush_after
= 0;
924 int needs_clflush_before
= 0;
925 struct sg_page_iter sg_iter
;
927 user_data
= to_user_ptr(args
->data_ptr
);
930 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
932 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
933 /* If we're not in the cpu write domain, set ourself into the gtt
934 * write domain and manually flush cachelines (if required). This
935 * optimizes for the case when the gpu will use the data
936 * right away and we therefore have to clflush anyway. */
937 needs_clflush_after
= cpu_write_needs_clflush(obj
);
938 ret
= i915_gem_object_wait_rendering(obj
, false);
942 /* Same trick applies to invalidate partially written cachelines read
944 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
945 needs_clflush_before
=
946 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
948 ret
= i915_gem_object_get_pages(obj
);
952 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
954 i915_gem_object_pin_pages(obj
);
956 offset
= args
->offset
;
959 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
960 offset
>> PAGE_SHIFT
) {
961 struct page
*page
= sg_page_iter_page(&sg_iter
);
962 int partial_cacheline_write
;
967 /* Operation in this page
969 * shmem_page_offset = offset within page in shmem file
970 * page_length = bytes to copy for this page
972 shmem_page_offset
= offset_in_page(offset
);
974 page_length
= remain
;
975 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
976 page_length
= PAGE_SIZE
- shmem_page_offset
;
978 /* If we don't overwrite a cacheline completely we need to be
979 * careful to have up-to-date data by first clflushing. Don't
980 * overcomplicate things and flush the entire patch. */
981 partial_cacheline_write
= needs_clflush_before
&&
982 ((shmem_page_offset
| page_length
)
983 & (boot_cpu_data
.x86_clflush_size
- 1));
985 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
986 (page_to_phys(page
) & (1 << 17)) != 0;
988 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
989 user_data
, page_do_bit17_swizzling
,
990 partial_cacheline_write
,
991 needs_clflush_after
);
996 mutex_unlock(&dev
->struct_mutex
);
997 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
998 user_data
, page_do_bit17_swizzling
,
999 partial_cacheline_write
,
1000 needs_clflush_after
);
1002 mutex_lock(&dev
->struct_mutex
);
1008 remain
-= page_length
;
1009 user_data
+= page_length
;
1010 offset
+= page_length
;
1014 i915_gem_object_unpin_pages(obj
);
1018 * Fixup: Flush cpu caches in case we didn't flush the dirty
1019 * cachelines in-line while writing and the object moved
1020 * out of the cpu write domain while we've dropped the lock.
1022 if (!needs_clflush_after
&&
1023 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1024 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1025 i915_gem_chipset_flush(dev
);
1029 if (needs_clflush_after
)
1030 i915_gem_chipset_flush(dev
);
1032 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1037 * Writes data to the object referenced by handle.
1039 * On error, the contents of the buffer that were to be modified are undefined.
1042 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1043 struct drm_file
*file
)
1045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1046 struct drm_i915_gem_pwrite
*args
= data
;
1047 struct drm_i915_gem_object
*obj
;
1050 if (args
->size
== 0)
1053 if (!access_ok(VERIFY_READ
,
1054 to_user_ptr(args
->data_ptr
),
1058 if (likely(!i915
.prefault_disable
)) {
1059 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1065 intel_runtime_pm_get(dev_priv
);
1067 ret
= i915_mutex_lock_interruptible(dev
);
1071 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1072 if (&obj
->base
== NULL
) {
1077 /* Bounds check destination. */
1078 if (args
->offset
> obj
->base
.size
||
1079 args
->size
> obj
->base
.size
- args
->offset
) {
1084 /* prime objects have no backing filp to GEM pread/pwrite
1087 if (!obj
->base
.filp
) {
1092 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1095 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1096 * it would end up going through the fenced access, and we'll get
1097 * different detiling behavior between reading and writing.
1098 * pread/pwrite currently are reading and writing from the CPU
1099 * perspective, requiring manual detiling by the client.
1101 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1102 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1103 cpu_write_needs_clflush(obj
)) {
1104 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1105 /* Note that the gtt paths might fail with non-page-backed user
1106 * pointers (e.g. gtt mappings when moving data between
1107 * textures). Fallback to the shmem path in that case. */
1110 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1111 if (obj
->phys_handle
)
1112 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1114 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1118 drm_gem_object_unreference(&obj
->base
);
1120 mutex_unlock(&dev
->struct_mutex
);
1122 intel_runtime_pm_put(dev_priv
);
1128 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1131 if (i915_reset_in_progress(error
)) {
1132 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133 * -EIO unconditionally for these. */
1137 /* Recovery complete, but the reset failed ... */
1138 if (i915_terminally_wedged(error
))
1142 * Check if GPU Reset is in progress - we need intel_ring_begin
1143 * to work properly to reinit the hw state while the gpu is
1144 * still marked as reset-in-progress. Handle this with a flag.
1146 if (!error
->reload_in_reset
)
1153 static void fake_irq(unsigned long data
)
1155 wake_up_process((struct task_struct
*)data
);
1158 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1159 struct intel_engine_cs
*ring
)
1161 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1164 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1166 unsigned long timeout
;
1168 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1171 timeout
= jiffies
+ 1;
1172 while (!need_resched()) {
1173 if (i915_gem_request_completed(req
, true))
1176 if (time_after_eq(jiffies
, timeout
))
1179 cpu_relax_lowlatency();
1181 if (i915_gem_request_completed(req
, false))
1188 * __i915_wait_request - wait until execution of request has finished
1190 * @reset_counter: reset sequence associated with the given request
1191 * @interruptible: do an interruptible wait (normally yes)
1192 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1194 * Note: It is of utmost importance that the passed in seqno and reset_counter
1195 * values have been read by the caller in an smp safe manner. Where read-side
1196 * locks are involved, it is sufficient to read the reset_counter before
1197 * unlocking the lock that protects the seqno. For lockless tricks, the
1198 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1201 * Returns 0 if the request was found within the alloted time. Else returns the
1202 * errno with remaining time filled in timeout argument.
1204 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1205 unsigned reset_counter
,
1208 struct intel_rps_client
*rps
)
1210 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1211 struct drm_device
*dev
= ring
->dev
;
1212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1213 const bool irq_test_in_progress
=
1214 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1216 unsigned long timeout_expire
;
1220 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1222 if (list_empty(&req
->list
))
1225 if (i915_gem_request_completed(req
, true))
1228 timeout_expire
= timeout
?
1229 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1231 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1232 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1234 /* Record current time in case interrupted by signal, or wedged */
1235 trace_i915_gem_request_wait_begin(req
);
1236 before
= ktime_get_raw_ns();
1238 /* Optimistic spin for the next jiffie before touching IRQs */
1239 ret
= __i915_spin_request(req
);
1243 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1249 struct timer_list timer
;
1251 prepare_to_wait(&ring
->irq_queue
, &wait
,
1252 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1254 /* We need to check whether any gpu reset happened in between
1255 * the caller grabbing the seqno and now ... */
1256 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1257 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1258 * is truely gone. */
1259 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1265 if (i915_gem_request_completed(req
, false)) {
1270 if (interruptible
&& signal_pending(current
)) {
1275 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1280 timer
.function
= NULL
;
1281 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1282 unsigned long expire
;
1284 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1285 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1286 mod_timer(&timer
, expire
);
1291 if (timer
.function
) {
1292 del_singleshot_timer_sync(&timer
);
1293 destroy_timer_on_stack(&timer
);
1296 if (!irq_test_in_progress
)
1297 ring
->irq_put(ring
);
1299 finish_wait(&ring
->irq_queue
, &wait
);
1302 now
= ktime_get_raw_ns();
1303 trace_i915_gem_request_wait_end(req
);
1306 s64 tres
= *timeout
- (now
- before
);
1308 *timeout
= tres
< 0 ? 0 : tres
;
1311 * Apparently ktime isn't accurate enough and occasionally has a
1312 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1313 * things up to make the test happy. We allow up to 1 jiffy.
1315 * This is a regrssion from the timespec->ktime conversion.
1317 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1324 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1325 struct drm_file
*file
)
1327 struct drm_i915_private
*dev_private
;
1328 struct drm_i915_file_private
*file_priv
;
1330 WARN_ON(!req
|| !file
|| req
->file_priv
);
1338 dev_private
= req
->ring
->dev
->dev_private
;
1339 file_priv
= file
->driver_priv
;
1341 spin_lock(&file_priv
->mm
.lock
);
1342 req
->file_priv
= file_priv
;
1343 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1344 spin_unlock(&file_priv
->mm
.lock
);
1346 req
->pid
= get_pid(task_pid(current
));
1352 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1354 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1359 spin_lock(&file_priv
->mm
.lock
);
1360 list_del(&request
->client_list
);
1361 request
->file_priv
= NULL
;
1362 spin_unlock(&file_priv
->mm
.lock
);
1364 put_pid(request
->pid
);
1365 request
->pid
= NULL
;
1368 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1370 trace_i915_gem_request_retire(request
);
1372 /* We know the GPU must have read the request to have
1373 * sent us the seqno + interrupt, so use the position
1374 * of tail of the request to update the last known position
1377 * Note this requires that we are always called in request
1380 request
->ringbuf
->last_retired_head
= request
->postfix
;
1382 list_del_init(&request
->list
);
1383 i915_gem_request_remove_from_client(request
);
1385 i915_gem_request_unreference(request
);
1389 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1391 struct intel_engine_cs
*engine
= req
->ring
;
1392 struct drm_i915_gem_request
*tmp
;
1394 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1396 if (list_empty(&req
->list
))
1400 tmp
= list_first_entry(&engine
->request_list
,
1401 typeof(*tmp
), list
);
1403 i915_gem_request_retire(tmp
);
1404 } while (tmp
!= req
);
1406 WARN_ON(i915_verify_lists(engine
->dev
));
1410 * Waits for a request to be signaled, and cleans up the
1411 * request and object lists appropriately for that event.
1414 i915_wait_request(struct drm_i915_gem_request
*req
)
1416 struct drm_device
*dev
;
1417 struct drm_i915_private
*dev_priv
;
1421 BUG_ON(req
== NULL
);
1423 dev
= req
->ring
->dev
;
1424 dev_priv
= dev
->dev_private
;
1425 interruptible
= dev_priv
->mm
.interruptible
;
1427 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1429 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1433 ret
= __i915_wait_request(req
,
1434 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1435 interruptible
, NULL
, NULL
);
1439 __i915_gem_request_retire__upto(req
);
1444 * Ensures that all rendering to the object has completed and the object is
1445 * safe to unbind from the GTT or access from the CPU.
1448 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1457 if (obj
->last_write_req
!= NULL
) {
1458 ret
= i915_wait_request(obj
->last_write_req
);
1462 i
= obj
->last_write_req
->ring
->id
;
1463 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1464 i915_gem_object_retire__read(obj
, i
);
1466 i915_gem_object_retire__write(obj
);
1469 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1470 if (obj
->last_read_req
[i
] == NULL
)
1473 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1477 i915_gem_object_retire__read(obj
, i
);
1479 RQ_BUG_ON(obj
->active
);
1486 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1487 struct drm_i915_gem_request
*req
)
1489 int ring
= req
->ring
->id
;
1491 if (obj
->last_read_req
[ring
] == req
)
1492 i915_gem_object_retire__read(obj
, ring
);
1493 else if (obj
->last_write_req
== req
)
1494 i915_gem_object_retire__write(obj
);
1496 __i915_gem_request_retire__upto(req
);
1499 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1500 * as the object state may change during this call.
1502 static __must_check
int
1503 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1504 struct intel_rps_client
*rps
,
1507 struct drm_device
*dev
= obj
->base
.dev
;
1508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1509 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1510 unsigned reset_counter
;
1513 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1514 BUG_ON(!dev_priv
->mm
.interruptible
);
1519 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1523 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1526 struct drm_i915_gem_request
*req
;
1528 req
= obj
->last_write_req
;
1532 requests
[n
++] = i915_gem_request_reference(req
);
1534 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1535 struct drm_i915_gem_request
*req
;
1537 req
= obj
->last_read_req
[i
];
1541 requests
[n
++] = i915_gem_request_reference(req
);
1545 mutex_unlock(&dev
->struct_mutex
);
1546 for (i
= 0; ret
== 0 && i
< n
; i
++)
1547 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1549 mutex_lock(&dev
->struct_mutex
);
1551 for (i
= 0; i
< n
; i
++) {
1553 i915_gem_object_retire_request(obj
, requests
[i
]);
1554 i915_gem_request_unreference(requests
[i
]);
1560 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1562 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1567 * Called when user space prepares to use an object with the CPU, either
1568 * through the mmap ioctl's mapping or a GTT mapping.
1571 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1572 struct drm_file
*file
)
1574 struct drm_i915_gem_set_domain
*args
= data
;
1575 struct drm_i915_gem_object
*obj
;
1576 uint32_t read_domains
= args
->read_domains
;
1577 uint32_t write_domain
= args
->write_domain
;
1580 /* Only handle setting domains to types used by the CPU. */
1581 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1584 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1587 /* Having something in the write domain implies it's in the read
1588 * domain, and only that read domain. Enforce that in the request.
1590 if (write_domain
!= 0 && read_domains
!= write_domain
)
1593 ret
= i915_mutex_lock_interruptible(dev
);
1597 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1598 if (&obj
->base
== NULL
) {
1603 /* Try to flush the object off the GPU without holding the lock.
1604 * We will repeat the flush holding the lock in the normal manner
1605 * to catch cases where we are gazumped.
1607 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1608 to_rps_client(file
),
1613 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1614 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1616 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1618 if (write_domain
!= 0)
1619 intel_fb_obj_invalidate(obj
,
1620 write_domain
== I915_GEM_DOMAIN_GTT
?
1621 ORIGIN_GTT
: ORIGIN_CPU
);
1624 drm_gem_object_unreference(&obj
->base
);
1626 mutex_unlock(&dev
->struct_mutex
);
1631 * Called when user space has done writes to this buffer
1634 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1635 struct drm_file
*file
)
1637 struct drm_i915_gem_sw_finish
*args
= data
;
1638 struct drm_i915_gem_object
*obj
;
1641 ret
= i915_mutex_lock_interruptible(dev
);
1645 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1646 if (&obj
->base
== NULL
) {
1651 /* Pinned buffers may be scanout, so flush the cache */
1652 if (obj
->pin_display
)
1653 i915_gem_object_flush_cpu_write_domain(obj
);
1655 drm_gem_object_unreference(&obj
->base
);
1657 mutex_unlock(&dev
->struct_mutex
);
1662 * Maps the contents of an object, returning the address it is mapped
1665 * While the mapping holds a reference on the contents of the object, it doesn't
1666 * imply a ref on the object itself.
1670 * DRM driver writers who look a this function as an example for how to do GEM
1671 * mmap support, please don't implement mmap support like here. The modern way
1672 * to implement DRM mmap support is with an mmap offset ioctl (like
1673 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1674 * That way debug tooling like valgrind will understand what's going on, hiding
1675 * the mmap call in a driver private ioctl will break that. The i915 driver only
1676 * does cpu mmaps this way because we didn't know better.
1679 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1680 struct drm_file
*file
)
1682 struct drm_i915_gem_mmap
*args
= data
;
1683 struct drm_gem_object
*obj
;
1686 if (args
->flags
& ~(I915_MMAP_WC
))
1689 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1692 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1696 /* prime objects have no backing filp to GEM mmap
1700 drm_gem_object_unreference_unlocked(obj
);
1704 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1705 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1707 if (args
->flags
& I915_MMAP_WC
) {
1708 struct mm_struct
*mm
= current
->mm
;
1709 struct vm_area_struct
*vma
;
1711 down_write(&mm
->mmap_sem
);
1712 vma
= find_vma(mm
, addr
);
1715 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1718 up_write(&mm
->mmap_sem
);
1720 drm_gem_object_unreference_unlocked(obj
);
1721 if (IS_ERR((void *)addr
))
1724 args
->addr_ptr
= (uint64_t) addr
;
1730 * i915_gem_fault - fault a page into the GTT
1731 * vma: VMA in question
1734 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1735 * from userspace. The fault handler takes care of binding the object to
1736 * the GTT (if needed), allocating and programming a fence register (again,
1737 * only if needed based on whether the old reg is still valid or the object
1738 * is tiled) and inserting a new PTE into the faulting process.
1740 * Note that the faulting process may involve evicting existing objects
1741 * from the GTT and/or fence registers to make room. So performance may
1742 * suffer if the GTT working set is large or there are few fence registers
1745 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1747 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1748 struct drm_device
*dev
= obj
->base
.dev
;
1749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1750 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1751 pgoff_t page_offset
;
1754 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1756 intel_runtime_pm_get(dev_priv
);
1758 /* We don't use vmf->pgoff since that has the fake offset */
1759 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1762 ret
= i915_mutex_lock_interruptible(dev
);
1766 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1768 /* Try to flush the object off the GPU first without holding the lock.
1769 * Upon reacquiring the lock, we will perform our sanity checks and then
1770 * repeat the flush holding the lock in the normal manner to catch cases
1771 * where we are gazumped.
1773 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1777 /* Access to snoopable pages through the GTT is incoherent. */
1778 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1783 /* Use a partial view if the object is bigger than the aperture. */
1784 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1785 obj
->tiling_mode
== I915_TILING_NONE
) {
1786 static const unsigned int chunk_size
= 256; // 1 MiB
1788 memset(&view
, 0, sizeof(view
));
1789 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1790 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1791 view
.params
.partial
.size
=
1794 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1795 view
.params
.partial
.offset
);
1798 /* Now pin it into the GTT if needed */
1799 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1803 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1807 ret
= i915_gem_object_get_fence(obj
);
1811 /* Finally, remap it using the new GTT offset */
1812 pfn
= dev_priv
->gtt
.mappable_base
+
1813 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1816 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1817 /* Overriding existing pages in partial view does not cause
1818 * us any trouble as TLBs are still valid because the fault
1819 * is due to userspace losing part of the mapping or never
1820 * having accessed it before (at this partials' range).
1822 unsigned long base
= vma
->vm_start
+
1823 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1826 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1827 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1832 obj
->fault_mappable
= true;
1834 if (!obj
->fault_mappable
) {
1835 unsigned long size
= min_t(unsigned long,
1836 vma
->vm_end
- vma
->vm_start
,
1840 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1841 ret
= vm_insert_pfn(vma
,
1842 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1848 obj
->fault_mappable
= true;
1850 ret
= vm_insert_pfn(vma
,
1851 (unsigned long)vmf
->virtual_address
,
1855 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1857 mutex_unlock(&dev
->struct_mutex
);
1862 * We eat errors when the gpu is terminally wedged to avoid
1863 * userspace unduly crashing (gl has no provisions for mmaps to
1864 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1865 * and so needs to be reported.
1867 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1868 ret
= VM_FAULT_SIGBUS
;
1873 * EAGAIN means the gpu is hung and we'll wait for the error
1874 * handler to reset everything when re-faulting in
1875 * i915_mutex_lock_interruptible.
1882 * EBUSY is ok: this just means that another thread
1883 * already did the job.
1885 ret
= VM_FAULT_NOPAGE
;
1892 ret
= VM_FAULT_SIGBUS
;
1895 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1896 ret
= VM_FAULT_SIGBUS
;
1900 intel_runtime_pm_put(dev_priv
);
1905 * i915_gem_release_mmap - remove physical page mappings
1906 * @obj: obj in question
1908 * Preserve the reservation of the mmapping with the DRM core code, but
1909 * relinquish ownership of the pages back to the system.
1911 * It is vital that we remove the page mapping if we have mapped a tiled
1912 * object through the GTT and then lose the fence register due to
1913 * resource pressure. Similarly if the object has been moved out of the
1914 * aperture, than pages mapped into userspace must be revoked. Removing the
1915 * mapping will then trigger a page fault on the next user access, allowing
1916 * fixup by i915_gem_fault().
1919 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1921 if (!obj
->fault_mappable
)
1924 drm_vma_node_unmap(&obj
->base
.vma_node
,
1925 obj
->base
.dev
->anon_inode
->i_mapping
);
1926 obj
->fault_mappable
= false;
1930 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1932 struct drm_i915_gem_object
*obj
;
1934 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1935 i915_gem_release_mmap(obj
);
1939 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1943 if (INTEL_INFO(dev
)->gen
>= 4 ||
1944 tiling_mode
== I915_TILING_NONE
)
1947 /* Previous chips need a power-of-two fence region when tiling */
1948 if (INTEL_INFO(dev
)->gen
== 3)
1949 gtt_size
= 1024*1024;
1951 gtt_size
= 512*1024;
1953 while (gtt_size
< size
)
1960 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1961 * @obj: object to check
1963 * Return the required GTT alignment for an object, taking into account
1964 * potential fence register mapping.
1967 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1968 int tiling_mode
, bool fenced
)
1971 * Minimum alignment is 4k (GTT page size), but might be greater
1972 * if a fence register is needed for the object.
1974 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1975 tiling_mode
== I915_TILING_NONE
)
1979 * Previous chips need to be aligned to the size of the smallest
1980 * fence register that can contain the object.
1982 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1985 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1987 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1990 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1993 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1995 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1999 /* Badly fragmented mmap space? The only way we can recover
2000 * space is by destroying unwanted objects. We can't randomly release
2001 * mmap_offsets as userspace expects them to be persistent for the
2002 * lifetime of the objects. The closest we can is to release the
2003 * offsets on purgeable objects by truncating it and marking it purged,
2004 * which prevents userspace from ever using that object again.
2006 i915_gem_shrink(dev_priv
,
2007 obj
->base
.size
>> PAGE_SHIFT
,
2009 I915_SHRINK_UNBOUND
|
2010 I915_SHRINK_PURGEABLE
);
2011 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2015 i915_gem_shrink_all(dev_priv
);
2016 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2018 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2023 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2025 drm_gem_free_mmap_offset(&obj
->base
);
2029 i915_gem_mmap_gtt(struct drm_file
*file
,
2030 struct drm_device
*dev
,
2034 struct drm_i915_gem_object
*obj
;
2037 ret
= i915_mutex_lock_interruptible(dev
);
2041 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2042 if (&obj
->base
== NULL
) {
2047 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2048 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2053 ret
= i915_gem_object_create_mmap_offset(obj
);
2057 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2060 drm_gem_object_unreference(&obj
->base
);
2062 mutex_unlock(&dev
->struct_mutex
);
2067 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2069 * @data: GTT mapping ioctl data
2070 * @file: GEM object info
2072 * Simply returns the fake offset to userspace so it can mmap it.
2073 * The mmap call will end up in drm_gem_mmap(), which will set things
2074 * up so we can get faults in the handler above.
2076 * The fault handler will take care of binding the object into the GTT
2077 * (since it may have been evicted to make room for something), allocating
2078 * a fence register, and mapping the appropriate aperture address into
2082 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2083 struct drm_file
*file
)
2085 struct drm_i915_gem_mmap_gtt
*args
= data
;
2087 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2090 /* Immediately discard the backing storage */
2092 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2094 i915_gem_object_free_mmap_offset(obj
);
2096 if (obj
->base
.filp
== NULL
)
2099 /* Our goal here is to return as much of the memory as
2100 * is possible back to the system as we are called from OOM.
2101 * To do this we must instruct the shmfs to drop all of its
2102 * backing pages, *now*.
2104 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2105 obj
->madv
= __I915_MADV_PURGED
;
2108 /* Try to discard unwanted pages */
2110 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2112 struct address_space
*mapping
;
2114 switch (obj
->madv
) {
2115 case I915_MADV_DONTNEED
:
2116 i915_gem_object_truncate(obj
);
2117 case __I915_MADV_PURGED
:
2121 if (obj
->base
.filp
== NULL
)
2124 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2125 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2129 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2131 struct sg_page_iter sg_iter
;
2134 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2136 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2138 /* In the event of a disaster, abandon all caches and
2139 * hope for the best.
2141 WARN_ON(ret
!= -EIO
);
2142 i915_gem_clflush_object(obj
, true);
2143 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2146 i915_gem_gtt_finish_object(obj
);
2148 if (i915_gem_object_needs_bit17_swizzle(obj
))
2149 i915_gem_object_save_bit_17_swizzle(obj
);
2151 if (obj
->madv
== I915_MADV_DONTNEED
)
2154 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2155 struct page
*page
= sg_page_iter_page(&sg_iter
);
2158 set_page_dirty(page
);
2160 if (obj
->madv
== I915_MADV_WILLNEED
)
2161 mark_page_accessed(page
);
2163 page_cache_release(page
);
2167 sg_free_table(obj
->pages
);
2172 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2174 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2176 if (obj
->pages
== NULL
)
2179 if (obj
->pages_pin_count
)
2182 BUG_ON(i915_gem_obj_bound_any(obj
));
2184 /* ->put_pages might need to allocate memory for the bit17 swizzle
2185 * array, hence protect them from being reaped by removing them from gtt
2187 list_del(&obj
->global_list
);
2189 ops
->put_pages(obj
);
2192 i915_gem_object_invalidate(obj
);
2198 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2200 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2202 struct address_space
*mapping
;
2203 struct sg_table
*st
;
2204 struct scatterlist
*sg
;
2205 struct sg_page_iter sg_iter
;
2207 unsigned long last_pfn
= 0; /* suppress gcc warning */
2211 /* Assert that the object is not currently in any GPU domain. As it
2212 * wasn't in the GTT, there shouldn't be any way it could have been in
2215 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2216 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2222 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2223 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2228 /* Get the list of pages out of our struct file. They'll be pinned
2229 * at this point until we release them.
2231 * Fail silently without starting the shrinker
2233 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2234 gfp
= mapping_gfp_mask(mapping
);
2235 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2236 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2239 for (i
= 0; i
< page_count
; i
++) {
2240 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2242 i915_gem_shrink(dev_priv
,
2245 I915_SHRINK_UNBOUND
|
2246 I915_SHRINK_PURGEABLE
);
2247 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2250 /* We've tried hard to allocate the memory by reaping
2251 * our own buffer, now let the real VM do its job and
2252 * go down in flames if truly OOM.
2254 i915_gem_shrink_all(dev_priv
);
2255 page
= shmem_read_mapping_page(mapping
, i
);
2257 ret
= PTR_ERR(page
);
2261 #ifdef CONFIG_SWIOTLB
2262 if (swiotlb_nr_tbl()) {
2264 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2269 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2273 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2275 sg
->length
+= PAGE_SIZE
;
2277 last_pfn
= page_to_pfn(page
);
2279 /* Check that the i965g/gm workaround works. */
2280 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2282 #ifdef CONFIG_SWIOTLB
2283 if (!swiotlb_nr_tbl())
2288 ret
= i915_gem_gtt_prepare_object(obj
);
2292 if (i915_gem_object_needs_bit17_swizzle(obj
))
2293 i915_gem_object_do_bit_17_swizzle(obj
);
2295 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2296 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2297 i915_gem_object_pin_pages(obj
);
2303 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2304 page_cache_release(sg_page_iter_page(&sg_iter
));
2308 /* shmemfs first checks if there is enough memory to allocate the page
2309 * and reports ENOSPC should there be insufficient, along with the usual
2310 * ENOMEM for a genuine allocation failure.
2312 * We use ENOSPC in our driver to mean that we have run out of aperture
2313 * space and so want to translate the error from shmemfs back to our
2314 * usual understanding of ENOMEM.
2322 /* Ensure that the associated pages are gathered from the backing storage
2323 * and pinned into our object. i915_gem_object_get_pages() may be called
2324 * multiple times before they are released by a single call to
2325 * i915_gem_object_put_pages() - once the pages are no longer referenced
2326 * either as a result of memory pressure (reaping pages under the shrinker)
2327 * or as the object is itself released.
2330 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2332 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2333 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2339 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2340 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2344 BUG_ON(obj
->pages_pin_count
);
2346 ret
= ops
->get_pages(obj
);
2350 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2352 obj
->get_page
.sg
= obj
->pages
->sgl
;
2353 obj
->get_page
.last
= 0;
2358 void i915_vma_move_to_active(struct i915_vma
*vma
,
2359 struct drm_i915_gem_request
*req
)
2361 struct drm_i915_gem_object
*obj
= vma
->obj
;
2362 struct intel_engine_cs
*ring
;
2364 ring
= i915_gem_request_get_ring(req
);
2366 /* Add a reference if we're newly entering the active list. */
2367 if (obj
->active
== 0)
2368 drm_gem_object_reference(&obj
->base
);
2369 obj
->active
|= intel_ring_flag(ring
);
2371 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2372 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2374 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2378 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2380 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2381 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2383 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2384 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2388 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2390 struct i915_vma
*vma
;
2392 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2393 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2395 list_del_init(&obj
->ring_list
[ring
]);
2396 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2398 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2399 i915_gem_object_retire__write(obj
);
2401 obj
->active
&= ~(1 << ring
);
2405 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2406 if (!list_empty(&vma
->mm_list
))
2407 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2410 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2411 drm_gem_object_unreference(&obj
->base
);
2415 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 struct intel_engine_cs
*ring
;
2421 /* Carefully retire all requests without writing to the rings */
2422 for_each_ring(ring
, dev_priv
, i
) {
2423 ret
= intel_ring_idle(ring
);
2427 i915_gem_retire_requests(dev
);
2429 /* Finally reset hw state */
2430 for_each_ring(ring
, dev_priv
, i
) {
2431 intel_ring_init_seqno(ring
, seqno
);
2433 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2434 ring
->semaphore
.sync_seqno
[j
] = 0;
2440 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2448 /* HWS page needs to be set less than what we
2449 * will inject to ring
2451 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2455 /* Carefully set the last_seqno value so that wrap
2456 * detection still works
2458 dev_priv
->next_seqno
= seqno
;
2459 dev_priv
->last_seqno
= seqno
- 1;
2460 if (dev_priv
->last_seqno
== 0)
2461 dev_priv
->last_seqno
--;
2467 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 /* reserve 0 for non-seqno */
2472 if (dev_priv
->next_seqno
== 0) {
2473 int ret
= i915_gem_init_seqno(dev
, 0);
2477 dev_priv
->next_seqno
= 1;
2480 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2485 * NB: This function is not allowed to fail. Doing so would mean the the
2486 * request is not being tracked for completion but the work itself is
2487 * going to happen on the hardware. This would be a Bad Thing(tm).
2489 void __i915_add_request(struct drm_i915_gem_request
*request
,
2490 struct drm_i915_gem_object
*obj
,
2493 struct intel_engine_cs
*ring
;
2494 struct drm_i915_private
*dev_priv
;
2495 struct intel_ringbuffer
*ringbuf
;
2499 if (WARN_ON(request
== NULL
))
2502 ring
= request
->ring
;
2503 dev_priv
= ring
->dev
->dev_private
;
2504 ringbuf
= request
->ringbuf
;
2507 * To ensure that this call will not fail, space for its emissions
2508 * should already have been reserved in the ring buffer. Let the ring
2509 * know that it is time to use that space up.
2511 intel_ring_reserved_space_use(ringbuf
);
2513 request_start
= intel_ring_get_tail(ringbuf
);
2515 * Emit any outstanding flushes - execbuf can fail to emit the flush
2516 * after having emitted the batchbuffer command. Hence we need to fix
2517 * things up similar to emitting the lazy request. The difference here
2518 * is that the flush _must_ happen before the next request, no matter
2522 if (i915
.enable_execlists
)
2523 ret
= logical_ring_flush_all_caches(request
);
2525 ret
= intel_ring_flush_all_caches(request
);
2526 /* Not allowed to fail! */
2527 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2530 /* Record the position of the start of the request so that
2531 * should we detect the updated seqno part-way through the
2532 * GPU processing the request, we never over-estimate the
2533 * position of the head.
2535 request
->postfix
= intel_ring_get_tail(ringbuf
);
2537 if (i915
.enable_execlists
)
2538 ret
= ring
->emit_request(request
);
2540 ret
= ring
->add_request(request
);
2542 request
->tail
= intel_ring_get_tail(ringbuf
);
2544 /* Not allowed to fail! */
2545 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2547 request
->head
= request_start
;
2549 /* Whilst this request exists, batch_obj will be on the
2550 * active_list, and so will hold the active reference. Only when this
2551 * request is retired will the the batch_obj be moved onto the
2552 * inactive_list and lose its active reference. Hence we do not need
2553 * to explicitly hold another reference here.
2555 request
->batch_obj
= obj
;
2557 request
->emitted_jiffies
= jiffies
;
2558 ring
->last_submitted_seqno
= request
->seqno
;
2559 list_add_tail(&request
->list
, &ring
->request_list
);
2561 trace_i915_gem_request_add(request
);
2563 i915_queue_hangcheck(ring
->dev
);
2565 queue_delayed_work(dev_priv
->wq
,
2566 &dev_priv
->mm
.retire_work
,
2567 round_jiffies_up_relative(HZ
));
2568 intel_mark_busy(dev_priv
->dev
);
2570 /* Sanity check that the reserved size was large enough. */
2571 intel_ring_reserved_space_end(ringbuf
);
2574 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2575 const struct intel_context
*ctx
)
2577 unsigned long elapsed
;
2579 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2581 if (ctx
->hang_stats
.banned
)
2584 if (ctx
->hang_stats
.ban_period_seconds
&&
2585 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2586 if (!i915_gem_context_is_default(ctx
)) {
2587 DRM_DEBUG("context hanging too fast, banning!\n");
2589 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2590 if (i915_stop_ring_allow_warn(dev_priv
))
2591 DRM_ERROR("gpu hanging too fast, banning!\n");
2599 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2600 struct intel_context
*ctx
,
2603 struct i915_ctx_hang_stats
*hs
;
2608 hs
= &ctx
->hang_stats
;
2611 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2613 hs
->guilty_ts
= get_seconds();
2615 hs
->batch_pending
++;
2619 void i915_gem_request_free(struct kref
*req_ref
)
2621 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2623 struct intel_context
*ctx
= req
->ctx
;
2626 i915_gem_request_remove_from_client(req
);
2629 if (i915
.enable_execlists
) {
2630 if (ctx
!= req
->ring
->default_context
)
2631 intel_lr_context_unpin(req
);
2634 i915_gem_context_unreference(ctx
);
2637 kmem_cache_free(req
->i915
->requests
, req
);
2640 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2641 struct intel_context
*ctx
,
2642 struct drm_i915_gem_request
**req_out
)
2644 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2645 struct drm_i915_gem_request
*req
;
2653 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2657 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2661 kref_init(&req
->ref
);
2662 req
->i915
= dev_priv
;
2665 i915_gem_context_reference(req
->ctx
);
2667 if (i915
.enable_execlists
)
2668 ret
= intel_logical_ring_alloc_request_extras(req
);
2670 ret
= intel_ring_alloc_request_extras(req
);
2672 i915_gem_context_unreference(req
->ctx
);
2677 * Reserve space in the ring buffer for all the commands required to
2678 * eventually emit this request. This is to guarantee that the
2679 * i915_add_request() call can't fail. Note that the reserve may need
2680 * to be redone if the request is not actually submitted straight
2681 * away, e.g. because a GPU scheduler has deferred it.
2683 if (i915
.enable_execlists
)
2684 ret
= intel_logical_ring_reserve_space(req
);
2686 ret
= intel_ring_reserve_space(req
);
2689 * At this point, the request is fully allocated even if not
2690 * fully prepared. Thus it can be cleaned up using the proper
2693 i915_gem_request_cancel(req
);
2701 kmem_cache_free(dev_priv
->requests
, req
);
2705 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2707 intel_ring_reserved_space_cancel(req
->ringbuf
);
2709 i915_gem_request_unreference(req
);
2712 struct drm_i915_gem_request
*
2713 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2715 struct drm_i915_gem_request
*request
;
2717 list_for_each_entry(request
, &ring
->request_list
, list
) {
2718 if (i915_gem_request_completed(request
, false))
2727 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2728 struct intel_engine_cs
*ring
)
2730 struct drm_i915_gem_request
*request
;
2733 request
= i915_gem_find_active_request(ring
);
2735 if (request
== NULL
)
2738 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2740 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2742 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2743 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2746 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2747 struct intel_engine_cs
*ring
)
2749 while (!list_empty(&ring
->active_list
)) {
2750 struct drm_i915_gem_object
*obj
;
2752 obj
= list_first_entry(&ring
->active_list
,
2753 struct drm_i915_gem_object
,
2754 ring_list
[ring
->id
]);
2756 i915_gem_object_retire__read(obj
, ring
->id
);
2760 * Clear the execlists queue up before freeing the requests, as those
2761 * are the ones that keep the context and ringbuffer backing objects
2764 while (!list_empty(&ring
->execlist_queue
)) {
2765 struct drm_i915_gem_request
*submit_req
;
2767 submit_req
= list_first_entry(&ring
->execlist_queue
,
2768 struct drm_i915_gem_request
,
2770 list_del(&submit_req
->execlist_link
);
2772 if (submit_req
->ctx
!= ring
->default_context
)
2773 intel_lr_context_unpin(submit_req
);
2775 i915_gem_request_unreference(submit_req
);
2779 * We must free the requests after all the corresponding objects have
2780 * been moved off active lists. Which is the same order as the normal
2781 * retire_requests function does. This is important if object hold
2782 * implicit references on things like e.g. ppgtt address spaces through
2785 while (!list_empty(&ring
->request_list
)) {
2786 struct drm_i915_gem_request
*request
;
2788 request
= list_first_entry(&ring
->request_list
,
2789 struct drm_i915_gem_request
,
2792 i915_gem_request_retire(request
);
2796 void i915_gem_restore_fences(struct drm_device
*dev
)
2798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2801 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2802 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2805 * Commit delayed tiling changes if we have an object still
2806 * attached to the fence, otherwise just clear the fence.
2809 i915_gem_object_update_fence(reg
->obj
, reg
,
2810 reg
->obj
->tiling_mode
);
2812 i915_gem_write_fence(dev
, i
, NULL
);
2817 void i915_gem_reset(struct drm_device
*dev
)
2819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 struct intel_engine_cs
*ring
;
2824 * Before we free the objects from the requests, we need to inspect
2825 * them for finding the guilty party. As the requests only borrow
2826 * their reference to the objects, the inspection must be done first.
2828 for_each_ring(ring
, dev_priv
, i
)
2829 i915_gem_reset_ring_status(dev_priv
, ring
);
2831 for_each_ring(ring
, dev_priv
, i
)
2832 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2834 i915_gem_context_reset(dev
);
2836 i915_gem_restore_fences(dev
);
2838 WARN_ON(i915_verify_lists(dev
));
2842 * This function clears the request list as sequence numbers are passed.
2845 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2847 WARN_ON(i915_verify_lists(ring
->dev
));
2849 /* Retire requests first as we use it above for the early return.
2850 * If we retire requests last, we may use a later seqno and so clear
2851 * the requests lists without clearing the active list, leading to
2854 while (!list_empty(&ring
->request_list
)) {
2855 struct drm_i915_gem_request
*request
;
2857 request
= list_first_entry(&ring
->request_list
,
2858 struct drm_i915_gem_request
,
2861 if (!i915_gem_request_completed(request
, true))
2864 i915_gem_request_retire(request
);
2867 /* Move any buffers on the active list that are no longer referenced
2868 * by the ringbuffer to the flushing/inactive lists as appropriate,
2869 * before we free the context associated with the requests.
2871 while (!list_empty(&ring
->active_list
)) {
2872 struct drm_i915_gem_object
*obj
;
2874 obj
= list_first_entry(&ring
->active_list
,
2875 struct drm_i915_gem_object
,
2876 ring_list
[ring
->id
]);
2878 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2881 i915_gem_object_retire__read(obj
, ring
->id
);
2884 if (unlikely(ring
->trace_irq_req
&&
2885 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2886 ring
->irq_put(ring
);
2887 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2890 WARN_ON(i915_verify_lists(ring
->dev
));
2894 i915_gem_retire_requests(struct drm_device
*dev
)
2896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2897 struct intel_engine_cs
*ring
;
2901 for_each_ring(ring
, dev_priv
, i
) {
2902 i915_gem_retire_requests_ring(ring
);
2903 idle
&= list_empty(&ring
->request_list
);
2904 if (i915
.enable_execlists
) {
2905 unsigned long flags
;
2907 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2908 idle
&= list_empty(&ring
->execlist_queue
);
2909 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2911 intel_execlists_retire_requests(ring
);
2916 mod_delayed_work(dev_priv
->wq
,
2917 &dev_priv
->mm
.idle_work
,
2918 msecs_to_jiffies(100));
2924 i915_gem_retire_work_handler(struct work_struct
*work
)
2926 struct drm_i915_private
*dev_priv
=
2927 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2928 struct drm_device
*dev
= dev_priv
->dev
;
2931 /* Come back later if the device is busy... */
2933 if (mutex_trylock(&dev
->struct_mutex
)) {
2934 idle
= i915_gem_retire_requests(dev
);
2935 mutex_unlock(&dev
->struct_mutex
);
2938 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2939 round_jiffies_up_relative(HZ
));
2943 i915_gem_idle_work_handler(struct work_struct
*work
)
2945 struct drm_i915_private
*dev_priv
=
2946 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2947 struct drm_device
*dev
= dev_priv
->dev
;
2948 struct intel_engine_cs
*ring
;
2951 for_each_ring(ring
, dev_priv
, i
)
2952 if (!list_empty(&ring
->request_list
))
2955 intel_mark_idle(dev
);
2957 if (mutex_trylock(&dev
->struct_mutex
)) {
2958 struct intel_engine_cs
*ring
;
2961 for_each_ring(ring
, dev_priv
, i
)
2962 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2964 mutex_unlock(&dev
->struct_mutex
);
2969 * Ensures that an object will eventually get non-busy by flushing any required
2970 * write domains, emitting any outstanding lazy request and retiring and
2971 * completed requests.
2974 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2981 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2982 struct drm_i915_gem_request
*req
;
2984 req
= obj
->last_read_req
[i
];
2988 if (list_empty(&req
->list
))
2991 if (i915_gem_request_completed(req
, true)) {
2992 __i915_gem_request_retire__upto(req
);
2994 i915_gem_object_retire__read(obj
, i
);
3002 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3003 * @DRM_IOCTL_ARGS: standard ioctl arguments
3005 * Returns 0 if successful, else an error is returned with the remaining time in
3006 * the timeout parameter.
3007 * -ETIME: object is still busy after timeout
3008 * -ERESTARTSYS: signal interrupted the wait
3009 * -ENONENT: object doesn't exist
3010 * Also possible, but rare:
3011 * -EAGAIN: GPU wedged
3013 * -ENODEV: Internal IRQ fail
3014 * -E?: The add request failed
3016 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3017 * non-zero timeout parameter the wait ioctl will wait for the given number of
3018 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3019 * without holding struct_mutex the object may become re-busied before this
3020 * function completes. A similar but shorter * race condition exists in the busy
3024 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3027 struct drm_i915_gem_wait
*args
= data
;
3028 struct drm_i915_gem_object
*obj
;
3029 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3030 unsigned reset_counter
;
3034 if (args
->flags
!= 0)
3037 ret
= i915_mutex_lock_interruptible(dev
);
3041 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3042 if (&obj
->base
== NULL
) {
3043 mutex_unlock(&dev
->struct_mutex
);
3047 /* Need to make sure the object gets inactive eventually. */
3048 ret
= i915_gem_object_flush_active(obj
);
3055 /* Do this after OLR check to make sure we make forward progress polling
3056 * on this IOCTL with a timeout == 0 (like busy ioctl)
3058 if (args
->timeout_ns
== 0) {
3063 drm_gem_object_unreference(&obj
->base
);
3064 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3066 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3067 if (obj
->last_read_req
[i
] == NULL
)
3070 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3073 mutex_unlock(&dev
->struct_mutex
);
3075 for (i
= 0; i
< n
; i
++) {
3077 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3078 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3080 i915_gem_request_unreference__unlocked(req
[i
]);
3085 drm_gem_object_unreference(&obj
->base
);
3086 mutex_unlock(&dev
->struct_mutex
);
3091 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3092 struct intel_engine_cs
*to
,
3093 struct drm_i915_gem_request
*from_req
,
3094 struct drm_i915_gem_request
**to_req
)
3096 struct intel_engine_cs
*from
;
3099 from
= i915_gem_request_get_ring(from_req
);
3103 if (i915_gem_request_completed(from_req
, true))
3106 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3107 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3108 ret
= __i915_wait_request(from_req
,
3109 atomic_read(&i915
->gpu_error
.reset_counter
),
3110 i915
->mm
.interruptible
,
3112 &i915
->rps
.semaphores
);
3116 i915_gem_object_retire_request(obj
, from_req
);
3118 int idx
= intel_ring_sync_index(from
, to
);
3119 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3123 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3126 if (*to_req
== NULL
) {
3127 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3132 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3133 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3137 /* We use last_read_req because sync_to()
3138 * might have just caused seqno wrap under
3141 from
->semaphore
.sync_seqno
[idx
] =
3142 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3149 * i915_gem_object_sync - sync an object to a ring.
3151 * @obj: object which may be in use on another ring.
3152 * @to: ring we wish to use the object on. May be NULL.
3153 * @to_req: request we wish to use the object for. See below.
3154 * This will be allocated and returned if a request is
3155 * required but not passed in.
3157 * This code is meant to abstract object synchronization with the GPU.
3158 * Calling with NULL implies synchronizing the object with the CPU
3159 * rather than a particular GPU ring. Conceptually we serialise writes
3160 * between engines inside the GPU. We only allow one engine to write
3161 * into a buffer at any time, but multiple readers. To ensure each has
3162 * a coherent view of memory, we must:
3164 * - If there is an outstanding write request to the object, the new
3165 * request must wait for it to complete (either CPU or in hw, requests
3166 * on the same ring will be naturally ordered).
3168 * - If we are a write request (pending_write_domain is set), the new
3169 * request must wait for outstanding read requests to complete.
3171 * For CPU synchronisation (NULL to) no request is required. For syncing with
3172 * rings to_req must be non-NULL. However, a request does not have to be
3173 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3174 * request will be allocated automatically and returned through *to_req. Note
3175 * that it is not guaranteed that commands will be emitted (because the system
3176 * might already be idle). Hence there is no need to create a request that
3177 * might never have any work submitted. Note further that if a request is
3178 * returned in *to_req, it is the responsibility of the caller to submit
3179 * that request (after potentially adding more work to it).
3181 * Returns 0 if successful, else propagates up the lower layer error.
3184 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3185 struct intel_engine_cs
*to
,
3186 struct drm_i915_gem_request
**to_req
)
3188 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3189 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3196 return i915_gem_object_wait_rendering(obj
, readonly
);
3200 if (obj
->last_write_req
)
3201 req
[n
++] = obj
->last_write_req
;
3203 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3204 if (obj
->last_read_req
[i
])
3205 req
[n
++] = obj
->last_read_req
[i
];
3207 for (i
= 0; i
< n
; i
++) {
3208 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3216 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3218 u32 old_write_domain
, old_read_domains
;
3220 /* Force a pagefault for domain tracking on next user access */
3221 i915_gem_release_mmap(obj
);
3223 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3226 /* Wait for any direct GTT access to complete */
3229 old_read_domains
= obj
->base
.read_domains
;
3230 old_write_domain
= obj
->base
.write_domain
;
3232 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3233 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3235 trace_i915_gem_object_change_domain(obj
,
3240 int i915_vma_unbind(struct i915_vma
*vma
)
3242 struct drm_i915_gem_object
*obj
= vma
->obj
;
3243 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3246 if (list_empty(&vma
->vma_link
))
3249 if (!drm_mm_node_allocated(&vma
->node
)) {
3250 i915_gem_vma_destroy(vma
);
3257 BUG_ON(obj
->pages
== NULL
);
3259 ret
= i915_gem_object_wait_rendering(obj
, false);
3262 /* Continue on if we fail due to EIO, the GPU is hung so we
3263 * should be safe and we need to cleanup or else we might
3264 * cause memory corruption through use-after-free.
3267 if (i915_is_ggtt(vma
->vm
) &&
3268 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3269 i915_gem_object_finish_gtt(obj
);
3271 /* release the fence reg _after_ flushing */
3272 ret
= i915_gem_object_put_fence(obj
);
3277 trace_i915_vma_unbind(vma
);
3279 vma
->vm
->unbind_vma(vma
);
3282 list_del_init(&vma
->mm_list
);
3283 if (i915_is_ggtt(vma
->vm
)) {
3284 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3285 obj
->map_and_fenceable
= false;
3286 } else if (vma
->ggtt_view
.pages
) {
3287 sg_free_table(vma
->ggtt_view
.pages
);
3288 kfree(vma
->ggtt_view
.pages
);
3290 vma
->ggtt_view
.pages
= NULL
;
3293 drm_mm_remove_node(&vma
->node
);
3294 i915_gem_vma_destroy(vma
);
3296 /* Since the unbound list is global, only move to that list if
3297 * no more VMAs exist. */
3298 if (list_empty(&obj
->vma_list
))
3299 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3301 /* And finally now the object is completely decoupled from this vma,
3302 * we can drop its hold on the backing storage and allow it to be
3303 * reaped by the shrinker.
3305 i915_gem_object_unpin_pages(obj
);
3310 int i915_gpu_idle(struct drm_device
*dev
)
3312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3313 struct intel_engine_cs
*ring
;
3316 /* Flush everything onto the inactive list. */
3317 for_each_ring(ring
, dev_priv
, i
) {
3318 if (!i915
.enable_execlists
) {
3319 struct drm_i915_gem_request
*req
;
3321 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3325 ret
= i915_switch_context(req
);
3327 i915_gem_request_cancel(req
);
3331 i915_add_request_no_flush(req
);
3334 ret
= intel_ring_idle(ring
);
3339 WARN_ON(i915_verify_lists(dev
));
3343 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3344 struct drm_i915_gem_object
*obj
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3348 int fence_pitch_shift
;
3350 if (INTEL_INFO(dev
)->gen
>= 6) {
3351 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3352 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3354 fence_reg
= FENCE_REG_965_0
;
3355 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3358 fence_reg
+= reg
* 8;
3360 /* To w/a incoherency with non-atomic 64-bit register updates,
3361 * we split the 64-bit update into two 32-bit writes. In order
3362 * for a partial fence not to be evaluated between writes, we
3363 * precede the update with write to turn off the fence register,
3364 * and only enable the fence as the last step.
3366 * For extra levels of paranoia, we make sure each step lands
3367 * before applying the next step.
3369 I915_WRITE(fence_reg
, 0);
3370 POSTING_READ(fence_reg
);
3373 u32 size
= i915_gem_obj_ggtt_size(obj
);
3376 /* Adjust fence size to match tiled area */
3377 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3378 uint32_t row_size
= obj
->stride
*
3379 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3380 size
= (size
/ row_size
) * row_size
;
3383 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3385 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3386 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3387 if (obj
->tiling_mode
== I915_TILING_Y
)
3388 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3389 val
|= I965_FENCE_REG_VALID
;
3391 I915_WRITE(fence_reg
+ 4, val
>> 32);
3392 POSTING_READ(fence_reg
+ 4);
3394 I915_WRITE(fence_reg
+ 0, val
);
3395 POSTING_READ(fence_reg
);
3397 I915_WRITE(fence_reg
+ 4, 0);
3398 POSTING_READ(fence_reg
+ 4);
3402 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3403 struct drm_i915_gem_object
*obj
)
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3409 u32 size
= i915_gem_obj_ggtt_size(obj
);
3413 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3414 (size
& -size
) != size
||
3415 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3416 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3417 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3419 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3424 /* Note: pitch better be a power of two tile widths */
3425 pitch_val
= obj
->stride
/ tile_width
;
3426 pitch_val
= ffs(pitch_val
) - 1;
3428 val
= i915_gem_obj_ggtt_offset(obj
);
3429 if (obj
->tiling_mode
== I915_TILING_Y
)
3430 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3431 val
|= I915_FENCE_SIZE_BITS(size
);
3432 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3433 val
|= I830_FENCE_REG_VALID
;
3438 reg
= FENCE_REG_830_0
+ reg
* 4;
3440 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3442 I915_WRITE(reg
, val
);
3446 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3447 struct drm_i915_gem_object
*obj
)
3449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3453 u32 size
= i915_gem_obj_ggtt_size(obj
);
3456 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3457 (size
& -size
) != size
||
3458 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3459 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3460 i915_gem_obj_ggtt_offset(obj
), size
);
3462 pitch_val
= obj
->stride
/ 128;
3463 pitch_val
= ffs(pitch_val
) - 1;
3465 val
= i915_gem_obj_ggtt_offset(obj
);
3466 if (obj
->tiling_mode
== I915_TILING_Y
)
3467 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3468 val
|= I830_FENCE_SIZE_BITS(size
);
3469 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3470 val
|= I830_FENCE_REG_VALID
;
3474 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3475 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3478 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3480 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3483 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3484 struct drm_i915_gem_object
*obj
)
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3488 /* Ensure that all CPU reads are completed before installing a fence
3489 * and all writes before removing the fence.
3491 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3494 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3495 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3496 obj
->stride
, obj
->tiling_mode
);
3499 i830_write_fence_reg(dev
, reg
, obj
);
3500 else if (IS_GEN3(dev
))
3501 i915_write_fence_reg(dev
, reg
, obj
);
3502 else if (INTEL_INFO(dev
)->gen
>= 4)
3503 i965_write_fence_reg(dev
, reg
, obj
);
3505 /* And similarly be paranoid that no direct access to this region
3506 * is reordered to before the fence is installed.
3508 if (i915_gem_object_needs_mb(obj
))
3512 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3513 struct drm_i915_fence_reg
*fence
)
3515 return fence
- dev_priv
->fence_regs
;
3518 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3519 struct drm_i915_fence_reg
*fence
,
3522 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3523 int reg
= fence_number(dev_priv
, fence
);
3525 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3528 obj
->fence_reg
= reg
;
3530 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3532 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3534 list_del_init(&fence
->lru_list
);
3536 obj
->fence_dirty
= false;
3540 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3542 if (obj
->last_fenced_req
) {
3543 int ret
= i915_wait_request(obj
->last_fenced_req
);
3547 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3554 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3556 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3557 struct drm_i915_fence_reg
*fence
;
3560 ret
= i915_gem_object_wait_fence(obj
);
3564 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3567 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3569 if (WARN_ON(fence
->pin_count
))
3572 i915_gem_object_fence_lost(obj
);
3573 i915_gem_object_update_fence(obj
, fence
, false);
3578 static struct drm_i915_fence_reg
*
3579 i915_find_fence_reg(struct drm_device
*dev
)
3581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3582 struct drm_i915_fence_reg
*reg
, *avail
;
3585 /* First try to find a free reg */
3587 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3588 reg
= &dev_priv
->fence_regs
[i
];
3592 if (!reg
->pin_count
)
3599 /* None available, try to steal one or wait for a user to finish */
3600 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3608 /* Wait for completion of pending flips which consume fences */
3609 if (intel_has_pending_fb_unpin(dev
))
3610 return ERR_PTR(-EAGAIN
);
3612 return ERR_PTR(-EDEADLK
);
3616 * i915_gem_object_get_fence - set up fencing for an object
3617 * @obj: object to map through a fence reg
3619 * When mapping objects through the GTT, userspace wants to be able to write
3620 * to them without having to worry about swizzling if the object is tiled.
3621 * This function walks the fence regs looking for a free one for @obj,
3622 * stealing one if it can't find any.
3624 * It then sets up the reg based on the object's properties: address, pitch
3625 * and tiling format.
3627 * For an untiled surface, this removes any existing fence.
3630 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3632 struct drm_device
*dev
= obj
->base
.dev
;
3633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3634 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3635 struct drm_i915_fence_reg
*reg
;
3638 /* Have we updated the tiling parameters upon the object and so
3639 * will need to serialise the write to the associated fence register?
3641 if (obj
->fence_dirty
) {
3642 ret
= i915_gem_object_wait_fence(obj
);
3647 /* Just update our place in the LRU if our fence is getting reused. */
3648 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3649 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3650 if (!obj
->fence_dirty
) {
3651 list_move_tail(®
->lru_list
,
3652 &dev_priv
->mm
.fence_list
);
3655 } else if (enable
) {
3656 if (WARN_ON(!obj
->map_and_fenceable
))
3659 reg
= i915_find_fence_reg(dev
);
3661 return PTR_ERR(reg
);
3664 struct drm_i915_gem_object
*old
= reg
->obj
;
3666 ret
= i915_gem_object_wait_fence(old
);
3670 i915_gem_object_fence_lost(old
);
3675 i915_gem_object_update_fence(obj
, reg
, enable
);
3680 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3681 unsigned long cache_level
)
3683 struct drm_mm_node
*gtt_space
= &vma
->node
;
3684 struct drm_mm_node
*other
;
3687 * On some machines we have to be careful when putting differing types
3688 * of snoopable memory together to avoid the prefetcher crossing memory
3689 * domains and dying. During vm initialisation, we decide whether or not
3690 * these constraints apply and set the drm_mm.color_adjust
3693 if (vma
->vm
->mm
.color_adjust
== NULL
)
3696 if (!drm_mm_node_allocated(gtt_space
))
3699 if (list_empty(>t_space
->node_list
))
3702 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3703 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3706 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3707 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3714 * Finds free space in the GTT aperture and binds the object or a view of it
3717 static struct i915_vma
*
3718 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3719 struct i915_address_space
*vm
,
3720 const struct i915_ggtt_view
*ggtt_view
,
3724 struct drm_device
*dev
= obj
->base
.dev
;
3725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3726 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3728 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3730 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3731 struct i915_vma
*vma
;
3734 if (i915_is_ggtt(vm
)) {
3737 if (WARN_ON(!ggtt_view
))
3738 return ERR_PTR(-EINVAL
);
3740 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3742 fence_size
= i915_gem_get_gtt_size(dev
,
3745 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3749 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3753 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3755 fence_size
= i915_gem_get_gtt_size(dev
,
3758 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3762 unfenced_alignment
=
3763 i915_gem_get_gtt_alignment(dev
,
3767 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3771 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3773 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3774 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3775 ggtt_view
? ggtt_view
->type
: 0,
3777 return ERR_PTR(-EINVAL
);
3780 /* If binding the object/GGTT view requires more space than the entire
3781 * aperture has, reject it early before evicting everything in a vain
3782 * attempt to find space.
3785 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%llu\n",
3786 ggtt_view
? ggtt_view
->type
: 0,
3788 flags
& PIN_MAPPABLE
? "mappable" : "total",
3790 return ERR_PTR(-E2BIG
);
3793 ret
= i915_gem_object_get_pages(obj
);
3795 return ERR_PTR(ret
);
3797 i915_gem_object_pin_pages(obj
);
3799 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3800 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3806 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3810 DRM_MM_SEARCH_DEFAULT
,
3811 DRM_MM_CREATE_DEFAULT
);
3813 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3822 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3824 goto err_remove_node
;
3827 trace_i915_vma_bind(vma
, flags
);
3828 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3830 goto err_remove_node
;
3832 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3833 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3838 drm_mm_remove_node(&vma
->node
);
3840 i915_gem_vma_destroy(vma
);
3843 i915_gem_object_unpin_pages(obj
);
3848 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3851 /* If we don't have a page list set up, then we're not pinned
3852 * to GPU, and we can ignore the cache flush because it'll happen
3853 * again at bind time.
3855 if (obj
->pages
== NULL
)
3859 * Stolen memory is always coherent with the GPU as it is explicitly
3860 * marked as wc by the system, or the system is cache-coherent.
3862 if (obj
->stolen
|| obj
->phys_handle
)
3865 /* If the GPU is snooping the contents of the CPU cache,
3866 * we do not need to manually clear the CPU cache lines. However,
3867 * the caches are only snooped when the render cache is
3868 * flushed/invalidated. As we always have to emit invalidations
3869 * and flushes when moving into and out of the RENDER domain, correct
3870 * snooping behaviour occurs naturally as the result of our domain
3873 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3874 obj
->cache_dirty
= true;
3878 trace_i915_gem_object_clflush(obj
);
3879 drm_clflush_sg(obj
->pages
);
3880 obj
->cache_dirty
= false;
3885 /** Flushes the GTT write domain for the object if it's dirty. */
3887 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3889 uint32_t old_write_domain
;
3891 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3894 /* No actual flushing is required for the GTT write domain. Writes
3895 * to it immediately go to main memory as far as we know, so there's
3896 * no chipset flush. It also doesn't land in render cache.
3898 * However, we do have to enforce the order so that all writes through
3899 * the GTT land before any writes to the device, such as updates to
3904 old_write_domain
= obj
->base
.write_domain
;
3905 obj
->base
.write_domain
= 0;
3907 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3909 trace_i915_gem_object_change_domain(obj
,
3910 obj
->base
.read_domains
,
3914 /** Flushes the CPU write domain for the object if it's dirty. */
3916 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3918 uint32_t old_write_domain
;
3920 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3923 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3924 i915_gem_chipset_flush(obj
->base
.dev
);
3926 old_write_domain
= obj
->base
.write_domain
;
3927 obj
->base
.write_domain
= 0;
3929 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3931 trace_i915_gem_object_change_domain(obj
,
3932 obj
->base
.read_domains
,
3937 * Moves a single object to the GTT read, and possibly write domain.
3939 * This function returns when the move is complete, including waiting on
3943 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3945 uint32_t old_write_domain
, old_read_domains
;
3946 struct i915_vma
*vma
;
3949 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3952 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3956 /* Flush and acquire obj->pages so that we are coherent through
3957 * direct access in memory with previous cached writes through
3958 * shmemfs and that our cache domain tracking remains valid.
3959 * For example, if the obj->filp was moved to swap without us
3960 * being notified and releasing the pages, we would mistakenly
3961 * continue to assume that the obj remained out of the CPU cached
3964 ret
= i915_gem_object_get_pages(obj
);
3968 i915_gem_object_flush_cpu_write_domain(obj
);
3970 /* Serialise direct access to this object with the barriers for
3971 * coherent writes from the GPU, by effectively invalidating the
3972 * GTT domain upon first access.
3974 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3977 old_write_domain
= obj
->base
.write_domain
;
3978 old_read_domains
= obj
->base
.read_domains
;
3980 /* It should now be out of any other write domains, and we can update
3981 * the domain values for our changes.
3983 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3984 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3986 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3987 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3991 trace_i915_gem_object_change_domain(obj
,
3995 /* And bump the LRU for this access */
3996 vma
= i915_gem_obj_to_ggtt(obj
);
3997 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3998 list_move_tail(&vma
->mm_list
,
3999 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
4004 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4005 enum i915_cache_level cache_level
)
4007 struct drm_device
*dev
= obj
->base
.dev
;
4008 struct i915_vma
*vma
, *next
;
4011 if (obj
->cache_level
== cache_level
)
4014 if (i915_gem_obj_is_pinned(obj
)) {
4015 DRM_DEBUG("can not change the cache level of pinned objects\n");
4019 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4020 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4021 ret
= i915_vma_unbind(vma
);
4027 if (i915_gem_obj_bound_any(obj
)) {
4028 ret
= i915_gem_object_wait_rendering(obj
, false);
4032 i915_gem_object_finish_gtt(obj
);
4034 /* Before SandyBridge, you could not use tiling or fence
4035 * registers with snooped memory, so relinquish any fences
4036 * currently pointing to our region in the aperture.
4038 if (INTEL_INFO(dev
)->gen
< 6) {
4039 ret
= i915_gem_object_put_fence(obj
);
4044 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4045 if (drm_mm_node_allocated(&vma
->node
)) {
4046 ret
= i915_vma_bind(vma
, cache_level
,
4053 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4054 vma
->node
.color
= cache_level
;
4055 obj
->cache_level
= cache_level
;
4057 if (obj
->cache_dirty
&&
4058 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4059 cpu_write_needs_clflush(obj
)) {
4060 if (i915_gem_clflush_object(obj
, true))
4061 i915_gem_chipset_flush(obj
->base
.dev
);
4067 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4068 struct drm_file
*file
)
4070 struct drm_i915_gem_caching
*args
= data
;
4071 struct drm_i915_gem_object
*obj
;
4073 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4074 if (&obj
->base
== NULL
)
4077 switch (obj
->cache_level
) {
4078 case I915_CACHE_LLC
:
4079 case I915_CACHE_L3_LLC
:
4080 args
->caching
= I915_CACHING_CACHED
;
4084 args
->caching
= I915_CACHING_DISPLAY
;
4088 args
->caching
= I915_CACHING_NONE
;
4092 drm_gem_object_unreference_unlocked(&obj
->base
);
4096 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4097 struct drm_file
*file
)
4099 struct drm_i915_gem_caching
*args
= data
;
4100 struct drm_i915_gem_object
*obj
;
4101 enum i915_cache_level level
;
4104 switch (args
->caching
) {
4105 case I915_CACHING_NONE
:
4106 level
= I915_CACHE_NONE
;
4108 case I915_CACHING_CACHED
:
4109 level
= I915_CACHE_LLC
;
4111 case I915_CACHING_DISPLAY
:
4112 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4118 ret
= i915_mutex_lock_interruptible(dev
);
4122 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4123 if (&obj
->base
== NULL
) {
4128 ret
= i915_gem_object_set_cache_level(obj
, level
);
4130 drm_gem_object_unreference(&obj
->base
);
4132 mutex_unlock(&dev
->struct_mutex
);
4137 * Prepare buffer for display plane (scanout, cursors, etc).
4138 * Can be called from an uninterruptible phase (modesetting) and allows
4139 * any flushes to be pipelined (for pageflips).
4142 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4144 struct intel_engine_cs
*pipelined
,
4145 struct drm_i915_gem_request
**pipelined_request
,
4146 const struct i915_ggtt_view
*view
)
4148 u32 old_read_domains
, old_write_domain
;
4151 ret
= i915_gem_object_sync(obj
, pipelined
, pipelined_request
);
4155 /* Mark the pin_display early so that we account for the
4156 * display coherency whilst setting up the cache domains.
4160 /* The display engine is not coherent with the LLC cache on gen6. As
4161 * a result, we make sure that the pinning that is about to occur is
4162 * done with uncached PTEs. This is lowest common denominator for all
4165 * However for gen6+, we could do better by using the GFDT bit instead
4166 * of uncaching, which would allow us to flush all the LLC-cached data
4167 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4169 ret
= i915_gem_object_set_cache_level(obj
,
4170 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4172 goto err_unpin_display
;
4174 /* As the user may map the buffer once pinned in the display plane
4175 * (e.g. libkms for the bootup splash), we have to ensure that we
4176 * always use map_and_fenceable for all scanout buffers.
4178 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4179 view
->type
== I915_GGTT_VIEW_NORMAL
?
4182 goto err_unpin_display
;
4184 i915_gem_object_flush_cpu_write_domain(obj
);
4186 old_write_domain
= obj
->base
.write_domain
;
4187 old_read_domains
= obj
->base
.read_domains
;
4189 /* It should now be out of any other write domains, and we can update
4190 * the domain values for our changes.
4192 obj
->base
.write_domain
= 0;
4193 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4195 trace_i915_gem_object_change_domain(obj
,
4207 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4208 const struct i915_ggtt_view
*view
)
4210 if (WARN_ON(obj
->pin_display
== 0))
4213 i915_gem_object_ggtt_unpin_view(obj
, view
);
4219 * Moves a single object to the CPU read, and possibly write domain.
4221 * This function returns when the move is complete, including waiting on
4225 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4227 uint32_t old_write_domain
, old_read_domains
;
4230 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4233 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4237 i915_gem_object_flush_gtt_write_domain(obj
);
4239 old_write_domain
= obj
->base
.write_domain
;
4240 old_read_domains
= obj
->base
.read_domains
;
4242 /* Flush the CPU cache if it's still invalid. */
4243 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4244 i915_gem_clflush_object(obj
, false);
4246 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4249 /* It should now be out of any other write domains, and we can update
4250 * the domain values for our changes.
4252 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4254 /* If we're writing through the CPU, then the GPU read domains will
4255 * need to be invalidated at next use.
4258 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4259 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4262 trace_i915_gem_object_change_domain(obj
,
4269 /* Throttle our rendering by waiting until the ring has completed our requests
4270 * emitted over 20 msec ago.
4272 * Note that if we were to use the current jiffies each time around the loop,
4273 * we wouldn't escape the function with any frames outstanding if the time to
4274 * render a frame was over 20ms.
4276 * This should get us reasonable parallelism between CPU and GPU but also
4277 * relatively low latency when blocking on a particular request to finish.
4280 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4283 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4284 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4285 struct drm_i915_gem_request
*request
, *target
= NULL
;
4286 unsigned reset_counter
;
4289 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4293 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4297 spin_lock(&file_priv
->mm
.lock
);
4298 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4299 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4303 * Note that the request might not have been submitted yet.
4304 * In which case emitted_jiffies will be zero.
4306 if (!request
->emitted_jiffies
)
4311 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4313 i915_gem_request_reference(target
);
4314 spin_unlock(&file_priv
->mm
.lock
);
4319 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4321 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4323 i915_gem_request_unreference__unlocked(target
);
4329 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4331 struct drm_i915_gem_object
*obj
= vma
->obj
;
4334 vma
->node
.start
& (alignment
- 1))
4337 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4340 if (flags
& PIN_OFFSET_BIAS
&&
4341 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4348 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4349 struct i915_address_space
*vm
,
4350 const struct i915_ggtt_view
*ggtt_view
,
4354 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4355 struct i915_vma
*vma
;
4359 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4362 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4365 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4368 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4371 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4372 i915_gem_obj_to_vma(obj
, vm
);
4375 return PTR_ERR(vma
);
4378 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4381 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4382 unsigned long offset
;
4383 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4384 i915_gem_obj_offset(obj
, vm
);
4385 WARN(vma
->pin_count
,
4386 "bo is already pinned in %s with incorrect alignment:"
4387 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4388 " obj->map_and_fenceable=%d\n",
4389 ggtt_view
? "ggtt" : "ppgtt",
4392 !!(flags
& PIN_MAPPABLE
),
4393 obj
->map_and_fenceable
);
4394 ret
= i915_vma_unbind(vma
);
4402 bound
= vma
? vma
->bound
: 0;
4403 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4404 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4407 return PTR_ERR(vma
);
4409 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4414 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4415 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4416 bool mappable
, fenceable
;
4417 u32 fence_size
, fence_alignment
;
4419 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4422 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4427 fenceable
= (vma
->node
.size
== fence_size
&&
4428 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4430 mappable
= (vma
->node
.start
+ fence_size
<=
4431 dev_priv
->gtt
.mappable_end
);
4433 obj
->map_and_fenceable
= mappable
&& fenceable
;
4435 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4443 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4444 struct i915_address_space
*vm
,
4448 return i915_gem_object_do_pin(obj
, vm
,
4449 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4454 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4455 const struct i915_ggtt_view
*view
,
4459 if (WARN_ONCE(!view
, "no view specified"))
4462 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4463 alignment
, flags
| PIN_GLOBAL
);
4467 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4468 const struct i915_ggtt_view
*view
)
4470 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4473 WARN_ON(vma
->pin_count
== 0);
4474 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4480 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4482 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4483 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4484 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4486 WARN_ON(!ggtt_vma
||
4487 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4488 ggtt_vma
->pin_count
);
4489 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4496 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4498 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4499 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4500 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4501 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4506 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4507 struct drm_file
*file
)
4509 struct drm_i915_gem_busy
*args
= data
;
4510 struct drm_i915_gem_object
*obj
;
4513 ret
= i915_mutex_lock_interruptible(dev
);
4517 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4518 if (&obj
->base
== NULL
) {
4523 /* Count all active objects as busy, even if they are currently not used
4524 * by the gpu. Users of this interface expect objects to eventually
4525 * become non-busy without any further actions, therefore emit any
4526 * necessary flushes here.
4528 ret
= i915_gem_object_flush_active(obj
);
4532 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4533 args
->busy
= obj
->active
<< 16;
4534 if (obj
->last_write_req
)
4535 args
->busy
|= obj
->last_write_req
->ring
->id
;
4538 drm_gem_object_unreference(&obj
->base
);
4540 mutex_unlock(&dev
->struct_mutex
);
4545 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4546 struct drm_file
*file_priv
)
4548 return i915_gem_ring_throttle(dev
, file_priv
);
4552 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4553 struct drm_file
*file_priv
)
4555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4556 struct drm_i915_gem_madvise
*args
= data
;
4557 struct drm_i915_gem_object
*obj
;
4560 switch (args
->madv
) {
4561 case I915_MADV_DONTNEED
:
4562 case I915_MADV_WILLNEED
:
4568 ret
= i915_mutex_lock_interruptible(dev
);
4572 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4573 if (&obj
->base
== NULL
) {
4578 if (i915_gem_obj_is_pinned(obj
)) {
4584 obj
->tiling_mode
!= I915_TILING_NONE
&&
4585 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4586 if (obj
->madv
== I915_MADV_WILLNEED
)
4587 i915_gem_object_unpin_pages(obj
);
4588 if (args
->madv
== I915_MADV_WILLNEED
)
4589 i915_gem_object_pin_pages(obj
);
4592 if (obj
->madv
!= __I915_MADV_PURGED
)
4593 obj
->madv
= args
->madv
;
4595 /* if the object is no longer attached, discard its backing storage */
4596 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4597 i915_gem_object_truncate(obj
);
4599 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4602 drm_gem_object_unreference(&obj
->base
);
4604 mutex_unlock(&dev
->struct_mutex
);
4608 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4609 const struct drm_i915_gem_object_ops
*ops
)
4613 INIT_LIST_HEAD(&obj
->global_list
);
4614 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4615 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4616 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4617 INIT_LIST_HEAD(&obj
->vma_list
);
4618 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4622 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4623 obj
->madv
= I915_MADV_WILLNEED
;
4625 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4628 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4629 .get_pages
= i915_gem_object_get_pages_gtt
,
4630 .put_pages
= i915_gem_object_put_pages_gtt
,
4633 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4636 struct drm_i915_gem_object
*obj
;
4637 struct address_space
*mapping
;
4640 obj
= i915_gem_object_alloc(dev
);
4644 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4645 i915_gem_object_free(obj
);
4649 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4650 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4651 /* 965gm cannot relocate objects above 4GiB. */
4652 mask
&= ~__GFP_HIGHMEM
;
4653 mask
|= __GFP_DMA32
;
4656 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4657 mapping_set_gfp_mask(mapping
, mask
);
4659 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4661 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4662 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4665 /* On some devices, we can have the GPU use the LLC (the CPU
4666 * cache) for about a 10% performance improvement
4667 * compared to uncached. Graphics requests other than
4668 * display scanout are coherent with the CPU in
4669 * accessing this cache. This means in this mode we
4670 * don't need to clflush on the CPU side, and on the
4671 * GPU side we only need to flush internal caches to
4672 * get data visible to the CPU.
4674 * However, we maintain the display planes as UC, and so
4675 * need to rebind when first used as such.
4677 obj
->cache_level
= I915_CACHE_LLC
;
4679 obj
->cache_level
= I915_CACHE_NONE
;
4681 trace_i915_gem_object_create(obj
);
4686 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4688 /* If we are the last user of the backing storage (be it shmemfs
4689 * pages or stolen etc), we know that the pages are going to be
4690 * immediately released. In this case, we can then skip copying
4691 * back the contents from the GPU.
4694 if (obj
->madv
!= I915_MADV_WILLNEED
)
4697 if (obj
->base
.filp
== NULL
)
4700 /* At first glance, this looks racy, but then again so would be
4701 * userspace racing mmap against close. However, the first external
4702 * reference to the filp can only be obtained through the
4703 * i915_gem_mmap_ioctl() which safeguards us against the user
4704 * acquiring such a reference whilst we are in the middle of
4705 * freeing the object.
4707 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4710 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4712 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4713 struct drm_device
*dev
= obj
->base
.dev
;
4714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4715 struct i915_vma
*vma
, *next
;
4717 intel_runtime_pm_get(dev_priv
);
4719 trace_i915_gem_object_destroy(obj
);
4721 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4725 ret
= i915_vma_unbind(vma
);
4726 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4727 bool was_interruptible
;
4729 was_interruptible
= dev_priv
->mm
.interruptible
;
4730 dev_priv
->mm
.interruptible
= false;
4732 WARN_ON(i915_vma_unbind(vma
));
4734 dev_priv
->mm
.interruptible
= was_interruptible
;
4738 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4739 * before progressing. */
4741 i915_gem_object_unpin_pages(obj
);
4743 WARN_ON(obj
->frontbuffer_bits
);
4745 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4746 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4747 obj
->tiling_mode
!= I915_TILING_NONE
)
4748 i915_gem_object_unpin_pages(obj
);
4750 if (WARN_ON(obj
->pages_pin_count
))
4751 obj
->pages_pin_count
= 0;
4752 if (discard_backing_storage(obj
))
4753 obj
->madv
= I915_MADV_DONTNEED
;
4754 i915_gem_object_put_pages(obj
);
4755 i915_gem_object_free_mmap_offset(obj
);
4759 if (obj
->base
.import_attach
)
4760 drm_prime_gem_destroy(&obj
->base
, NULL
);
4762 if (obj
->ops
->release
)
4763 obj
->ops
->release(obj
);
4765 drm_gem_object_release(&obj
->base
);
4766 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4769 i915_gem_object_free(obj
);
4771 intel_runtime_pm_put(dev_priv
);
4774 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4775 struct i915_address_space
*vm
)
4777 struct i915_vma
*vma
;
4778 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4779 if (i915_is_ggtt(vma
->vm
) &&
4780 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4788 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4789 const struct i915_ggtt_view
*view
)
4791 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4792 struct i915_vma
*vma
;
4794 if (WARN_ONCE(!view
, "no view specified"))
4795 return ERR_PTR(-EINVAL
);
4797 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4798 if (vma
->vm
== ggtt
&&
4799 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4804 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4806 struct i915_address_space
*vm
= NULL
;
4807 WARN_ON(vma
->node
.allocated
);
4809 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4810 if (!list_empty(&vma
->exec_list
))
4815 if (!i915_is_ggtt(vm
))
4816 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4818 list_del(&vma
->vma_link
);
4820 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4824 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4827 struct intel_engine_cs
*ring
;
4830 for_each_ring(ring
, dev_priv
, i
)
4831 dev_priv
->gt
.stop_ring(ring
);
4835 i915_gem_suspend(struct drm_device
*dev
)
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4840 mutex_lock(&dev
->struct_mutex
);
4841 ret
= i915_gpu_idle(dev
);
4845 i915_gem_retire_requests(dev
);
4847 i915_gem_stop_ringbuffers(dev
);
4848 mutex_unlock(&dev
->struct_mutex
);
4850 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4851 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4852 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4854 /* Assert that we sucessfully flushed all the work and
4855 * reset the GPU back to its idle, low power state.
4857 WARN_ON(dev_priv
->mm
.busy
);
4862 mutex_unlock(&dev
->struct_mutex
);
4866 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4868 struct intel_engine_cs
*ring
= req
->ring
;
4869 struct drm_device
*dev
= ring
->dev
;
4870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4871 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4872 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4875 if (!HAS_L3_DPF(dev
) || !remap_info
)
4878 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4883 * Note: We do not worry about the concurrent register cacheline hang
4884 * here because no other code should access these registers other than
4885 * at initialization time.
4887 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4888 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4889 intel_ring_emit(ring
, reg_base
+ i
);
4890 intel_ring_emit(ring
, remap_info
[i
/4]);
4893 intel_ring_advance(ring
);
4898 void i915_gem_init_swizzling(struct drm_device
*dev
)
4900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4902 if (INTEL_INFO(dev
)->gen
< 5 ||
4903 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4906 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4907 DISP_TILE_SURFACE_SWIZZLING
);
4912 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4914 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4915 else if (IS_GEN7(dev
))
4916 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4917 else if (IS_GEN8(dev
))
4918 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4924 intel_enable_blt(struct drm_device
*dev
)
4929 /* The blitter was dysfunctional on early prototypes */
4930 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4931 DRM_INFO("BLT not supported on this pre-production hardware;"
4932 " graphics performance will be degraded.\n");
4939 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4943 I915_WRITE(RING_CTL(base
), 0);
4944 I915_WRITE(RING_HEAD(base
), 0);
4945 I915_WRITE(RING_TAIL(base
), 0);
4946 I915_WRITE(RING_START(base
), 0);
4949 static void init_unused_rings(struct drm_device
*dev
)
4952 init_unused_ring(dev
, PRB1_BASE
);
4953 init_unused_ring(dev
, SRB0_BASE
);
4954 init_unused_ring(dev
, SRB1_BASE
);
4955 init_unused_ring(dev
, SRB2_BASE
);
4956 init_unused_ring(dev
, SRB3_BASE
);
4957 } else if (IS_GEN2(dev
)) {
4958 init_unused_ring(dev
, SRB0_BASE
);
4959 init_unused_ring(dev
, SRB1_BASE
);
4960 } else if (IS_GEN3(dev
)) {
4961 init_unused_ring(dev
, PRB1_BASE
);
4962 init_unused_ring(dev
, PRB2_BASE
);
4966 int i915_gem_init_rings(struct drm_device
*dev
)
4968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4971 ret
= intel_init_render_ring_buffer(dev
);
4976 ret
= intel_init_bsd_ring_buffer(dev
);
4978 goto cleanup_render_ring
;
4981 if (intel_enable_blt(dev
)) {
4982 ret
= intel_init_blt_ring_buffer(dev
);
4984 goto cleanup_bsd_ring
;
4987 if (HAS_VEBOX(dev
)) {
4988 ret
= intel_init_vebox_ring_buffer(dev
);
4990 goto cleanup_blt_ring
;
4993 if (HAS_BSD2(dev
)) {
4994 ret
= intel_init_bsd2_ring_buffer(dev
);
4996 goto cleanup_vebox_ring
;
4999 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
5001 goto cleanup_bsd2_ring
;
5006 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
5008 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
5010 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
5012 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
5013 cleanup_render_ring
:
5014 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
5020 i915_gem_init_hw(struct drm_device
*dev
)
5022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5023 struct intel_engine_cs
*ring
;
5026 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
5029 /* Double layer security blanket, see i915_gem_init() */
5030 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5032 if (dev_priv
->ellc_size
)
5033 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5035 if (IS_HASWELL(dev
))
5036 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5037 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5039 if (HAS_PCH_NOP(dev
)) {
5040 if (IS_IVYBRIDGE(dev
)) {
5041 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5042 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5043 I915_WRITE(GEN7_MSG_CTL
, temp
);
5044 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5045 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5046 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5047 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5051 i915_gem_init_swizzling(dev
);
5054 * At least 830 can leave some of the unused rings
5055 * "active" (ie. head != tail) after resume which
5056 * will prevent c3 entry. Makes sure all unused rings
5059 init_unused_rings(dev
);
5061 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
5063 ret
= i915_ppgtt_init_hw(dev
);
5065 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5069 /* Need to do basic initialisation of all rings first: */
5070 for_each_ring(ring
, dev_priv
, i
) {
5071 ret
= ring
->init_hw(ring
);
5076 /* Now it is safe to go back round and do everything else: */
5077 for_each_ring(ring
, dev_priv
, i
) {
5078 struct drm_i915_gem_request
*req
;
5080 WARN_ON(!ring
->default_context
);
5082 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
5084 i915_gem_cleanup_ringbuffer(dev
);
5088 if (ring
->id
== RCS
) {
5089 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
5090 i915_gem_l3_remap(req
, j
);
5093 ret
= i915_ppgtt_init_ring(req
);
5094 if (ret
&& ret
!= -EIO
) {
5095 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
5096 i915_gem_request_cancel(req
);
5097 i915_gem_cleanup_ringbuffer(dev
);
5101 ret
= i915_gem_context_enable(req
);
5102 if (ret
&& ret
!= -EIO
) {
5103 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
5104 i915_gem_request_cancel(req
);
5105 i915_gem_cleanup_ringbuffer(dev
);
5109 i915_add_request_no_flush(req
);
5113 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5117 int i915_gem_init(struct drm_device
*dev
)
5119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5122 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5123 i915
.enable_execlists
);
5125 mutex_lock(&dev
->struct_mutex
);
5127 if (IS_VALLEYVIEW(dev
)) {
5128 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5129 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5130 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5131 VLV_GTLC_ALLOWWAKEACK
), 10))
5132 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5135 if (!i915
.enable_execlists
) {
5136 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5137 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5138 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5139 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5141 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5142 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5143 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5144 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5147 /* This is just a security blanket to placate dragons.
5148 * On some systems, we very sporadically observe that the first TLBs
5149 * used by the CS may be stale, despite us poking the TLB reset. If
5150 * we hold the forcewake during initialisation these problems
5151 * just magically go away.
5153 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5155 ret
= i915_gem_init_userptr(dev
);
5159 i915_gem_init_global_gtt(dev
);
5161 ret
= i915_gem_context_init(dev
);
5165 ret
= dev_priv
->gt
.init_rings(dev
);
5169 ret
= i915_gem_init_hw(dev
);
5171 /* Allow ring initialisation to fail by marking the GPU as
5172 * wedged. But we only want to do this where the GPU is angry,
5173 * for all other failure, such as an allocation failure, bail.
5175 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5176 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5181 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5182 mutex_unlock(&dev
->struct_mutex
);
5188 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5191 struct intel_engine_cs
*ring
;
5194 for_each_ring(ring
, dev_priv
, i
)
5195 dev_priv
->gt
.cleanup_ring(ring
);
5197 if (i915
.enable_execlists
)
5199 * Neither the BIOS, ourselves or any other kernel
5200 * expects the system to be in execlists mode on startup,
5201 * so we need to reset the GPU back to legacy mode.
5203 intel_gpu_reset(dev
);
5207 init_ring_lists(struct intel_engine_cs
*ring
)
5209 INIT_LIST_HEAD(&ring
->active_list
);
5210 INIT_LIST_HEAD(&ring
->request_list
);
5213 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5214 struct i915_address_space
*vm
)
5216 if (!i915_is_ggtt(vm
))
5217 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5218 vm
->dev
= dev_priv
->dev
;
5219 INIT_LIST_HEAD(&vm
->active_list
);
5220 INIT_LIST_HEAD(&vm
->inactive_list
);
5221 INIT_LIST_HEAD(&vm
->global_link
);
5222 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5226 i915_gem_load(struct drm_device
*dev
)
5228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5232 kmem_cache_create("i915_gem_object",
5233 sizeof(struct drm_i915_gem_object
), 0,
5237 kmem_cache_create("i915_gem_vma",
5238 sizeof(struct i915_vma
), 0,
5241 dev_priv
->requests
=
5242 kmem_cache_create("i915_gem_request",
5243 sizeof(struct drm_i915_gem_request
), 0,
5247 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5248 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5250 INIT_LIST_HEAD(&dev_priv
->context_list
);
5251 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5252 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5253 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5254 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5255 init_ring_lists(&dev_priv
->ring
[i
]);
5256 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5257 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5258 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5259 i915_gem_retire_work_handler
);
5260 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5261 i915_gem_idle_work_handler
);
5262 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5264 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5266 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5267 dev_priv
->num_fence_regs
= 32;
5268 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5269 dev_priv
->num_fence_regs
= 16;
5271 dev_priv
->num_fence_regs
= 8;
5273 if (intel_vgpu_active(dev
))
5274 dev_priv
->num_fence_regs
=
5275 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5277 /* Initialize fence registers to zero */
5278 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5279 i915_gem_restore_fences(dev
);
5281 i915_gem_detect_bit_6_swizzle(dev
);
5282 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5284 dev_priv
->mm
.interruptible
= true;
5286 i915_gem_shrinker_init(dev_priv
);
5288 mutex_init(&dev_priv
->fb_tracking
.lock
);
5291 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5293 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5295 /* Clean up our request list when the client is going away, so that
5296 * later retire_requests won't dereference our soon-to-be-gone
5299 spin_lock(&file_priv
->mm
.lock
);
5300 while (!list_empty(&file_priv
->mm
.request_list
)) {
5301 struct drm_i915_gem_request
*request
;
5303 request
= list_first_entry(&file_priv
->mm
.request_list
,
5304 struct drm_i915_gem_request
,
5306 list_del(&request
->client_list
);
5307 request
->file_priv
= NULL
;
5309 spin_unlock(&file_priv
->mm
.lock
);
5311 if (!list_empty(&file_priv
->rps
.link
)) {
5312 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5313 list_del(&file_priv
->rps
.link
);
5314 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5318 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5320 struct drm_i915_file_private
*file_priv
;
5323 DRM_DEBUG_DRIVER("\n");
5325 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5329 file
->driver_priv
= file_priv
;
5330 file_priv
->dev_priv
= dev
->dev_private
;
5331 file_priv
->file
= file
;
5332 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5334 spin_lock_init(&file_priv
->mm
.lock
);
5335 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5337 ret
= i915_gem_context_open(dev
, file
);
5345 * i915_gem_track_fb - update frontbuffer tracking
5346 * old: current GEM buffer for the frontbuffer slots
5347 * new: new GEM buffer for the frontbuffer slots
5348 * frontbuffer_bits: bitmask of frontbuffer slots
5350 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5351 * from @old and setting them in @new. Both @old and @new can be NULL.
5353 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5354 struct drm_i915_gem_object
*new,
5355 unsigned frontbuffer_bits
)
5358 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5359 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5360 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5364 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5365 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5366 new->frontbuffer_bits
|= frontbuffer_bits
;
5370 /* All the new VM stuff */
5372 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5373 struct i915_address_space
*vm
)
5375 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5376 struct i915_vma
*vma
;
5378 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5380 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5381 if (i915_is_ggtt(vma
->vm
) &&
5382 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5385 return vma
->node
.start
;
5388 WARN(1, "%s vma for this object not found.\n",
5389 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5394 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5395 const struct i915_ggtt_view
*view
)
5397 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5398 struct i915_vma
*vma
;
5400 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5401 if (vma
->vm
== ggtt
&&
5402 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5403 return vma
->node
.start
;
5405 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5409 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5410 struct i915_address_space
*vm
)
5412 struct i915_vma
*vma
;
5414 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5415 if (i915_is_ggtt(vma
->vm
) &&
5416 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5418 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5425 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5426 const struct i915_ggtt_view
*view
)
5428 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5429 struct i915_vma
*vma
;
5431 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5432 if (vma
->vm
== ggtt
&&
5433 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5434 drm_mm_node_allocated(&vma
->node
))
5440 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5442 struct i915_vma
*vma
;
5444 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5445 if (drm_mm_node_allocated(&vma
->node
))
5451 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5452 struct i915_address_space
*vm
)
5454 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5455 struct i915_vma
*vma
;
5457 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5459 BUG_ON(list_empty(&o
->vma_list
));
5461 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5462 if (i915_is_ggtt(vma
->vm
) &&
5463 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5466 return vma
->node
.size
;
5471 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5473 struct i915_vma
*vma
;
5474 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5475 if (vma
->pin_count
> 0)