2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 drm_gem_object_handle_unreference_unlocked(obj
);
136 args
->handle
= handle
;
142 fast_shmem_read(struct page
**pages
,
143 loff_t page_base
, int page_offset
,
150 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
153 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
154 kunmap_atomic(vaddr
, KM_USER0
);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
164 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
165 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
167 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
168 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
172 slow_shmem_copy(struct page
*dst_page
,
174 struct page
*src_page
,
178 char *dst_vaddr
, *src_vaddr
;
180 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
181 if (dst_vaddr
== NULL
)
184 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
185 if (src_vaddr
== NULL
) {
186 kunmap_atomic(dst_vaddr
, KM_USER0
);
190 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
192 kunmap_atomic(src_vaddr
, KM_USER1
);
193 kunmap_atomic(dst_vaddr
, KM_USER0
);
199 slow_shmem_bit17_copy(struct page
*gpu_page
,
201 struct page
*cpu_page
,
206 char *gpu_vaddr
, *cpu_vaddr
;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page
, cpu_offset
,
212 gpu_page
, gpu_offset
, length
);
214 return slow_shmem_copy(gpu_page
, gpu_offset
,
215 cpu_page
, cpu_offset
, length
);
218 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
219 if (gpu_vaddr
== NULL
)
222 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
223 if (cpu_vaddr
== NULL
) {
224 kunmap_atomic(gpu_vaddr
, KM_USER0
);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
233 int this_length
= min(cacheline_end
- gpu_offset
, length
);
234 int swizzled_gpu_offset
= gpu_offset
^ 64;
237 memcpy(cpu_vaddr
+ cpu_offset
,
238 gpu_vaddr
+ swizzled_gpu_offset
,
241 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
242 cpu_vaddr
+ cpu_offset
,
245 cpu_offset
+= this_length
;
246 gpu_offset
+= this_length
;
247 length
-= this_length
;
250 kunmap_atomic(cpu_vaddr
, KM_USER1
);
251 kunmap_atomic(gpu_vaddr
, KM_USER0
);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
263 struct drm_i915_gem_pread
*args
,
264 struct drm_file
*file_priv
)
266 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
268 loff_t offset
, page_base
;
269 char __user
*user_data
;
270 int page_offset
, page_length
;
273 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
276 mutex_lock(&dev
->struct_mutex
);
278 ret
= i915_gem_object_get_pages(obj
, 0);
282 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
287 obj_priv
= obj
->driver_private
;
288 offset
= args
->offset
;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base
= (offset
& ~(PAGE_SIZE
-1));
298 page_offset
= offset
& (PAGE_SIZE
-1);
299 page_length
= remain
;
300 if ((page_offset
+ remain
) > PAGE_SIZE
)
301 page_length
= PAGE_SIZE
- page_offset
;
303 ret
= fast_shmem_read(obj_priv
->pages
,
304 page_base
, page_offset
,
305 user_data
, page_length
);
309 remain
-= page_length
;
310 user_data
+= page_length
;
311 offset
+= page_length
;
315 i915_gem_object_put_pages(obj
);
317 mutex_unlock(&dev
->struct_mutex
);
323 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
327 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
329 /* If we've insufficient memory to map in the pages, attempt
330 * to make some space by throwing out some old buffers.
332 if (ret
== -ENOMEM
) {
333 struct drm_device
*dev
= obj
->dev
;
335 ret
= i915_gem_evict_something(dev
, obj
->size
);
339 ret
= i915_gem_object_get_pages(obj
, 0);
346 * This is the fallback shmem pread path, which allocates temporary storage
347 * in kernel space to copy_to_user into outside of the struct_mutex, so we
348 * can copy out of the object's backing pages while holding the struct mutex
349 * and not take page faults.
352 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
353 struct drm_i915_gem_pread
*args
,
354 struct drm_file
*file_priv
)
356 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
357 struct mm_struct
*mm
= current
->mm
;
358 struct page
**user_pages
;
360 loff_t offset
, pinned_pages
, i
;
361 loff_t first_data_page
, last_data_page
, num_pages
;
362 int shmem_page_index
, shmem_page_offset
;
363 int data_page_index
, data_page_offset
;
366 uint64_t data_ptr
= args
->data_ptr
;
367 int do_bit17_swizzling
;
371 /* Pin the user pages containing the data. We can't fault while
372 * holding the struct mutex, yet we want to hold it while
373 * dereferencing the user data.
375 first_data_page
= data_ptr
/ PAGE_SIZE
;
376 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
377 num_pages
= last_data_page
- first_data_page
+ 1;
379 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
380 if (user_pages
== NULL
)
383 down_read(&mm
->mmap_sem
);
384 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
385 num_pages
, 1, 0, user_pages
, NULL
);
386 up_read(&mm
->mmap_sem
);
387 if (pinned_pages
< num_pages
) {
389 goto fail_put_user_pages
;
392 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
394 mutex_lock(&dev
->struct_mutex
);
396 ret
= i915_gem_object_get_pages_or_evict(obj
);
400 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
405 obj_priv
= obj
->driver_private
;
406 offset
= args
->offset
;
409 /* Operation in this page
411 * shmem_page_index = page number within shmem file
412 * shmem_page_offset = offset within page in shmem file
413 * data_page_index = page number in get_user_pages return
414 * data_page_offset = offset with data_page_index page.
415 * page_length = bytes to copy for this page
417 shmem_page_index
= offset
/ PAGE_SIZE
;
418 shmem_page_offset
= offset
& ~PAGE_MASK
;
419 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
420 data_page_offset
= data_ptr
& ~PAGE_MASK
;
422 page_length
= remain
;
423 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
424 page_length
= PAGE_SIZE
- shmem_page_offset
;
425 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
426 page_length
= PAGE_SIZE
- data_page_offset
;
428 if (do_bit17_swizzling
) {
429 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
431 user_pages
[data_page_index
],
436 ret
= slow_shmem_copy(user_pages
[data_page_index
],
438 obj_priv
->pages
[shmem_page_index
],
445 remain
-= page_length
;
446 data_ptr
+= page_length
;
447 offset
+= page_length
;
451 i915_gem_object_put_pages(obj
);
453 mutex_unlock(&dev
->struct_mutex
);
455 for (i
= 0; i
< pinned_pages
; i
++) {
456 SetPageDirty(user_pages
[i
]);
457 page_cache_release(user_pages
[i
]);
459 drm_free_large(user_pages
);
465 * Reads data from the object referenced by handle.
467 * On error, the contents of *data are undefined.
470 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
471 struct drm_file
*file_priv
)
473 struct drm_i915_gem_pread
*args
= data
;
474 struct drm_gem_object
*obj
;
475 struct drm_i915_gem_object
*obj_priv
;
478 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
481 obj_priv
= obj
->driver_private
;
483 /* Bounds check source.
485 * XXX: This could use review for overflow issues...
487 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
488 args
->offset
+ args
->size
> obj
->size
) {
489 drm_gem_object_unreference_unlocked(obj
);
493 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
494 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
496 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
498 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
502 drm_gem_object_unreference_unlocked(obj
);
507 /* This is the fast write path which cannot handle
508 * page faults in the source data
512 fast_user_write(struct io_mapping
*mapping
,
513 loff_t page_base
, int page_offset
,
514 char __user
*user_data
,
518 unsigned long unwritten
;
520 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
521 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
523 io_mapping_unmap_atomic(vaddr_atomic
);
529 /* Here's the write path which can sleep for
534 slow_kernel_write(struct io_mapping
*mapping
,
535 loff_t gtt_base
, int gtt_offset
,
536 struct page
*user_page
, int user_offset
,
539 char *src_vaddr
, *dst_vaddr
;
540 unsigned long unwritten
;
542 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
543 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
544 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
545 src_vaddr
+ user_offset
,
547 kunmap_atomic(src_vaddr
, KM_USER1
);
548 io_mapping_unmap_atomic(dst_vaddr
);
555 fast_shmem_write(struct page
**pages
,
556 loff_t page_base
, int page_offset
,
561 unsigned long unwritten
;
563 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
566 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
567 kunmap_atomic(vaddr
, KM_USER0
);
575 * This is the fast pwrite path, where we copy the data directly from the
576 * user into the GTT, uncached.
579 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
580 struct drm_i915_gem_pwrite
*args
,
581 struct drm_file
*file_priv
)
583 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
584 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
586 loff_t offset
, page_base
;
587 char __user
*user_data
;
588 int page_offset
, page_length
;
591 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
593 if (!access_ok(VERIFY_READ
, user_data
, remain
))
597 mutex_lock(&dev
->struct_mutex
);
598 ret
= i915_gem_object_pin(obj
, 0);
600 mutex_unlock(&dev
->struct_mutex
);
603 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
607 obj_priv
= obj
->driver_private
;
608 offset
= obj_priv
->gtt_offset
+ args
->offset
;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base
= (offset
& ~(PAGE_SIZE
-1));
618 page_offset
= offset
& (PAGE_SIZE
-1);
619 page_length
= remain
;
620 if ((page_offset
+ remain
) > PAGE_SIZE
)
621 page_length
= PAGE_SIZE
- page_offset
;
623 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
624 page_offset
, user_data
, page_length
);
626 /* If we get a fault while copying data, then (presumably) our
627 * source page isn't available. Return the error and we'll
628 * retry in the slow path.
633 remain
-= page_length
;
634 user_data
+= page_length
;
635 offset
+= page_length
;
639 i915_gem_object_unpin(obj
);
640 mutex_unlock(&dev
->struct_mutex
);
646 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
647 * the memory and maps it using kmap_atomic for copying.
649 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
650 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
654 struct drm_i915_gem_pwrite
*args
,
655 struct drm_file
*file_priv
)
657 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
658 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
660 loff_t gtt_page_base
, offset
;
661 loff_t first_data_page
, last_data_page
, num_pages
;
662 loff_t pinned_pages
, i
;
663 struct page
**user_pages
;
664 struct mm_struct
*mm
= current
->mm
;
665 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
667 uint64_t data_ptr
= args
->data_ptr
;
671 /* Pin the user pages containing the data. We can't fault while
672 * holding the struct mutex, and all of the pwrite implementations
673 * want to hold it while dereferencing the user data.
675 first_data_page
= data_ptr
/ PAGE_SIZE
;
676 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
677 num_pages
= last_data_page
- first_data_page
+ 1;
679 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
680 if (user_pages
== NULL
)
683 down_read(&mm
->mmap_sem
);
684 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
685 num_pages
, 0, 0, user_pages
, NULL
);
686 up_read(&mm
->mmap_sem
);
687 if (pinned_pages
< num_pages
) {
689 goto out_unpin_pages
;
692 mutex_lock(&dev
->struct_mutex
);
693 ret
= i915_gem_object_pin(obj
, 0);
697 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
699 goto out_unpin_object
;
701 obj_priv
= obj
->driver_private
;
702 offset
= obj_priv
->gtt_offset
+ args
->offset
;
705 /* Operation in this page
707 * gtt_page_base = page offset within aperture
708 * gtt_page_offset = offset within page in aperture
709 * data_page_index = page number in get_user_pages return
710 * data_page_offset = offset with data_page_index page.
711 * page_length = bytes to copy for this page
713 gtt_page_base
= offset
& PAGE_MASK
;
714 gtt_page_offset
= offset
& ~PAGE_MASK
;
715 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
716 data_page_offset
= data_ptr
& ~PAGE_MASK
;
718 page_length
= remain
;
719 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
720 page_length
= PAGE_SIZE
- gtt_page_offset
;
721 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
722 page_length
= PAGE_SIZE
- data_page_offset
;
724 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
725 gtt_page_base
, gtt_page_offset
,
726 user_pages
[data_page_index
],
730 /* If we get a fault while copying data, then (presumably) our
731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
735 goto out_unpin_object
;
737 remain
-= page_length
;
738 offset
+= page_length
;
739 data_ptr
+= page_length
;
743 i915_gem_object_unpin(obj
);
745 mutex_unlock(&dev
->struct_mutex
);
747 for (i
= 0; i
< pinned_pages
; i
++)
748 page_cache_release(user_pages
[i
]);
749 drm_free_large(user_pages
);
755 * This is the fast shmem pwrite path, which attempts to directly
756 * copy_from_user into the kmapped pages backing the object.
759 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file_priv
)
763 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
765 loff_t offset
, page_base
;
766 char __user
*user_data
;
767 int page_offset
, page_length
;
770 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
773 mutex_lock(&dev
->struct_mutex
);
775 ret
= i915_gem_object_get_pages(obj
, 0);
779 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
783 obj_priv
= obj
->driver_private
;
784 offset
= args
->offset
;
788 /* Operation in this page
790 * page_base = page offset within aperture
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_base
= (offset
& ~(PAGE_SIZE
-1));
795 page_offset
= offset
& (PAGE_SIZE
-1);
796 page_length
= remain
;
797 if ((page_offset
+ remain
) > PAGE_SIZE
)
798 page_length
= PAGE_SIZE
- page_offset
;
800 ret
= fast_shmem_write(obj_priv
->pages
,
801 page_base
, page_offset
,
802 user_data
, page_length
);
806 remain
-= page_length
;
807 user_data
+= page_length
;
808 offset
+= page_length
;
812 i915_gem_object_put_pages(obj
);
814 mutex_unlock(&dev
->struct_mutex
);
820 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
821 * the memory and maps it using kmap_atomic for copying.
823 * This avoids taking mmap_sem for faulting on the user's address while the
824 * struct_mutex is held.
827 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
828 struct drm_i915_gem_pwrite
*args
,
829 struct drm_file
*file_priv
)
831 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
832 struct mm_struct
*mm
= current
->mm
;
833 struct page
**user_pages
;
835 loff_t offset
, pinned_pages
, i
;
836 loff_t first_data_page
, last_data_page
, num_pages
;
837 int shmem_page_index
, shmem_page_offset
;
838 int data_page_index
, data_page_offset
;
841 uint64_t data_ptr
= args
->data_ptr
;
842 int do_bit17_swizzling
;
846 /* Pin the user pages containing the data. We can't fault while
847 * holding the struct mutex, and all of the pwrite implementations
848 * want to hold it while dereferencing the user data.
850 first_data_page
= data_ptr
/ PAGE_SIZE
;
851 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
852 num_pages
= last_data_page
- first_data_page
+ 1;
854 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
855 if (user_pages
== NULL
)
858 down_read(&mm
->mmap_sem
);
859 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
860 num_pages
, 0, 0, user_pages
, NULL
);
861 up_read(&mm
->mmap_sem
);
862 if (pinned_pages
< num_pages
) {
864 goto fail_put_user_pages
;
867 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
869 mutex_lock(&dev
->struct_mutex
);
871 ret
= i915_gem_object_get_pages_or_evict(obj
);
875 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
879 obj_priv
= obj
->driver_private
;
880 offset
= args
->offset
;
884 /* Operation in this page
886 * shmem_page_index = page number within shmem file
887 * shmem_page_offset = offset within page in shmem file
888 * data_page_index = page number in get_user_pages return
889 * data_page_offset = offset with data_page_index page.
890 * page_length = bytes to copy for this page
892 shmem_page_index
= offset
/ PAGE_SIZE
;
893 shmem_page_offset
= offset
& ~PAGE_MASK
;
894 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
895 data_page_offset
= data_ptr
& ~PAGE_MASK
;
897 page_length
= remain
;
898 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
899 page_length
= PAGE_SIZE
- shmem_page_offset
;
900 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
901 page_length
= PAGE_SIZE
- data_page_offset
;
903 if (do_bit17_swizzling
) {
904 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
906 user_pages
[data_page_index
],
911 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
913 user_pages
[data_page_index
],
920 remain
-= page_length
;
921 data_ptr
+= page_length
;
922 offset
+= page_length
;
926 i915_gem_object_put_pages(obj
);
928 mutex_unlock(&dev
->struct_mutex
);
930 for (i
= 0; i
< pinned_pages
; i
++)
931 page_cache_release(user_pages
[i
]);
932 drm_free_large(user_pages
);
938 * Writes data to the object referenced by handle.
940 * On error, the contents of the buffer that were to be modified are undefined.
943 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
944 struct drm_file
*file_priv
)
946 struct drm_i915_gem_pwrite
*args
= data
;
947 struct drm_gem_object
*obj
;
948 struct drm_i915_gem_object
*obj_priv
;
951 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
954 obj_priv
= obj
->driver_private
;
956 /* Bounds check destination.
958 * XXX: This could use review for overflow issues...
960 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
961 args
->offset
+ args
->size
> obj
->size
) {
962 drm_gem_object_unreference_unlocked(obj
);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
972 if (obj_priv
->phys_obj
)
973 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
974 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
975 dev
->gtt_total
!= 0) {
976 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
977 if (ret
== -EFAULT
) {
978 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
982 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
984 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
985 if (ret
== -EFAULT
) {
986 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
993 DRM_INFO("pwrite failed %d\n", ret
);
996 drm_gem_object_unreference_unlocked(obj
);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1007 struct drm_file
*file_priv
)
1009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1010 struct drm_i915_gem_set_domain
*args
= data
;
1011 struct drm_gem_object
*obj
;
1012 struct drm_i915_gem_object
*obj_priv
;
1013 uint32_t read_domains
= args
->read_domains
;
1014 uint32_t write_domain
= args
->write_domain
;
1017 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1024 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain
!= 0 && read_domains
!= write_domain
)
1033 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1036 obj_priv
= obj
->driver_private
;
1038 mutex_lock(&dev
->struct_mutex
);
1040 intel_mark_busy(dev
, obj
);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj
, obj
->size
, read_domains
, write_domain
);
1046 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1047 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1053 list_move_tail(&obj_priv
->fence_list
,
1054 &dev_priv
->mm
.fence_list
);
1057 /* Silently promote "you're not bound, there was nothing to do"
1058 * to success, since the client was just asking us to
1059 * make sure everything was done.
1064 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1067 drm_gem_object_unreference(obj
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file_priv
)
1079 struct drm_i915_gem_sw_finish
*args
= data
;
1080 struct drm_gem_object
*obj
;
1081 struct drm_i915_gem_object
*obj_priv
;
1084 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1087 mutex_lock(&dev
->struct_mutex
);
1088 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1090 mutex_unlock(&dev
->struct_mutex
);
1095 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096 __func__
, args
->handle
, obj
, obj
->size
);
1098 obj_priv
= obj
->driver_private
;
1100 /* Pinned buffers may be scanout, so flush the cache */
1101 if (obj_priv
->pin_count
)
1102 i915_gem_object_flush_cpu_write_domain(obj
);
1104 drm_gem_object_unreference(obj
);
1105 mutex_unlock(&dev
->struct_mutex
);
1110 * Maps the contents of an object, returning the address it is mapped
1113 * While the mapping holds a reference on the contents of the object, it doesn't
1114 * imply a ref on the object itself.
1117 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
)
1120 struct drm_i915_gem_mmap
*args
= data
;
1121 struct drm_gem_object
*obj
;
1125 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1128 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1132 offset
= args
->offset
;
1134 down_write(¤t
->mm
->mmap_sem
);
1135 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1136 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1138 up_write(¤t
->mm
->mmap_sem
);
1139 drm_gem_object_unreference_unlocked(obj
);
1140 if (IS_ERR((void *)addr
))
1143 args
->addr_ptr
= (uint64_t) addr
;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1166 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1167 struct drm_device
*dev
= obj
->dev
;
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1170 pgoff_t page_offset
;
1173 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1175 /* We don't use vmf->pgoff since that has the fake offset */
1176 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1179 /* Now bind it into the GTT if needed */
1180 mutex_lock(&dev
->struct_mutex
);
1181 if (!obj_priv
->gtt_space
) {
1182 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1186 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1188 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1193 /* Need a new fence register? */
1194 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1195 ret
= i915_gem_object_get_fence_reg(obj
);
1200 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1203 /* Finally, remap it using the new GTT offset */
1204 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1206 mutex_unlock(&dev
->struct_mutex
);
1211 return VM_FAULT_NOPAGE
;
1214 return VM_FAULT_OOM
;
1216 return VM_FAULT_SIGBUS
;
1221 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222 * @obj: obj in question
1224 * GEM memory mapping works by handing back to userspace a fake mmap offset
1225 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1226 * up the object based on the offset and sets up the various memory mapping
1229 * This routine allocates and attaches a fake offset for @obj.
1232 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1234 struct drm_device
*dev
= obj
->dev
;
1235 struct drm_gem_mm
*mm
= dev
->mm_private
;
1236 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1237 struct drm_map_list
*list
;
1238 struct drm_local_map
*map
;
1241 /* Set the object up for mmap'ing */
1242 list
= &obj
->map_list
;
1243 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1248 map
->type
= _DRM_GEM
;
1249 map
->size
= obj
->size
;
1252 /* Get a DRM GEM mmap offset allocated... */
1253 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1254 obj
->size
/ PAGE_SIZE
, 0, 0);
1255 if (!list
->file_offset_node
) {
1256 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1261 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1262 obj
->size
/ PAGE_SIZE
, 0);
1263 if (!list
->file_offset_node
) {
1268 list
->hash
.key
= list
->file_offset_node
->start
;
1269 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1270 DRM_ERROR("failed to add to map hash\n");
1275 /* By now we should be all set, any drm_mmap request on the offset
1276 * below will get to our mmap & fault handler */
1277 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1282 drm_mm_put_block(list
->file_offset_node
);
1290 * i915_gem_release_mmap - remove physical page mappings
1291 * @obj: obj in question
1293 * Preserve the reservation of the mmapping with the DRM core code, but
1294 * relinquish ownership of the pages back to the system.
1296 * It is vital that we remove the page mapping if we have mapped a tiled
1297 * object through the GTT and then lose the fence register due to
1298 * resource pressure. Similarly if the object has been moved out of the
1299 * aperture, than pages mapped into userspace must be revoked. Removing the
1300 * mapping will then trigger a page fault on the next user access, allowing
1301 * fixup by i915_gem_fault().
1304 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1306 struct drm_device
*dev
= obj
->dev
;
1307 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1309 if (dev
->dev_mapping
)
1310 unmap_mapping_range(dev
->dev_mapping
,
1311 obj_priv
->mmap_offset
, obj
->size
, 1);
1315 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1317 struct drm_device
*dev
= obj
->dev
;
1318 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1319 struct drm_gem_mm
*mm
= dev
->mm_private
;
1320 struct drm_map_list
*list
;
1322 list
= &obj
->map_list
;
1323 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1325 if (list
->file_offset_node
) {
1326 drm_mm_put_block(list
->file_offset_node
);
1327 list
->file_offset_node
= NULL
;
1335 obj_priv
->mmap_offset
= 0;
1339 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340 * @obj: object to check
1342 * Return the required GTT alignment for an object, taking into account
1343 * potential fence register mapping if needed.
1346 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1348 struct drm_device
*dev
= obj
->dev
;
1349 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1353 * Minimum alignment is 4k (GTT page size), but might be greater
1354 * if a fence register is needed for the object.
1356 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1360 * Previous chips need to be aligned to the size of the smallest
1361 * fence register that can contain the object.
1368 for (i
= start
; i
< obj
->size
; i
<<= 1)
1375 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @data: GTT mapping ioctl data
1378 * @file_priv: GEM object info
1380 * Simply returns the fake offset to userspace so it can mmap it.
1381 * The mmap call will end up in drm_gem_mmap(), which will set things
1382 * up so we can get faults in the handler above.
1384 * The fault handler will take care of binding the object into the GTT
1385 * (since it may have been evicted to make room for something), allocating
1386 * a fence register, and mapping the appropriate aperture address into
1390 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1391 struct drm_file
*file_priv
)
1393 struct drm_i915_gem_mmap_gtt
*args
= data
;
1394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 struct drm_gem_object
*obj
;
1396 struct drm_i915_gem_object
*obj_priv
;
1399 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1402 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1406 mutex_lock(&dev
->struct_mutex
);
1408 obj_priv
= obj
->driver_private
;
1410 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1411 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412 drm_gem_object_unreference(obj
);
1413 mutex_unlock(&dev
->struct_mutex
);
1418 if (!obj_priv
->mmap_offset
) {
1419 ret
= i915_gem_create_mmap_offset(obj
);
1421 drm_gem_object_unreference(obj
);
1422 mutex_unlock(&dev
->struct_mutex
);
1427 args
->offset
= obj_priv
->mmap_offset
;
1430 * Pull it into the GTT so that we have a page list (makes the
1431 * initial fault faster and any subsequent flushing possible).
1433 if (!obj_priv
->agp_mem
) {
1434 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1436 drm_gem_object_unreference(obj
);
1437 mutex_unlock(&dev
->struct_mutex
);
1440 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1443 drm_gem_object_unreference(obj
);
1444 mutex_unlock(&dev
->struct_mutex
);
1450 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1452 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1453 int page_count
= obj
->size
/ PAGE_SIZE
;
1456 BUG_ON(obj_priv
->pages_refcount
== 0);
1457 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1459 if (--obj_priv
->pages_refcount
!= 0)
1462 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1463 i915_gem_object_save_bit_17_swizzle(obj
);
1465 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1466 obj_priv
->dirty
= 0;
1468 for (i
= 0; i
< page_count
; i
++) {
1469 if (obj_priv
->pages
[i
] == NULL
)
1472 if (obj_priv
->dirty
)
1473 set_page_dirty(obj_priv
->pages
[i
]);
1475 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1476 mark_page_accessed(obj_priv
->pages
[i
]);
1478 page_cache_release(obj_priv
->pages
[i
]);
1480 obj_priv
->dirty
= 0;
1482 drm_free_large(obj_priv
->pages
);
1483 obj_priv
->pages
= NULL
;
1487 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1489 struct drm_device
*dev
= obj
->dev
;
1490 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1491 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv
->active
) {
1495 drm_gem_object_reference(obj
);
1496 obj_priv
->active
= 1;
1498 /* Move from whatever list we were on to the tail of execution. */
1499 spin_lock(&dev_priv
->mm
.active_list_lock
);
1500 list_move_tail(&obj_priv
->list
,
1501 &dev_priv
->mm
.active_list
);
1502 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1503 obj_priv
->last_rendering_seqno
= seqno
;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1513 BUG_ON(!obj_priv
->active
);
1514 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1515 obj_priv
->last_rendering_seqno
= 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1523 struct inode
*inode
;
1525 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1526 if (inode
->i_op
->truncate
)
1527 inode
->i_op
->truncate (inode
);
1529 obj_priv
->madv
= __I915_MADV_PURGED
;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1535 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1541 struct drm_device
*dev
= obj
->dev
;
1542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1543 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1545 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1546 if (obj_priv
->pin_count
!= 0)
1547 list_del_init(&obj_priv
->list
);
1549 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1551 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1553 obj_priv
->last_rendering_seqno
= 0;
1554 if (obj_priv
->active
) {
1555 obj_priv
->active
= 0;
1556 drm_gem_object_unreference(obj
);
1558 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1562 * Creates a new sequence number, emitting a write of it to the status page
1563 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1565 * Must be called with struct_lock held.
1567 * Returned sequence numbers are nonzero on success.
1570 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1571 uint32_t flush_domains
)
1573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1574 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1575 struct drm_i915_gem_request
*request
;
1580 if (file_priv
!= NULL
)
1581 i915_file_priv
= file_priv
->driver_priv
;
1583 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1584 if (request
== NULL
)
1587 /* Grab the seqno we're going to make this request be, and bump the
1588 * next (skipping 0 so it can be the reserved no-seqno value).
1590 seqno
= dev_priv
->mm
.next_gem_seqno
;
1591 dev_priv
->mm
.next_gem_seqno
++;
1592 if (dev_priv
->mm
.next_gem_seqno
== 0)
1593 dev_priv
->mm
.next_gem_seqno
++;
1596 OUT_RING(MI_STORE_DWORD_INDEX
);
1597 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1600 OUT_RING(MI_USER_INTERRUPT
);
1603 DRM_DEBUG_DRIVER("%d\n", seqno
);
1605 request
->seqno
= seqno
;
1606 request
->emitted_jiffies
= jiffies
;
1607 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1608 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1609 if (i915_file_priv
) {
1610 list_add_tail(&request
->client_list
,
1611 &i915_file_priv
->mm
.request_list
);
1613 INIT_LIST_HEAD(&request
->client_list
);
1616 /* Associate any objects on the flushing list matching the write
1617 * domain we're flushing with our flush.
1619 if (flush_domains
!= 0) {
1620 struct drm_i915_gem_object
*obj_priv
, *next
;
1622 list_for_each_entry_safe(obj_priv
, next
,
1623 &dev_priv
->mm
.gpu_write_list
,
1625 struct drm_gem_object
*obj
= obj_priv
->obj
;
1627 if ((obj
->write_domain
& flush_domains
) ==
1628 obj
->write_domain
) {
1629 uint32_t old_write_domain
= obj
->write_domain
;
1631 obj
->write_domain
= 0;
1632 list_del_init(&obj_priv
->gpu_write_list
);
1633 i915_gem_object_move_to_active(obj
, seqno
);
1635 trace_i915_gem_object_change_domain(obj
,
1643 if (!dev_priv
->mm
.suspended
) {
1644 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1646 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device
*dev
)
1660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1661 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1662 uint32_t flush_domains
= 0;
1665 /* The sampler always gets flushed on i965 (sigh) */
1667 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1670 OUT_RING(0); /* noop */
1672 return flush_domains
;
1676 * Moves buffers associated only with the given active seqno from the active
1677 * to inactive list, potentially freeing them.
1680 i915_gem_retire_request(struct drm_device
*dev
,
1681 struct drm_i915_gem_request
*request
)
1683 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1685 trace_i915_gem_request_retire(dev
, request
->seqno
);
1687 /* Move any buffers on the active list that are no longer referenced
1688 * by the ringbuffer to the flushing/inactive lists as appropriate.
1690 spin_lock(&dev_priv
->mm
.active_list_lock
);
1691 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1692 struct drm_gem_object
*obj
;
1693 struct drm_i915_gem_object
*obj_priv
;
1695 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1696 struct drm_i915_gem_object
,
1698 obj
= obj_priv
->obj
;
1700 /* If the seqno being retired doesn't match the oldest in the
1701 * list, then the oldest in the list must still be newer than
1704 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1708 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1709 __func__
, request
->seqno
, obj
);
1712 if (obj
->write_domain
!= 0)
1713 i915_gem_object_move_to_flushing(obj
);
1715 /* Take a reference on the object so it won't be
1716 * freed while the spinlock is held. The list
1717 * protection for this spinlock is safe when breaking
1718 * the lock like this since the next thing we do
1719 * is just get the head of the list again.
1721 drm_gem_object_reference(obj
);
1722 i915_gem_object_move_to_inactive(obj
);
1723 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1724 drm_gem_object_unreference(obj
);
1725 spin_lock(&dev_priv
->mm
.active_list_lock
);
1729 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1733 * Returns true if seq1 is later than seq2.
1736 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1738 return (int32_t)(seq1
- seq2
) >= 0;
1742 i915_get_gem_seqno(struct drm_device
*dev
)
1744 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1746 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1750 * This function clears the request list as sequence numbers are passed.
1753 i915_gem_retire_requests(struct drm_device
*dev
)
1755 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1758 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1761 seqno
= i915_get_gem_seqno(dev
);
1763 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1764 struct drm_i915_gem_request
*request
;
1765 uint32_t retiring_seqno
;
1767 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1768 struct drm_i915_gem_request
,
1770 retiring_seqno
= request
->seqno
;
1772 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1773 atomic_read(&dev_priv
->mm
.wedged
)) {
1774 i915_gem_retire_request(dev
, request
);
1776 list_del(&request
->list
);
1777 list_del(&request
->client_list
);
1783 if (unlikely (dev_priv
->trace_irq_seqno
&&
1784 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1785 i915_user_irq_put(dev
);
1786 dev_priv
->trace_irq_seqno
= 0;
1791 i915_gem_retire_work_handler(struct work_struct
*work
)
1793 drm_i915_private_t
*dev_priv
;
1794 struct drm_device
*dev
;
1796 dev_priv
= container_of(work
, drm_i915_private_t
,
1797 mm
.retire_work
.work
);
1798 dev
= dev_priv
->dev
;
1800 mutex_lock(&dev
->struct_mutex
);
1801 i915_gem_retire_requests(dev
);
1802 if (!dev_priv
->mm
.suspended
&&
1803 !list_empty(&dev_priv
->mm
.request_list
))
1804 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1805 mutex_unlock(&dev
->struct_mutex
);
1809 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1811 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1817 if (atomic_read(&dev_priv
->mm
.wedged
))
1820 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1821 if (HAS_PCH_SPLIT(dev
))
1822 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1824 ier
= I915_READ(IER
);
1826 DRM_ERROR("something (likely vbetool) disabled "
1827 "interrupts, re-enabling\n");
1828 i915_driver_irq_preinstall(dev
);
1829 i915_driver_irq_postinstall(dev
);
1832 trace_i915_gem_request_wait_begin(dev
, seqno
);
1834 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1835 i915_user_irq_get(dev
);
1837 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1838 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1839 atomic_read(&dev_priv
->mm
.wedged
));
1841 wait_event(dev_priv
->irq_queue
,
1842 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1843 atomic_read(&dev_priv
->mm
.wedged
));
1845 i915_user_irq_put(dev
);
1846 dev_priv
->mm
.waiting_gem_seqno
= 0;
1848 trace_i915_gem_request_wait_end(dev
, seqno
);
1850 if (atomic_read(&dev_priv
->mm
.wedged
))
1853 if (ret
&& ret
!= -ERESTARTSYS
)
1854 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1855 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1857 /* Directly dispatch request retiring. While we have the work queue
1858 * to handle this, the waiter on a request often wants an associated
1859 * buffer to have made it to the inactive list, and we would need
1860 * a separate wait queue to handle that.
1863 i915_gem_retire_requests(dev
);
1869 * Waits for a sequence number to be signaled, and cleans up the
1870 * request and object lists appropriately for that event.
1873 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1875 return i915_do_wait_request(dev
, seqno
, 1);
1879 i915_gem_flush(struct drm_device
*dev
,
1880 uint32_t invalidate_domains
,
1881 uint32_t flush_domains
)
1883 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1888 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1889 invalidate_domains
, flush_domains
);
1891 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1892 invalidate_domains
, flush_domains
);
1894 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1895 drm_agp_chipset_flush(dev
);
1897 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1899 * read/write caches:
1901 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1902 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1903 * also flushed at 2d versus 3d pipeline switches.
1907 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1908 * MI_READ_FLUSH is set, and is always flushed on 965.
1910 * I915_GEM_DOMAIN_COMMAND may not exist?
1912 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1913 * invalidated when MI_EXE_FLUSH is set.
1915 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1916 * invalidated with every MI_FLUSH.
1920 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1921 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1922 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1923 * are flushed at any MI_FLUSH.
1926 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1927 if ((invalidate_domains
|flush_domains
) &
1928 I915_GEM_DOMAIN_RENDER
)
1929 cmd
&= ~MI_NO_WRITE_FLUSH
;
1930 if (!IS_I965G(dev
)) {
1932 * On the 965, the sampler cache always gets flushed
1933 * and this bit is reserved.
1935 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1936 cmd
|= MI_READ_FLUSH
;
1938 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1939 cmd
|= MI_EXE_FLUSH
;
1942 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1952 * Ensures that all rendering to the object has completed and the object is
1953 * safe to unbind from the GTT or access from the CPU.
1956 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1958 struct drm_device
*dev
= obj
->dev
;
1959 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1962 /* This function only exists to support waiting for existing rendering,
1963 * not for emitting required flushes.
1965 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1967 /* If there is rendering queued on the buffer being evicted, wait for
1970 if (obj_priv
->active
) {
1972 DRM_INFO("%s: object %p wait for seqno %08x\n",
1973 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1975 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1984 * Unbinds an object from the GTT aperture.
1987 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1989 struct drm_device
*dev
= obj
->dev
;
1990 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1991 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1995 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1996 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1998 if (obj_priv
->gtt_space
== NULL
)
2001 if (obj_priv
->pin_count
!= 0) {
2002 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006 /* blow away mappings if mapped through GTT */
2007 i915_gem_release_mmap(obj
);
2009 /* Move the object to the CPU domain to ensure that
2010 * any possible CPU writes while it's not in the GTT
2011 * are flushed when we go to remap it. This will
2012 * also ensure that all pending GPU writes are finished
2015 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2017 if (ret
!= -ERESTARTSYS
)
2018 DRM_ERROR("set_domain failed: %d\n", ret
);
2022 BUG_ON(obj_priv
->active
);
2024 /* release the fence reg _after_ flushing */
2025 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2026 i915_gem_clear_fence_reg(obj
);
2028 if (obj_priv
->agp_mem
!= NULL
) {
2029 drm_unbind_agp(obj_priv
->agp_mem
);
2030 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2031 obj_priv
->agp_mem
= NULL
;
2034 i915_gem_object_put_pages(obj
);
2035 BUG_ON(obj_priv
->pages_refcount
);
2037 if (obj_priv
->gtt_space
) {
2038 atomic_dec(&dev
->gtt_count
);
2039 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2041 drm_mm_put_block(obj_priv
->gtt_space
);
2042 obj_priv
->gtt_space
= NULL
;
2045 /* Remove ourselves from the LRU list if present. */
2046 spin_lock(&dev_priv
->mm
.active_list_lock
);
2047 if (!list_empty(&obj_priv
->list
))
2048 list_del_init(&obj_priv
->list
);
2049 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2051 if (i915_gem_object_is_purgeable(obj_priv
))
2052 i915_gem_object_truncate(obj
);
2054 trace_i915_gem_object_unbind(obj
);
2059 static struct drm_gem_object
*
2060 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2062 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2063 struct drm_i915_gem_object
*obj_priv
;
2064 struct drm_gem_object
*best
= NULL
;
2065 struct drm_gem_object
*first
= NULL
;
2067 /* Try to find the smallest clean object */
2068 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2069 struct drm_gem_object
*obj
= obj_priv
->obj
;
2070 if (obj
->size
>= min_size
) {
2071 if ((!obj_priv
->dirty
||
2072 i915_gem_object_is_purgeable(obj_priv
)) &&
2073 (!best
|| obj
->size
< best
->size
)) {
2075 if (best
->size
== min_size
)
2083 return best
? best
: first
;
2087 i915_gem_evict_everything(struct drm_device
*dev
)
2089 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2094 spin_lock(&dev_priv
->mm
.active_list_lock
);
2095 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2096 list_empty(&dev_priv
->mm
.flushing_list
) &&
2097 list_empty(&dev_priv
->mm
.active_list
));
2098 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2103 /* Flush everything (on to the inactive lists) and evict */
2104 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2105 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2109 ret
= i915_wait_request(dev
, seqno
);
2113 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2115 ret
= i915_gem_evict_from_inactive_list(dev
);
2119 spin_lock(&dev_priv
->mm
.active_list_lock
);
2120 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2121 list_empty(&dev_priv
->mm
.flushing_list
) &&
2122 list_empty(&dev_priv
->mm
.active_list
));
2123 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2124 BUG_ON(!lists_empty
);
2130 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2132 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2133 struct drm_gem_object
*obj
;
2137 i915_gem_retire_requests(dev
);
2139 /* If there's an inactive buffer available now, grab it
2142 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2144 struct drm_i915_gem_object
*obj_priv
;
2147 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2149 obj_priv
= obj
->driver_private
;
2150 BUG_ON(obj_priv
->pin_count
!= 0);
2151 BUG_ON(obj_priv
->active
);
2153 /* Wait on the rendering and unbind the buffer. */
2154 return i915_gem_object_unbind(obj
);
2157 /* If we didn't get anything, but the ring is still processing
2158 * things, wait for the next to finish and hopefully leave us
2159 * a buffer to evict.
2161 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2162 struct drm_i915_gem_request
*request
;
2164 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2165 struct drm_i915_gem_request
,
2168 ret
= i915_wait_request(dev
, request
->seqno
);
2175 /* If we didn't have anything on the request list but there
2176 * are buffers awaiting a flush, emit one and try again.
2177 * When we wait on it, those buffers waiting for that flush
2178 * will get moved to inactive.
2180 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2181 struct drm_i915_gem_object
*obj_priv
;
2183 /* Find an object that we can immediately reuse */
2184 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2185 obj
= obj_priv
->obj
;
2186 if (obj
->size
>= min_size
)
2198 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2202 ret
= i915_wait_request(dev
, seqno
);
2210 /* If we didn't do any of the above, there's no single buffer
2211 * large enough to swap out for the new one, so just evict
2212 * everything and start again. (This should be rare.)
2214 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2215 return i915_gem_evict_from_inactive_list(dev
);
2217 return i915_gem_evict_everything(dev
);
2222 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2225 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2227 struct address_space
*mapping
;
2228 struct inode
*inode
;
2232 if (obj_priv
->pages_refcount
++ != 0)
2235 /* Get the list of pages out of our struct file. They'll be pinned
2236 * at this point until we release them.
2238 page_count
= obj
->size
/ PAGE_SIZE
;
2239 BUG_ON(obj_priv
->pages
!= NULL
);
2240 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2241 if (obj_priv
->pages
== NULL
) {
2242 obj_priv
->pages_refcount
--;
2246 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2247 mapping
= inode
->i_mapping
;
2248 for (i
= 0; i
< page_count
; i
++) {
2249 page
= read_cache_page_gfp(mapping
, i
,
2250 mapping_gfp_mask (mapping
) |
2254 ret
= PTR_ERR(page
);
2255 i915_gem_object_put_pages(obj
);
2258 obj_priv
->pages
[i
] = page
;
2261 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2262 i915_gem_object_do_bit_17_swizzle(obj
);
2267 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2269 struct drm_gem_object
*obj
= reg
->obj
;
2270 struct drm_device
*dev
= obj
->dev
;
2271 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2272 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2273 int regnum
= obj_priv
->fence_reg
;
2276 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2278 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2279 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2280 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2282 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2283 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2284 val
|= I965_FENCE_REG_VALID
;
2286 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2289 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2291 struct drm_gem_object
*obj
= reg
->obj
;
2292 struct drm_device
*dev
= obj
->dev
;
2293 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2294 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2295 int regnum
= obj_priv
->fence_reg
;
2298 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2300 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2301 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2302 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2303 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2304 val
|= I965_FENCE_REG_VALID
;
2306 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2309 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2311 struct drm_gem_object
*obj
= reg
->obj
;
2312 struct drm_device
*dev
= obj
->dev
;
2313 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2314 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2315 int regnum
= obj_priv
->fence_reg
;
2317 uint32_t fence_reg
, val
;
2320 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2321 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2322 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2323 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2327 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2328 HAS_128_BYTE_Y_TILING(dev
))
2333 /* Note: pitch better be a power of two tile widths */
2334 pitch_val
= obj_priv
->stride
/ tile_width
;
2335 pitch_val
= ffs(pitch_val
) - 1;
2337 val
= obj_priv
->gtt_offset
;
2338 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2339 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2340 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2341 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2342 val
|= I830_FENCE_REG_VALID
;
2345 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2347 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2348 I915_WRITE(fence_reg
, val
);
2351 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2353 struct drm_gem_object
*obj
= reg
->obj
;
2354 struct drm_device
*dev
= obj
->dev
;
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2356 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2357 int regnum
= obj_priv
->fence_reg
;
2360 uint32_t fence_size_bits
;
2362 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2363 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2364 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2365 __func__
, obj_priv
->gtt_offset
);
2369 pitch_val
= obj_priv
->stride
/ 128;
2370 pitch_val
= ffs(pitch_val
) - 1;
2371 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2373 val
= obj_priv
->gtt_offset
;
2374 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2375 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2376 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2377 WARN_ON(fence_size_bits
& ~0x00000f00);
2378 val
|= fence_size_bits
;
2379 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2380 val
|= I830_FENCE_REG_VALID
;
2382 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2386 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2387 * @obj: object to map through a fence reg
2389 * When mapping objects through the GTT, userspace wants to be able to write
2390 * to them without having to worry about swizzling if the object is tiled.
2392 * This function walks the fence regs looking for a free one for @obj,
2393 * stealing one if it can't find any.
2395 * It then sets up the reg based on the object's properties: address, pitch
2396 * and tiling format.
2399 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2401 struct drm_device
*dev
= obj
->dev
;
2402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2403 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2404 struct drm_i915_fence_reg
*reg
= NULL
;
2405 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2408 /* Just update our place in the LRU if our fence is getting used. */
2409 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2410 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2414 switch (obj_priv
->tiling_mode
) {
2415 case I915_TILING_NONE
:
2416 WARN(1, "allocating a fence for non-tiled object?\n");
2419 if (!obj_priv
->stride
)
2421 WARN((obj_priv
->stride
& (512 - 1)),
2422 "object 0x%08x is X tiled but has non-512B pitch\n",
2423 obj_priv
->gtt_offset
);
2426 if (!obj_priv
->stride
)
2428 WARN((obj_priv
->stride
& (128 - 1)),
2429 "object 0x%08x is Y tiled but has non-128B pitch\n",
2430 obj_priv
->gtt_offset
);
2434 /* First try to find a free reg */
2436 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2437 reg
= &dev_priv
->fence_regs
[i
];
2441 old_obj_priv
= reg
->obj
->driver_private
;
2442 if (!old_obj_priv
->pin_count
)
2446 /* None available, try to steal one or wait for a user to finish */
2447 if (i
== dev_priv
->num_fence_regs
) {
2448 struct drm_gem_object
*old_obj
= NULL
;
2453 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2455 old_obj
= old_obj_priv
->obj
;
2457 if (old_obj_priv
->pin_count
)
2460 /* Take a reference, as otherwise the wait_rendering
2461 * below may cause the object to get freed out from
2464 drm_gem_object_reference(old_obj
);
2469 i
= old_obj_priv
->fence_reg
;
2470 reg
= &dev_priv
->fence_regs
[i
];
2472 ret
= i915_gem_object_put_fence_reg(old_obj
);
2473 drm_gem_object_unreference(old_obj
);
2478 obj_priv
->fence_reg
= i
;
2479 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2484 sandybridge_write_fence_reg(reg
);
2485 else if (IS_I965G(dev
))
2486 i965_write_fence_reg(reg
);
2487 else if (IS_I9XX(dev
))
2488 i915_write_fence_reg(reg
);
2490 i830_write_fence_reg(reg
);
2492 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2498 * i915_gem_clear_fence_reg - clear out fence register info
2499 * @obj: object to clear
2501 * Zeroes out the fence register itself and clears out the associated
2502 * data structures in dev_priv and obj_priv.
2505 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2507 struct drm_device
*dev
= obj
->dev
;
2508 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2509 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2512 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2513 (obj_priv
->fence_reg
* 8), 0);
2514 } else if (IS_I965G(dev
)) {
2515 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2519 if (obj_priv
->fence_reg
< 8)
2520 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2522 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2525 I915_WRITE(fence_reg
, 0);
2528 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2529 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2530 list_del_init(&obj_priv
->fence_list
);
2534 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2535 * to the buffer to finish, and then resets the fence register.
2536 * @obj: tiled object holding a fence register.
2538 * Zeroes out the fence register itself and clears out the associated
2539 * data structures in dev_priv and obj_priv.
2542 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2544 struct drm_device
*dev
= obj
->dev
;
2545 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2547 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2550 /* If we've changed tiling, GTT-mappings of the object
2551 * need to re-fault to ensure that the correct fence register
2552 * setup is in place.
2554 i915_gem_release_mmap(obj
);
2556 /* On the i915, GPU access to tiled buffers is via a fence,
2557 * therefore we must wait for any outstanding access to complete
2558 * before clearing the fence.
2560 if (!IS_I965G(dev
)) {
2563 i915_gem_object_flush_gpu_write_domain(obj
);
2564 ret
= i915_gem_object_wait_rendering(obj
);
2569 i915_gem_object_flush_gtt_write_domain(obj
);
2570 i915_gem_clear_fence_reg (obj
);
2576 * Finds free space in the GTT aperture and binds the object there.
2579 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2581 struct drm_device
*dev
= obj
->dev
;
2582 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2583 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2584 struct drm_mm_node
*free_space
;
2585 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2588 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2589 DRM_ERROR("Attempting to bind a purgeable object\n");
2594 alignment
= i915_gem_get_gtt_alignment(obj
);
2595 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2596 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2601 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2602 obj
->size
, alignment
, 0);
2603 if (free_space
!= NULL
) {
2604 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2606 if (obj_priv
->gtt_space
!= NULL
) {
2607 obj_priv
->gtt_space
->private = obj
;
2608 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2611 if (obj_priv
->gtt_space
== NULL
) {
2612 /* If the gtt is empty and we're still having trouble
2613 * fitting our object in, we're out of memory.
2616 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2618 ret
= i915_gem_evict_something(dev
, obj
->size
);
2626 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2627 obj
->size
, obj_priv
->gtt_offset
);
2629 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2631 drm_mm_put_block(obj_priv
->gtt_space
);
2632 obj_priv
->gtt_space
= NULL
;
2634 if (ret
== -ENOMEM
) {
2635 /* first try to clear up some space from the GTT */
2636 ret
= i915_gem_evict_something(dev
, obj
->size
);
2638 /* now try to shrink everyone else */
2653 /* Create an AGP memory structure pointing at our pages, and bind it
2656 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2658 obj
->size
>> PAGE_SHIFT
,
2659 obj_priv
->gtt_offset
,
2660 obj_priv
->agp_type
);
2661 if (obj_priv
->agp_mem
== NULL
) {
2662 i915_gem_object_put_pages(obj
);
2663 drm_mm_put_block(obj_priv
->gtt_space
);
2664 obj_priv
->gtt_space
= NULL
;
2666 ret
= i915_gem_evict_something(dev
, obj
->size
);
2672 atomic_inc(&dev
->gtt_count
);
2673 atomic_add(obj
->size
, &dev
->gtt_memory
);
2675 /* Assert that the object is not currently in any GPU domain. As it
2676 * wasn't in the GTT, there shouldn't be any way it could have been in
2679 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2680 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2682 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2688 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2690 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2692 /* If we don't have a page list set up, then we're not pinned
2693 * to GPU, and we can ignore the cache flush because it'll happen
2694 * again at bind time.
2696 if (obj_priv
->pages
== NULL
)
2699 trace_i915_gem_object_clflush(obj
);
2701 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2704 /** Flushes any GPU write domain for the object if it's dirty. */
2706 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2708 struct drm_device
*dev
= obj
->dev
;
2710 uint32_t old_write_domain
;
2712 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2715 /* Queue the GPU write cache flushing we need. */
2716 old_write_domain
= obj
->write_domain
;
2717 i915_gem_flush(dev
, 0, obj
->write_domain
);
2718 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2719 BUG_ON(obj
->write_domain
);
2720 i915_gem_object_move_to_active(obj
, seqno
);
2722 trace_i915_gem_object_change_domain(obj
,
2727 /** Flushes the GTT write domain for the object if it's dirty. */
2729 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2731 uint32_t old_write_domain
;
2733 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2736 /* No actual flushing is required for the GTT write domain. Writes
2737 * to it immediately go to main memory as far as we know, so there's
2738 * no chipset flush. It also doesn't land in render cache.
2740 old_write_domain
= obj
->write_domain
;
2741 obj
->write_domain
= 0;
2743 trace_i915_gem_object_change_domain(obj
,
2748 /** Flushes the CPU write domain for the object if it's dirty. */
2750 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2752 struct drm_device
*dev
= obj
->dev
;
2753 uint32_t old_write_domain
;
2755 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2758 i915_gem_clflush_object(obj
);
2759 drm_agp_chipset_flush(dev
);
2760 old_write_domain
= obj
->write_domain
;
2761 obj
->write_domain
= 0;
2763 trace_i915_gem_object_change_domain(obj
,
2769 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2771 switch (obj
->write_domain
) {
2772 case I915_GEM_DOMAIN_GTT
:
2773 i915_gem_object_flush_gtt_write_domain(obj
);
2775 case I915_GEM_DOMAIN_CPU
:
2776 i915_gem_object_flush_cpu_write_domain(obj
);
2779 i915_gem_object_flush_gpu_write_domain(obj
);
2785 * Moves a single object to the GTT read, and possibly write domain.
2787 * This function returns when the move is complete, including waiting on
2791 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2793 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2794 uint32_t old_write_domain
, old_read_domains
;
2797 /* Not valid to be called on unbound objects. */
2798 if (obj_priv
->gtt_space
== NULL
)
2801 i915_gem_object_flush_gpu_write_domain(obj
);
2802 /* Wait on any GPU rendering and flushing to occur. */
2803 ret
= i915_gem_object_wait_rendering(obj
);
2807 old_write_domain
= obj
->write_domain
;
2808 old_read_domains
= obj
->read_domains
;
2810 /* If we're writing through the GTT domain, then CPU and GPU caches
2811 * will need to be invalidated at next use.
2814 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2816 i915_gem_object_flush_cpu_write_domain(obj
);
2818 /* It should now be out of any other write domains, and we can update
2819 * the domain values for our changes.
2821 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2822 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2824 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2825 obj_priv
->dirty
= 1;
2828 trace_i915_gem_object_change_domain(obj
,
2836 * Prepare buffer for display plane. Use uninterruptible for possible flush
2837 * wait, as in modesetting process we're not supposed to be interrupted.
2840 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2842 struct drm_device
*dev
= obj
->dev
;
2843 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2844 uint32_t old_write_domain
, old_read_domains
;
2847 /* Not valid to be called on unbound objects. */
2848 if (obj_priv
->gtt_space
== NULL
)
2851 i915_gem_object_flush_gpu_write_domain(obj
);
2853 /* Wait on any GPU rendering and flushing to occur. */
2854 if (obj_priv
->active
) {
2856 DRM_INFO("%s: object %p wait for seqno %08x\n",
2857 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2859 ret
= i915_do_wait_request(dev
, obj_priv
->last_rendering_seqno
, 0);
2864 old_write_domain
= obj
->write_domain
;
2865 old_read_domains
= obj
->read_domains
;
2867 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2869 i915_gem_object_flush_cpu_write_domain(obj
);
2871 /* It should now be out of any other write domains, and we can update
2872 * the domain values for our changes.
2874 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2875 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2876 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2877 obj_priv
->dirty
= 1;
2879 trace_i915_gem_object_change_domain(obj
,
2887 * Moves a single object to the CPU read, and possibly write domain.
2889 * This function returns when the move is complete, including waiting on
2893 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2895 uint32_t old_write_domain
, old_read_domains
;
2898 i915_gem_object_flush_gpu_write_domain(obj
);
2899 /* Wait on any GPU rendering and flushing to occur. */
2900 ret
= i915_gem_object_wait_rendering(obj
);
2904 i915_gem_object_flush_gtt_write_domain(obj
);
2906 /* If we have a partially-valid cache of the object in the CPU,
2907 * finish invalidating it and free the per-page flags.
2909 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2911 old_write_domain
= obj
->write_domain
;
2912 old_read_domains
= obj
->read_domains
;
2914 /* Flush the CPU cache if it's still invalid. */
2915 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2916 i915_gem_clflush_object(obj
);
2918 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2921 /* It should now be out of any other write domains, and we can update
2922 * the domain values for our changes.
2924 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2926 /* If we're writing through the CPU, then the GPU read domains will
2927 * need to be invalidated at next use.
2930 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2931 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2934 trace_i915_gem_object_change_domain(obj
,
2942 * Set the next domain for the specified object. This
2943 * may not actually perform the necessary flushing/invaliding though,
2944 * as that may want to be batched with other set_domain operations
2946 * This is (we hope) the only really tricky part of gem. The goal
2947 * is fairly simple -- track which caches hold bits of the object
2948 * and make sure they remain coherent. A few concrete examples may
2949 * help to explain how it works. For shorthand, we use the notation
2950 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2951 * a pair of read and write domain masks.
2953 * Case 1: the batch buffer
2959 * 5. Unmapped from GTT
2962 * Let's take these a step at a time
2965 * Pages allocated from the kernel may still have
2966 * cache contents, so we set them to (CPU, CPU) always.
2967 * 2. Written by CPU (using pwrite)
2968 * The pwrite function calls set_domain (CPU, CPU) and
2969 * this function does nothing (as nothing changes)
2971 * This function asserts that the object is not
2972 * currently in any GPU-based read or write domains
2974 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2975 * As write_domain is zero, this function adds in the
2976 * current read domains (CPU+COMMAND, 0).
2977 * flush_domains is set to CPU.
2978 * invalidate_domains is set to COMMAND
2979 * clflush is run to get data out of the CPU caches
2980 * then i915_dev_set_domain calls i915_gem_flush to
2981 * emit an MI_FLUSH and drm_agp_chipset_flush
2982 * 5. Unmapped from GTT
2983 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2984 * flush_domains and invalidate_domains end up both zero
2985 * so no flushing/invalidating happens
2989 * Case 2: The shared render buffer
2993 * 3. Read/written by GPU
2994 * 4. set_domain to (CPU,CPU)
2995 * 5. Read/written by CPU
2996 * 6. Read/written by GPU
2999 * Same as last example, (CPU, CPU)
3001 * Nothing changes (assertions find that it is not in the GPU)
3002 * 3. Read/written by GPU
3003 * execbuffer calls set_domain (RENDER, RENDER)
3004 * flush_domains gets CPU
3005 * invalidate_domains gets GPU
3007 * MI_FLUSH and drm_agp_chipset_flush
3008 * 4. set_domain (CPU, CPU)
3009 * flush_domains gets GPU
3010 * invalidate_domains gets CPU
3011 * wait_rendering (obj) to make sure all drawing is complete.
3012 * This will include an MI_FLUSH to get the data from GPU
3014 * clflush (obj) to invalidate the CPU cache
3015 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3016 * 5. Read/written by CPU
3017 * cache lines are loaded and dirtied
3018 * 6. Read written by GPU
3019 * Same as last GPU access
3021 * Case 3: The constant buffer
3026 * 4. Updated (written) by CPU again
3035 * flush_domains = CPU
3036 * invalidate_domains = RENDER
3039 * drm_agp_chipset_flush
3040 * 4. Updated (written) by CPU again
3042 * flush_domains = 0 (no previous write domain)
3043 * invalidate_domains = 0 (no new read domains)
3046 * flush_domains = CPU
3047 * invalidate_domains = RENDER
3050 * drm_agp_chipset_flush
3053 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3055 struct drm_device
*dev
= obj
->dev
;
3056 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3057 uint32_t invalidate_domains
= 0;
3058 uint32_t flush_domains
= 0;
3059 uint32_t old_read_domains
;
3061 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3062 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3064 intel_mark_busy(dev
, obj
);
3067 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3069 obj
->read_domains
, obj
->pending_read_domains
,
3070 obj
->write_domain
, obj
->pending_write_domain
);
3073 * If the object isn't moving to a new write domain,
3074 * let the object stay in multiple read domains
3076 if (obj
->pending_write_domain
== 0)
3077 obj
->pending_read_domains
|= obj
->read_domains
;
3079 obj_priv
->dirty
= 1;
3082 * Flush the current write domain if
3083 * the new read domains don't match. Invalidate
3084 * any read domains which differ from the old
3087 if (obj
->write_domain
&&
3088 obj
->write_domain
!= obj
->pending_read_domains
) {
3089 flush_domains
|= obj
->write_domain
;
3090 invalidate_domains
|=
3091 obj
->pending_read_domains
& ~obj
->write_domain
;
3094 * Invalidate any read caches which may have
3095 * stale data. That is, any new read domains.
3097 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3098 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3100 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3101 __func__
, flush_domains
, invalidate_domains
);
3103 i915_gem_clflush_object(obj
);
3106 old_read_domains
= obj
->read_domains
;
3108 /* The actual obj->write_domain will be updated with
3109 * pending_write_domain after we emit the accumulated flush for all
3110 * of our domain changes in execbuffers (which clears objects'
3111 * write_domains). So if we have a current write domain that we
3112 * aren't changing, set pending_write_domain to that.
3114 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3115 obj
->pending_write_domain
= obj
->write_domain
;
3116 obj
->read_domains
= obj
->pending_read_domains
;
3118 dev
->invalidate_domains
|= invalidate_domains
;
3119 dev
->flush_domains
|= flush_domains
;
3121 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3123 obj
->read_domains
, obj
->write_domain
,
3124 dev
->invalidate_domains
, dev
->flush_domains
);
3127 trace_i915_gem_object_change_domain(obj
,
3133 * Moves the object from a partially CPU read to a full one.
3135 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3136 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3139 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3141 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3143 if (!obj_priv
->page_cpu_valid
)
3146 /* If we're partially in the CPU read domain, finish moving it in.
3148 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3151 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3152 if (obj_priv
->page_cpu_valid
[i
])
3154 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3158 /* Free the page_cpu_valid mappings which are now stale, whether
3159 * or not we've got I915_GEM_DOMAIN_CPU.
3161 kfree(obj_priv
->page_cpu_valid
);
3162 obj_priv
->page_cpu_valid
= NULL
;
3166 * Set the CPU read domain on a range of the object.
3168 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3169 * not entirely valid. The page_cpu_valid member of the object flags which
3170 * pages have been flushed, and will be respected by
3171 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3172 * of the whole object.
3174 * This function returns when the move is complete, including waiting on
3178 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3179 uint64_t offset
, uint64_t size
)
3181 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3182 uint32_t old_read_domains
;
3185 if (offset
== 0 && size
== obj
->size
)
3186 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3188 i915_gem_object_flush_gpu_write_domain(obj
);
3189 /* Wait on any GPU rendering and flushing to occur. */
3190 ret
= i915_gem_object_wait_rendering(obj
);
3193 i915_gem_object_flush_gtt_write_domain(obj
);
3195 /* If we're already fully in the CPU read domain, we're done. */
3196 if (obj_priv
->page_cpu_valid
== NULL
&&
3197 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3200 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3201 * newly adding I915_GEM_DOMAIN_CPU
3203 if (obj_priv
->page_cpu_valid
== NULL
) {
3204 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3206 if (obj_priv
->page_cpu_valid
== NULL
)
3208 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3209 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3211 /* Flush the cache on any pages that are still invalid from the CPU's
3214 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3216 if (obj_priv
->page_cpu_valid
[i
])
3219 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3221 obj_priv
->page_cpu_valid
[i
] = 1;
3224 /* It should now be out of any other write domains, and we can update
3225 * the domain values for our changes.
3227 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3229 old_read_domains
= obj
->read_domains
;
3230 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3232 trace_i915_gem_object_change_domain(obj
,
3240 * Pin an object to the GTT and evaluate the relocations landing in it.
3243 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3244 struct drm_file
*file_priv
,
3245 struct drm_i915_gem_exec_object2
*entry
,
3246 struct drm_i915_gem_relocation_entry
*relocs
)
3248 struct drm_device
*dev
= obj
->dev
;
3249 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3250 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3252 void __iomem
*reloc_page
;
3255 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3256 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3258 /* Check fence reg constraints and rebind if necessary */
3259 if (need_fence
&& !i915_gem_object_fence_offset_ok(obj
,
3260 obj_priv
->tiling_mode
))
3261 i915_gem_object_unbind(obj
);
3263 /* Choose the GTT offset for our buffer and put it there. */
3264 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3269 * Pre-965 chips need a fence register set up in order to
3270 * properly handle blits to/from tiled surfaces.
3273 ret
= i915_gem_object_get_fence_reg(obj
);
3275 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3276 DRM_ERROR("Failure to install fence: %d\n",
3278 i915_gem_object_unpin(obj
);
3283 entry
->offset
= obj_priv
->gtt_offset
;
3285 /* Apply the relocations, using the GTT aperture to avoid cache
3286 * flushing requirements.
3288 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3289 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3290 struct drm_gem_object
*target_obj
;
3291 struct drm_i915_gem_object
*target_obj_priv
;
3292 uint32_t reloc_val
, reloc_offset
;
3293 uint32_t __iomem
*reloc_entry
;
3295 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3296 reloc
->target_handle
);
3297 if (target_obj
== NULL
) {
3298 i915_gem_object_unpin(obj
);
3301 target_obj_priv
= target_obj
->driver_private
;
3304 DRM_INFO("%s: obj %p offset %08x target %d "
3305 "read %08x write %08x gtt %08x "
3306 "presumed %08x delta %08x\n",
3309 (int) reloc
->offset
,
3310 (int) reloc
->target_handle
,
3311 (int) reloc
->read_domains
,
3312 (int) reloc
->write_domain
,
3313 (int) target_obj_priv
->gtt_offset
,
3314 (int) reloc
->presumed_offset
,
3318 /* The target buffer should have appeared before us in the
3319 * exec_object list, so it should have a GTT space bound by now.
3321 if (target_obj_priv
->gtt_space
== NULL
) {
3322 DRM_ERROR("No GTT space found for object %d\n",
3323 reloc
->target_handle
);
3324 drm_gem_object_unreference(target_obj
);
3325 i915_gem_object_unpin(obj
);
3329 /* Validate that the target is in a valid r/w GPU domain */
3330 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3331 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3332 DRM_ERROR("reloc with read/write CPU domains: "
3333 "obj %p target %d offset %d "
3334 "read %08x write %08x",
3335 obj
, reloc
->target_handle
,
3336 (int) reloc
->offset
,
3337 reloc
->read_domains
,
3338 reloc
->write_domain
);
3339 drm_gem_object_unreference(target_obj
);
3340 i915_gem_object_unpin(obj
);
3343 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3344 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3345 DRM_ERROR("Write domain conflict: "
3346 "obj %p target %d offset %d "
3347 "new %08x old %08x\n",
3348 obj
, reloc
->target_handle
,
3349 (int) reloc
->offset
,
3350 reloc
->write_domain
,
3351 target_obj
->pending_write_domain
);
3352 drm_gem_object_unreference(target_obj
);
3353 i915_gem_object_unpin(obj
);
3357 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3358 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3360 /* If the relocation already has the right value in it, no
3361 * more work needs to be done.
3363 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3364 drm_gem_object_unreference(target_obj
);
3368 /* Check that the relocation address is valid... */
3369 if (reloc
->offset
> obj
->size
- 4) {
3370 DRM_ERROR("Relocation beyond object bounds: "
3371 "obj %p target %d offset %d size %d.\n",
3372 obj
, reloc
->target_handle
,
3373 (int) reloc
->offset
, (int) obj
->size
);
3374 drm_gem_object_unreference(target_obj
);
3375 i915_gem_object_unpin(obj
);
3378 if (reloc
->offset
& 3) {
3379 DRM_ERROR("Relocation not 4-byte aligned: "
3380 "obj %p target %d offset %d.\n",
3381 obj
, reloc
->target_handle
,
3382 (int) reloc
->offset
);
3383 drm_gem_object_unreference(target_obj
);
3384 i915_gem_object_unpin(obj
);
3388 /* and points to somewhere within the target object. */
3389 if (reloc
->delta
>= target_obj
->size
) {
3390 DRM_ERROR("Relocation beyond target object bounds: "
3391 "obj %p target %d delta %d size %d.\n",
3392 obj
, reloc
->target_handle
,
3393 (int) reloc
->delta
, (int) target_obj
->size
);
3394 drm_gem_object_unreference(target_obj
);
3395 i915_gem_object_unpin(obj
);
3399 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3401 drm_gem_object_unreference(target_obj
);
3402 i915_gem_object_unpin(obj
);
3406 /* Map the page containing the relocation we're going to
3409 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3410 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3413 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3414 (reloc_offset
& (PAGE_SIZE
- 1)));
3415 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3418 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3419 obj
, (unsigned int) reloc
->offset
,
3420 readl(reloc_entry
), reloc_val
);
3422 writel(reloc_val
, reloc_entry
);
3423 io_mapping_unmap_atomic(reloc_page
);
3425 /* The updated presumed offset for this entry will be
3426 * copied back out to the user.
3428 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3430 drm_gem_object_unreference(target_obj
);
3435 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3440 /** Dispatch a batchbuffer to the ring
3443 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3444 struct drm_i915_gem_execbuffer2
*exec
,
3445 struct drm_clip_rect
*cliprects
,
3446 uint64_t exec_offset
)
3448 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3449 int nbox
= exec
->num_cliprects
;
3451 uint32_t exec_start
, exec_len
;
3454 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3455 exec_len
= (uint32_t) exec
->batch_len
;
3457 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3459 count
= nbox
? nbox
: 1;
3461 for (i
= 0; i
< count
; i
++) {
3463 int ret
= i915_emit_box(dev
, cliprects
, i
,
3464 exec
->DR1
, exec
->DR4
);
3469 if (IS_I830(dev
) || IS_845G(dev
)) {
3471 OUT_RING(MI_BATCH_BUFFER
);
3472 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3473 OUT_RING(exec_start
+ exec_len
- 4);
3478 if (IS_I965G(dev
)) {
3479 OUT_RING(MI_BATCH_BUFFER_START
|
3481 MI_BATCH_NON_SECURE_I965
);
3482 OUT_RING(exec_start
);
3484 OUT_RING(MI_BATCH_BUFFER_START
|
3486 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3492 /* XXX breadcrumb */
3496 /* Throttle our rendering by waiting until the ring has completed our requests
3497 * emitted over 20 msec ago.
3499 * Note that if we were to use the current jiffies each time around the loop,
3500 * we wouldn't escape the function with any frames outstanding if the time to
3501 * render a frame was over 20ms.
3503 * This should get us reasonable parallelism between CPU and GPU but also
3504 * relatively low latency when blocking on a particular request to finish.
3507 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3509 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3511 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3513 mutex_lock(&dev
->struct_mutex
);
3514 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3515 struct drm_i915_gem_request
*request
;
3517 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3518 struct drm_i915_gem_request
,
3521 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3524 ret
= i915_wait_request(dev
, request
->seqno
);
3528 mutex_unlock(&dev
->struct_mutex
);
3534 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3535 uint32_t buffer_count
,
3536 struct drm_i915_gem_relocation_entry
**relocs
)
3538 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3542 for (i
= 0; i
< buffer_count
; i
++) {
3543 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3545 reloc_count
+= exec_list
[i
].relocation_count
;
3548 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3549 if (*relocs
== NULL
) {
3550 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3554 for (i
= 0; i
< buffer_count
; i
++) {
3555 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3557 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3559 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3561 exec_list
[i
].relocation_count
*
3564 drm_free_large(*relocs
);
3569 reloc_index
+= exec_list
[i
].relocation_count
;
3576 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3577 uint32_t buffer_count
,
3578 struct drm_i915_gem_relocation_entry
*relocs
)
3580 uint32_t reloc_count
= 0, i
;
3586 for (i
= 0; i
< buffer_count
; i
++) {
3587 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3590 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3592 unwritten
= copy_to_user(user_relocs
,
3593 &relocs
[reloc_count
],
3594 exec_list
[i
].relocation_count
*
3602 reloc_count
+= exec_list
[i
].relocation_count
;
3606 drm_free_large(relocs
);
3612 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3613 uint64_t exec_offset
)
3615 uint32_t exec_start
, exec_len
;
3617 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3618 exec_len
= (uint32_t) exec
->batch_len
;
3620 if ((exec_start
| exec_len
) & 0x7)
3630 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3631 struct drm_gem_object
**object_list
,
3634 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3635 struct drm_i915_gem_object
*obj_priv
;
3640 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3641 &wait
, TASK_INTERRUPTIBLE
);
3642 for (i
= 0; i
< count
; i
++) {
3643 obj_priv
= object_list
[i
]->driver_private
;
3644 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3650 if (!signal_pending(current
)) {
3651 mutex_unlock(&dev
->struct_mutex
);
3653 mutex_lock(&dev
->struct_mutex
);
3659 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3665 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3666 struct drm_file
*file_priv
,
3667 struct drm_i915_gem_execbuffer2
*args
,
3668 struct drm_i915_gem_exec_object2
*exec_list
)
3670 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3671 struct drm_gem_object
**object_list
= NULL
;
3672 struct drm_gem_object
*batch_obj
;
3673 struct drm_i915_gem_object
*obj_priv
;
3674 struct drm_clip_rect
*cliprects
= NULL
;
3675 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3676 int ret
= 0, ret2
, i
, pinned
= 0;
3677 uint64_t exec_offset
;
3678 uint32_t seqno
, flush_domains
, reloc_index
;
3679 int pin_tries
, flips
;
3682 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3683 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3686 if (args
->buffer_count
< 1) {
3687 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3690 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3691 if (object_list
== NULL
) {
3692 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3693 args
->buffer_count
);
3698 if (args
->num_cliprects
!= 0) {
3699 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3701 if (cliprects
== NULL
) {
3706 ret
= copy_from_user(cliprects
,
3707 (struct drm_clip_rect __user
*)
3708 (uintptr_t) args
->cliprects_ptr
,
3709 sizeof(*cliprects
) * args
->num_cliprects
);
3711 DRM_ERROR("copy %d cliprects failed: %d\n",
3712 args
->num_cliprects
, ret
);
3717 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3722 mutex_lock(&dev
->struct_mutex
);
3724 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3726 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3727 mutex_unlock(&dev
->struct_mutex
);
3732 if (dev_priv
->mm
.suspended
) {
3733 mutex_unlock(&dev
->struct_mutex
);
3738 /* Look up object handles */
3740 for (i
= 0; i
< args
->buffer_count
; i
++) {
3741 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3742 exec_list
[i
].handle
);
3743 if (object_list
[i
] == NULL
) {
3744 DRM_ERROR("Invalid object handle %d at index %d\n",
3745 exec_list
[i
].handle
, i
);
3746 /* prevent error path from reading uninitialized data */
3747 args
->buffer_count
= i
+ 1;
3752 obj_priv
= object_list
[i
]->driver_private
;
3753 if (obj_priv
->in_execbuffer
) {
3754 DRM_ERROR("Object %p appears more than once in object list\n",
3756 /* prevent error path from reading uninitialized data */
3757 args
->buffer_count
= i
+ 1;
3761 obj_priv
->in_execbuffer
= true;
3762 flips
+= atomic_read(&obj_priv
->pending_flip
);
3766 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3767 args
->buffer_count
);
3772 /* Pin and relocate */
3773 for (pin_tries
= 0; ; pin_tries
++) {
3777 for (i
= 0; i
< args
->buffer_count
; i
++) {
3778 object_list
[i
]->pending_read_domains
= 0;
3779 object_list
[i
]->pending_write_domain
= 0;
3780 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3783 &relocs
[reloc_index
]);
3787 reloc_index
+= exec_list
[i
].relocation_count
;
3793 /* error other than GTT full, or we've already tried again */
3794 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3795 if (ret
!= -ERESTARTSYS
) {
3796 unsigned long long total_size
= 0;
3797 for (i
= 0; i
< args
->buffer_count
; i
++)
3798 total_size
+= object_list
[i
]->size
;
3799 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3800 pinned
+1, args
->buffer_count
,
3802 DRM_ERROR("%d objects [%d pinned], "
3803 "%d object bytes [%d pinned], "
3804 "%d/%d gtt bytes\n",
3805 atomic_read(&dev
->object_count
),
3806 atomic_read(&dev
->pin_count
),
3807 atomic_read(&dev
->object_memory
),
3808 atomic_read(&dev
->pin_memory
),
3809 atomic_read(&dev
->gtt_memory
),
3815 /* unpin all of our buffers */
3816 for (i
= 0; i
< pinned
; i
++)
3817 i915_gem_object_unpin(object_list
[i
]);
3820 /* evict everyone we can from the aperture */
3821 ret
= i915_gem_evict_everything(dev
);
3822 if (ret
&& ret
!= -ENOSPC
)
3826 /* Set the pending read domains for the batch buffer to COMMAND */
3827 batch_obj
= object_list
[args
->buffer_count
-1];
3828 if (batch_obj
->pending_write_domain
) {
3829 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3833 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3835 /* Sanity check the batch buffer, prior to moving objects */
3836 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3837 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3839 DRM_ERROR("execbuf with invalid offset/length\n");
3843 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3845 /* Zero the global flush/invalidate flags. These
3846 * will be modified as new domains are computed
3849 dev
->invalidate_domains
= 0;
3850 dev
->flush_domains
= 0;
3852 for (i
= 0; i
< args
->buffer_count
; i
++) {
3853 struct drm_gem_object
*obj
= object_list
[i
];
3855 /* Compute new gpu domains and update invalidate/flush */
3856 i915_gem_object_set_to_gpu_domain(obj
);
3859 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3861 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3863 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3865 dev
->invalidate_domains
,
3866 dev
->flush_domains
);
3869 dev
->invalidate_domains
,
3870 dev
->flush_domains
);
3871 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
)
3872 (void)i915_add_request(dev
, file_priv
,
3873 dev
->flush_domains
);
3876 for (i
= 0; i
< args
->buffer_count
; i
++) {
3877 struct drm_gem_object
*obj
= object_list
[i
];
3878 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3879 uint32_t old_write_domain
= obj
->write_domain
;
3881 obj
->write_domain
= obj
->pending_write_domain
;
3882 if (obj
->write_domain
)
3883 list_move_tail(&obj_priv
->gpu_write_list
,
3884 &dev_priv
->mm
.gpu_write_list
);
3886 list_del_init(&obj_priv
->gpu_write_list
);
3888 trace_i915_gem_object_change_domain(obj
,
3893 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3896 for (i
= 0; i
< args
->buffer_count
; i
++) {
3897 i915_gem_object_check_coherency(object_list
[i
],
3898 exec_list
[i
].handle
);
3903 i915_gem_dump_object(batch_obj
,
3909 /* Exec the batchbuffer */
3910 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3912 DRM_ERROR("dispatch failed %d\n", ret
);
3917 * Ensure that the commands in the batch buffer are
3918 * finished before the interrupt fires
3920 flush_domains
= i915_retire_commands(dev
);
3922 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3925 * Get a seqno representing the execution of the current buffer,
3926 * which we can wait on. We would like to mitigate these interrupts,
3927 * likely by only creating seqnos occasionally (so that we have
3928 * *some* interrupts representing completion of buffers that we can
3929 * wait on when trying to clear up gtt space).
3931 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3933 for (i
= 0; i
< args
->buffer_count
; i
++) {
3934 struct drm_gem_object
*obj
= object_list
[i
];
3936 i915_gem_object_move_to_active(obj
, seqno
);
3938 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3942 i915_dump_lru(dev
, __func__
);
3945 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3948 for (i
= 0; i
< pinned
; i
++)
3949 i915_gem_object_unpin(object_list
[i
]);
3951 for (i
= 0; i
< args
->buffer_count
; i
++) {
3952 if (object_list
[i
]) {
3953 obj_priv
= object_list
[i
]->driver_private
;
3954 obj_priv
->in_execbuffer
= false;
3956 drm_gem_object_unreference(object_list
[i
]);
3959 mutex_unlock(&dev
->struct_mutex
);
3962 /* Copy the updated relocations out regardless of current error
3963 * state. Failure to update the relocs would mean that the next
3964 * time userland calls execbuf, it would do so with presumed offset
3965 * state that didn't match the actual object state.
3967 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3970 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3976 drm_free_large(object_list
);
3983 * Legacy execbuffer just creates an exec2 list from the original exec object
3984 * list array and passes it to the real function.
3987 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3988 struct drm_file
*file_priv
)
3990 struct drm_i915_gem_execbuffer
*args
= data
;
3991 struct drm_i915_gem_execbuffer2 exec2
;
3992 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3993 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3997 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3998 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4001 if (args
->buffer_count
< 1) {
4002 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4006 /* Copy in the exec list from userland */
4007 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4008 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4009 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4010 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4011 args
->buffer_count
);
4012 drm_free_large(exec_list
);
4013 drm_free_large(exec2_list
);
4016 ret
= copy_from_user(exec_list
,
4017 (struct drm_i915_relocation_entry __user
*)
4018 (uintptr_t) args
->buffers_ptr
,
4019 sizeof(*exec_list
) * args
->buffer_count
);
4021 DRM_ERROR("copy %d exec entries failed %d\n",
4022 args
->buffer_count
, ret
);
4023 drm_free_large(exec_list
);
4024 drm_free_large(exec2_list
);
4028 for (i
= 0; i
< args
->buffer_count
; i
++) {
4029 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4030 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4031 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4032 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4033 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4035 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4037 exec2_list
[i
].flags
= 0;
4040 exec2
.buffers_ptr
= args
->buffers_ptr
;
4041 exec2
.buffer_count
= args
->buffer_count
;
4042 exec2
.batch_start_offset
= args
->batch_start_offset
;
4043 exec2
.batch_len
= args
->batch_len
;
4044 exec2
.DR1
= args
->DR1
;
4045 exec2
.DR4
= args
->DR4
;
4046 exec2
.num_cliprects
= args
->num_cliprects
;
4047 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4050 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4052 /* Copy the new buffer offsets back to the user's exec list. */
4053 for (i
= 0; i
< args
->buffer_count
; i
++)
4054 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4055 /* ... and back out to userspace */
4056 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4057 (uintptr_t) args
->buffers_ptr
,
4059 sizeof(*exec_list
) * args
->buffer_count
);
4062 DRM_ERROR("failed to copy %d exec entries "
4063 "back to user (%d)\n",
4064 args
->buffer_count
, ret
);
4068 drm_free_large(exec_list
);
4069 drm_free_large(exec2_list
);
4074 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4075 struct drm_file
*file_priv
)
4077 struct drm_i915_gem_execbuffer2
*args
= data
;
4078 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4082 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4083 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4086 if (args
->buffer_count
< 1) {
4087 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4091 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4092 if (exec2_list
== NULL
) {
4093 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4094 args
->buffer_count
);
4097 ret
= copy_from_user(exec2_list
,
4098 (struct drm_i915_relocation_entry __user
*)
4099 (uintptr_t) args
->buffers_ptr
,
4100 sizeof(*exec2_list
) * args
->buffer_count
);
4102 DRM_ERROR("copy %d exec entries failed %d\n",
4103 args
->buffer_count
, ret
);
4104 drm_free_large(exec2_list
);
4108 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4110 /* Copy the new buffer offsets back to the user's exec list. */
4111 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4112 (uintptr_t) args
->buffers_ptr
,
4114 sizeof(*exec2_list
) * args
->buffer_count
);
4117 DRM_ERROR("failed to copy %d exec entries "
4118 "back to user (%d)\n",
4119 args
->buffer_count
, ret
);
4123 drm_free_large(exec2_list
);
4128 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4130 struct drm_device
*dev
= obj
->dev
;
4131 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4134 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4135 if (obj_priv
->gtt_space
== NULL
) {
4136 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4141 obj_priv
->pin_count
++;
4143 /* If the object is not active and not pending a flush,
4144 * remove it from the inactive list
4146 if (obj_priv
->pin_count
== 1) {
4147 atomic_inc(&dev
->pin_count
);
4148 atomic_add(obj
->size
, &dev
->pin_memory
);
4149 if (!obj_priv
->active
&&
4150 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4151 !list_empty(&obj_priv
->list
))
4152 list_del_init(&obj_priv
->list
);
4154 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4160 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4162 struct drm_device
*dev
= obj
->dev
;
4163 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4164 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4166 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4167 obj_priv
->pin_count
--;
4168 BUG_ON(obj_priv
->pin_count
< 0);
4169 BUG_ON(obj_priv
->gtt_space
== NULL
);
4171 /* If the object is no longer pinned, and is
4172 * neither active nor being flushed, then stick it on
4175 if (obj_priv
->pin_count
== 0) {
4176 if (!obj_priv
->active
&&
4177 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4178 list_move_tail(&obj_priv
->list
,
4179 &dev_priv
->mm
.inactive_list
);
4180 atomic_dec(&dev
->pin_count
);
4181 atomic_sub(obj
->size
, &dev
->pin_memory
);
4183 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4187 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4188 struct drm_file
*file_priv
)
4190 struct drm_i915_gem_pin
*args
= data
;
4191 struct drm_gem_object
*obj
;
4192 struct drm_i915_gem_object
*obj_priv
;
4195 mutex_lock(&dev
->struct_mutex
);
4197 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4199 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4201 mutex_unlock(&dev
->struct_mutex
);
4204 obj_priv
= obj
->driver_private
;
4206 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4207 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4208 drm_gem_object_unreference(obj
);
4209 mutex_unlock(&dev
->struct_mutex
);
4213 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4214 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4216 drm_gem_object_unreference(obj
);
4217 mutex_unlock(&dev
->struct_mutex
);
4221 obj_priv
->user_pin_count
++;
4222 obj_priv
->pin_filp
= file_priv
;
4223 if (obj_priv
->user_pin_count
== 1) {
4224 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4226 drm_gem_object_unreference(obj
);
4227 mutex_unlock(&dev
->struct_mutex
);
4232 /* XXX - flush the CPU caches for pinned objects
4233 * as the X server doesn't manage domains yet
4235 i915_gem_object_flush_cpu_write_domain(obj
);
4236 args
->offset
= obj_priv
->gtt_offset
;
4237 drm_gem_object_unreference(obj
);
4238 mutex_unlock(&dev
->struct_mutex
);
4244 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4245 struct drm_file
*file_priv
)
4247 struct drm_i915_gem_pin
*args
= data
;
4248 struct drm_gem_object
*obj
;
4249 struct drm_i915_gem_object
*obj_priv
;
4251 mutex_lock(&dev
->struct_mutex
);
4253 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4255 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4257 mutex_unlock(&dev
->struct_mutex
);
4261 obj_priv
= obj
->driver_private
;
4262 if (obj_priv
->pin_filp
!= file_priv
) {
4263 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4265 drm_gem_object_unreference(obj
);
4266 mutex_unlock(&dev
->struct_mutex
);
4269 obj_priv
->user_pin_count
--;
4270 if (obj_priv
->user_pin_count
== 0) {
4271 obj_priv
->pin_filp
= NULL
;
4272 i915_gem_object_unpin(obj
);
4275 drm_gem_object_unreference(obj
);
4276 mutex_unlock(&dev
->struct_mutex
);
4281 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4282 struct drm_file
*file_priv
)
4284 struct drm_i915_gem_busy
*args
= data
;
4285 struct drm_gem_object
*obj
;
4286 struct drm_i915_gem_object
*obj_priv
;
4288 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4290 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4295 mutex_lock(&dev
->struct_mutex
);
4296 /* Update the active list for the hardware's current position.
4297 * Otherwise this only updates on a delayed timer or when irqs are
4298 * actually unmasked, and our working set ends up being larger than
4301 i915_gem_retire_requests(dev
);
4303 obj_priv
= obj
->driver_private
;
4304 /* Don't count being on the flushing list against the object being
4305 * done. Otherwise, a buffer left on the flushing list but not getting
4306 * flushed (because nobody's flushing that domain) won't ever return
4307 * unbusy and get reused by libdrm's bo cache. The other expected
4308 * consumer of this interface, OpenGL's occlusion queries, also specs
4309 * that the objects get unbusy "eventually" without any interference.
4311 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4313 drm_gem_object_unreference(obj
);
4314 mutex_unlock(&dev
->struct_mutex
);
4319 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4320 struct drm_file
*file_priv
)
4322 return i915_gem_ring_throttle(dev
, file_priv
);
4326 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4327 struct drm_file
*file_priv
)
4329 struct drm_i915_gem_madvise
*args
= data
;
4330 struct drm_gem_object
*obj
;
4331 struct drm_i915_gem_object
*obj_priv
;
4333 switch (args
->madv
) {
4334 case I915_MADV_DONTNEED
:
4335 case I915_MADV_WILLNEED
:
4341 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4343 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4348 mutex_lock(&dev
->struct_mutex
);
4349 obj_priv
= obj
->driver_private
;
4351 if (obj_priv
->pin_count
) {
4352 drm_gem_object_unreference(obj
);
4353 mutex_unlock(&dev
->struct_mutex
);
4355 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4359 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4360 obj_priv
->madv
= args
->madv
;
4362 /* if the object is no longer bound, discard its backing storage */
4363 if (i915_gem_object_is_purgeable(obj_priv
) &&
4364 obj_priv
->gtt_space
== NULL
)
4365 i915_gem_object_truncate(obj
);
4367 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4369 drm_gem_object_unreference(obj
);
4370 mutex_unlock(&dev
->struct_mutex
);
4375 int i915_gem_init_object(struct drm_gem_object
*obj
)
4377 struct drm_i915_gem_object
*obj_priv
;
4379 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4380 if (obj_priv
== NULL
)
4384 * We've just allocated pages from the kernel,
4385 * so they've just been written by the CPU with
4386 * zeros. They'll need to be clflushed before we
4387 * use them with the GPU.
4389 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4390 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4392 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4394 obj
->driver_private
= obj_priv
;
4395 obj_priv
->obj
= obj
;
4396 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4397 INIT_LIST_HEAD(&obj_priv
->list
);
4398 INIT_LIST_HEAD(&obj_priv
->gpu_write_list
);
4399 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4400 obj_priv
->madv
= I915_MADV_WILLNEED
;
4402 trace_i915_gem_object_create(obj
);
4407 void i915_gem_free_object(struct drm_gem_object
*obj
)
4409 struct drm_device
*dev
= obj
->dev
;
4410 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4412 trace_i915_gem_object_destroy(obj
);
4414 while (obj_priv
->pin_count
> 0)
4415 i915_gem_object_unpin(obj
);
4417 if (obj_priv
->phys_obj
)
4418 i915_gem_detach_phys_object(dev
, obj
);
4420 i915_gem_object_unbind(obj
);
4422 if (obj_priv
->mmap_offset
)
4423 i915_gem_free_mmap_offset(obj
);
4425 kfree(obj_priv
->page_cpu_valid
);
4426 kfree(obj_priv
->bit_17
);
4427 kfree(obj
->driver_private
);
4430 /** Unbinds all inactive objects. */
4432 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4436 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4437 struct drm_gem_object
*obj
;
4440 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4441 struct drm_i915_gem_object
,
4444 ret
= i915_gem_object_unbind(obj
);
4446 DRM_ERROR("Error unbinding object: %d\n", ret
);
4455 i915_gpu_idle(struct drm_device
*dev
)
4457 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4461 spin_lock(&dev_priv
->mm
.active_list_lock
);
4462 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4463 list_empty(&dev_priv
->mm
.active_list
);
4464 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4469 /* Flush everything onto the inactive list. */
4470 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4471 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4475 return i915_wait_request(dev
, seqno
);
4479 i915_gem_idle(struct drm_device
*dev
)
4481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4484 mutex_lock(&dev
->struct_mutex
);
4486 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4487 mutex_unlock(&dev
->struct_mutex
);
4491 ret
= i915_gpu_idle(dev
);
4493 mutex_unlock(&dev
->struct_mutex
);
4497 /* Under UMS, be paranoid and evict. */
4498 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4499 ret
= i915_gem_evict_from_inactive_list(dev
);
4501 mutex_unlock(&dev
->struct_mutex
);
4506 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4507 * We need to replace this with a semaphore, or something.
4508 * And not confound mm.suspended!
4510 dev_priv
->mm
.suspended
= 1;
4511 del_timer(&dev_priv
->hangcheck_timer
);
4513 i915_kernel_lost_context(dev
);
4514 i915_gem_cleanup_ringbuffer(dev
);
4516 mutex_unlock(&dev
->struct_mutex
);
4518 /* Cancel the retire work handler, which should be idle now. */
4519 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4525 i915_gem_init_hws(struct drm_device
*dev
)
4527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4528 struct drm_gem_object
*obj
;
4529 struct drm_i915_gem_object
*obj_priv
;
4532 /* If we need a physical address for the status page, it's already
4533 * initialized at driver load time.
4535 if (!I915_NEED_GFX_HWS(dev
))
4538 obj
= drm_gem_object_alloc(dev
, 4096);
4540 DRM_ERROR("Failed to allocate status page\n");
4543 obj_priv
= obj
->driver_private
;
4544 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4546 ret
= i915_gem_object_pin(obj
, 4096);
4548 drm_gem_object_unreference(obj
);
4552 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4554 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4555 if (dev_priv
->hw_status_page
== NULL
) {
4556 DRM_ERROR("Failed to map status page.\n");
4557 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4558 i915_gem_object_unpin(obj
);
4559 drm_gem_object_unreference(obj
);
4562 dev_priv
->hws_obj
= obj
;
4563 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4565 I915_WRITE(HWS_PGA_GEN6
, dev_priv
->status_gfx_addr
);
4566 I915_READ(HWS_PGA_GEN6
); /* posting read */
4568 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4569 I915_READ(HWS_PGA
); /* posting read */
4571 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4577 i915_gem_cleanup_hws(struct drm_device
*dev
)
4579 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4580 struct drm_gem_object
*obj
;
4581 struct drm_i915_gem_object
*obj_priv
;
4583 if (dev_priv
->hws_obj
== NULL
)
4586 obj
= dev_priv
->hws_obj
;
4587 obj_priv
= obj
->driver_private
;
4589 kunmap(obj_priv
->pages
[0]);
4590 i915_gem_object_unpin(obj
);
4591 drm_gem_object_unreference(obj
);
4592 dev_priv
->hws_obj
= NULL
;
4594 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4595 dev_priv
->hw_status_page
= NULL
;
4597 /* Write high address into HWS_PGA when disabling. */
4598 I915_WRITE(HWS_PGA
, 0x1ffff000);
4602 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4605 struct drm_gem_object
*obj
;
4606 struct drm_i915_gem_object
*obj_priv
;
4607 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4611 ret
= i915_gem_init_hws(dev
);
4615 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4617 DRM_ERROR("Failed to allocate ringbuffer\n");
4618 i915_gem_cleanup_hws(dev
);
4621 obj_priv
= obj
->driver_private
;
4623 ret
= i915_gem_object_pin(obj
, 4096);
4625 drm_gem_object_unreference(obj
);
4626 i915_gem_cleanup_hws(dev
);
4630 /* Set up the kernel mapping for the ring. */
4631 ring
->Size
= obj
->size
;
4633 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4634 ring
->map
.size
= obj
->size
;
4636 ring
->map
.flags
= 0;
4639 drm_core_ioremap_wc(&ring
->map
, dev
);
4640 if (ring
->map
.handle
== NULL
) {
4641 DRM_ERROR("Failed to map ringbuffer.\n");
4642 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4643 i915_gem_object_unpin(obj
);
4644 drm_gem_object_unreference(obj
);
4645 i915_gem_cleanup_hws(dev
);
4648 ring
->ring_obj
= obj
;
4649 ring
->virtual_start
= ring
->map
.handle
;
4651 /* Stop the ring if it's running. */
4652 I915_WRITE(PRB0_CTL
, 0);
4653 I915_WRITE(PRB0_TAIL
, 0);
4654 I915_WRITE(PRB0_HEAD
, 0);
4656 /* Initialize the ring. */
4657 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4658 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4660 /* G45 ring initialization fails to reset head to zero */
4662 DRM_ERROR("Ring head not reset to zero "
4663 "ctl %08x head %08x tail %08x start %08x\n",
4664 I915_READ(PRB0_CTL
),
4665 I915_READ(PRB0_HEAD
),
4666 I915_READ(PRB0_TAIL
),
4667 I915_READ(PRB0_START
));
4668 I915_WRITE(PRB0_HEAD
, 0);
4670 DRM_ERROR("Ring head forced to zero "
4671 "ctl %08x head %08x tail %08x start %08x\n",
4672 I915_READ(PRB0_CTL
),
4673 I915_READ(PRB0_HEAD
),
4674 I915_READ(PRB0_TAIL
),
4675 I915_READ(PRB0_START
));
4678 I915_WRITE(PRB0_CTL
,
4679 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4683 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4685 /* If the head is still not zero, the ring is dead */
4687 DRM_ERROR("Ring initialization failed "
4688 "ctl %08x head %08x tail %08x start %08x\n",
4689 I915_READ(PRB0_CTL
),
4690 I915_READ(PRB0_HEAD
),
4691 I915_READ(PRB0_TAIL
),
4692 I915_READ(PRB0_START
));
4696 /* Update our cache of the ring state */
4697 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4698 i915_kernel_lost_context(dev
);
4700 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4701 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4702 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4703 if (ring
->space
< 0)
4704 ring
->space
+= ring
->Size
;
4711 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4713 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4715 if (dev_priv
->ring
.ring_obj
== NULL
)
4718 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4720 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4721 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4722 dev_priv
->ring
.ring_obj
= NULL
;
4723 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4725 i915_gem_cleanup_hws(dev
);
4729 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4730 struct drm_file
*file_priv
)
4732 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4735 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4738 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4739 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4740 atomic_set(&dev_priv
->mm
.wedged
, 0);
4743 mutex_lock(&dev
->struct_mutex
);
4744 dev_priv
->mm
.suspended
= 0;
4746 ret
= i915_gem_init_ringbuffer(dev
);
4748 mutex_unlock(&dev
->struct_mutex
);
4752 spin_lock(&dev_priv
->mm
.active_list_lock
);
4753 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4754 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4756 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4757 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4758 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4759 mutex_unlock(&dev
->struct_mutex
);
4761 drm_irq_install(dev
);
4767 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4768 struct drm_file
*file_priv
)
4770 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4773 drm_irq_uninstall(dev
);
4774 return i915_gem_idle(dev
);
4778 i915_gem_lastclose(struct drm_device
*dev
)
4782 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4785 ret
= i915_gem_idle(dev
);
4787 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4791 i915_gem_load(struct drm_device
*dev
)
4794 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4796 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4797 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4798 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4799 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4800 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4801 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4802 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4803 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4804 i915_gem_retire_work_handler
);
4805 dev_priv
->mm
.next_gem_seqno
= 1;
4807 spin_lock(&shrink_list_lock
);
4808 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4809 spin_unlock(&shrink_list_lock
);
4811 /* Old X drivers will take 0-2 for front, back, depth buffers */
4812 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4813 dev_priv
->fence_reg_start
= 3;
4815 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4816 dev_priv
->num_fence_regs
= 16;
4818 dev_priv
->num_fence_regs
= 8;
4820 /* Initialize fence registers to zero */
4821 if (IS_I965G(dev
)) {
4822 for (i
= 0; i
< 16; i
++)
4823 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4825 for (i
= 0; i
< 8; i
++)
4826 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4827 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4828 for (i
= 0; i
< 8; i
++)
4829 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4831 i915_gem_detect_bit_6_swizzle(dev
);
4832 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4836 * Create a physically contiguous memory object for this object
4837 * e.g. for cursor + overlay regs
4839 int i915_gem_init_phys_object(struct drm_device
*dev
,
4842 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4843 struct drm_i915_gem_phys_object
*phys_obj
;
4846 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4849 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4855 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4856 if (!phys_obj
->handle
) {
4861 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4864 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4872 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4874 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4875 struct drm_i915_gem_phys_object
*phys_obj
;
4877 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4880 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4881 if (phys_obj
->cur_obj
) {
4882 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4886 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4888 drm_pci_free(dev
, phys_obj
->handle
);
4890 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4893 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4897 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4898 i915_gem_free_phys_object(dev
, i
);
4901 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4902 struct drm_gem_object
*obj
)
4904 struct drm_i915_gem_object
*obj_priv
;
4909 obj_priv
= obj
->driver_private
;
4910 if (!obj_priv
->phys_obj
)
4913 ret
= i915_gem_object_get_pages(obj
, 0);
4917 page_count
= obj
->size
/ PAGE_SIZE
;
4919 for (i
= 0; i
< page_count
; i
++) {
4920 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4921 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4923 memcpy(dst
, src
, PAGE_SIZE
);
4924 kunmap_atomic(dst
, KM_USER0
);
4926 drm_clflush_pages(obj_priv
->pages
, page_count
);
4927 drm_agp_chipset_flush(dev
);
4929 i915_gem_object_put_pages(obj
);
4931 obj_priv
->phys_obj
->cur_obj
= NULL
;
4932 obj_priv
->phys_obj
= NULL
;
4936 i915_gem_attach_phys_object(struct drm_device
*dev
,
4937 struct drm_gem_object
*obj
, int id
)
4939 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4940 struct drm_i915_gem_object
*obj_priv
;
4945 if (id
> I915_MAX_PHYS_OBJECT
)
4948 obj_priv
= obj
->driver_private
;
4950 if (obj_priv
->phys_obj
) {
4951 if (obj_priv
->phys_obj
->id
== id
)
4953 i915_gem_detach_phys_object(dev
, obj
);
4957 /* create a new object */
4958 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4959 ret
= i915_gem_init_phys_object(dev
, id
,
4962 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4967 /* bind to the object */
4968 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4969 obj_priv
->phys_obj
->cur_obj
= obj
;
4971 ret
= i915_gem_object_get_pages(obj
, 0);
4973 DRM_ERROR("failed to get page list\n");
4977 page_count
= obj
->size
/ PAGE_SIZE
;
4979 for (i
= 0; i
< page_count
; i
++) {
4980 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4981 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4983 memcpy(dst
, src
, PAGE_SIZE
);
4984 kunmap_atomic(src
, KM_USER0
);
4987 i915_gem_object_put_pages(obj
);
4995 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4996 struct drm_i915_gem_pwrite
*args
,
4997 struct drm_file
*file_priv
)
4999 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
5002 char __user
*user_data
;
5004 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5005 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5007 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
5008 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
5012 drm_agp_chipset_flush(dev
);
5016 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
5018 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
5020 /* Clean up our request list when the client is going away, so that
5021 * later retire_requests won't dereference our soon-to-be-gone
5024 mutex_lock(&dev
->struct_mutex
);
5025 while (!list_empty(&i915_file_priv
->mm
.request_list
))
5026 list_del_init(i915_file_priv
->mm
.request_list
.next
);
5027 mutex_unlock(&dev
->struct_mutex
);
5031 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
5033 drm_i915_private_t
*dev_priv
, *next_dev
;
5034 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5036 int would_deadlock
= 1;
5038 /* "fast-path" to count number of available objects */
5039 if (nr_to_scan
== 0) {
5040 spin_lock(&shrink_list_lock
);
5041 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5042 struct drm_device
*dev
= dev_priv
->dev
;
5044 if (mutex_trylock(&dev
->struct_mutex
)) {
5045 list_for_each_entry(obj_priv
,
5046 &dev_priv
->mm
.inactive_list
,
5049 mutex_unlock(&dev
->struct_mutex
);
5052 spin_unlock(&shrink_list_lock
);
5054 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5057 spin_lock(&shrink_list_lock
);
5059 /* first scan for clean buffers */
5060 list_for_each_entry_safe(dev_priv
, next_dev
,
5061 &shrink_list
, mm
.shrink_list
) {
5062 struct drm_device
*dev
= dev_priv
->dev
;
5064 if (! mutex_trylock(&dev
->struct_mutex
))
5067 spin_unlock(&shrink_list_lock
);
5069 i915_gem_retire_requests(dev
);
5071 list_for_each_entry_safe(obj_priv
, next_obj
,
5072 &dev_priv
->mm
.inactive_list
,
5074 if (i915_gem_object_is_purgeable(obj_priv
)) {
5075 i915_gem_object_unbind(obj_priv
->obj
);
5076 if (--nr_to_scan
<= 0)
5081 spin_lock(&shrink_list_lock
);
5082 mutex_unlock(&dev
->struct_mutex
);
5086 if (nr_to_scan
<= 0)
5090 /* second pass, evict/count anything still on the inactive list */
5091 list_for_each_entry_safe(dev_priv
, next_dev
,
5092 &shrink_list
, mm
.shrink_list
) {
5093 struct drm_device
*dev
= dev_priv
->dev
;
5095 if (! mutex_trylock(&dev
->struct_mutex
))
5098 spin_unlock(&shrink_list_lock
);
5100 list_for_each_entry_safe(obj_priv
, next_obj
,
5101 &dev_priv
->mm
.inactive_list
,
5103 if (nr_to_scan
> 0) {
5104 i915_gem_object_unbind(obj_priv
->obj
);
5110 spin_lock(&shrink_list_lock
);
5111 mutex_unlock(&dev
->struct_mutex
);
5116 spin_unlock(&shrink_list_lock
);
5121 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5126 static struct shrinker shrinker
= {
5127 .shrink
= i915_gem_shrink
,
5128 .seeks
= DEFAULT_SEEKS
,
5132 i915_gem_shrinker_init(void)
5134 register_shrinker(&shrinker
);
5138 i915_gem_shrinker_exit(void)
5140 unregister_shrinker(&shrinker
);