2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->error_completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
167 args
->gtt_end
, args
->gtt_end
);
168 mutex_unlock(&dev
->struct_mutex
);
174 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
175 struct drm_file
*file
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_gem_get_aperture
*args
= data
;
179 struct drm_i915_gem_object
*obj
;
183 mutex_lock(&dev
->struct_mutex
);
184 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
186 pinned
+= obj
->gtt_space
->size
;
187 mutex_unlock(&dev
->struct_mutex
);
189 args
->aper_size
= dev_priv
->mm
.gtt_total
;
190 args
->aper_available_size
= args
->aper_size
- pinned
;
196 i915_gem_create(struct drm_file
*file
,
197 struct drm_device
*dev
,
201 struct drm_i915_gem_object
*obj
;
205 size
= roundup(size
, PAGE_SIZE
);
209 /* Allocate the new object */
210 obj
= i915_gem_alloc_object(dev
, size
);
214 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
216 drm_gem_object_release(&obj
->base
);
217 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
222 /* drop reference from allocate - handle holds it now */
223 drm_gem_object_unreference(&obj
->base
);
224 trace_i915_gem_object_create(obj
);
231 i915_gem_dumb_create(struct drm_file
*file
,
232 struct drm_device
*dev
,
233 struct drm_mode_create_dumb
*args
)
235 /* have to work out size/pitch and return them */
236 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
237 args
->size
= args
->pitch
* args
->height
;
238 return i915_gem_create(file
, dev
,
239 args
->size
, &args
->handle
);
242 int i915_gem_dumb_destroy(struct drm_file
*file
,
243 struct drm_device
*dev
,
246 return drm_gem_handle_delete(file
, handle
);
250 * Creates a new mm object and returns a handle to it.
253 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
254 struct drm_file
*file
)
256 struct drm_i915_gem_create
*args
= data
;
258 return i915_gem_create(file
, dev
,
259 args
->size
, &args
->handle
);
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
264 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
266 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
267 obj
->tiling_mode
!= I915_TILING_NONE
;
271 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
272 const char *gpu_vaddr
, int gpu_offset
,
275 int ret
, cpu_offset
= 0;
278 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
279 int this_length
= min(cacheline_end
- gpu_offset
, length
);
280 int swizzled_gpu_offset
= gpu_offset
^ 64;
282 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
283 gpu_vaddr
+ swizzled_gpu_offset
,
288 cpu_offset
+= this_length
;
289 gpu_offset
+= this_length
;
290 length
-= this_length
;
297 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
298 const char __user
*cpu_vaddr
,
301 int ret
, cpu_offset
= 0;
304 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
305 int this_length
= min(cacheline_end
- gpu_offset
, length
);
306 int swizzled_gpu_offset
= gpu_offset
^ 64;
308 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
309 cpu_vaddr
+ cpu_offset
,
314 cpu_offset
+= this_length
;
315 gpu_offset
+= this_length
;
316 length
-= this_length
;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
327 char __user
*user_data
,
328 bool page_do_bit17_swizzling
, bool needs_clflush
)
333 if (unlikely(page_do_bit17_swizzling
))
336 vaddr
= kmap_atomic(page
);
338 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
340 ret
= __copy_to_user_inatomic(user_data
,
341 vaddr
+ shmem_page_offset
,
343 kunmap_atomic(vaddr
);
345 return ret
? -EFAULT
: 0;
349 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
352 if (unlikely(swizzled
)) {
353 unsigned long start
= (unsigned long) addr
;
354 unsigned long end
= (unsigned long) addr
+ length
;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start
= round_down(start
, 128);
361 end
= round_up(end
, 128);
363 drm_clflush_virt_range((void *)start
, end
- start
);
365 drm_clflush_virt_range(addr
, length
);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
374 char __user
*user_data
,
375 bool page_do_bit17_swizzling
, bool needs_clflush
)
382 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
384 page_do_bit17_swizzling
);
386 if (page_do_bit17_swizzling
)
387 ret
= __copy_to_user_swizzled(user_data
,
388 vaddr
, shmem_page_offset
,
391 ret
= __copy_to_user(user_data
,
392 vaddr
+ shmem_page_offset
,
396 return ret
? - EFAULT
: 0;
400 i915_gem_shmem_pread(struct drm_device
*dev
,
401 struct drm_i915_gem_object
*obj
,
402 struct drm_i915_gem_pread
*args
,
403 struct drm_file
*file
)
405 char __user
*user_data
;
408 int shmem_page_offset
, page_length
, ret
= 0;
409 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int hit_slowpath
= 0;
412 int needs_clflush
= 0;
413 struct scatterlist
*sg
;
416 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
419 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj
->cache_level
== I915_CACHE_NONE
)
428 if (obj
->gtt_space
) {
429 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
435 ret
= i915_gem_object_get_pages(obj
);
439 i915_gem_object_pin_pages(obj
);
441 offset
= args
->offset
;
443 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
446 if (i
< offset
>> PAGE_SHIFT
)
452 /* Operation in this page
454 * shmem_page_offset = offset within page in shmem file
455 * page_length = bytes to copy for this page
457 shmem_page_offset
= offset_in_page(offset
);
458 page_length
= remain
;
459 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
460 page_length
= PAGE_SIZE
- shmem_page_offset
;
463 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
464 (page_to_phys(page
) & (1 << 17)) != 0;
466 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
467 user_data
, page_do_bit17_swizzling
,
473 mutex_unlock(&dev
->struct_mutex
);
476 ret
= fault_in_multipages_writeable(user_data
, remain
);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
486 user_data
, page_do_bit17_swizzling
,
489 mutex_lock(&dev
->struct_mutex
);
492 mark_page_accessed(page
);
497 remain
-= page_length
;
498 user_data
+= page_length
;
499 offset
+= page_length
;
503 i915_gem_object_unpin_pages(obj
);
506 /* Fixup: Kill any reinstated backing storage pages */
507 if (obj
->madv
== __I915_MADV_PURGED
)
508 i915_gem_object_truncate(obj
);
515 * Reads data from the object referenced by handle.
517 * On error, the contents of *data are undefined.
520 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
521 struct drm_file
*file
)
523 struct drm_i915_gem_pread
*args
= data
;
524 struct drm_i915_gem_object
*obj
;
530 if (!access_ok(VERIFY_WRITE
,
531 (char __user
*)(uintptr_t)args
->data_ptr
,
535 ret
= i915_mutex_lock_interruptible(dev
);
539 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
540 if (&obj
->base
== NULL
) {
545 /* Bounds check source. */
546 if (args
->offset
> obj
->base
.size
||
547 args
->size
> obj
->base
.size
- args
->offset
) {
552 /* prime objects have no backing filp to GEM pread/pwrite
555 if (!obj
->base
.filp
) {
560 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
562 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
565 drm_gem_object_unreference(&obj
->base
);
567 mutex_unlock(&dev
->struct_mutex
);
571 /* This is the fast write path which cannot handle
572 * page faults in the source data
576 fast_user_write(struct io_mapping
*mapping
,
577 loff_t page_base
, int page_offset
,
578 char __user
*user_data
,
581 void __iomem
*vaddr_atomic
;
583 unsigned long unwritten
;
585 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
586 /* We can use the cpu mem copy function because this is X86. */
587 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
588 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
590 io_mapping_unmap_atomic(vaddr_atomic
);
595 * This is the fast pwrite path, where we copy the data directly from the
596 * user into the GTT, uncached.
599 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
600 struct drm_i915_gem_object
*obj
,
601 struct drm_i915_gem_pwrite
*args
,
602 struct drm_file
*file
)
604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
606 loff_t offset
, page_base
;
607 char __user
*user_data
;
608 int page_offset
, page_length
, ret
;
610 ret
= i915_gem_object_pin(obj
, 0, true, true);
614 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
618 ret
= i915_gem_object_put_fence(obj
);
622 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
625 offset
= obj
->gtt_offset
+ args
->offset
;
628 /* Operation in this page
630 * page_base = page offset within aperture
631 * page_offset = offset within page
632 * page_length = bytes to copy for this page
634 page_base
= offset
& PAGE_MASK
;
635 page_offset
= offset_in_page(offset
);
636 page_length
= remain
;
637 if ((page_offset
+ remain
) > PAGE_SIZE
)
638 page_length
= PAGE_SIZE
- page_offset
;
640 /* If we get a fault while copying data, then (presumably) our
641 * source page isn't available. Return the error and we'll
642 * retry in the slow path.
644 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
645 page_offset
, user_data
, page_length
)) {
650 remain
-= page_length
;
651 user_data
+= page_length
;
652 offset
+= page_length
;
656 i915_gem_object_unpin(obj
);
661 /* Per-page copy function for the shmem pwrite fastpath.
662 * Flushes invalid cachelines before writing to the target if
663 * needs_clflush_before is set and flushes out any written cachelines after
664 * writing if needs_clflush is set. */
666 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
667 char __user
*user_data
,
668 bool page_do_bit17_swizzling
,
669 bool needs_clflush_before
,
670 bool needs_clflush_after
)
675 if (unlikely(page_do_bit17_swizzling
))
678 vaddr
= kmap_atomic(page
);
679 if (needs_clflush_before
)
680 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
682 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
685 if (needs_clflush_after
)
686 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
688 kunmap_atomic(vaddr
);
690 return ret
? -EFAULT
: 0;
693 /* Only difference to the fast-path function is that this can handle bit17
694 * and uses non-atomic copy and kmap functions. */
696 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
697 char __user
*user_data
,
698 bool page_do_bit17_swizzling
,
699 bool needs_clflush_before
,
700 bool needs_clflush_after
)
706 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
707 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
709 page_do_bit17_swizzling
);
710 if (page_do_bit17_swizzling
)
711 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
715 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
718 if (needs_clflush_after
)
719 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
721 page_do_bit17_swizzling
);
724 return ret
? -EFAULT
: 0;
728 i915_gem_shmem_pwrite(struct drm_device
*dev
,
729 struct drm_i915_gem_object
*obj
,
730 struct drm_i915_gem_pwrite
*args
,
731 struct drm_file
*file
)
735 char __user
*user_data
;
736 int shmem_page_offset
, page_length
, ret
= 0;
737 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
738 int hit_slowpath
= 0;
739 int needs_clflush_after
= 0;
740 int needs_clflush_before
= 0;
742 struct scatterlist
*sg
;
744 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
747 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
749 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
750 /* If we're not in the cpu write domain, set ourself into the gtt
751 * write domain and manually flush cachelines (if required). This
752 * optimizes for the case when the gpu will use the data
753 * right away and we therefore have to clflush anyway. */
754 if (obj
->cache_level
== I915_CACHE_NONE
)
755 needs_clflush_after
= 1;
756 if (obj
->gtt_space
) {
757 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
762 /* Same trick applies for invalidate partially written cachelines before
764 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
765 && obj
->cache_level
== I915_CACHE_NONE
)
766 needs_clflush_before
= 1;
768 ret
= i915_gem_object_get_pages(obj
);
772 i915_gem_object_pin_pages(obj
);
774 offset
= args
->offset
;
777 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
779 int partial_cacheline_write
;
781 if (i
< offset
>> PAGE_SHIFT
)
787 /* Operation in this page
789 * shmem_page_offset = offset within page in shmem file
790 * page_length = bytes to copy for this page
792 shmem_page_offset
= offset_in_page(offset
);
794 page_length
= remain
;
795 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
796 page_length
= PAGE_SIZE
- shmem_page_offset
;
798 /* If we don't overwrite a cacheline completely we need to be
799 * careful to have up-to-date data by first clflushing. Don't
800 * overcomplicate things and flush the entire patch. */
801 partial_cacheline_write
= needs_clflush_before
&&
802 ((shmem_page_offset
| page_length
)
803 & (boot_cpu_data
.x86_clflush_size
- 1));
806 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
807 (page_to_phys(page
) & (1 << 17)) != 0;
809 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
810 user_data
, page_do_bit17_swizzling
,
811 partial_cacheline_write
,
812 needs_clflush_after
);
817 mutex_unlock(&dev
->struct_mutex
);
818 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
819 user_data
, page_do_bit17_swizzling
,
820 partial_cacheline_write
,
821 needs_clflush_after
);
823 mutex_lock(&dev
->struct_mutex
);
826 set_page_dirty(page
);
827 mark_page_accessed(page
);
832 remain
-= page_length
;
833 user_data
+= page_length
;
834 offset
+= page_length
;
838 i915_gem_object_unpin_pages(obj
);
841 /* Fixup: Kill any reinstated backing storage pages */
842 if (obj
->madv
== __I915_MADV_PURGED
)
843 i915_gem_object_truncate(obj
);
844 /* and flush dirty cachelines in case the object isn't in the cpu write
846 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
847 i915_gem_clflush_object(obj
);
848 i915_gem_chipset_flush(dev
);
852 if (needs_clflush_after
)
853 i915_gem_chipset_flush(dev
);
859 * Writes data to the object referenced by handle.
861 * On error, the contents of the buffer that were to be modified are undefined.
864 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
865 struct drm_file
*file
)
867 struct drm_i915_gem_pwrite
*args
= data
;
868 struct drm_i915_gem_object
*obj
;
874 if (!access_ok(VERIFY_READ
,
875 (char __user
*)(uintptr_t)args
->data_ptr
,
879 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
884 ret
= i915_mutex_lock_interruptible(dev
);
888 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
889 if (&obj
->base
== NULL
) {
894 /* Bounds check destination. */
895 if (args
->offset
> obj
->base
.size
||
896 args
->size
> obj
->base
.size
- args
->offset
) {
901 /* prime objects have no backing filp to GEM pread/pwrite
904 if (!obj
->base
.filp
) {
909 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
912 /* We can only do the GTT pwrite on untiled buffers, as otherwise
913 * it would end up going through the fenced access, and we'll get
914 * different detiling behavior between reading and writing.
915 * pread/pwrite currently are reading and writing from the CPU
916 * perspective, requiring manual detiling by the client.
919 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
923 if (obj
->cache_level
== I915_CACHE_NONE
&&
924 obj
->tiling_mode
== I915_TILING_NONE
&&
925 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
926 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
927 /* Note that the gtt paths might fail with non-page-backed user
928 * pointers (e.g. gtt mappings when moving data between
929 * textures). Fallback to the shmem path in that case. */
932 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
933 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
936 drm_gem_object_unreference(&obj
->base
);
938 mutex_unlock(&dev
->struct_mutex
);
943 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
946 if (atomic_read(&dev_priv
->mm
.wedged
)) {
947 struct completion
*x
= &dev_priv
->error_completion
;
948 bool recovery_complete
;
951 /* Give the error handler a chance to run. */
952 spin_lock_irqsave(&x
->wait
.lock
, flags
);
953 recovery_complete
= x
->done
> 0;
954 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
956 /* Non-interruptible callers can't handle -EAGAIN, hence return
957 * -EIO unconditionally for these. */
961 /* Recovery complete, but still wedged means reset failure. */
962 if (recovery_complete
)
972 * Compare seqno against outstanding lazy request. Emit a request if they are
976 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
980 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
983 if (seqno
== ring
->outstanding_lazy_request
)
984 ret
= i915_add_request(ring
, NULL
, NULL
);
990 * __wait_seqno - wait until execution of seqno has finished
991 * @ring: the ring expected to report seqno
993 * @interruptible: do an interruptible wait (normally yes)
994 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
996 * Returns 0 if the seqno was found within the alloted time. Else returns the
997 * errno with remaining time filled in timeout argument.
999 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1000 bool interruptible
, struct timespec
*timeout
)
1002 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1003 struct timespec before
, now
, wait_time
={1,0};
1004 unsigned long timeout_jiffies
;
1006 bool wait_forever
= true;
1009 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1012 trace_i915_gem_request_wait_begin(ring
, seqno
);
1014 if (timeout
!= NULL
) {
1015 wait_time
= *timeout
;
1016 wait_forever
= false;
1019 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1021 if (WARN_ON(!ring
->irq_get(ring
)))
1024 /* Record current time in case interrupted by signal, or wedged * */
1025 getrawmonotonic(&before
);
1028 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029 atomic_read(&dev_priv->mm.wedged))
1032 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1036 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1039 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1042 } while (end
== 0 && wait_forever
);
1044 getrawmonotonic(&now
);
1046 ring
->irq_put(ring
);
1047 trace_i915_gem_request_wait_end(ring
, seqno
);
1051 struct timespec sleep_time
= timespec_sub(now
, before
);
1052 *timeout
= timespec_sub(*timeout
, sleep_time
);
1057 case -EAGAIN
: /* Wedged */
1058 case -ERESTARTSYS
: /* Signal */
1060 case 0: /* Timeout */
1062 set_normalized_timespec(timeout
, 0, 0);
1064 default: /* Completed */
1065 WARN_ON(end
< 0); /* We're not aware of other errors */
1071 * Waits for a sequence number to be signaled, and cleans up the
1072 * request and object lists appropriately for that event.
1075 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1077 struct drm_device
*dev
= ring
->dev
;
1078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1079 bool interruptible
= dev_priv
->mm
.interruptible
;
1082 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1085 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1089 ret
= i915_gem_check_olr(ring
, seqno
);
1093 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1097 * Ensures that all rendering to the object has completed and the object is
1098 * safe to unbind from the GTT or access from the CPU.
1100 static __must_check
int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1104 struct intel_ring_buffer
*ring
= obj
->ring
;
1108 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1112 ret
= i915_wait_seqno(ring
, seqno
);
1116 i915_gem_retire_requests_ring(ring
);
1118 /* Manually manage the write flush as we may have not yet
1119 * retired the buffer.
1121 if (obj
->last_write_seqno
&&
1122 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1123 obj
->last_write_seqno
= 0;
1124 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131 * as the object state may change during this call.
1133 static __must_check
int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1137 struct drm_device
*dev
= obj
->base
.dev
;
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1139 struct intel_ring_buffer
*ring
= obj
->ring
;
1143 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1144 BUG_ON(!dev_priv
->mm
.interruptible
);
1146 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1150 ret
= i915_gem_check_wedge(dev_priv
, true);
1154 ret
= i915_gem_check_olr(ring
, seqno
);
1158 mutex_unlock(&dev
->struct_mutex
);
1159 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1160 mutex_lock(&dev
->struct_mutex
);
1162 i915_gem_retire_requests_ring(ring
);
1164 /* Manually manage the write flush as we may have not yet
1165 * retired the buffer.
1167 if (obj
->last_write_seqno
&&
1168 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1169 obj
->last_write_seqno
= 0;
1170 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1177 * Called when user space prepares to use an object with the CPU, either
1178 * through the mmap ioctl's mapping or a GTT mapping.
1181 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1182 struct drm_file
*file
)
1184 struct drm_i915_gem_set_domain
*args
= data
;
1185 struct drm_i915_gem_object
*obj
;
1186 uint32_t read_domains
= args
->read_domains
;
1187 uint32_t write_domain
= args
->write_domain
;
1190 /* Only handle setting domains to types used by the CPU. */
1191 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1194 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1197 /* Having something in the write domain implies it's in the read
1198 * domain, and only that read domain. Enforce that in the request.
1200 if (write_domain
!= 0 && read_domains
!= write_domain
)
1203 ret
= i915_mutex_lock_interruptible(dev
);
1207 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1208 if (&obj
->base
== NULL
) {
1213 /* Try to flush the object off the GPU without holding the lock.
1214 * We will repeat the flush holding the lock in the normal manner
1215 * to catch cases where we are gazumped.
1217 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1221 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1222 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1224 /* Silently promote "you're not bound, there was nothing to do"
1225 * to success, since the client was just asking us to
1226 * make sure everything was done.
1231 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1235 drm_gem_object_unreference(&obj
->base
);
1237 mutex_unlock(&dev
->struct_mutex
);
1242 * Called when user space has done writes to this buffer
1245 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1246 struct drm_file
*file
)
1248 struct drm_i915_gem_sw_finish
*args
= data
;
1249 struct drm_i915_gem_object
*obj
;
1252 ret
= i915_mutex_lock_interruptible(dev
);
1256 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1257 if (&obj
->base
== NULL
) {
1262 /* Pinned buffers may be scanout, so flush the cache */
1264 i915_gem_object_flush_cpu_write_domain(obj
);
1266 drm_gem_object_unreference(&obj
->base
);
1268 mutex_unlock(&dev
->struct_mutex
);
1273 * Maps the contents of an object, returning the address it is mapped
1276 * While the mapping holds a reference on the contents of the object, it doesn't
1277 * imply a ref on the object itself.
1280 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1281 struct drm_file
*file
)
1283 struct drm_i915_gem_mmap
*args
= data
;
1284 struct drm_gem_object
*obj
;
1287 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1291 /* prime objects have no backing filp to GEM mmap
1295 drm_gem_object_unreference_unlocked(obj
);
1299 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1300 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1302 drm_gem_object_unreference_unlocked(obj
);
1303 if (IS_ERR((void *)addr
))
1306 args
->addr_ptr
= (uint64_t) addr
;
1312 * i915_gem_fault - fault a page into the GTT
1313 * vma: VMA in question
1316 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317 * from userspace. The fault handler takes care of binding the object to
1318 * the GTT (if needed), allocating and programming a fence register (again,
1319 * only if needed based on whether the old reg is still valid or the object
1320 * is tiled) and inserting a new PTE into the faulting process.
1322 * Note that the faulting process may involve evicting existing objects
1323 * from the GTT and/or fence registers to make room. So performance may
1324 * suffer if the GTT working set is large or there are few fence registers
1327 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1329 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1330 struct drm_device
*dev
= obj
->base
.dev
;
1331 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1332 pgoff_t page_offset
;
1335 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1337 /* We don't use vmf->pgoff since that has the fake offset */
1338 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1341 ret
= i915_mutex_lock_interruptible(dev
);
1345 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1347 /* Now bind it into the GTT if needed */
1348 ret
= i915_gem_object_pin(obj
, 0, true, false);
1352 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1356 ret
= i915_gem_object_get_fence(obj
);
1360 obj
->fault_mappable
= true;
1362 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1365 /* Finally, remap it using the new GTT offset */
1366 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1368 i915_gem_object_unpin(obj
);
1370 mutex_unlock(&dev
->struct_mutex
);
1374 /* If this -EIO is due to a gpu hang, give the reset code a
1375 * chance to clean up the mess. Otherwise return the proper
1377 if (!atomic_read(&dev_priv
->mm
.wedged
))
1378 return VM_FAULT_SIGBUS
;
1380 /* Give the error handler a chance to run and move the
1381 * objects off the GPU active list. Next time we service the
1382 * fault, we should be able to transition the page into the
1383 * GTT without touching the GPU (and so avoid further
1384 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1385 * with coherency, just lost writes.
1393 * EBUSY is ok: this just means that another thread
1394 * already did the job.
1396 return VM_FAULT_NOPAGE
;
1398 return VM_FAULT_OOM
;
1400 return VM_FAULT_SIGBUS
;
1402 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1403 return VM_FAULT_SIGBUS
;
1408 * i915_gem_release_mmap - remove physical page mappings
1409 * @obj: obj in question
1411 * Preserve the reservation of the mmapping with the DRM core code, but
1412 * relinquish ownership of the pages back to the system.
1414 * It is vital that we remove the page mapping if we have mapped a tiled
1415 * object through the GTT and then lose the fence register due to
1416 * resource pressure. Similarly if the object has been moved out of the
1417 * aperture, than pages mapped into userspace must be revoked. Removing the
1418 * mapping will then trigger a page fault on the next user access, allowing
1419 * fixup by i915_gem_fault().
1422 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1424 if (!obj
->fault_mappable
)
1427 if (obj
->base
.dev
->dev_mapping
)
1428 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1429 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1432 obj
->fault_mappable
= false;
1436 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1440 if (INTEL_INFO(dev
)->gen
>= 4 ||
1441 tiling_mode
== I915_TILING_NONE
)
1444 /* Previous chips need a power-of-two fence region when tiling */
1445 if (INTEL_INFO(dev
)->gen
== 3)
1446 gtt_size
= 1024*1024;
1448 gtt_size
= 512*1024;
1450 while (gtt_size
< size
)
1457 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458 * @obj: object to check
1460 * Return the required GTT alignment for an object, taking into account
1461 * potential fence register mapping.
1464 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1469 * Minimum alignment is 4k (GTT page size), but might be greater
1470 * if a fence register is needed for the object.
1472 if (INTEL_INFO(dev
)->gen
>= 4 ||
1473 tiling_mode
== I915_TILING_NONE
)
1477 * Previous chips need to be aligned to the size of the smallest
1478 * fence register that can contain the object.
1480 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1484 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1487 * @size: size of the object
1488 * @tiling_mode: tiling mode of the object
1490 * Return the required GTT alignment for an object, only taking into account
1491 * unfenced tiled surface requirements.
1494 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1499 * Minimum alignment is 4k (GTT page size) for sane hw.
1501 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1502 tiling_mode
== I915_TILING_NONE
)
1505 /* Previous hardware however needs to be aligned to a power-of-two
1506 * tile height. The simplest method for determining this is to reuse
1507 * the power-of-tile object size.
1509 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1512 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1514 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1517 if (obj
->base
.map_list
.map
)
1520 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1522 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1526 /* Badly fragmented mmap space? The only way we can recover
1527 * space is by destroying unwanted objects. We can't randomly release
1528 * mmap_offsets as userspace expects them to be persistent for the
1529 * lifetime of the objects. The closest we can is to release the
1530 * offsets on purgeable objects by truncating it and marking it purged,
1531 * which prevents userspace from ever using that object again.
1533 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1534 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1538 i915_gem_shrink_all(dev_priv
);
1539 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1541 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1546 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1548 if (!obj
->base
.map_list
.map
)
1551 drm_gem_free_mmap_offset(&obj
->base
);
1555 i915_gem_mmap_gtt(struct drm_file
*file
,
1556 struct drm_device
*dev
,
1560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1561 struct drm_i915_gem_object
*obj
;
1564 ret
= i915_mutex_lock_interruptible(dev
);
1568 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1569 if (&obj
->base
== NULL
) {
1574 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1579 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1580 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1585 ret
= i915_gem_object_create_mmap_offset(obj
);
1589 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1592 drm_gem_object_unreference(&obj
->base
);
1594 mutex_unlock(&dev
->struct_mutex
);
1599 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1601 * @data: GTT mapping ioctl data
1602 * @file: GEM object info
1604 * Simply returns the fake offset to userspace so it can mmap it.
1605 * The mmap call will end up in drm_gem_mmap(), which will set things
1606 * up so we can get faults in the handler above.
1608 * The fault handler will take care of binding the object into the GTT
1609 * (since it may have been evicted to make room for something), allocating
1610 * a fence register, and mapping the appropriate aperture address into
1614 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1615 struct drm_file
*file
)
1617 struct drm_i915_gem_mmap_gtt
*args
= data
;
1619 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1622 /* Immediately discard the backing storage */
1624 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1626 struct inode
*inode
;
1628 i915_gem_object_free_mmap_offset(obj
);
1630 if (obj
->base
.filp
== NULL
)
1633 /* Our goal here is to return as much of the memory as
1634 * is possible back to the system as we are called from OOM.
1635 * To do this we must instruct the shmfs to drop all of its
1636 * backing pages, *now*.
1638 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1639 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1641 obj
->madv
= __I915_MADV_PURGED
;
1645 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1647 return obj
->madv
== I915_MADV_DONTNEED
;
1651 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1653 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1654 struct scatterlist
*sg
;
1657 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1659 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1661 /* In the event of a disaster, abandon all caches and
1662 * hope for the best.
1664 WARN_ON(ret
!= -EIO
);
1665 i915_gem_clflush_object(obj
);
1666 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1669 if (i915_gem_object_needs_bit17_swizzle(obj
))
1670 i915_gem_object_save_bit_17_swizzle(obj
);
1672 if (obj
->madv
== I915_MADV_DONTNEED
)
1675 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1676 struct page
*page
= sg_page(sg
);
1679 set_page_dirty(page
);
1681 if (obj
->madv
== I915_MADV_WILLNEED
)
1682 mark_page_accessed(page
);
1684 page_cache_release(page
);
1688 sg_free_table(obj
->pages
);
1693 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1695 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1697 if (obj
->pages
== NULL
)
1700 BUG_ON(obj
->gtt_space
);
1702 if (obj
->pages_pin_count
)
1705 /* ->put_pages might need to allocate memory for the bit17 swizzle
1706 * array, hence protect them from being reaped by removing them from gtt
1708 list_del(&obj
->gtt_list
);
1710 ops
->put_pages(obj
);
1713 if (i915_gem_object_is_purgeable(obj
))
1714 i915_gem_object_truncate(obj
);
1720 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1722 struct drm_i915_gem_object
*obj
, *next
;
1725 list_for_each_entry_safe(obj
, next
,
1726 &dev_priv
->mm
.unbound_list
,
1728 if (i915_gem_object_is_purgeable(obj
) &&
1729 i915_gem_object_put_pages(obj
) == 0) {
1730 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1731 if (count
>= target
)
1736 list_for_each_entry_safe(obj
, next
,
1737 &dev_priv
->mm
.inactive_list
,
1739 if (i915_gem_object_is_purgeable(obj
) &&
1740 i915_gem_object_unbind(obj
) == 0 &&
1741 i915_gem_object_put_pages(obj
) == 0) {
1742 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1743 if (count
>= target
)
1752 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1754 struct drm_i915_gem_object
*obj
, *next
;
1756 i915_gem_evict_everything(dev_priv
->dev
);
1758 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1759 i915_gem_object_put_pages(obj
);
1763 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1765 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1767 struct address_space
*mapping
;
1768 struct sg_table
*st
;
1769 struct scatterlist
*sg
;
1773 /* Assert that the object is not currently in any GPU domain. As it
1774 * wasn't in the GTT, there shouldn't be any way it could have been in
1777 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1778 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1780 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1784 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1785 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1791 /* Get the list of pages out of our struct file. They'll be pinned
1792 * at this point until we release them.
1794 * Fail silently without starting the shrinker
1796 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1797 gfp
= mapping_gfp_mask(mapping
);
1798 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1799 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1800 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1801 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1803 i915_gem_purge(dev_priv
, page_count
);
1804 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1807 /* We've tried hard to allocate the memory by reaping
1808 * our own buffer, now let the real VM do its job and
1809 * go down in flames if truly OOM.
1811 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1812 gfp
|= __GFP_IO
| __GFP_WAIT
;
1814 i915_gem_shrink_all(dev_priv
);
1815 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1819 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1820 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1823 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1828 if (i915_gem_object_needs_bit17_swizzle(obj
))
1829 i915_gem_object_do_bit_17_swizzle(obj
);
1834 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1835 page_cache_release(sg_page(sg
));
1838 return PTR_ERR(page
);
1841 /* Ensure that the associated pages are gathered from the backing storage
1842 * and pinned into our object. i915_gem_object_get_pages() may be called
1843 * multiple times before they are released by a single call to
1844 * i915_gem_object_put_pages() - once the pages are no longer referenced
1845 * either as a result of memory pressure (reaping pages under the shrinker)
1846 * or as the object is itself released.
1849 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1851 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1852 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1858 BUG_ON(obj
->pages_pin_count
);
1860 ret
= ops
->get_pages(obj
);
1864 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1869 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1870 struct intel_ring_buffer
*ring
)
1872 struct drm_device
*dev
= obj
->base
.dev
;
1873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1874 u32 seqno
= intel_ring_get_seqno(ring
);
1876 BUG_ON(ring
== NULL
);
1879 /* Add a reference if we're newly entering the active list. */
1881 drm_gem_object_reference(&obj
->base
);
1885 /* Move from whatever list we were on to the tail of execution. */
1886 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1887 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1889 obj
->last_read_seqno
= seqno
;
1891 if (obj
->fenced_gpu_access
) {
1892 obj
->last_fenced_seqno
= seqno
;
1894 /* Bump MRU to take account of the delayed flush */
1895 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1896 struct drm_i915_fence_reg
*reg
;
1898 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1899 list_move_tail(®
->lru_list
,
1900 &dev_priv
->mm
.fence_list
);
1906 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1908 struct drm_device
*dev
= obj
->base
.dev
;
1909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1912 BUG_ON(!obj
->active
);
1914 if (obj
->pin_count
) /* are we a framebuffer? */
1915 intel_mark_fb_idle(obj
);
1917 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1919 list_del_init(&obj
->ring_list
);
1922 obj
->last_read_seqno
= 0;
1923 obj
->last_write_seqno
= 0;
1924 obj
->base
.write_domain
= 0;
1926 obj
->last_fenced_seqno
= 0;
1927 obj
->fenced_gpu_access
= false;
1930 drm_gem_object_unreference(&obj
->base
);
1932 WARN_ON(i915_verify_lists(dev
));
1936 i915_gem_handle_seqno_wrap(struct drm_device
*dev
)
1938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1939 struct intel_ring_buffer
*ring
;
1942 /* The hardware uses various monotonic 32-bit counters, if we
1943 * detect that they will wraparound we need to idle the GPU
1944 * and reset those counters.
1947 for_each_ring(ring
, dev_priv
, i
) {
1948 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1949 ret
|= ring
->sync_seqno
[j
] != 0;
1954 ret
= i915_gpu_idle(dev
);
1958 i915_gem_retire_requests(dev
);
1959 for_each_ring(ring
, dev_priv
, i
) {
1960 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1961 ring
->sync_seqno
[j
] = 0;
1968 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1972 /* reserve 0 for non-seqno */
1973 if (dev_priv
->next_seqno
== 0) {
1974 int ret
= i915_gem_handle_seqno_wrap(dev
);
1978 dev_priv
->next_seqno
= 1;
1981 *seqno
= dev_priv
->next_seqno
++;
1986 i915_add_request(struct intel_ring_buffer
*ring
,
1987 struct drm_file
*file
,
1990 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1991 struct drm_i915_gem_request
*request
;
1992 u32 request_ring_position
;
1997 * Emit any outstanding flushes - execbuf can fail to emit the flush
1998 * after having emitted the batchbuffer command. Hence we need to fix
1999 * things up similar to emitting the lazy request. The difference here
2000 * is that the flush _must_ happen before the next request, no matter
2003 ret
= intel_ring_flush_all_caches(ring
);
2007 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2008 if (request
== NULL
)
2012 /* Record the position of the start of the request so that
2013 * should we detect the updated seqno part-way through the
2014 * GPU processing the request, we never over-estimate the
2015 * position of the head.
2017 request_ring_position
= intel_ring_get_tail(ring
);
2019 ret
= ring
->add_request(ring
);
2025 request
->seqno
= intel_ring_get_seqno(ring
);
2026 request
->ring
= ring
;
2027 request
->tail
= request_ring_position
;
2028 request
->emitted_jiffies
= jiffies
;
2029 was_empty
= list_empty(&ring
->request_list
);
2030 list_add_tail(&request
->list
, &ring
->request_list
);
2031 request
->file_priv
= NULL
;
2034 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2036 spin_lock(&file_priv
->mm
.lock
);
2037 request
->file_priv
= file_priv
;
2038 list_add_tail(&request
->client_list
,
2039 &file_priv
->mm
.request_list
);
2040 spin_unlock(&file_priv
->mm
.lock
);
2043 trace_i915_gem_request_add(ring
, request
->seqno
);
2044 ring
->outstanding_lazy_request
= 0;
2046 if (!dev_priv
->mm
.suspended
) {
2047 if (i915_enable_hangcheck
) {
2048 mod_timer(&dev_priv
->hangcheck_timer
,
2049 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2052 queue_delayed_work(dev_priv
->wq
,
2053 &dev_priv
->mm
.retire_work
,
2054 round_jiffies_up_relative(HZ
));
2055 intel_mark_busy(dev_priv
->dev
);
2060 *out_seqno
= request
->seqno
;
2065 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2067 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2072 spin_lock(&file_priv
->mm
.lock
);
2073 if (request
->file_priv
) {
2074 list_del(&request
->client_list
);
2075 request
->file_priv
= NULL
;
2077 spin_unlock(&file_priv
->mm
.lock
);
2080 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2081 struct intel_ring_buffer
*ring
)
2083 while (!list_empty(&ring
->request_list
)) {
2084 struct drm_i915_gem_request
*request
;
2086 request
= list_first_entry(&ring
->request_list
,
2087 struct drm_i915_gem_request
,
2090 list_del(&request
->list
);
2091 i915_gem_request_remove_from_client(request
);
2095 while (!list_empty(&ring
->active_list
)) {
2096 struct drm_i915_gem_object
*obj
;
2098 obj
= list_first_entry(&ring
->active_list
,
2099 struct drm_i915_gem_object
,
2102 i915_gem_object_move_to_inactive(obj
);
2106 static void i915_gem_reset_fences(struct drm_device
*dev
)
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2111 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2112 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2114 i915_gem_write_fence(dev
, i
, NULL
);
2117 i915_gem_object_fence_lost(reg
->obj
);
2121 INIT_LIST_HEAD(®
->lru_list
);
2124 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2127 void i915_gem_reset(struct drm_device
*dev
)
2129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 struct drm_i915_gem_object
*obj
;
2131 struct intel_ring_buffer
*ring
;
2134 for_each_ring(ring
, dev_priv
, i
)
2135 i915_gem_reset_ring_lists(dev_priv
, ring
);
2137 /* Move everything out of the GPU domains to ensure we do any
2138 * necessary invalidation upon reuse.
2140 list_for_each_entry(obj
,
2141 &dev_priv
->mm
.inactive_list
,
2144 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2147 /* The fence registers are invalidated so clear them out */
2148 i915_gem_reset_fences(dev
);
2152 * This function clears the request list as sequence numbers are passed.
2155 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2159 if (list_empty(&ring
->request_list
))
2162 WARN_ON(i915_verify_lists(ring
->dev
));
2164 seqno
= ring
->get_seqno(ring
, true);
2166 while (!list_empty(&ring
->request_list
)) {
2167 struct drm_i915_gem_request
*request
;
2169 request
= list_first_entry(&ring
->request_list
,
2170 struct drm_i915_gem_request
,
2173 if (!i915_seqno_passed(seqno
, request
->seqno
))
2176 trace_i915_gem_request_retire(ring
, request
->seqno
);
2177 /* We know the GPU must have read the request to have
2178 * sent us the seqno + interrupt, so use the position
2179 * of tail of the request to update the last known position
2182 ring
->last_retired_head
= request
->tail
;
2184 list_del(&request
->list
);
2185 i915_gem_request_remove_from_client(request
);
2189 /* Move any buffers on the active list that are no longer referenced
2190 * by the ringbuffer to the flushing/inactive lists as appropriate.
2192 while (!list_empty(&ring
->active_list
)) {
2193 struct drm_i915_gem_object
*obj
;
2195 obj
= list_first_entry(&ring
->active_list
,
2196 struct drm_i915_gem_object
,
2199 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2202 i915_gem_object_move_to_inactive(obj
);
2205 if (unlikely(ring
->trace_irq_seqno
&&
2206 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2207 ring
->irq_put(ring
);
2208 ring
->trace_irq_seqno
= 0;
2211 WARN_ON(i915_verify_lists(ring
->dev
));
2215 i915_gem_retire_requests(struct drm_device
*dev
)
2217 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2218 struct intel_ring_buffer
*ring
;
2221 for_each_ring(ring
, dev_priv
, i
)
2222 i915_gem_retire_requests_ring(ring
);
2226 i915_gem_retire_work_handler(struct work_struct
*work
)
2228 drm_i915_private_t
*dev_priv
;
2229 struct drm_device
*dev
;
2230 struct intel_ring_buffer
*ring
;
2234 dev_priv
= container_of(work
, drm_i915_private_t
,
2235 mm
.retire_work
.work
);
2236 dev
= dev_priv
->dev
;
2238 /* Come back later if the device is busy... */
2239 if (!mutex_trylock(&dev
->struct_mutex
)) {
2240 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2241 round_jiffies_up_relative(HZ
));
2245 i915_gem_retire_requests(dev
);
2247 /* Send a periodic flush down the ring so we don't hold onto GEM
2248 * objects indefinitely.
2251 for_each_ring(ring
, dev_priv
, i
) {
2252 if (ring
->gpu_caches_dirty
)
2253 i915_add_request(ring
, NULL
, NULL
);
2255 idle
&= list_empty(&ring
->request_list
);
2258 if (!dev_priv
->mm
.suspended
&& !idle
)
2259 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2260 round_jiffies_up_relative(HZ
));
2262 intel_mark_idle(dev
);
2264 mutex_unlock(&dev
->struct_mutex
);
2268 * Ensures that an object will eventually get non-busy by flushing any required
2269 * write domains, emitting any outstanding lazy request and retiring and
2270 * completed requests.
2273 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2278 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2282 i915_gem_retire_requests_ring(obj
->ring
);
2289 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2290 * @DRM_IOCTL_ARGS: standard ioctl arguments
2292 * Returns 0 if successful, else an error is returned with the remaining time in
2293 * the timeout parameter.
2294 * -ETIME: object is still busy after timeout
2295 * -ERESTARTSYS: signal interrupted the wait
2296 * -ENONENT: object doesn't exist
2297 * Also possible, but rare:
2298 * -EAGAIN: GPU wedged
2300 * -ENODEV: Internal IRQ fail
2301 * -E?: The add request failed
2303 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2304 * non-zero timeout parameter the wait ioctl will wait for the given number of
2305 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2306 * without holding struct_mutex the object may become re-busied before this
2307 * function completes. A similar but shorter * race condition exists in the busy
2311 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2313 struct drm_i915_gem_wait
*args
= data
;
2314 struct drm_i915_gem_object
*obj
;
2315 struct intel_ring_buffer
*ring
= NULL
;
2316 struct timespec timeout_stack
, *timeout
= NULL
;
2320 if (args
->timeout_ns
>= 0) {
2321 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2322 timeout
= &timeout_stack
;
2325 ret
= i915_mutex_lock_interruptible(dev
);
2329 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2330 if (&obj
->base
== NULL
) {
2331 mutex_unlock(&dev
->struct_mutex
);
2335 /* Need to make sure the object gets inactive eventually. */
2336 ret
= i915_gem_object_flush_active(obj
);
2341 seqno
= obj
->last_read_seqno
;
2348 /* Do this after OLR check to make sure we make forward progress polling
2349 * on this IOCTL with a 0 timeout (like busy ioctl)
2351 if (!args
->timeout_ns
) {
2356 drm_gem_object_unreference(&obj
->base
);
2357 mutex_unlock(&dev
->struct_mutex
);
2359 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2361 WARN_ON(!timespec_valid(timeout
));
2362 args
->timeout_ns
= timespec_to_ns(timeout
);
2367 drm_gem_object_unreference(&obj
->base
);
2368 mutex_unlock(&dev
->struct_mutex
);
2373 * i915_gem_object_sync - sync an object to a ring.
2375 * @obj: object which may be in use on another ring.
2376 * @to: ring we wish to use the object on. May be NULL.
2378 * This code is meant to abstract object synchronization with the GPU.
2379 * Calling with NULL implies synchronizing the object with the CPU
2380 * rather than a particular GPU ring.
2382 * Returns 0 if successful, else propagates up the lower layer error.
2385 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2386 struct intel_ring_buffer
*to
)
2388 struct intel_ring_buffer
*from
= obj
->ring
;
2392 if (from
== NULL
|| to
== from
)
2395 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2396 return i915_gem_object_wait_rendering(obj
, false);
2398 idx
= intel_ring_sync_index(from
, to
);
2400 seqno
= obj
->last_read_seqno
;
2401 if (seqno
<= from
->sync_seqno
[idx
])
2404 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2408 ret
= to
->sync_to(to
, from
, seqno
);
2410 /* We use last_read_seqno because sync_to()
2411 * might have just caused seqno wrap under
2414 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2419 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2421 u32 old_write_domain
, old_read_domains
;
2423 /* Act a barrier for all accesses through the GTT */
2426 /* Force a pagefault for domain tracking on next user access */
2427 i915_gem_release_mmap(obj
);
2429 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2432 old_read_domains
= obj
->base
.read_domains
;
2433 old_write_domain
= obj
->base
.write_domain
;
2435 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2436 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2438 trace_i915_gem_object_change_domain(obj
,
2444 * Unbinds an object from the GTT aperture.
2447 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2449 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2452 if (obj
->gtt_space
== NULL
)
2458 BUG_ON(obj
->pages
== NULL
);
2460 ret
= i915_gem_object_finish_gpu(obj
);
2463 /* Continue on if we fail due to EIO, the GPU is hung so we
2464 * should be safe and we need to cleanup or else we might
2465 * cause memory corruption through use-after-free.
2468 i915_gem_object_finish_gtt(obj
);
2470 /* release the fence reg _after_ flushing */
2471 ret
= i915_gem_object_put_fence(obj
);
2475 trace_i915_gem_object_unbind(obj
);
2477 if (obj
->has_global_gtt_mapping
)
2478 i915_gem_gtt_unbind_object(obj
);
2479 if (obj
->has_aliasing_ppgtt_mapping
) {
2480 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2481 obj
->has_aliasing_ppgtt_mapping
= 0;
2483 i915_gem_gtt_finish_object(obj
);
2485 list_del(&obj
->mm_list
);
2486 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2487 /* Avoid an unnecessary call to unbind on rebind. */
2488 obj
->map_and_fenceable
= true;
2490 drm_mm_put_block(obj
->gtt_space
);
2491 obj
->gtt_space
= NULL
;
2492 obj
->gtt_offset
= 0;
2497 int i915_gpu_idle(struct drm_device
*dev
)
2499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2500 struct intel_ring_buffer
*ring
;
2503 /* Flush everything onto the inactive list. */
2504 for_each_ring(ring
, dev_priv
, i
) {
2505 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2509 ret
= intel_ring_idle(ring
);
2517 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2518 struct drm_i915_gem_object
*obj
)
2520 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2524 u32 size
= obj
->gtt_space
->size
;
2526 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2528 val
|= obj
->gtt_offset
& 0xfffff000;
2529 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2530 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2532 if (obj
->tiling_mode
== I915_TILING_Y
)
2533 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2534 val
|= I965_FENCE_REG_VALID
;
2538 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2539 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2542 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2543 struct drm_i915_gem_object
*obj
)
2545 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2549 u32 size
= obj
->gtt_space
->size
;
2551 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2553 val
|= obj
->gtt_offset
& 0xfffff000;
2554 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2555 if (obj
->tiling_mode
== I915_TILING_Y
)
2556 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2557 val
|= I965_FENCE_REG_VALID
;
2561 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2562 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2565 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2566 struct drm_i915_gem_object
*obj
)
2568 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2572 u32 size
= obj
->gtt_space
->size
;
2576 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2577 (size
& -size
) != size
||
2578 (obj
->gtt_offset
& (size
- 1)),
2579 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2580 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2582 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2587 /* Note: pitch better be a power of two tile widths */
2588 pitch_val
= obj
->stride
/ tile_width
;
2589 pitch_val
= ffs(pitch_val
) - 1;
2591 val
= obj
->gtt_offset
;
2592 if (obj
->tiling_mode
== I915_TILING_Y
)
2593 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2594 val
|= I915_FENCE_SIZE_BITS(size
);
2595 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2596 val
|= I830_FENCE_REG_VALID
;
2601 reg
= FENCE_REG_830_0
+ reg
* 4;
2603 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2605 I915_WRITE(reg
, val
);
2609 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2610 struct drm_i915_gem_object
*obj
)
2612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2616 u32 size
= obj
->gtt_space
->size
;
2619 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2620 (size
& -size
) != size
||
2621 (obj
->gtt_offset
& (size
- 1)),
2622 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2623 obj
->gtt_offset
, size
);
2625 pitch_val
= obj
->stride
/ 128;
2626 pitch_val
= ffs(pitch_val
) - 1;
2628 val
= obj
->gtt_offset
;
2629 if (obj
->tiling_mode
== I915_TILING_Y
)
2630 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2631 val
|= I830_FENCE_SIZE_BITS(size
);
2632 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2633 val
|= I830_FENCE_REG_VALID
;
2637 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2638 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2641 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2642 struct drm_i915_gem_object
*obj
)
2644 switch (INTEL_INFO(dev
)->gen
) {
2646 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2648 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2649 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2650 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2655 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2656 struct drm_i915_fence_reg
*fence
)
2658 return fence
- dev_priv
->fence_regs
;
2661 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2662 struct drm_i915_fence_reg
*fence
,
2665 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2666 int reg
= fence_number(dev_priv
, fence
);
2668 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2671 obj
->fence_reg
= reg
;
2673 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2675 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2677 list_del_init(&fence
->lru_list
);
2682 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2684 if (obj
->last_fenced_seqno
) {
2685 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2689 obj
->last_fenced_seqno
= 0;
2692 /* Ensure that all CPU reads are completed before installing a fence
2693 * and all writes before removing the fence.
2695 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2698 obj
->fenced_gpu_access
= false;
2703 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2705 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2708 ret
= i915_gem_object_flush_fence(obj
);
2712 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2715 i915_gem_object_update_fence(obj
,
2716 &dev_priv
->fence_regs
[obj
->fence_reg
],
2718 i915_gem_object_fence_lost(obj
);
2723 static struct drm_i915_fence_reg
*
2724 i915_find_fence_reg(struct drm_device
*dev
)
2726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2727 struct drm_i915_fence_reg
*reg
, *avail
;
2730 /* First try to find a free reg */
2732 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2733 reg
= &dev_priv
->fence_regs
[i
];
2737 if (!reg
->pin_count
)
2744 /* None available, try to steal one or wait for a user to finish */
2745 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2756 * i915_gem_object_get_fence - set up fencing for an object
2757 * @obj: object to map through a fence reg
2759 * When mapping objects through the GTT, userspace wants to be able to write
2760 * to them without having to worry about swizzling if the object is tiled.
2761 * This function walks the fence regs looking for a free one for @obj,
2762 * stealing one if it can't find any.
2764 * It then sets up the reg based on the object's properties: address, pitch
2765 * and tiling format.
2767 * For an untiled surface, this removes any existing fence.
2770 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2772 struct drm_device
*dev
= obj
->base
.dev
;
2773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2774 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2775 struct drm_i915_fence_reg
*reg
;
2778 /* Have we updated the tiling parameters upon the object and so
2779 * will need to serialise the write to the associated fence register?
2781 if (obj
->fence_dirty
) {
2782 ret
= i915_gem_object_flush_fence(obj
);
2787 /* Just update our place in the LRU if our fence is getting reused. */
2788 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2789 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2790 if (!obj
->fence_dirty
) {
2791 list_move_tail(®
->lru_list
,
2792 &dev_priv
->mm
.fence_list
);
2795 } else if (enable
) {
2796 reg
= i915_find_fence_reg(dev
);
2801 struct drm_i915_gem_object
*old
= reg
->obj
;
2803 ret
= i915_gem_object_flush_fence(old
);
2807 i915_gem_object_fence_lost(old
);
2812 i915_gem_object_update_fence(obj
, reg
, enable
);
2813 obj
->fence_dirty
= false;
2818 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2819 struct drm_mm_node
*gtt_space
,
2820 unsigned long cache_level
)
2822 struct drm_mm_node
*other
;
2824 /* On non-LLC machines we have to be careful when putting differing
2825 * types of snoopable memory together to avoid the prefetcher
2826 * crossing memory domains and dieing.
2831 if (gtt_space
== NULL
)
2834 if (list_empty(>t_space
->node_list
))
2837 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2838 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2841 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2842 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2848 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2852 struct drm_i915_gem_object
*obj
;
2855 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2856 if (obj
->gtt_space
== NULL
) {
2857 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2862 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2863 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2864 obj
->gtt_space
->start
,
2865 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2867 obj
->gtt_space
->color
);
2872 if (!i915_gem_valid_gtt_space(dev
,
2874 obj
->cache_level
)) {
2875 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2876 obj
->gtt_space
->start
,
2877 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2889 * Finds free space in the GTT aperture and binds the object there.
2892 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2894 bool map_and_fenceable
,
2897 struct drm_device
*dev
= obj
->base
.dev
;
2898 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2899 struct drm_mm_node
*node
;
2900 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2901 bool mappable
, fenceable
;
2904 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2905 DRM_ERROR("Attempting to bind a purgeable object\n");
2909 fence_size
= i915_gem_get_gtt_size(dev
,
2912 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2915 unfenced_alignment
=
2916 i915_gem_get_unfenced_gtt_alignment(dev
,
2921 alignment
= map_and_fenceable
? fence_alignment
:
2923 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2924 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2928 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2930 /* If the object is bigger than the entire aperture, reject it early
2931 * before evicting everything in a vain attempt to find space.
2933 if (obj
->base
.size
>
2934 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2935 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2939 ret
= i915_gem_object_get_pages(obj
);
2943 i915_gem_object_pin_pages(obj
);
2945 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2947 i915_gem_object_unpin_pages(obj
);
2952 if (map_and_fenceable
)
2953 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2954 size
, alignment
, obj
->cache_level
,
2955 0, dev_priv
->mm
.gtt_mappable_end
);
2957 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2958 size
, alignment
, obj
->cache_level
);
2960 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2967 i915_gem_object_unpin_pages(obj
);
2971 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
2972 i915_gem_object_unpin_pages(obj
);
2973 drm_mm_put_block(node
);
2977 ret
= i915_gem_gtt_prepare_object(obj
);
2979 i915_gem_object_unpin_pages(obj
);
2980 drm_mm_put_block(node
);
2984 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2985 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2987 obj
->gtt_space
= node
;
2988 obj
->gtt_offset
= node
->start
;
2991 node
->size
== fence_size
&&
2992 (node
->start
& (fence_alignment
- 1)) == 0;
2995 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2997 obj
->map_and_fenceable
= mappable
&& fenceable
;
2999 i915_gem_object_unpin_pages(obj
);
3000 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3001 i915_gem_verify_gtt(dev
);
3006 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3008 /* If we don't have a page list set up, then we're not pinned
3009 * to GPU, and we can ignore the cache flush because it'll happen
3010 * again at bind time.
3012 if (obj
->pages
== NULL
)
3015 /* If the GPU is snooping the contents of the CPU cache,
3016 * we do not need to manually clear the CPU cache lines. However,
3017 * the caches are only snooped when the render cache is
3018 * flushed/invalidated. As we always have to emit invalidations
3019 * and flushes when moving into and out of the RENDER domain, correct
3020 * snooping behaviour occurs naturally as the result of our domain
3023 if (obj
->cache_level
!= I915_CACHE_NONE
)
3026 trace_i915_gem_object_clflush(obj
);
3028 drm_clflush_sg(obj
->pages
);
3031 /** Flushes the GTT write domain for the object if it's dirty. */
3033 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3035 uint32_t old_write_domain
;
3037 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3040 /* No actual flushing is required for the GTT write domain. Writes
3041 * to it immediately go to main memory as far as we know, so there's
3042 * no chipset flush. It also doesn't land in render cache.
3044 * However, we do have to enforce the order so that all writes through
3045 * the GTT land before any writes to the device, such as updates to
3050 old_write_domain
= obj
->base
.write_domain
;
3051 obj
->base
.write_domain
= 0;
3053 trace_i915_gem_object_change_domain(obj
,
3054 obj
->base
.read_domains
,
3058 /** Flushes the CPU write domain for the object if it's dirty. */
3060 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3062 uint32_t old_write_domain
;
3064 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3067 i915_gem_clflush_object(obj
);
3068 i915_gem_chipset_flush(obj
->base
.dev
);
3069 old_write_domain
= obj
->base
.write_domain
;
3070 obj
->base
.write_domain
= 0;
3072 trace_i915_gem_object_change_domain(obj
,
3073 obj
->base
.read_domains
,
3078 * Moves a single object to the GTT read, and possibly write domain.
3080 * This function returns when the move is complete, including waiting on
3084 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3086 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3087 uint32_t old_write_domain
, old_read_domains
;
3090 /* Not valid to be called on unbound objects. */
3091 if (obj
->gtt_space
== NULL
)
3094 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3097 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3101 i915_gem_object_flush_cpu_write_domain(obj
);
3103 old_write_domain
= obj
->base
.write_domain
;
3104 old_read_domains
= obj
->base
.read_domains
;
3106 /* It should now be out of any other write domains, and we can update
3107 * the domain values for our changes.
3109 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3110 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3112 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3113 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3117 trace_i915_gem_object_change_domain(obj
,
3121 /* And bump the LRU for this access */
3122 if (i915_gem_object_is_inactive(obj
))
3123 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3128 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3129 enum i915_cache_level cache_level
)
3131 struct drm_device
*dev
= obj
->base
.dev
;
3132 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3135 if (obj
->cache_level
== cache_level
)
3138 if (obj
->pin_count
) {
3139 DRM_DEBUG("can not change the cache level of pinned objects\n");
3143 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3144 ret
= i915_gem_object_unbind(obj
);
3149 if (obj
->gtt_space
) {
3150 ret
= i915_gem_object_finish_gpu(obj
);
3154 i915_gem_object_finish_gtt(obj
);
3156 /* Before SandyBridge, you could not use tiling or fence
3157 * registers with snooped memory, so relinquish any fences
3158 * currently pointing to our region in the aperture.
3160 if (INTEL_INFO(dev
)->gen
< 6) {
3161 ret
= i915_gem_object_put_fence(obj
);
3166 if (obj
->has_global_gtt_mapping
)
3167 i915_gem_gtt_bind_object(obj
, cache_level
);
3168 if (obj
->has_aliasing_ppgtt_mapping
)
3169 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3172 obj
->gtt_space
->color
= cache_level
;
3175 if (cache_level
== I915_CACHE_NONE
) {
3176 u32 old_read_domains
, old_write_domain
;
3178 /* If we're coming from LLC cached, then we haven't
3179 * actually been tracking whether the data is in the
3180 * CPU cache or not, since we only allow one bit set
3181 * in obj->write_domain and have been skipping the clflushes.
3182 * Just set it to the CPU cache for now.
3184 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3185 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3187 old_read_domains
= obj
->base
.read_domains
;
3188 old_write_domain
= obj
->base
.write_domain
;
3190 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3191 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3193 trace_i915_gem_object_change_domain(obj
,
3198 obj
->cache_level
= cache_level
;
3199 i915_gem_verify_gtt(dev
);
3203 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3204 struct drm_file
*file
)
3206 struct drm_i915_gem_caching
*args
= data
;
3207 struct drm_i915_gem_object
*obj
;
3210 ret
= i915_mutex_lock_interruptible(dev
);
3214 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3215 if (&obj
->base
== NULL
) {
3220 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3222 drm_gem_object_unreference(&obj
->base
);
3224 mutex_unlock(&dev
->struct_mutex
);
3228 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3229 struct drm_file
*file
)
3231 struct drm_i915_gem_caching
*args
= data
;
3232 struct drm_i915_gem_object
*obj
;
3233 enum i915_cache_level level
;
3236 switch (args
->caching
) {
3237 case I915_CACHING_NONE
:
3238 level
= I915_CACHE_NONE
;
3240 case I915_CACHING_CACHED
:
3241 level
= I915_CACHE_LLC
;
3247 ret
= i915_mutex_lock_interruptible(dev
);
3251 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3252 if (&obj
->base
== NULL
) {
3257 ret
= i915_gem_object_set_cache_level(obj
, level
);
3259 drm_gem_object_unreference(&obj
->base
);
3261 mutex_unlock(&dev
->struct_mutex
);
3266 * Prepare buffer for display plane (scanout, cursors, etc).
3267 * Can be called from an uninterruptible phase (modesetting) and allows
3268 * any flushes to be pipelined (for pageflips).
3271 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3273 struct intel_ring_buffer
*pipelined
)
3275 u32 old_read_domains
, old_write_domain
;
3278 if (pipelined
!= obj
->ring
) {
3279 ret
= i915_gem_object_sync(obj
, pipelined
);
3284 /* The display engine is not coherent with the LLC cache on gen6. As
3285 * a result, we make sure that the pinning that is about to occur is
3286 * done with uncached PTEs. This is lowest common denominator for all
3289 * However for gen6+, we could do better by using the GFDT bit instead
3290 * of uncaching, which would allow us to flush all the LLC-cached data
3291 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3293 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3297 /* As the user may map the buffer once pinned in the display plane
3298 * (e.g. libkms for the bootup splash), we have to ensure that we
3299 * always use map_and_fenceable for all scanout buffers.
3301 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3305 i915_gem_object_flush_cpu_write_domain(obj
);
3307 old_write_domain
= obj
->base
.write_domain
;
3308 old_read_domains
= obj
->base
.read_domains
;
3310 /* It should now be out of any other write domains, and we can update
3311 * the domain values for our changes.
3313 obj
->base
.write_domain
= 0;
3314 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3316 trace_i915_gem_object_change_domain(obj
,
3324 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3328 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3331 ret
= i915_gem_object_wait_rendering(obj
, false);
3335 /* Ensure that we invalidate the GPU's caches and TLBs. */
3336 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3341 * Moves a single object to the CPU read, and possibly write domain.
3343 * This function returns when the move is complete, including waiting on
3347 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3349 uint32_t old_write_domain
, old_read_domains
;
3352 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3355 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3359 i915_gem_object_flush_gtt_write_domain(obj
);
3361 old_write_domain
= obj
->base
.write_domain
;
3362 old_read_domains
= obj
->base
.read_domains
;
3364 /* Flush the CPU cache if it's still invalid. */
3365 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3366 i915_gem_clflush_object(obj
);
3368 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3371 /* It should now be out of any other write domains, and we can update
3372 * the domain values for our changes.
3374 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3376 /* If we're writing through the CPU, then the GPU read domains will
3377 * need to be invalidated at next use.
3380 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3381 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3384 trace_i915_gem_object_change_domain(obj
,
3391 /* Throttle our rendering by waiting until the ring has completed our requests
3392 * emitted over 20 msec ago.
3394 * Note that if we were to use the current jiffies each time around the loop,
3395 * we wouldn't escape the function with any frames outstanding if the time to
3396 * render a frame was over 20ms.
3398 * This should get us reasonable parallelism between CPU and GPU but also
3399 * relatively low latency when blocking on a particular request to finish.
3402 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3405 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3406 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3407 struct drm_i915_gem_request
*request
;
3408 struct intel_ring_buffer
*ring
= NULL
;
3412 if (atomic_read(&dev_priv
->mm
.wedged
))
3415 spin_lock(&file_priv
->mm
.lock
);
3416 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3417 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3420 ring
= request
->ring
;
3421 seqno
= request
->seqno
;
3423 spin_unlock(&file_priv
->mm
.lock
);
3428 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3430 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3436 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3438 bool map_and_fenceable
,
3443 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3446 if (obj
->gtt_space
!= NULL
) {
3447 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3448 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3449 WARN(obj
->pin_count
,
3450 "bo is already pinned with incorrect alignment:"
3451 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3452 " obj->map_and_fenceable=%d\n",
3453 obj
->gtt_offset
, alignment
,
3455 obj
->map_and_fenceable
);
3456 ret
= i915_gem_object_unbind(obj
);
3462 if (obj
->gtt_space
== NULL
) {
3463 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3465 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3471 if (!dev_priv
->mm
.aliasing_ppgtt
)
3472 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3475 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3476 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3479 obj
->pin_mappable
|= map_and_fenceable
;
3485 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3487 BUG_ON(obj
->pin_count
== 0);
3488 BUG_ON(obj
->gtt_space
== NULL
);
3490 if (--obj
->pin_count
== 0)
3491 obj
->pin_mappable
= false;
3495 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3496 struct drm_file
*file
)
3498 struct drm_i915_gem_pin
*args
= data
;
3499 struct drm_i915_gem_object
*obj
;
3502 ret
= i915_mutex_lock_interruptible(dev
);
3506 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3507 if (&obj
->base
== NULL
) {
3512 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3513 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3518 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3519 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3525 obj
->user_pin_count
++;
3526 obj
->pin_filp
= file
;
3527 if (obj
->user_pin_count
== 1) {
3528 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3533 /* XXX - flush the CPU caches for pinned objects
3534 * as the X server doesn't manage domains yet
3536 i915_gem_object_flush_cpu_write_domain(obj
);
3537 args
->offset
= obj
->gtt_offset
;
3539 drm_gem_object_unreference(&obj
->base
);
3541 mutex_unlock(&dev
->struct_mutex
);
3546 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3547 struct drm_file
*file
)
3549 struct drm_i915_gem_pin
*args
= data
;
3550 struct drm_i915_gem_object
*obj
;
3553 ret
= i915_mutex_lock_interruptible(dev
);
3557 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3558 if (&obj
->base
== NULL
) {
3563 if (obj
->pin_filp
!= file
) {
3564 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3569 obj
->user_pin_count
--;
3570 if (obj
->user_pin_count
== 0) {
3571 obj
->pin_filp
= NULL
;
3572 i915_gem_object_unpin(obj
);
3576 drm_gem_object_unreference(&obj
->base
);
3578 mutex_unlock(&dev
->struct_mutex
);
3583 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3584 struct drm_file
*file
)
3586 struct drm_i915_gem_busy
*args
= data
;
3587 struct drm_i915_gem_object
*obj
;
3590 ret
= i915_mutex_lock_interruptible(dev
);
3594 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3595 if (&obj
->base
== NULL
) {
3600 /* Count all active objects as busy, even if they are currently not used
3601 * by the gpu. Users of this interface expect objects to eventually
3602 * become non-busy without any further actions, therefore emit any
3603 * necessary flushes here.
3605 ret
= i915_gem_object_flush_active(obj
);
3607 args
->busy
= obj
->active
;
3609 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3610 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3613 drm_gem_object_unreference(&obj
->base
);
3615 mutex_unlock(&dev
->struct_mutex
);
3620 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3621 struct drm_file
*file_priv
)
3623 return i915_gem_ring_throttle(dev
, file_priv
);
3627 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3628 struct drm_file
*file_priv
)
3630 struct drm_i915_gem_madvise
*args
= data
;
3631 struct drm_i915_gem_object
*obj
;
3634 switch (args
->madv
) {
3635 case I915_MADV_DONTNEED
:
3636 case I915_MADV_WILLNEED
:
3642 ret
= i915_mutex_lock_interruptible(dev
);
3646 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3647 if (&obj
->base
== NULL
) {
3652 if (obj
->pin_count
) {
3657 if (obj
->madv
!= __I915_MADV_PURGED
)
3658 obj
->madv
= args
->madv
;
3660 /* if the object is no longer attached, discard its backing storage */
3661 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3662 i915_gem_object_truncate(obj
);
3664 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3667 drm_gem_object_unreference(&obj
->base
);
3669 mutex_unlock(&dev
->struct_mutex
);
3673 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3674 const struct drm_i915_gem_object_ops
*ops
)
3676 INIT_LIST_HEAD(&obj
->mm_list
);
3677 INIT_LIST_HEAD(&obj
->gtt_list
);
3678 INIT_LIST_HEAD(&obj
->ring_list
);
3679 INIT_LIST_HEAD(&obj
->exec_list
);
3683 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3684 obj
->madv
= I915_MADV_WILLNEED
;
3685 /* Avoid an unnecessary call to unbind on the first bind. */
3686 obj
->map_and_fenceable
= true;
3688 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3691 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3692 .get_pages
= i915_gem_object_get_pages_gtt
,
3693 .put_pages
= i915_gem_object_put_pages_gtt
,
3696 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3699 struct drm_i915_gem_object
*obj
;
3700 struct address_space
*mapping
;
3703 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3707 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3712 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3713 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3714 /* 965gm cannot relocate objects above 4GiB. */
3715 mask
&= ~__GFP_HIGHMEM
;
3716 mask
|= __GFP_DMA32
;
3719 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3720 mapping_set_gfp_mask(mapping
, mask
);
3722 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3724 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3725 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3728 /* On some devices, we can have the GPU use the LLC (the CPU
3729 * cache) for about a 10% performance improvement
3730 * compared to uncached. Graphics requests other than
3731 * display scanout are coherent with the CPU in
3732 * accessing this cache. This means in this mode we
3733 * don't need to clflush on the CPU side, and on the
3734 * GPU side we only need to flush internal caches to
3735 * get data visible to the CPU.
3737 * However, we maintain the display planes as UC, and so
3738 * need to rebind when first used as such.
3740 obj
->cache_level
= I915_CACHE_LLC
;
3742 obj
->cache_level
= I915_CACHE_NONE
;
3747 int i915_gem_init_object(struct drm_gem_object
*obj
)
3754 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3756 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3757 struct drm_device
*dev
= obj
->base
.dev
;
3758 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3760 trace_i915_gem_object_destroy(obj
);
3763 i915_gem_detach_phys_object(dev
, obj
);
3766 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3767 bool was_interruptible
;
3769 was_interruptible
= dev_priv
->mm
.interruptible
;
3770 dev_priv
->mm
.interruptible
= false;
3772 WARN_ON(i915_gem_object_unbind(obj
));
3774 dev_priv
->mm
.interruptible
= was_interruptible
;
3777 obj
->pages_pin_count
= 0;
3778 i915_gem_object_put_pages(obj
);
3779 i915_gem_object_free_mmap_offset(obj
);
3783 if (obj
->base
.import_attach
)
3784 drm_prime_gem_destroy(&obj
->base
, NULL
);
3786 drm_gem_object_release(&obj
->base
);
3787 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3794 i915_gem_idle(struct drm_device
*dev
)
3796 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3799 mutex_lock(&dev
->struct_mutex
);
3801 if (dev_priv
->mm
.suspended
) {
3802 mutex_unlock(&dev
->struct_mutex
);
3806 ret
= i915_gpu_idle(dev
);
3808 mutex_unlock(&dev
->struct_mutex
);
3811 i915_gem_retire_requests(dev
);
3813 /* Under UMS, be paranoid and evict. */
3814 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3815 i915_gem_evict_everything(dev
);
3817 i915_gem_reset_fences(dev
);
3819 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3820 * We need to replace this with a semaphore, or something.
3821 * And not confound mm.suspended!
3823 dev_priv
->mm
.suspended
= 1;
3824 del_timer_sync(&dev_priv
->hangcheck_timer
);
3826 i915_kernel_lost_context(dev
);
3827 i915_gem_cleanup_ringbuffer(dev
);
3829 mutex_unlock(&dev
->struct_mutex
);
3831 /* Cancel the retire work handler, which should be idle now. */
3832 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3837 void i915_gem_l3_remap(struct drm_device
*dev
)
3839 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3843 if (!IS_IVYBRIDGE(dev
))
3846 if (!dev_priv
->l3_parity
.remap_info
)
3849 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3850 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3851 POSTING_READ(GEN7_MISCCPCTL
);
3853 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3854 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3855 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3856 DRM_DEBUG("0x%x was already programmed to %x\n",
3857 GEN7_L3LOG_BASE
+ i
, remap
);
3858 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3859 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3860 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3863 /* Make sure all the writes land before disabling dop clock gating */
3864 POSTING_READ(GEN7_L3LOG_BASE
);
3866 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3869 void i915_gem_init_swizzling(struct drm_device
*dev
)
3871 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3873 if (INTEL_INFO(dev
)->gen
< 5 ||
3874 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3877 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3878 DISP_TILE_SURFACE_SWIZZLING
);
3883 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3885 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3887 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3891 intel_enable_blt(struct drm_device
*dev
)
3896 /* The blitter was dysfunctional on early prototypes */
3897 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3898 DRM_INFO("BLT not supported on this pre-production hardware;"
3899 " graphics performance will be degraded.\n");
3907 i915_gem_init_hw(struct drm_device
*dev
)
3909 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3912 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3915 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3916 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3918 i915_gem_l3_remap(dev
);
3920 i915_gem_init_swizzling(dev
);
3922 ret
= intel_init_render_ring_buffer(dev
);
3927 ret
= intel_init_bsd_ring_buffer(dev
);
3929 goto cleanup_render_ring
;
3932 if (intel_enable_blt(dev
)) {
3933 ret
= intel_init_blt_ring_buffer(dev
);
3935 goto cleanup_bsd_ring
;
3938 dev_priv
->next_seqno
= 1;
3941 * XXX: There was some w/a described somewhere suggesting loading
3942 * contexts before PPGTT.
3944 i915_gem_context_init(dev
);
3945 i915_gem_init_ppgtt(dev
);
3950 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3951 cleanup_render_ring
:
3952 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3957 intel_enable_ppgtt(struct drm_device
*dev
)
3959 if (i915_enable_ppgtt
>= 0)
3960 return i915_enable_ppgtt
;
3962 #ifdef CONFIG_INTEL_IOMMU
3963 /* Disable ppgtt on SNB if VT-d is on. */
3964 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3971 int i915_gem_init(struct drm_device
*dev
)
3973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3974 unsigned long gtt_size
, mappable_size
;
3977 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3978 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3980 mutex_lock(&dev
->struct_mutex
);
3981 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3982 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3983 * aperture accordingly when using aliasing ppgtt. */
3984 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3986 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3988 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3990 mutex_unlock(&dev
->struct_mutex
);
3994 /* Let GEM Manage all of the aperture.
3996 * However, leave one page at the end still bound to the scratch
3997 * page. There are a number of places where the hardware
3998 * apparently prefetches past the end of the object, and we've
3999 * seen multiple hangs with the GPU head pointer stuck in a
4000 * batchbuffer bound at the last page of the aperture. One page
4001 * should be enough to keep any prefetching inside of the
4004 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
4008 ret
= i915_gem_init_hw(dev
);
4009 mutex_unlock(&dev
->struct_mutex
);
4011 i915_gem_cleanup_aliasing_ppgtt(dev
);
4015 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4016 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4017 dev_priv
->dri1
.allow_batchbuffer
= 1;
4022 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4024 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4025 struct intel_ring_buffer
*ring
;
4028 for_each_ring(ring
, dev_priv
, i
)
4029 intel_cleanup_ring_buffer(ring
);
4033 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4034 struct drm_file
*file_priv
)
4036 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4039 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4042 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4043 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4044 atomic_set(&dev_priv
->mm
.wedged
, 0);
4047 mutex_lock(&dev
->struct_mutex
);
4048 dev_priv
->mm
.suspended
= 0;
4050 ret
= i915_gem_init_hw(dev
);
4052 mutex_unlock(&dev
->struct_mutex
);
4056 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4057 mutex_unlock(&dev
->struct_mutex
);
4059 ret
= drm_irq_install(dev
);
4061 goto cleanup_ringbuffer
;
4066 mutex_lock(&dev
->struct_mutex
);
4067 i915_gem_cleanup_ringbuffer(dev
);
4068 dev_priv
->mm
.suspended
= 1;
4069 mutex_unlock(&dev
->struct_mutex
);
4075 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4076 struct drm_file
*file_priv
)
4078 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4081 drm_irq_uninstall(dev
);
4082 return i915_gem_idle(dev
);
4086 i915_gem_lastclose(struct drm_device
*dev
)
4090 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4093 ret
= i915_gem_idle(dev
);
4095 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4099 init_ring_lists(struct intel_ring_buffer
*ring
)
4101 INIT_LIST_HEAD(&ring
->active_list
);
4102 INIT_LIST_HEAD(&ring
->request_list
);
4106 i915_gem_load(struct drm_device
*dev
)
4109 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4111 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4112 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4113 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4114 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4115 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4116 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4117 init_ring_lists(&dev_priv
->ring
[i
]);
4118 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4119 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4120 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4121 i915_gem_retire_work_handler
);
4122 init_completion(&dev_priv
->error_completion
);
4124 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4126 I915_WRITE(MI_ARB_STATE
,
4127 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4130 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4132 /* Old X drivers will take 0-2 for front, back, depth buffers */
4133 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4134 dev_priv
->fence_reg_start
= 3;
4136 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4137 dev_priv
->num_fence_regs
= 16;
4139 dev_priv
->num_fence_regs
= 8;
4141 /* Initialize fence registers to zero */
4142 i915_gem_reset_fences(dev
);
4144 i915_gem_detect_bit_6_swizzle(dev
);
4145 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4147 dev_priv
->mm
.interruptible
= true;
4149 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4150 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4151 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4155 * Create a physically contiguous memory object for this object
4156 * e.g. for cursor + overlay regs
4158 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4159 int id
, int size
, int align
)
4161 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4162 struct drm_i915_gem_phys_object
*phys_obj
;
4165 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4168 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4174 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4175 if (!phys_obj
->handle
) {
4180 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4183 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4191 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4193 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4194 struct drm_i915_gem_phys_object
*phys_obj
;
4196 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4199 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4200 if (phys_obj
->cur_obj
) {
4201 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4205 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4207 drm_pci_free(dev
, phys_obj
->handle
);
4209 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4212 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4216 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4217 i915_gem_free_phys_object(dev
, i
);
4220 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4221 struct drm_i915_gem_object
*obj
)
4223 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4230 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4232 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4233 for (i
= 0; i
< page_count
; i
++) {
4234 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4235 if (!IS_ERR(page
)) {
4236 char *dst
= kmap_atomic(page
);
4237 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4240 drm_clflush_pages(&page
, 1);
4242 set_page_dirty(page
);
4243 mark_page_accessed(page
);
4244 page_cache_release(page
);
4247 i915_gem_chipset_flush(dev
);
4249 obj
->phys_obj
->cur_obj
= NULL
;
4250 obj
->phys_obj
= NULL
;
4254 i915_gem_attach_phys_object(struct drm_device
*dev
,
4255 struct drm_i915_gem_object
*obj
,
4259 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4260 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4265 if (id
> I915_MAX_PHYS_OBJECT
)
4268 if (obj
->phys_obj
) {
4269 if (obj
->phys_obj
->id
== id
)
4271 i915_gem_detach_phys_object(dev
, obj
);
4274 /* create a new object */
4275 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4276 ret
= i915_gem_init_phys_object(dev
, id
,
4277 obj
->base
.size
, align
);
4279 DRM_ERROR("failed to init phys object %d size: %zu\n",
4280 id
, obj
->base
.size
);
4285 /* bind to the object */
4286 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4287 obj
->phys_obj
->cur_obj
= obj
;
4289 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4291 for (i
= 0; i
< page_count
; i
++) {
4295 page
= shmem_read_mapping_page(mapping
, i
);
4297 return PTR_ERR(page
);
4299 src
= kmap_atomic(page
);
4300 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4301 memcpy(dst
, src
, PAGE_SIZE
);
4304 mark_page_accessed(page
);
4305 page_cache_release(page
);
4312 i915_gem_phys_pwrite(struct drm_device
*dev
,
4313 struct drm_i915_gem_object
*obj
,
4314 struct drm_i915_gem_pwrite
*args
,
4315 struct drm_file
*file_priv
)
4317 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4318 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4320 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4321 unsigned long unwritten
;
4323 /* The physical object once assigned is fixed for the lifetime
4324 * of the obj, so we can safely drop the lock and continue
4327 mutex_unlock(&dev
->struct_mutex
);
4328 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4329 mutex_lock(&dev
->struct_mutex
);
4334 i915_gem_chipset_flush(dev
);
4338 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4340 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4342 /* Clean up our request list when the client is going away, so that
4343 * later retire_requests won't dereference our soon-to-be-gone
4346 spin_lock(&file_priv
->mm
.lock
);
4347 while (!list_empty(&file_priv
->mm
.request_list
)) {
4348 struct drm_i915_gem_request
*request
;
4350 request
= list_first_entry(&file_priv
->mm
.request_list
,
4351 struct drm_i915_gem_request
,
4353 list_del(&request
->client_list
);
4354 request
->file_priv
= NULL
;
4356 spin_unlock(&file_priv
->mm
.lock
);
4359 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4361 if (!mutex_is_locked(mutex
))
4364 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4365 return mutex
->owner
== task
;
4367 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4373 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4375 struct drm_i915_private
*dev_priv
=
4376 container_of(shrinker
,
4377 struct drm_i915_private
,
4378 mm
.inactive_shrinker
);
4379 struct drm_device
*dev
= dev_priv
->dev
;
4380 struct drm_i915_gem_object
*obj
;
4381 int nr_to_scan
= sc
->nr_to_scan
;
4385 if (!mutex_trylock(&dev
->struct_mutex
)) {
4386 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4389 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4396 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4398 i915_gem_shrink_all(dev_priv
);
4402 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4403 if (obj
->pages_pin_count
== 0)
4404 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4405 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4406 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4407 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4410 mutex_unlock(&dev
->struct_mutex
);