2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
522 i915_gem_object_retire(obj
);
525 ret
= i915_gem_object_get_pages(obj
);
529 i915_gem_object_pin_pages(obj
);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
539 char __user
*user_data
,
540 bool page_do_bit17_swizzling
, bool needs_clflush
)
545 if (unlikely(page_do_bit17_swizzling
))
548 vaddr
= kmap_atomic(page
);
550 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
552 ret
= __copy_to_user_inatomic(user_data
,
553 vaddr
+ shmem_page_offset
,
555 kunmap_atomic(vaddr
);
557 return ret
? -EFAULT
: 0;
561 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
564 if (unlikely(swizzled
)) {
565 unsigned long start
= (unsigned long) addr
;
566 unsigned long end
= (unsigned long) addr
+ length
;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start
= round_down(start
, 128);
573 end
= round_up(end
, 128);
575 drm_clflush_virt_range((void *)start
, end
- start
);
577 drm_clflush_virt_range(addr
, length
);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
586 char __user
*user_data
,
587 bool page_do_bit17_swizzling
, bool needs_clflush
)
594 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
596 page_do_bit17_swizzling
);
598 if (page_do_bit17_swizzling
)
599 ret
= __copy_to_user_swizzled(user_data
,
600 vaddr
, shmem_page_offset
,
603 ret
= __copy_to_user(user_data
,
604 vaddr
+ shmem_page_offset
,
608 return ret
? - EFAULT
: 0;
612 i915_gem_shmem_pread(struct drm_device
*dev
,
613 struct drm_i915_gem_object
*obj
,
614 struct drm_i915_gem_pread
*args
,
615 struct drm_file
*file
)
617 char __user
*user_data
;
620 int shmem_page_offset
, page_length
, ret
= 0;
621 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
623 int needs_clflush
= 0;
624 struct sg_page_iter sg_iter
;
626 user_data
= to_user_ptr(args
->data_ptr
);
629 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
631 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
635 offset
= args
->offset
;
637 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
638 offset
>> PAGE_SHIFT
) {
639 struct page
*page
= sg_page_iter_page(&sg_iter
);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset
= offset_in_page(offset
);
650 page_length
= remain
;
651 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
652 page_length
= PAGE_SIZE
- shmem_page_offset
;
654 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
655 (page_to_phys(page
) & (1 << 17)) != 0;
657 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
663 mutex_unlock(&dev
->struct_mutex
);
665 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
666 ret
= fault_in_multipages_writeable(user_data
, remain
);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
676 user_data
, page_do_bit17_swizzling
,
679 mutex_lock(&dev
->struct_mutex
);
685 remain
-= page_length
;
686 user_data
+= page_length
;
687 offset
+= page_length
;
691 i915_gem_object_unpin_pages(obj
);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
703 struct drm_file
*file
)
705 struct drm_i915_gem_pread
*args
= data
;
706 struct drm_i915_gem_object
*obj
;
712 if (!access_ok(VERIFY_WRITE
,
713 to_user_ptr(args
->data_ptr
),
717 ret
= i915_mutex_lock_interruptible(dev
);
721 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
722 if (&obj
->base
== NULL
) {
727 /* Bounds check source. */
728 if (args
->offset
> obj
->base
.size
||
729 args
->size
> obj
->base
.size
- args
->offset
) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj
->base
.filp
) {
742 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
744 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
747 drm_gem_object_unreference(&obj
->base
);
749 mutex_unlock(&dev
->struct_mutex
);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping
*mapping
,
759 loff_t page_base
, int page_offset
,
760 char __user
*user_data
,
763 void __iomem
*vaddr_atomic
;
765 unsigned long unwritten
;
767 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
770 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
772 io_mapping_unmap_atomic(vaddr_atomic
);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
782 struct drm_i915_gem_object
*obj
,
783 struct drm_i915_gem_pwrite
*args
,
784 struct drm_file
*file
)
786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
788 loff_t offset
, page_base
;
789 char __user
*user_data
;
790 int page_offset
, page_length
, ret
;
792 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
796 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
800 ret
= i915_gem_object_put_fence(obj
);
804 user_data
= to_user_ptr(args
->data_ptr
);
807 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
809 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base
= offset
& PAGE_MASK
;
819 page_offset
= offset_in_page(offset
);
820 page_length
= remain
;
821 if ((page_offset
+ remain
) > PAGE_SIZE
)
822 page_length
= PAGE_SIZE
- page_offset
;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
829 page_offset
, user_data
, page_length
)) {
834 remain
-= page_length
;
835 user_data
+= page_length
;
836 offset
+= page_length
;
840 intel_fb_obj_flush(obj
, false);
842 i915_gem_object_ggtt_unpin(obj
);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
853 char __user
*user_data
,
854 bool page_do_bit17_swizzling
,
855 bool needs_clflush_before
,
856 bool needs_clflush_after
)
861 if (unlikely(page_do_bit17_swizzling
))
864 vaddr
= kmap_atomic(page
);
865 if (needs_clflush_before
)
866 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
868 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
869 user_data
, page_length
);
870 if (needs_clflush_after
)
871 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
873 kunmap_atomic(vaddr
);
875 return ret
? -EFAULT
: 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
882 char __user
*user_data
,
883 bool page_do_bit17_swizzling
,
884 bool needs_clflush_before
,
885 bool needs_clflush_after
)
891 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
892 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
894 page_do_bit17_swizzling
);
895 if (page_do_bit17_swizzling
)
896 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
900 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
903 if (needs_clflush_after
)
904 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
906 page_do_bit17_swizzling
);
909 return ret
? -EFAULT
: 0;
913 i915_gem_shmem_pwrite(struct drm_device
*dev
,
914 struct drm_i915_gem_object
*obj
,
915 struct drm_i915_gem_pwrite
*args
,
916 struct drm_file
*file
)
920 char __user
*user_data
;
921 int shmem_page_offset
, page_length
, ret
= 0;
922 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
923 int hit_slowpath
= 0;
924 int needs_clflush_after
= 0;
925 int needs_clflush_before
= 0;
926 struct sg_page_iter sg_iter
;
928 user_data
= to_user_ptr(args
->data_ptr
);
931 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after
= cpu_write_needs_clflush(obj
);
939 ret
= i915_gem_object_wait_rendering(obj
, false);
943 i915_gem_object_retire(obj
);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
957 i915_gem_object_pin_pages(obj
);
959 offset
= args
->offset
;
962 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
963 offset
>> PAGE_SHIFT
) {
964 struct page
*page
= sg_page_iter_page(&sg_iter
);
965 int partial_cacheline_write
;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset
= offset_in_page(offset
);
977 page_length
= remain
;
978 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
979 page_length
= PAGE_SIZE
- shmem_page_offset
;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write
= needs_clflush_before
&&
985 ((shmem_page_offset
| page_length
)
986 & (boot_cpu_data
.x86_clflush_size
- 1));
988 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
989 (page_to_phys(page
) & (1 << 17)) != 0;
991 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
992 user_data
, page_do_bit17_swizzling
,
993 partial_cacheline_write
,
994 needs_clflush_after
);
999 mutex_unlock(&dev
->struct_mutex
);
1000 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1001 user_data
, page_do_bit17_swizzling
,
1002 partial_cacheline_write
,
1003 needs_clflush_after
);
1005 mutex_lock(&dev
->struct_mutex
);
1011 remain
-= page_length
;
1012 user_data
+= page_length
;
1013 offset
+= page_length
;
1017 i915_gem_object_unpin_pages(obj
);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after
&&
1026 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1027 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1028 i915_gem_chipset_flush(dev
);
1032 if (needs_clflush_after
)
1033 i915_gem_chipset_flush(dev
);
1035 intel_fb_obj_flush(obj
, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_i915_gem_pwrite
*args
= data
;
1050 struct drm_i915_gem_object
*obj
;
1053 if (args
->size
== 0)
1056 if (!access_ok(VERIFY_READ
,
1057 to_user_ptr(args
->data_ptr
),
1061 if (likely(!i915
.prefault_disable
)) {
1062 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1068 intel_runtime_pm_get(dev_priv
);
1070 ret
= i915_mutex_lock_interruptible(dev
);
1074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1075 if (&obj
->base
== NULL
) {
1080 /* Bounds check destination. */
1081 if (args
->offset
> obj
->base
.size
||
1082 args
->size
> obj
->base
.size
- args
->offset
) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj
->base
.filp
) {
1095 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1105 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1106 cpu_write_needs_clflush(obj
)) {
1107 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1114 if (obj
->phys_handle
)
1115 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1117 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1121 drm_gem_object_unreference(&obj
->base
);
1123 mutex_unlock(&dev
->struct_mutex
);
1125 intel_runtime_pm_put(dev_priv
);
1131 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1134 if (i915_reset_in_progress(error
)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error
))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error
->reload_in_reset
)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1164 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1167 if (req
== req
->ring
->outstanding_lazy_request
)
1168 ret
= i915_add_request(req
->ring
);
1173 static void fake_irq(unsigned long data
)
1175 wake_up_process((struct task_struct
*)data
);
1178 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1179 struct intel_engine_cs
*ring
)
1181 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1184 static int __i915_spin_request(struct drm_i915_gem_request
*rq
)
1186 unsigned long timeout
;
1188 if (i915_gem_request_get_ring(rq
)->irq_refcount
)
1191 timeout
= jiffies
+ 1;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(rq
, true))
1196 if (time_after_eq(jiffies
, timeout
))
1199 cpu_relax_lowlatency();
1201 if (i915_gem_request_completed(rq
, false))
1208 * __i915_wait_request - wait until execution of request has finished
1210 * @reset_counter: reset sequence associated with the given request
1211 * @interruptible: do an interruptible wait (normally yes)
1212 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1214 * Note: It is of utmost importance that the passed in seqno and reset_counter
1215 * values have been read by the caller in an smp safe manner. Where read-side
1216 * locks are involved, it is sufficient to read the reset_counter before
1217 * unlocking the lock that protects the seqno. For lockless tricks, the
1218 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1221 * Returns 0 if the request was found within the alloted time. Else returns the
1222 * errno with remaining time filled in timeout argument.
1224 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1225 unsigned reset_counter
,
1228 struct drm_i915_file_private
*file_priv
)
1230 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1231 struct drm_device
*dev
= ring
->dev
;
1232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1233 const bool irq_test_in_progress
=
1234 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1236 unsigned long timeout_expire
;
1240 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1242 if (i915_gem_request_completed(req
, true))
1245 timeout_expire
= timeout
?
1246 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1248 if (INTEL_INFO(dev
)->gen
>= 6)
1249 gen6_rps_boost(dev_priv
, file_priv
);
1251 /* Record current time in case interrupted by signal, or wedged */
1252 trace_i915_gem_request_wait_begin(req
);
1253 before
= ktime_get_raw_ns();
1255 /* Optimistic spin for the next jiffie before touching IRQs */
1256 ret
= __i915_spin_request(req
);
1260 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1266 struct timer_list timer
;
1268 prepare_to_wait(&ring
->irq_queue
, &wait
,
1269 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1271 /* We need to check whether any gpu reset happened in between
1272 * the caller grabbing the seqno and now ... */
1273 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1274 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1275 * is truely gone. */
1276 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1282 if (i915_gem_request_completed(req
, false)) {
1287 if (interruptible
&& signal_pending(current
)) {
1292 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1297 timer
.function
= NULL
;
1298 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1299 unsigned long expire
;
1301 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1302 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1303 mod_timer(&timer
, expire
);
1308 if (timer
.function
) {
1309 del_singleshot_timer_sync(&timer
);
1310 destroy_timer_on_stack(&timer
);
1313 if (!irq_test_in_progress
)
1314 ring
->irq_put(ring
);
1316 finish_wait(&ring
->irq_queue
, &wait
);
1319 now
= ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(req
);
1323 s64 tres
= *timeout
- (now
- before
);
1325 *timeout
= tres
< 0 ? 0 : tres
;
1328 * Apparently ktime isn't accurate enough and occasionally has a
1329 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1330 * things up to make the test happy. We allow up to 1 jiffy.
1332 * This is a regrssion from the timespec->ktime conversion.
1334 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1342 * Waits for a request to be signaled, and cleans up the
1343 * request and object lists appropriately for that event.
1346 i915_wait_request(struct drm_i915_gem_request
*req
)
1348 struct drm_device
*dev
;
1349 struct drm_i915_private
*dev_priv
;
1351 unsigned reset_counter
;
1354 BUG_ON(req
== NULL
);
1356 dev
= req
->ring
->dev
;
1357 dev_priv
= dev
->dev_private
;
1358 interruptible
= dev_priv
->mm
.interruptible
;
1360 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1362 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1366 ret
= i915_gem_check_olr(req
);
1370 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1371 i915_gem_request_reference(req
);
1372 ret
= __i915_wait_request(req
, reset_counter
,
1373 interruptible
, NULL
, NULL
);
1374 i915_gem_request_unreference(req
);
1379 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1384 /* Manually manage the write flush as we may have not yet
1385 * retired the buffer.
1387 * Note that the last_write_req is always the earlier of
1388 * the two (read/write) requests, so if we haved successfully waited,
1389 * we know we have passed the last write.
1391 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1397 * Ensures that all rendering to the object has completed and the object is
1398 * safe to unbind from the GTT or access from the CPU.
1400 static __must_check
int
1401 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1404 struct drm_i915_gem_request
*req
;
1407 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1411 ret
= i915_wait_request(req
);
1415 return i915_gem_object_wait_rendering__tail(obj
);
1418 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1419 * as the object state may change during this call.
1421 static __must_check
int
1422 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1423 struct drm_i915_file_private
*file_priv
,
1426 struct drm_i915_gem_request
*req
;
1427 struct drm_device
*dev
= obj
->base
.dev
;
1428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1429 unsigned reset_counter
;
1432 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1433 BUG_ON(!dev_priv
->mm
.interruptible
);
1435 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1439 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1443 ret
= i915_gem_check_olr(req
);
1447 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1448 i915_gem_request_reference(req
);
1449 mutex_unlock(&dev
->struct_mutex
);
1450 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1451 mutex_lock(&dev
->struct_mutex
);
1452 i915_gem_request_unreference(req
);
1456 return i915_gem_object_wait_rendering__tail(obj
);
1460 * Called when user space prepares to use an object with the CPU, either
1461 * through the mmap ioctl's mapping or a GTT mapping.
1464 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1465 struct drm_file
*file
)
1467 struct drm_i915_gem_set_domain
*args
= data
;
1468 struct drm_i915_gem_object
*obj
;
1469 uint32_t read_domains
= args
->read_domains
;
1470 uint32_t write_domain
= args
->write_domain
;
1473 /* Only handle setting domains to types used by the CPU. */
1474 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1477 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1480 /* Having something in the write domain implies it's in the read
1481 * domain, and only that read domain. Enforce that in the request.
1483 if (write_domain
!= 0 && read_domains
!= write_domain
)
1486 ret
= i915_mutex_lock_interruptible(dev
);
1490 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1491 if (&obj
->base
== NULL
) {
1496 /* Try to flush the object off the GPU without holding the lock.
1497 * We will repeat the flush holding the lock in the normal manner
1498 * to catch cases where we are gazumped.
1500 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1506 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1507 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1509 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1512 drm_gem_object_unreference(&obj
->base
);
1514 mutex_unlock(&dev
->struct_mutex
);
1519 * Called when user space has done writes to this buffer
1522 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1523 struct drm_file
*file
)
1525 struct drm_i915_gem_sw_finish
*args
= data
;
1526 struct drm_i915_gem_object
*obj
;
1529 ret
= i915_mutex_lock_interruptible(dev
);
1533 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1534 if (&obj
->base
== NULL
) {
1539 /* Pinned buffers may be scanout, so flush the cache */
1540 if (obj
->pin_display
)
1541 i915_gem_object_flush_cpu_write_domain(obj
);
1543 drm_gem_object_unreference(&obj
->base
);
1545 mutex_unlock(&dev
->struct_mutex
);
1550 * Maps the contents of an object, returning the address it is mapped
1553 * While the mapping holds a reference on the contents of the object, it doesn't
1554 * imply a ref on the object itself.
1558 * DRM driver writers who look a this function as an example for how to do GEM
1559 * mmap support, please don't implement mmap support like here. The modern way
1560 * to implement DRM mmap support is with an mmap offset ioctl (like
1561 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1562 * That way debug tooling like valgrind will understand what's going on, hiding
1563 * the mmap call in a driver private ioctl will break that. The i915 driver only
1564 * does cpu mmaps this way because we didn't know better.
1567 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1568 struct drm_file
*file
)
1570 struct drm_i915_gem_mmap
*args
= data
;
1571 struct drm_gem_object
*obj
;
1574 if (args
->flags
& ~(I915_MMAP_WC
))
1577 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1580 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1584 /* prime objects have no backing filp to GEM mmap
1588 drm_gem_object_unreference_unlocked(obj
);
1592 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1593 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1595 if (args
->flags
& I915_MMAP_WC
) {
1596 struct mm_struct
*mm
= current
->mm
;
1597 struct vm_area_struct
*vma
;
1599 down_write(&mm
->mmap_sem
);
1600 vma
= find_vma(mm
, addr
);
1603 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1606 up_write(&mm
->mmap_sem
);
1608 drm_gem_object_unreference_unlocked(obj
);
1609 if (IS_ERR((void *)addr
))
1612 args
->addr_ptr
= (uint64_t) addr
;
1618 * i915_gem_fault - fault a page into the GTT
1619 * vma: VMA in question
1622 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1623 * from userspace. The fault handler takes care of binding the object to
1624 * the GTT (if needed), allocating and programming a fence register (again,
1625 * only if needed based on whether the old reg is still valid or the object
1626 * is tiled) and inserting a new PTE into the faulting process.
1628 * Note that the faulting process may involve evicting existing objects
1629 * from the GTT and/or fence registers to make room. So performance may
1630 * suffer if the GTT working set is large or there are few fence registers
1633 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1635 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1636 struct drm_device
*dev
= obj
->base
.dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1639 pgoff_t page_offset
;
1642 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1644 intel_runtime_pm_get(dev_priv
);
1646 /* We don't use vmf->pgoff since that has the fake offset */
1647 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1650 ret
= i915_mutex_lock_interruptible(dev
);
1654 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1656 /* Try to flush the object off the GPU first without holding the lock.
1657 * Upon reacquiring the lock, we will perform our sanity checks and then
1658 * repeat the flush holding the lock in the normal manner to catch cases
1659 * where we are gazumped.
1661 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1665 /* Access to snoopable pages through the GTT is incoherent. */
1666 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1671 /* Use a partial view if the object is bigger than the aperture. */
1672 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1673 obj
->tiling_mode
== I915_TILING_NONE
) {
1674 static const unsigned int chunk_size
= 256; // 1 MiB
1676 memset(&view
, 0, sizeof(view
));
1677 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1678 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1679 view
.params
.partial
.size
=
1682 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1683 view
.params
.partial
.offset
);
1686 /* Now pin it into the GTT if needed */
1687 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1691 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1695 ret
= i915_gem_object_get_fence(obj
);
1699 /* Finally, remap it using the new GTT offset */
1700 pfn
= dev_priv
->gtt
.mappable_base
+
1701 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1704 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1705 /* Overriding existing pages in partial view does not cause
1706 * us any trouble as TLBs are still valid because the fault
1707 * is due to userspace losing part of the mapping or never
1708 * having accessed it before (at this partials' range).
1710 unsigned long base
= vma
->vm_start
+
1711 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1714 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1715 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1720 obj
->fault_mappable
= true;
1722 if (!obj
->fault_mappable
) {
1723 unsigned long size
= min_t(unsigned long,
1724 vma
->vm_end
- vma
->vm_start
,
1728 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1729 ret
= vm_insert_pfn(vma
,
1730 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1736 obj
->fault_mappable
= true;
1738 ret
= vm_insert_pfn(vma
,
1739 (unsigned long)vmf
->virtual_address
,
1743 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1745 mutex_unlock(&dev
->struct_mutex
);
1750 * We eat errors when the gpu is terminally wedged to avoid
1751 * userspace unduly crashing (gl has no provisions for mmaps to
1752 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1753 * and so needs to be reported.
1755 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1756 ret
= VM_FAULT_SIGBUS
;
1761 * EAGAIN means the gpu is hung and we'll wait for the error
1762 * handler to reset everything when re-faulting in
1763 * i915_mutex_lock_interruptible.
1770 * EBUSY is ok: this just means that another thread
1771 * already did the job.
1773 ret
= VM_FAULT_NOPAGE
;
1780 ret
= VM_FAULT_SIGBUS
;
1783 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1784 ret
= VM_FAULT_SIGBUS
;
1788 intel_runtime_pm_put(dev_priv
);
1793 * i915_gem_release_mmap - remove physical page mappings
1794 * @obj: obj in question
1796 * Preserve the reservation of the mmapping with the DRM core code, but
1797 * relinquish ownership of the pages back to the system.
1799 * It is vital that we remove the page mapping if we have mapped a tiled
1800 * object through the GTT and then lose the fence register due to
1801 * resource pressure. Similarly if the object has been moved out of the
1802 * aperture, than pages mapped into userspace must be revoked. Removing the
1803 * mapping will then trigger a page fault on the next user access, allowing
1804 * fixup by i915_gem_fault().
1807 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1809 if (!obj
->fault_mappable
)
1812 drm_vma_node_unmap(&obj
->base
.vma_node
,
1813 obj
->base
.dev
->anon_inode
->i_mapping
);
1814 obj
->fault_mappable
= false;
1818 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1820 struct drm_i915_gem_object
*obj
;
1822 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1823 i915_gem_release_mmap(obj
);
1827 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1831 if (INTEL_INFO(dev
)->gen
>= 4 ||
1832 tiling_mode
== I915_TILING_NONE
)
1835 /* Previous chips need a power-of-two fence region when tiling */
1836 if (INTEL_INFO(dev
)->gen
== 3)
1837 gtt_size
= 1024*1024;
1839 gtt_size
= 512*1024;
1841 while (gtt_size
< size
)
1848 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1849 * @obj: object to check
1851 * Return the required GTT alignment for an object, taking into account
1852 * potential fence register mapping.
1855 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1856 int tiling_mode
, bool fenced
)
1859 * Minimum alignment is 4k (GTT page size), but might be greater
1860 * if a fence register is needed for the object.
1862 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1863 tiling_mode
== I915_TILING_NONE
)
1867 * Previous chips need to be aligned to the size of the smallest
1868 * fence register that can contain the object.
1870 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1873 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1875 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1878 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1881 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1883 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1887 /* Badly fragmented mmap space? The only way we can recover
1888 * space is by destroying unwanted objects. We can't randomly release
1889 * mmap_offsets as userspace expects them to be persistent for the
1890 * lifetime of the objects. The closest we can is to release the
1891 * offsets on purgeable objects by truncating it and marking it purged,
1892 * which prevents userspace from ever using that object again.
1894 i915_gem_shrink(dev_priv
,
1895 obj
->base
.size
>> PAGE_SHIFT
,
1897 I915_SHRINK_UNBOUND
|
1898 I915_SHRINK_PURGEABLE
);
1899 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1903 i915_gem_shrink_all(dev_priv
);
1904 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1906 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1911 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1913 drm_gem_free_mmap_offset(&obj
->base
);
1917 i915_gem_mmap_gtt(struct drm_file
*file
,
1918 struct drm_device
*dev
,
1922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1923 struct drm_i915_gem_object
*obj
;
1926 ret
= i915_mutex_lock_interruptible(dev
);
1930 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1931 if (&obj
->base
== NULL
) {
1936 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1937 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1942 ret
= i915_gem_object_create_mmap_offset(obj
);
1946 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1949 drm_gem_object_unreference(&obj
->base
);
1951 mutex_unlock(&dev
->struct_mutex
);
1956 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1958 * @data: GTT mapping ioctl data
1959 * @file: GEM object info
1961 * Simply returns the fake offset to userspace so it can mmap it.
1962 * The mmap call will end up in drm_gem_mmap(), which will set things
1963 * up so we can get faults in the handler above.
1965 * The fault handler will take care of binding the object into the GTT
1966 * (since it may have been evicted to make room for something), allocating
1967 * a fence register, and mapping the appropriate aperture address into
1971 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1972 struct drm_file
*file
)
1974 struct drm_i915_gem_mmap_gtt
*args
= data
;
1976 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1979 /* Immediately discard the backing storage */
1981 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1983 i915_gem_object_free_mmap_offset(obj
);
1985 if (obj
->base
.filp
== NULL
)
1988 /* Our goal here is to return as much of the memory as
1989 * is possible back to the system as we are called from OOM.
1990 * To do this we must instruct the shmfs to drop all of its
1991 * backing pages, *now*.
1993 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1994 obj
->madv
= __I915_MADV_PURGED
;
1997 /* Try to discard unwanted pages */
1999 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2001 struct address_space
*mapping
;
2003 switch (obj
->madv
) {
2004 case I915_MADV_DONTNEED
:
2005 i915_gem_object_truncate(obj
);
2006 case __I915_MADV_PURGED
:
2010 if (obj
->base
.filp
== NULL
)
2013 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2014 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2018 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2020 struct sg_page_iter sg_iter
;
2023 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2025 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2027 /* In the event of a disaster, abandon all caches and
2028 * hope for the best.
2030 WARN_ON(ret
!= -EIO
);
2031 i915_gem_clflush_object(obj
, true);
2032 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2035 if (i915_gem_object_needs_bit17_swizzle(obj
))
2036 i915_gem_object_save_bit_17_swizzle(obj
);
2038 if (obj
->madv
== I915_MADV_DONTNEED
)
2041 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2042 struct page
*page
= sg_page_iter_page(&sg_iter
);
2045 set_page_dirty(page
);
2047 if (obj
->madv
== I915_MADV_WILLNEED
)
2048 mark_page_accessed(page
);
2050 page_cache_release(page
);
2054 sg_free_table(obj
->pages
);
2059 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2061 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2063 if (obj
->pages
== NULL
)
2066 if (obj
->pages_pin_count
)
2069 BUG_ON(i915_gem_obj_bound_any(obj
));
2071 /* ->put_pages might need to allocate memory for the bit17 swizzle
2072 * array, hence protect them from being reaped by removing them from gtt
2074 list_del(&obj
->global_list
);
2076 ops
->put_pages(obj
);
2079 i915_gem_object_invalidate(obj
);
2085 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2087 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2089 struct address_space
*mapping
;
2090 struct sg_table
*st
;
2091 struct scatterlist
*sg
;
2092 struct sg_page_iter sg_iter
;
2094 unsigned long last_pfn
= 0; /* suppress gcc warning */
2097 /* Assert that the object is not currently in any GPU domain. As it
2098 * wasn't in the GTT, there shouldn't be any way it could have been in
2101 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2102 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2104 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2108 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2109 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2114 /* Get the list of pages out of our struct file. They'll be pinned
2115 * at this point until we release them.
2117 * Fail silently without starting the shrinker
2119 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2120 gfp
= mapping_gfp_mask(mapping
);
2121 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2122 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2125 for (i
= 0; i
< page_count
; i
++) {
2126 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2128 i915_gem_shrink(dev_priv
,
2131 I915_SHRINK_UNBOUND
|
2132 I915_SHRINK_PURGEABLE
);
2133 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2136 /* We've tried hard to allocate the memory by reaping
2137 * our own buffer, now let the real VM do its job and
2138 * go down in flames if truly OOM.
2140 i915_gem_shrink_all(dev_priv
);
2141 page
= shmem_read_mapping_page(mapping
, i
);
2145 #ifdef CONFIG_SWIOTLB
2146 if (swiotlb_nr_tbl()) {
2148 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2153 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2157 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2159 sg
->length
+= PAGE_SIZE
;
2161 last_pfn
= page_to_pfn(page
);
2163 /* Check that the i965g/gm workaround works. */
2164 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2166 #ifdef CONFIG_SWIOTLB
2167 if (!swiotlb_nr_tbl())
2172 if (i915_gem_object_needs_bit17_swizzle(obj
))
2173 i915_gem_object_do_bit_17_swizzle(obj
);
2175 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2176 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2177 i915_gem_object_pin_pages(obj
);
2183 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2184 page_cache_release(sg_page_iter_page(&sg_iter
));
2188 /* shmemfs first checks if there is enough memory to allocate the page
2189 * and reports ENOSPC should there be insufficient, along with the usual
2190 * ENOMEM for a genuine allocation failure.
2192 * We use ENOSPC in our driver to mean that we have run out of aperture
2193 * space and so want to translate the error from shmemfs back to our
2194 * usual understanding of ENOMEM.
2196 if (PTR_ERR(page
) == -ENOSPC
)
2199 return PTR_ERR(page
);
2202 /* Ensure that the associated pages are gathered from the backing storage
2203 * and pinned into our object. i915_gem_object_get_pages() may be called
2204 * multiple times before they are released by a single call to
2205 * i915_gem_object_put_pages() - once the pages are no longer referenced
2206 * either as a result of memory pressure (reaping pages under the shrinker)
2207 * or as the object is itself released.
2210 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2212 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2213 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2219 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2220 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2224 BUG_ON(obj
->pages_pin_count
);
2226 ret
= ops
->get_pages(obj
);
2230 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2232 obj
->get_page
.sg
= obj
->pages
->sgl
;
2233 obj
->get_page
.last
= 0;
2239 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2240 struct intel_engine_cs
*ring
)
2242 struct drm_i915_gem_request
*req
;
2243 struct intel_engine_cs
*old_ring
;
2245 BUG_ON(ring
== NULL
);
2247 req
= intel_ring_get_request(ring
);
2248 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2250 if (old_ring
!= ring
&& obj
->last_write_req
) {
2251 /* Keep the request relative to the current ring */
2252 i915_gem_request_assign(&obj
->last_write_req
, req
);
2255 /* Add a reference if we're newly entering the active list. */
2257 drm_gem_object_reference(&obj
->base
);
2261 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2263 i915_gem_request_assign(&obj
->last_read_req
, req
);
2266 void i915_vma_move_to_active(struct i915_vma
*vma
,
2267 struct intel_engine_cs
*ring
)
2269 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2270 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2274 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2276 struct i915_vma
*vma
;
2278 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2279 BUG_ON(!obj
->active
);
2281 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2282 if (!list_empty(&vma
->mm_list
))
2283 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2286 intel_fb_obj_flush(obj
, true);
2288 list_del_init(&obj
->ring_list
);
2290 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2291 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2292 obj
->base
.write_domain
= 0;
2294 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2297 drm_gem_object_unreference(&obj
->base
);
2299 WARN_ON(i915_verify_lists(dev
));
2303 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2305 if (obj
->last_read_req
== NULL
)
2308 if (i915_gem_request_completed(obj
->last_read_req
, true))
2309 i915_gem_object_move_to_inactive(obj
);
2313 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2316 struct intel_engine_cs
*ring
;
2319 /* Carefully retire all requests without writing to the rings */
2320 for_each_ring(ring
, dev_priv
, i
) {
2321 ret
= intel_ring_idle(ring
);
2325 i915_gem_retire_requests(dev
);
2327 /* Finally reset hw state */
2328 for_each_ring(ring
, dev_priv
, i
) {
2329 intel_ring_init_seqno(ring
, seqno
);
2331 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2332 ring
->semaphore
.sync_seqno
[j
] = 0;
2338 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2346 /* HWS page needs to be set less than what we
2347 * will inject to ring
2349 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2353 /* Carefully set the last_seqno value so that wrap
2354 * detection still works
2356 dev_priv
->next_seqno
= seqno
;
2357 dev_priv
->last_seqno
= seqno
- 1;
2358 if (dev_priv
->last_seqno
== 0)
2359 dev_priv
->last_seqno
--;
2365 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2369 /* reserve 0 for non-seqno */
2370 if (dev_priv
->next_seqno
== 0) {
2371 int ret
= i915_gem_init_seqno(dev
, 0);
2375 dev_priv
->next_seqno
= 1;
2378 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2382 int __i915_add_request(struct intel_engine_cs
*ring
,
2383 struct drm_file
*file
,
2384 struct drm_i915_gem_object
*obj
)
2386 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2387 struct drm_i915_gem_request
*request
;
2388 struct intel_ringbuffer
*ringbuf
;
2392 request
= ring
->outstanding_lazy_request
;
2393 if (WARN_ON(request
== NULL
))
2396 if (i915
.enable_execlists
) {
2397 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2399 ringbuf
= ring
->buffer
;
2401 request_start
= intel_ring_get_tail(ringbuf
);
2403 * Emit any outstanding flushes - execbuf can fail to emit the flush
2404 * after having emitted the batchbuffer command. Hence we need to fix
2405 * things up similar to emitting the lazy request. The difference here
2406 * is that the flush _must_ happen before the next request, no matter
2409 if (i915
.enable_execlists
) {
2410 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2414 ret
= intel_ring_flush_all_caches(ring
);
2419 /* Record the position of the start of the request so that
2420 * should we detect the updated seqno part-way through the
2421 * GPU processing the request, we never over-estimate the
2422 * position of the head.
2424 request
->postfix
= intel_ring_get_tail(ringbuf
);
2426 if (i915
.enable_execlists
) {
2427 ret
= ring
->emit_request(ringbuf
, request
);
2431 ret
= ring
->add_request(ring
);
2435 request
->tail
= intel_ring_get_tail(ringbuf
);
2438 request
->head
= request_start
;
2440 /* Whilst this request exists, batch_obj will be on the
2441 * active_list, and so will hold the active reference. Only when this
2442 * request is retired will the the batch_obj be moved onto the
2443 * inactive_list and lose its active reference. Hence we do not need
2444 * to explicitly hold another reference here.
2446 request
->batch_obj
= obj
;
2448 if (!i915
.enable_execlists
) {
2449 /* Hold a reference to the current context so that we can inspect
2450 * it later in case a hangcheck error event fires.
2452 request
->ctx
= ring
->last_context
;
2454 i915_gem_context_reference(request
->ctx
);
2457 request
->emitted_jiffies
= jiffies
;
2458 list_add_tail(&request
->list
, &ring
->request_list
);
2459 request
->file_priv
= NULL
;
2462 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2464 spin_lock(&file_priv
->mm
.lock
);
2465 request
->file_priv
= file_priv
;
2466 list_add_tail(&request
->client_list
,
2467 &file_priv
->mm
.request_list
);
2468 spin_unlock(&file_priv
->mm
.lock
);
2470 request
->pid
= get_pid(task_pid(current
));
2473 trace_i915_gem_request_add(request
);
2474 ring
->outstanding_lazy_request
= NULL
;
2476 i915_queue_hangcheck(ring
->dev
);
2478 queue_delayed_work(dev_priv
->wq
,
2479 &dev_priv
->mm
.retire_work
,
2480 round_jiffies_up_relative(HZ
));
2481 intel_mark_busy(dev_priv
->dev
);
2487 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2489 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2494 spin_lock(&file_priv
->mm
.lock
);
2495 list_del(&request
->client_list
);
2496 request
->file_priv
= NULL
;
2497 spin_unlock(&file_priv
->mm
.lock
);
2500 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2501 const struct intel_context
*ctx
)
2503 unsigned long elapsed
;
2505 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2507 if (ctx
->hang_stats
.banned
)
2510 if (ctx
->hang_stats
.ban_period_seconds
&&
2511 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2512 if (!i915_gem_context_is_default(ctx
)) {
2513 DRM_DEBUG("context hanging too fast, banning!\n");
2515 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2516 if (i915_stop_ring_allow_warn(dev_priv
))
2517 DRM_ERROR("gpu hanging too fast, banning!\n");
2525 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2526 struct intel_context
*ctx
,
2529 struct i915_ctx_hang_stats
*hs
;
2534 hs
= &ctx
->hang_stats
;
2537 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2539 hs
->guilty_ts
= get_seconds();
2541 hs
->batch_pending
++;
2545 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2547 list_del(&request
->list
);
2548 i915_gem_request_remove_from_client(request
);
2550 put_pid(request
->pid
);
2552 i915_gem_request_unreference(request
);
2555 void i915_gem_request_free(struct kref
*req_ref
)
2557 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2559 struct intel_context
*ctx
= req
->ctx
;
2562 if (i915
.enable_execlists
) {
2563 struct intel_engine_cs
*ring
= req
->ring
;
2565 if (ctx
!= ring
->default_context
)
2566 intel_lr_context_unpin(ring
, ctx
);
2569 i915_gem_context_unreference(ctx
);
2572 kmem_cache_free(req
->i915
->requests
, req
);
2575 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2576 struct intel_context
*ctx
)
2578 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2579 struct drm_i915_gem_request
*rq
;
2582 if (ring
->outstanding_lazy_request
)
2585 rq
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2589 kref_init(&rq
->ref
);
2590 rq
->i915
= dev_priv
;
2592 ret
= i915_gem_get_seqno(ring
->dev
, &rq
->seqno
);
2600 if (i915
.enable_execlists
)
2601 ret
= intel_logical_ring_alloc_request_extras(rq
, ctx
);
2603 ret
= intel_ring_alloc_request_extras(rq
);
2609 ring
->outstanding_lazy_request
= rq
;
2613 struct drm_i915_gem_request
*
2614 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2616 struct drm_i915_gem_request
*request
;
2618 list_for_each_entry(request
, &ring
->request_list
, list
) {
2619 if (i915_gem_request_completed(request
, false))
2628 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2629 struct intel_engine_cs
*ring
)
2631 struct drm_i915_gem_request
*request
;
2634 request
= i915_gem_find_active_request(ring
);
2636 if (request
== NULL
)
2639 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2641 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2643 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2644 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2647 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2648 struct intel_engine_cs
*ring
)
2650 while (!list_empty(&ring
->active_list
)) {
2651 struct drm_i915_gem_object
*obj
;
2653 obj
= list_first_entry(&ring
->active_list
,
2654 struct drm_i915_gem_object
,
2657 i915_gem_object_move_to_inactive(obj
);
2661 * Clear the execlists queue up before freeing the requests, as those
2662 * are the ones that keep the context and ringbuffer backing objects
2665 while (!list_empty(&ring
->execlist_queue
)) {
2666 struct drm_i915_gem_request
*submit_req
;
2668 submit_req
= list_first_entry(&ring
->execlist_queue
,
2669 struct drm_i915_gem_request
,
2671 list_del(&submit_req
->execlist_link
);
2673 if (submit_req
->ctx
!= ring
->default_context
)
2674 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2676 i915_gem_request_unreference(submit_req
);
2680 * We must free the requests after all the corresponding objects have
2681 * been moved off active lists. Which is the same order as the normal
2682 * retire_requests function does. This is important if object hold
2683 * implicit references on things like e.g. ppgtt address spaces through
2686 while (!list_empty(&ring
->request_list
)) {
2687 struct drm_i915_gem_request
*request
;
2689 request
= list_first_entry(&ring
->request_list
,
2690 struct drm_i915_gem_request
,
2693 i915_gem_free_request(request
);
2696 /* This may not have been flushed before the reset, so clean it now */
2697 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2700 void i915_gem_restore_fences(struct drm_device
*dev
)
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2705 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2706 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2709 * Commit delayed tiling changes if we have an object still
2710 * attached to the fence, otherwise just clear the fence.
2713 i915_gem_object_update_fence(reg
->obj
, reg
,
2714 reg
->obj
->tiling_mode
);
2716 i915_gem_write_fence(dev
, i
, NULL
);
2721 void i915_gem_reset(struct drm_device
*dev
)
2723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2724 struct intel_engine_cs
*ring
;
2728 * Before we free the objects from the requests, we need to inspect
2729 * them for finding the guilty party. As the requests only borrow
2730 * their reference to the objects, the inspection must be done first.
2732 for_each_ring(ring
, dev_priv
, i
)
2733 i915_gem_reset_ring_status(dev_priv
, ring
);
2735 for_each_ring(ring
, dev_priv
, i
)
2736 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2738 i915_gem_context_reset(dev
);
2740 i915_gem_restore_fences(dev
);
2744 * This function clears the request list as sequence numbers are passed.
2747 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2749 if (list_empty(&ring
->request_list
))
2752 WARN_ON(i915_verify_lists(ring
->dev
));
2754 /* Retire requests first as we use it above for the early return.
2755 * If we retire requests last, we may use a later seqno and so clear
2756 * the requests lists without clearing the active list, leading to
2759 while (!list_empty(&ring
->request_list
)) {
2760 struct drm_i915_gem_request
*request
;
2762 request
= list_first_entry(&ring
->request_list
,
2763 struct drm_i915_gem_request
,
2766 if (!i915_gem_request_completed(request
, true))
2769 trace_i915_gem_request_retire(request
);
2771 /* We know the GPU must have read the request to have
2772 * sent us the seqno + interrupt, so use the position
2773 * of tail of the request to update the last known position
2776 request
->ringbuf
->last_retired_head
= request
->postfix
;
2778 i915_gem_free_request(request
);
2781 /* Move any buffers on the active list that are no longer referenced
2782 * by the ringbuffer to the flushing/inactive lists as appropriate,
2783 * before we free the context associated with the requests.
2785 while (!list_empty(&ring
->active_list
)) {
2786 struct drm_i915_gem_object
*obj
;
2788 obj
= list_first_entry(&ring
->active_list
,
2789 struct drm_i915_gem_object
,
2792 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2795 i915_gem_object_move_to_inactive(obj
);
2798 if (unlikely(ring
->trace_irq_req
&&
2799 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2800 ring
->irq_put(ring
);
2801 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2804 WARN_ON(i915_verify_lists(ring
->dev
));
2808 i915_gem_retire_requests(struct drm_device
*dev
)
2810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 struct intel_engine_cs
*ring
;
2815 for_each_ring(ring
, dev_priv
, i
) {
2816 i915_gem_retire_requests_ring(ring
);
2817 idle
&= list_empty(&ring
->request_list
);
2818 if (i915
.enable_execlists
) {
2819 unsigned long flags
;
2821 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2822 idle
&= list_empty(&ring
->execlist_queue
);
2823 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2825 intel_execlists_retire_requests(ring
);
2830 mod_delayed_work(dev_priv
->wq
,
2831 &dev_priv
->mm
.idle_work
,
2832 msecs_to_jiffies(100));
2838 i915_gem_retire_work_handler(struct work_struct
*work
)
2840 struct drm_i915_private
*dev_priv
=
2841 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2842 struct drm_device
*dev
= dev_priv
->dev
;
2845 /* Come back later if the device is busy... */
2847 if (mutex_trylock(&dev
->struct_mutex
)) {
2848 idle
= i915_gem_retire_requests(dev
);
2849 mutex_unlock(&dev
->struct_mutex
);
2852 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2853 round_jiffies_up_relative(HZ
));
2857 i915_gem_idle_work_handler(struct work_struct
*work
)
2859 struct drm_i915_private
*dev_priv
=
2860 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2861 struct drm_device
*dev
= dev_priv
->dev
;
2862 struct intel_engine_cs
*ring
;
2865 for_each_ring(ring
, dev_priv
, i
)
2866 if (!list_empty(&ring
->request_list
))
2869 intel_mark_idle(dev
);
2871 if (mutex_trylock(&dev
->struct_mutex
)) {
2872 struct intel_engine_cs
*ring
;
2875 for_each_ring(ring
, dev_priv
, i
)
2876 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2878 mutex_unlock(&dev
->struct_mutex
);
2883 * Ensures that an object will eventually get non-busy by flushing any required
2884 * write domains, emitting any outstanding lazy request and retiring and
2885 * completed requests.
2888 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2890 struct intel_engine_cs
*ring
;
2894 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2896 ret
= i915_gem_check_olr(obj
->last_read_req
);
2900 i915_gem_retire_requests_ring(ring
);
2907 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2908 * @DRM_IOCTL_ARGS: standard ioctl arguments
2910 * Returns 0 if successful, else an error is returned with the remaining time in
2911 * the timeout parameter.
2912 * -ETIME: object is still busy after timeout
2913 * -ERESTARTSYS: signal interrupted the wait
2914 * -ENONENT: object doesn't exist
2915 * Also possible, but rare:
2916 * -EAGAIN: GPU wedged
2918 * -ENODEV: Internal IRQ fail
2919 * -E?: The add request failed
2921 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2922 * non-zero timeout parameter the wait ioctl will wait for the given number of
2923 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2924 * without holding struct_mutex the object may become re-busied before this
2925 * function completes. A similar but shorter * race condition exists in the busy
2929 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2932 struct drm_i915_gem_wait
*args
= data
;
2933 struct drm_i915_gem_object
*obj
;
2934 struct drm_i915_gem_request
*req
;
2935 unsigned reset_counter
;
2938 if (args
->flags
!= 0)
2941 ret
= i915_mutex_lock_interruptible(dev
);
2945 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2946 if (&obj
->base
== NULL
) {
2947 mutex_unlock(&dev
->struct_mutex
);
2951 /* Need to make sure the object gets inactive eventually. */
2952 ret
= i915_gem_object_flush_active(obj
);
2956 if (!obj
->active
|| !obj
->last_read_req
)
2959 req
= obj
->last_read_req
;
2961 /* Do this after OLR check to make sure we make forward progress polling
2962 * on this IOCTL with a timeout == 0 (like busy ioctl)
2964 if (args
->timeout_ns
== 0) {
2969 drm_gem_object_unreference(&obj
->base
);
2970 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2971 i915_gem_request_reference(req
);
2972 mutex_unlock(&dev
->struct_mutex
);
2974 ret
= __i915_wait_request(req
, reset_counter
, true,
2975 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
2977 i915_gem_request_unreference__unlocked(req
);
2981 drm_gem_object_unreference(&obj
->base
);
2982 mutex_unlock(&dev
->struct_mutex
);
2987 * i915_gem_object_sync - sync an object to a ring.
2989 * @obj: object which may be in use on another ring.
2990 * @to: ring we wish to use the object on. May be NULL.
2992 * This code is meant to abstract object synchronization with the GPU.
2993 * Calling with NULL implies synchronizing the object with the CPU
2994 * rather than a particular GPU ring.
2996 * Returns 0 if successful, else propagates up the lower layer error.
2999 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3000 struct intel_engine_cs
*to
)
3002 struct intel_engine_cs
*from
;
3006 from
= i915_gem_request_get_ring(obj
->last_read_req
);
3008 if (from
== NULL
|| to
== from
)
3011 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
3012 return i915_gem_object_wait_rendering(obj
, false);
3014 idx
= intel_ring_sync_index(from
, to
);
3016 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
3017 /* Optimization: Avoid semaphore sync when we are sure we already
3018 * waited for an object with higher seqno */
3019 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3022 ret
= i915_gem_check_olr(obj
->last_read_req
);
3026 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
3027 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3029 /* We use last_read_req because sync_to()
3030 * might have just caused seqno wrap under
3033 from
->semaphore
.sync_seqno
[idx
] =
3034 i915_gem_request_get_seqno(obj
->last_read_req
);
3039 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3041 u32 old_write_domain
, old_read_domains
;
3043 /* Force a pagefault for domain tracking on next user access */
3044 i915_gem_release_mmap(obj
);
3046 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3049 /* Wait for any direct GTT access to complete */
3052 old_read_domains
= obj
->base
.read_domains
;
3053 old_write_domain
= obj
->base
.write_domain
;
3055 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3056 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3058 trace_i915_gem_object_change_domain(obj
,
3063 int i915_vma_unbind(struct i915_vma
*vma
)
3065 struct drm_i915_gem_object
*obj
= vma
->obj
;
3066 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3069 if (list_empty(&vma
->vma_link
))
3072 if (!drm_mm_node_allocated(&vma
->node
)) {
3073 i915_gem_vma_destroy(vma
);
3080 BUG_ON(obj
->pages
== NULL
);
3082 ret
= i915_gem_object_finish_gpu(obj
);
3085 /* Continue on if we fail due to EIO, the GPU is hung so we
3086 * should be safe and we need to cleanup or else we might
3087 * cause memory corruption through use-after-free.
3090 if (i915_is_ggtt(vma
->vm
) &&
3091 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3092 i915_gem_object_finish_gtt(obj
);
3094 /* release the fence reg _after_ flushing */
3095 ret
= i915_gem_object_put_fence(obj
);
3100 trace_i915_vma_unbind(vma
);
3102 vma
->vm
->unbind_vma(vma
);
3105 list_del_init(&vma
->mm_list
);
3106 if (i915_is_ggtt(vma
->vm
)) {
3107 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3108 obj
->map_and_fenceable
= false;
3109 } else if (vma
->ggtt_view
.pages
) {
3110 sg_free_table(vma
->ggtt_view
.pages
);
3111 kfree(vma
->ggtt_view
.pages
);
3112 vma
->ggtt_view
.pages
= NULL
;
3116 drm_mm_remove_node(&vma
->node
);
3117 i915_gem_vma_destroy(vma
);
3119 /* Since the unbound list is global, only move to that list if
3120 * no more VMAs exist. */
3121 if (list_empty(&obj
->vma_list
)) {
3122 /* Throw away the active reference before
3123 * moving to the unbound list. */
3124 i915_gem_object_retire(obj
);
3126 i915_gem_gtt_finish_object(obj
);
3127 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3130 /* And finally now the object is completely decoupled from this vma,
3131 * we can drop its hold on the backing storage and allow it to be
3132 * reaped by the shrinker.
3134 i915_gem_object_unpin_pages(obj
);
3139 int i915_gpu_idle(struct drm_device
*dev
)
3141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3142 struct intel_engine_cs
*ring
;
3145 /* Flush everything onto the inactive list. */
3146 for_each_ring(ring
, dev_priv
, i
) {
3147 if (!i915
.enable_execlists
) {
3148 ret
= i915_switch_context(ring
, ring
->default_context
);
3153 ret
= intel_ring_idle(ring
);
3161 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3162 struct drm_i915_gem_object
*obj
)
3164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3166 int fence_pitch_shift
;
3168 if (INTEL_INFO(dev
)->gen
>= 6) {
3169 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3170 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3172 fence_reg
= FENCE_REG_965_0
;
3173 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3176 fence_reg
+= reg
* 8;
3178 /* To w/a incoherency with non-atomic 64-bit register updates,
3179 * we split the 64-bit update into two 32-bit writes. In order
3180 * for a partial fence not to be evaluated between writes, we
3181 * precede the update with write to turn off the fence register,
3182 * and only enable the fence as the last step.
3184 * For extra levels of paranoia, we make sure each step lands
3185 * before applying the next step.
3187 I915_WRITE(fence_reg
, 0);
3188 POSTING_READ(fence_reg
);
3191 u32 size
= i915_gem_obj_ggtt_size(obj
);
3194 /* Adjust fence size to match tiled area */
3195 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3196 uint32_t row_size
= obj
->stride
*
3197 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3198 size
= (size
/ row_size
) * row_size
;
3201 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3203 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3204 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3205 if (obj
->tiling_mode
== I915_TILING_Y
)
3206 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3207 val
|= I965_FENCE_REG_VALID
;
3209 I915_WRITE(fence_reg
+ 4, val
>> 32);
3210 POSTING_READ(fence_reg
+ 4);
3212 I915_WRITE(fence_reg
+ 0, val
);
3213 POSTING_READ(fence_reg
);
3215 I915_WRITE(fence_reg
+ 4, 0);
3216 POSTING_READ(fence_reg
+ 4);
3220 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3221 struct drm_i915_gem_object
*obj
)
3223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3227 u32 size
= i915_gem_obj_ggtt_size(obj
);
3231 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3232 (size
& -size
) != size
||
3233 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3234 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3235 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3237 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3242 /* Note: pitch better be a power of two tile widths */
3243 pitch_val
= obj
->stride
/ tile_width
;
3244 pitch_val
= ffs(pitch_val
) - 1;
3246 val
= i915_gem_obj_ggtt_offset(obj
);
3247 if (obj
->tiling_mode
== I915_TILING_Y
)
3248 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3249 val
|= I915_FENCE_SIZE_BITS(size
);
3250 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3251 val
|= I830_FENCE_REG_VALID
;
3256 reg
= FENCE_REG_830_0
+ reg
* 4;
3258 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3260 I915_WRITE(reg
, val
);
3264 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3265 struct drm_i915_gem_object
*obj
)
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3271 u32 size
= i915_gem_obj_ggtt_size(obj
);
3274 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3275 (size
& -size
) != size
||
3276 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3277 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3278 i915_gem_obj_ggtt_offset(obj
), size
);
3280 pitch_val
= obj
->stride
/ 128;
3281 pitch_val
= ffs(pitch_val
) - 1;
3283 val
= i915_gem_obj_ggtt_offset(obj
);
3284 if (obj
->tiling_mode
== I915_TILING_Y
)
3285 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3286 val
|= I830_FENCE_SIZE_BITS(size
);
3287 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3288 val
|= I830_FENCE_REG_VALID
;
3292 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3293 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3296 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3298 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3301 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3302 struct drm_i915_gem_object
*obj
)
3304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 /* Ensure that all CPU reads are completed before installing a fence
3307 * and all writes before removing the fence.
3309 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3312 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3313 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3314 obj
->stride
, obj
->tiling_mode
);
3317 i830_write_fence_reg(dev
, reg
, obj
);
3318 else if (IS_GEN3(dev
))
3319 i915_write_fence_reg(dev
, reg
, obj
);
3320 else if (INTEL_INFO(dev
)->gen
>= 4)
3321 i965_write_fence_reg(dev
, reg
, obj
);
3323 /* And similarly be paranoid that no direct access to this region
3324 * is reordered to before the fence is installed.
3326 if (i915_gem_object_needs_mb(obj
))
3330 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3331 struct drm_i915_fence_reg
*fence
)
3333 return fence
- dev_priv
->fence_regs
;
3336 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3337 struct drm_i915_fence_reg
*fence
,
3340 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3341 int reg
= fence_number(dev_priv
, fence
);
3343 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3346 obj
->fence_reg
= reg
;
3348 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3350 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3352 list_del_init(&fence
->lru_list
);
3354 obj
->fence_dirty
= false;
3358 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3360 if (obj
->last_fenced_req
) {
3361 int ret
= i915_wait_request(obj
->last_fenced_req
);
3365 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3372 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3374 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3375 struct drm_i915_fence_reg
*fence
;
3378 ret
= i915_gem_object_wait_fence(obj
);
3382 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3385 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3387 if (WARN_ON(fence
->pin_count
))
3390 i915_gem_object_fence_lost(obj
);
3391 i915_gem_object_update_fence(obj
, fence
, false);
3396 static struct drm_i915_fence_reg
*
3397 i915_find_fence_reg(struct drm_device
*dev
)
3399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3400 struct drm_i915_fence_reg
*reg
, *avail
;
3403 /* First try to find a free reg */
3405 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3406 reg
= &dev_priv
->fence_regs
[i
];
3410 if (!reg
->pin_count
)
3417 /* None available, try to steal one or wait for a user to finish */
3418 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3426 /* Wait for completion of pending flips which consume fences */
3427 if (intel_has_pending_fb_unpin(dev
))
3428 return ERR_PTR(-EAGAIN
);
3430 return ERR_PTR(-EDEADLK
);
3434 * i915_gem_object_get_fence - set up fencing for an object
3435 * @obj: object to map through a fence reg
3437 * When mapping objects through the GTT, userspace wants to be able to write
3438 * to them without having to worry about swizzling if the object is tiled.
3439 * This function walks the fence regs looking for a free one for @obj,
3440 * stealing one if it can't find any.
3442 * It then sets up the reg based on the object's properties: address, pitch
3443 * and tiling format.
3445 * For an untiled surface, this removes any existing fence.
3448 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3450 struct drm_device
*dev
= obj
->base
.dev
;
3451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3452 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3453 struct drm_i915_fence_reg
*reg
;
3456 /* Have we updated the tiling parameters upon the object and so
3457 * will need to serialise the write to the associated fence register?
3459 if (obj
->fence_dirty
) {
3460 ret
= i915_gem_object_wait_fence(obj
);
3465 /* Just update our place in the LRU if our fence is getting reused. */
3466 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3467 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3468 if (!obj
->fence_dirty
) {
3469 list_move_tail(®
->lru_list
,
3470 &dev_priv
->mm
.fence_list
);
3473 } else if (enable
) {
3474 if (WARN_ON(!obj
->map_and_fenceable
))
3477 reg
= i915_find_fence_reg(dev
);
3479 return PTR_ERR(reg
);
3482 struct drm_i915_gem_object
*old
= reg
->obj
;
3484 ret
= i915_gem_object_wait_fence(old
);
3488 i915_gem_object_fence_lost(old
);
3493 i915_gem_object_update_fence(obj
, reg
, enable
);
3498 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3499 unsigned long cache_level
)
3501 struct drm_mm_node
*gtt_space
= &vma
->node
;
3502 struct drm_mm_node
*other
;
3505 * On some machines we have to be careful when putting differing types
3506 * of snoopable memory together to avoid the prefetcher crossing memory
3507 * domains and dying. During vm initialisation, we decide whether or not
3508 * these constraints apply and set the drm_mm.color_adjust
3511 if (vma
->vm
->mm
.color_adjust
== NULL
)
3514 if (!drm_mm_node_allocated(gtt_space
))
3517 if (list_empty(>t_space
->node_list
))
3520 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3521 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3524 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3525 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3532 * Finds free space in the GTT aperture and binds the object or a view of it
3535 static struct i915_vma
*
3536 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3537 struct i915_address_space
*vm
,
3538 const struct i915_ggtt_view
*ggtt_view
,
3542 struct drm_device
*dev
= obj
->base
.dev
;
3543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3544 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3545 unsigned long start
=
3546 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3548 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3549 struct i915_vma
*vma
;
3552 if (i915_is_ggtt(vm
)) {
3555 if (WARN_ON(!ggtt_view
))
3556 return ERR_PTR(-EINVAL
);
3558 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3560 fence_size
= i915_gem_get_gtt_size(dev
,
3563 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3567 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3571 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3573 fence_size
= i915_gem_get_gtt_size(dev
,
3576 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3580 unfenced_alignment
=
3581 i915_gem_get_gtt_alignment(dev
,
3585 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3589 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3591 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3592 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3593 ggtt_view
? ggtt_view
->type
: 0,
3595 return ERR_PTR(-EINVAL
);
3598 /* If binding the object/GGTT view requires more space than the entire
3599 * aperture has, reject it early before evicting everything in a vain
3600 * attempt to find space.
3603 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3604 ggtt_view
? ggtt_view
->type
: 0,
3606 flags
& PIN_MAPPABLE
? "mappable" : "total",
3608 return ERR_PTR(-E2BIG
);
3611 ret
= i915_gem_object_get_pages(obj
);
3613 return ERR_PTR(ret
);
3615 i915_gem_object_pin_pages(obj
);
3617 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3618 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3624 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3628 DRM_MM_SEARCH_DEFAULT
,
3629 DRM_MM_CREATE_DEFAULT
);
3631 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3640 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3642 goto err_remove_node
;
3645 ret
= i915_gem_gtt_prepare_object(obj
);
3647 goto err_remove_node
;
3649 trace_i915_vma_bind(vma
, flags
);
3650 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3652 goto err_finish_gtt
;
3654 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3655 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3660 i915_gem_gtt_finish_object(obj
);
3662 drm_mm_remove_node(&vma
->node
);
3664 i915_gem_vma_destroy(vma
);
3667 i915_gem_object_unpin_pages(obj
);
3672 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3675 /* If we don't have a page list set up, then we're not pinned
3676 * to GPU, and we can ignore the cache flush because it'll happen
3677 * again at bind time.
3679 if (obj
->pages
== NULL
)
3683 * Stolen memory is always coherent with the GPU as it is explicitly
3684 * marked as wc by the system, or the system is cache-coherent.
3686 if (obj
->stolen
|| obj
->phys_handle
)
3689 /* If the GPU is snooping the contents of the CPU cache,
3690 * we do not need to manually clear the CPU cache lines. However,
3691 * the caches are only snooped when the render cache is
3692 * flushed/invalidated. As we always have to emit invalidations
3693 * and flushes when moving into and out of the RENDER domain, correct
3694 * snooping behaviour occurs naturally as the result of our domain
3697 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3698 obj
->cache_dirty
= true;
3702 trace_i915_gem_object_clflush(obj
);
3703 drm_clflush_sg(obj
->pages
);
3704 obj
->cache_dirty
= false;
3709 /** Flushes the GTT write domain for the object if it's dirty. */
3711 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3713 uint32_t old_write_domain
;
3715 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3718 /* No actual flushing is required for the GTT write domain. Writes
3719 * to it immediately go to main memory as far as we know, so there's
3720 * no chipset flush. It also doesn't land in render cache.
3722 * However, we do have to enforce the order so that all writes through
3723 * the GTT land before any writes to the device, such as updates to
3728 old_write_domain
= obj
->base
.write_domain
;
3729 obj
->base
.write_domain
= 0;
3731 intel_fb_obj_flush(obj
, false);
3733 trace_i915_gem_object_change_domain(obj
,
3734 obj
->base
.read_domains
,
3738 /** Flushes the CPU write domain for the object if it's dirty. */
3740 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3742 uint32_t old_write_domain
;
3744 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3747 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3748 i915_gem_chipset_flush(obj
->base
.dev
);
3750 old_write_domain
= obj
->base
.write_domain
;
3751 obj
->base
.write_domain
= 0;
3753 intel_fb_obj_flush(obj
, false);
3755 trace_i915_gem_object_change_domain(obj
,
3756 obj
->base
.read_domains
,
3761 * Moves a single object to the GTT read, and possibly write domain.
3763 * This function returns when the move is complete, including waiting on
3767 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3769 uint32_t old_write_domain
, old_read_domains
;
3770 struct i915_vma
*vma
;
3773 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3776 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3780 i915_gem_object_retire(obj
);
3782 /* Flush and acquire obj->pages so that we are coherent through
3783 * direct access in memory with previous cached writes through
3784 * shmemfs and that our cache domain tracking remains valid.
3785 * For example, if the obj->filp was moved to swap without us
3786 * being notified and releasing the pages, we would mistakenly
3787 * continue to assume that the obj remained out of the CPU cached
3790 ret
= i915_gem_object_get_pages(obj
);
3794 i915_gem_object_flush_cpu_write_domain(obj
);
3796 /* Serialise direct access to this object with the barriers for
3797 * coherent writes from the GPU, by effectively invalidating the
3798 * GTT domain upon first access.
3800 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3803 old_write_domain
= obj
->base
.write_domain
;
3804 old_read_domains
= obj
->base
.read_domains
;
3806 /* It should now be out of any other write domains, and we can update
3807 * the domain values for our changes.
3809 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3810 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3812 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3813 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3818 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3820 trace_i915_gem_object_change_domain(obj
,
3824 /* And bump the LRU for this access */
3825 vma
= i915_gem_obj_to_ggtt(obj
);
3826 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3827 list_move_tail(&vma
->mm_list
,
3828 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3833 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3834 enum i915_cache_level cache_level
)
3836 struct drm_device
*dev
= obj
->base
.dev
;
3837 struct i915_vma
*vma
, *next
;
3840 if (obj
->cache_level
== cache_level
)
3843 if (i915_gem_obj_is_pinned(obj
)) {
3844 DRM_DEBUG("can not change the cache level of pinned objects\n");
3848 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3849 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3850 ret
= i915_vma_unbind(vma
);
3856 if (i915_gem_obj_bound_any(obj
)) {
3857 ret
= i915_gem_object_finish_gpu(obj
);
3861 i915_gem_object_finish_gtt(obj
);
3863 /* Before SandyBridge, you could not use tiling or fence
3864 * registers with snooped memory, so relinquish any fences
3865 * currently pointing to our region in the aperture.
3867 if (INTEL_INFO(dev
)->gen
< 6) {
3868 ret
= i915_gem_object_put_fence(obj
);
3873 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3874 if (drm_mm_node_allocated(&vma
->node
)) {
3875 ret
= i915_vma_bind(vma
, cache_level
,
3882 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3883 vma
->node
.color
= cache_level
;
3884 obj
->cache_level
= cache_level
;
3886 if (obj
->cache_dirty
&&
3887 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3888 cpu_write_needs_clflush(obj
)) {
3889 if (i915_gem_clflush_object(obj
, true))
3890 i915_gem_chipset_flush(obj
->base
.dev
);
3896 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3897 struct drm_file
*file
)
3899 struct drm_i915_gem_caching
*args
= data
;
3900 struct drm_i915_gem_object
*obj
;
3902 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3903 if (&obj
->base
== NULL
)
3906 switch (obj
->cache_level
) {
3907 case I915_CACHE_LLC
:
3908 case I915_CACHE_L3_LLC
:
3909 args
->caching
= I915_CACHING_CACHED
;
3913 args
->caching
= I915_CACHING_DISPLAY
;
3917 args
->caching
= I915_CACHING_NONE
;
3921 drm_gem_object_unreference_unlocked(&obj
->base
);
3925 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3926 struct drm_file
*file
)
3928 struct drm_i915_gem_caching
*args
= data
;
3929 struct drm_i915_gem_object
*obj
;
3930 enum i915_cache_level level
;
3933 switch (args
->caching
) {
3934 case I915_CACHING_NONE
:
3935 level
= I915_CACHE_NONE
;
3937 case I915_CACHING_CACHED
:
3938 level
= I915_CACHE_LLC
;
3940 case I915_CACHING_DISPLAY
:
3941 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3947 ret
= i915_mutex_lock_interruptible(dev
);
3951 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3952 if (&obj
->base
== NULL
) {
3957 ret
= i915_gem_object_set_cache_level(obj
, level
);
3959 drm_gem_object_unreference(&obj
->base
);
3961 mutex_unlock(&dev
->struct_mutex
);
3966 * Prepare buffer for display plane (scanout, cursors, etc).
3967 * Can be called from an uninterruptible phase (modesetting) and allows
3968 * any flushes to be pipelined (for pageflips).
3971 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3973 struct intel_engine_cs
*pipelined
,
3974 const struct i915_ggtt_view
*view
)
3976 u32 old_read_domains
, old_write_domain
;
3979 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3980 ret
= i915_gem_object_sync(obj
, pipelined
);
3985 /* Mark the pin_display early so that we account for the
3986 * display coherency whilst setting up the cache domains.
3990 /* The display engine is not coherent with the LLC cache on gen6. As
3991 * a result, we make sure that the pinning that is about to occur is
3992 * done with uncached PTEs. This is lowest common denominator for all
3995 * However for gen6+, we could do better by using the GFDT bit instead
3996 * of uncaching, which would allow us to flush all the LLC-cached data
3997 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3999 ret
= i915_gem_object_set_cache_level(obj
,
4000 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4002 goto err_unpin_display
;
4004 /* As the user may map the buffer once pinned in the display plane
4005 * (e.g. libkms for the bootup splash), we have to ensure that we
4006 * always use map_and_fenceable for all scanout buffers.
4008 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4009 view
->type
== I915_GGTT_VIEW_NORMAL
?
4012 goto err_unpin_display
;
4014 i915_gem_object_flush_cpu_write_domain(obj
);
4016 old_write_domain
= obj
->base
.write_domain
;
4017 old_read_domains
= obj
->base
.read_domains
;
4019 /* It should now be out of any other write domains, and we can update
4020 * the domain values for our changes.
4022 obj
->base
.write_domain
= 0;
4023 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4025 trace_i915_gem_object_change_domain(obj
,
4037 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4038 const struct i915_ggtt_view
*view
)
4040 if (WARN_ON(obj
->pin_display
== 0))
4043 i915_gem_object_ggtt_unpin_view(obj
, view
);
4049 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4053 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4056 ret
= i915_gem_object_wait_rendering(obj
, false);
4060 /* Ensure that we invalidate the GPU's caches and TLBs. */
4061 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4066 * Moves a single object to the CPU read, and possibly write domain.
4068 * This function returns when the move is complete, including waiting on
4072 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4074 uint32_t old_write_domain
, old_read_domains
;
4077 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4080 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4084 i915_gem_object_retire(obj
);
4085 i915_gem_object_flush_gtt_write_domain(obj
);
4087 old_write_domain
= obj
->base
.write_domain
;
4088 old_read_domains
= obj
->base
.read_domains
;
4090 /* Flush the CPU cache if it's still invalid. */
4091 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4092 i915_gem_clflush_object(obj
, false);
4094 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4097 /* It should now be out of any other write domains, and we can update
4098 * the domain values for our changes.
4100 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4102 /* If we're writing through the CPU, then the GPU read domains will
4103 * need to be invalidated at next use.
4106 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4107 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4111 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4113 trace_i915_gem_object_change_domain(obj
,
4120 /* Throttle our rendering by waiting until the ring has completed our requests
4121 * emitted over 20 msec ago.
4123 * Note that if we were to use the current jiffies each time around the loop,
4124 * we wouldn't escape the function with any frames outstanding if the time to
4125 * render a frame was over 20ms.
4127 * This should get us reasonable parallelism between CPU and GPU but also
4128 * relatively low latency when blocking on a particular request to finish.
4131 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4134 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4135 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4136 struct drm_i915_gem_request
*request
, *target
= NULL
;
4137 unsigned reset_counter
;
4140 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4144 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4148 spin_lock(&file_priv
->mm
.lock
);
4149 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4150 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4155 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4157 i915_gem_request_reference(target
);
4158 spin_unlock(&file_priv
->mm
.lock
);
4163 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4165 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4167 i915_gem_request_unreference__unlocked(target
);
4173 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4175 struct drm_i915_gem_object
*obj
= vma
->obj
;
4178 vma
->node
.start
& (alignment
- 1))
4181 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4184 if (flags
& PIN_OFFSET_BIAS
&&
4185 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4192 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4193 struct i915_address_space
*vm
,
4194 const struct i915_ggtt_view
*ggtt_view
,
4198 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4199 struct i915_vma
*vma
;
4203 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4206 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4209 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4212 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4215 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4216 i915_gem_obj_to_vma(obj
, vm
);
4219 return PTR_ERR(vma
);
4222 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4225 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4226 unsigned long offset
;
4227 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4228 i915_gem_obj_offset(obj
, vm
);
4229 WARN(vma
->pin_count
,
4230 "bo is already pinned in %s with incorrect alignment:"
4231 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4232 " obj->map_and_fenceable=%d\n",
4233 ggtt_view
? "ggtt" : "ppgtt",
4236 !!(flags
& PIN_MAPPABLE
),
4237 obj
->map_and_fenceable
);
4238 ret
= i915_vma_unbind(vma
);
4246 bound
= vma
? vma
->bound
: 0;
4247 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4248 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4251 return PTR_ERR(vma
);
4253 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4258 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4259 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4260 bool mappable
, fenceable
;
4261 u32 fence_size
, fence_alignment
;
4263 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4266 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4271 fenceable
= (vma
->node
.size
== fence_size
&&
4272 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4274 mappable
= (vma
->node
.start
+ fence_size
<=
4275 dev_priv
->gtt
.mappable_end
);
4277 obj
->map_and_fenceable
= mappable
&& fenceable
;
4279 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4287 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4288 struct i915_address_space
*vm
,
4292 return i915_gem_object_do_pin(obj
, vm
,
4293 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4298 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4299 const struct i915_ggtt_view
*view
,
4303 if (WARN_ONCE(!view
, "no view specified"))
4306 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4307 alignment
, flags
| PIN_GLOBAL
);
4311 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4312 const struct i915_ggtt_view
*view
)
4314 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4317 WARN_ON(vma
->pin_count
== 0);
4318 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4324 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4326 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4327 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4328 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4330 WARN_ON(!ggtt_vma
||
4331 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4332 ggtt_vma
->pin_count
);
4333 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4340 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4342 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4343 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4344 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4345 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4350 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4351 struct drm_file
*file
)
4353 struct drm_i915_gem_busy
*args
= data
;
4354 struct drm_i915_gem_object
*obj
;
4357 ret
= i915_mutex_lock_interruptible(dev
);
4361 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4362 if (&obj
->base
== NULL
) {
4367 /* Count all active objects as busy, even if they are currently not used
4368 * by the gpu. Users of this interface expect objects to eventually
4369 * become non-busy without any further actions, therefore emit any
4370 * necessary flushes here.
4372 ret
= i915_gem_object_flush_active(obj
);
4374 args
->busy
= obj
->active
;
4375 if (obj
->last_read_req
) {
4376 struct intel_engine_cs
*ring
;
4377 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4378 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4379 args
->busy
|= intel_ring_flag(ring
) << 16;
4382 drm_gem_object_unreference(&obj
->base
);
4384 mutex_unlock(&dev
->struct_mutex
);
4389 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4390 struct drm_file
*file_priv
)
4392 return i915_gem_ring_throttle(dev
, file_priv
);
4396 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4397 struct drm_file
*file_priv
)
4399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 struct drm_i915_gem_madvise
*args
= data
;
4401 struct drm_i915_gem_object
*obj
;
4404 switch (args
->madv
) {
4405 case I915_MADV_DONTNEED
:
4406 case I915_MADV_WILLNEED
:
4412 ret
= i915_mutex_lock_interruptible(dev
);
4416 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4417 if (&obj
->base
== NULL
) {
4422 if (i915_gem_obj_is_pinned(obj
)) {
4428 obj
->tiling_mode
!= I915_TILING_NONE
&&
4429 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4430 if (obj
->madv
== I915_MADV_WILLNEED
)
4431 i915_gem_object_unpin_pages(obj
);
4432 if (args
->madv
== I915_MADV_WILLNEED
)
4433 i915_gem_object_pin_pages(obj
);
4436 if (obj
->madv
!= __I915_MADV_PURGED
)
4437 obj
->madv
= args
->madv
;
4439 /* if the object is no longer attached, discard its backing storage */
4440 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4441 i915_gem_object_truncate(obj
);
4443 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4446 drm_gem_object_unreference(&obj
->base
);
4448 mutex_unlock(&dev
->struct_mutex
);
4452 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4453 const struct drm_i915_gem_object_ops
*ops
)
4455 INIT_LIST_HEAD(&obj
->global_list
);
4456 INIT_LIST_HEAD(&obj
->ring_list
);
4457 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4458 INIT_LIST_HEAD(&obj
->vma_list
);
4459 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4463 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4464 obj
->madv
= I915_MADV_WILLNEED
;
4466 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4469 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4470 .get_pages
= i915_gem_object_get_pages_gtt
,
4471 .put_pages
= i915_gem_object_put_pages_gtt
,
4474 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4477 struct drm_i915_gem_object
*obj
;
4478 struct address_space
*mapping
;
4481 obj
= i915_gem_object_alloc(dev
);
4485 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4486 i915_gem_object_free(obj
);
4490 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4491 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4492 /* 965gm cannot relocate objects above 4GiB. */
4493 mask
&= ~__GFP_HIGHMEM
;
4494 mask
|= __GFP_DMA32
;
4497 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4498 mapping_set_gfp_mask(mapping
, mask
);
4500 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4502 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4503 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4506 /* On some devices, we can have the GPU use the LLC (the CPU
4507 * cache) for about a 10% performance improvement
4508 * compared to uncached. Graphics requests other than
4509 * display scanout are coherent with the CPU in
4510 * accessing this cache. This means in this mode we
4511 * don't need to clflush on the CPU side, and on the
4512 * GPU side we only need to flush internal caches to
4513 * get data visible to the CPU.
4515 * However, we maintain the display planes as UC, and so
4516 * need to rebind when first used as such.
4518 obj
->cache_level
= I915_CACHE_LLC
;
4520 obj
->cache_level
= I915_CACHE_NONE
;
4522 trace_i915_gem_object_create(obj
);
4527 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4529 /* If we are the last user of the backing storage (be it shmemfs
4530 * pages or stolen etc), we know that the pages are going to be
4531 * immediately released. In this case, we can then skip copying
4532 * back the contents from the GPU.
4535 if (obj
->madv
!= I915_MADV_WILLNEED
)
4538 if (obj
->base
.filp
== NULL
)
4541 /* At first glance, this looks racy, but then again so would be
4542 * userspace racing mmap against close. However, the first external
4543 * reference to the filp can only be obtained through the
4544 * i915_gem_mmap_ioctl() which safeguards us against the user
4545 * acquiring such a reference whilst we are in the middle of
4546 * freeing the object.
4548 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4551 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4553 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4554 struct drm_device
*dev
= obj
->base
.dev
;
4555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4556 struct i915_vma
*vma
, *next
;
4558 intel_runtime_pm_get(dev_priv
);
4560 trace_i915_gem_object_destroy(obj
);
4562 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4566 ret
= i915_vma_unbind(vma
);
4567 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4568 bool was_interruptible
;
4570 was_interruptible
= dev_priv
->mm
.interruptible
;
4571 dev_priv
->mm
.interruptible
= false;
4573 WARN_ON(i915_vma_unbind(vma
));
4575 dev_priv
->mm
.interruptible
= was_interruptible
;
4579 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4580 * before progressing. */
4582 i915_gem_object_unpin_pages(obj
);
4584 WARN_ON(obj
->frontbuffer_bits
);
4586 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4587 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4588 obj
->tiling_mode
!= I915_TILING_NONE
)
4589 i915_gem_object_unpin_pages(obj
);
4591 if (WARN_ON(obj
->pages_pin_count
))
4592 obj
->pages_pin_count
= 0;
4593 if (discard_backing_storage(obj
))
4594 obj
->madv
= I915_MADV_DONTNEED
;
4595 i915_gem_object_put_pages(obj
);
4596 i915_gem_object_free_mmap_offset(obj
);
4600 if (obj
->base
.import_attach
)
4601 drm_prime_gem_destroy(&obj
->base
, NULL
);
4603 if (obj
->ops
->release
)
4604 obj
->ops
->release(obj
);
4606 drm_gem_object_release(&obj
->base
);
4607 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4610 i915_gem_object_free(obj
);
4612 intel_runtime_pm_put(dev_priv
);
4615 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4616 struct i915_address_space
*vm
)
4618 struct i915_vma
*vma
;
4619 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4620 if (i915_is_ggtt(vma
->vm
) &&
4621 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4629 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4630 const struct i915_ggtt_view
*view
)
4632 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4633 struct i915_vma
*vma
;
4635 if (WARN_ONCE(!view
, "no view specified"))
4636 return ERR_PTR(-EINVAL
);
4638 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4639 if (vma
->vm
== ggtt
&&
4640 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4645 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4647 struct i915_address_space
*vm
= NULL
;
4648 WARN_ON(vma
->node
.allocated
);
4650 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4651 if (!list_empty(&vma
->exec_list
))
4656 if (!i915_is_ggtt(vm
))
4657 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4659 list_del(&vma
->vma_link
);
4661 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4665 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4668 struct intel_engine_cs
*ring
;
4671 for_each_ring(ring
, dev_priv
, i
)
4672 dev_priv
->gt
.stop_ring(ring
);
4676 i915_gem_suspend(struct drm_device
*dev
)
4678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4681 mutex_lock(&dev
->struct_mutex
);
4682 ret
= i915_gpu_idle(dev
);
4686 i915_gem_retire_requests(dev
);
4688 i915_gem_stop_ringbuffers(dev
);
4689 mutex_unlock(&dev
->struct_mutex
);
4691 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4692 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4693 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4695 /* Assert that we sucessfully flushed all the work and
4696 * reset the GPU back to its idle, low power state.
4698 WARN_ON(dev_priv
->mm
.busy
);
4703 mutex_unlock(&dev
->struct_mutex
);
4707 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4709 struct drm_device
*dev
= ring
->dev
;
4710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4711 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4712 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4715 if (!HAS_L3_DPF(dev
) || !remap_info
)
4718 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4723 * Note: We do not worry about the concurrent register cacheline hang
4724 * here because no other code should access these registers other than
4725 * at initialization time.
4727 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4728 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4729 intel_ring_emit(ring
, reg_base
+ i
);
4730 intel_ring_emit(ring
, remap_info
[i
/4]);
4733 intel_ring_advance(ring
);
4738 void i915_gem_init_swizzling(struct drm_device
*dev
)
4740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4742 if (INTEL_INFO(dev
)->gen
< 5 ||
4743 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4746 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4747 DISP_TILE_SURFACE_SWIZZLING
);
4752 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4754 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4755 else if (IS_GEN7(dev
))
4756 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4757 else if (IS_GEN8(dev
))
4758 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4764 intel_enable_blt(struct drm_device
*dev
)
4769 /* The blitter was dysfunctional on early prototypes */
4770 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4771 DRM_INFO("BLT not supported on this pre-production hardware;"
4772 " graphics performance will be degraded.\n");
4779 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4783 I915_WRITE(RING_CTL(base
), 0);
4784 I915_WRITE(RING_HEAD(base
), 0);
4785 I915_WRITE(RING_TAIL(base
), 0);
4786 I915_WRITE(RING_START(base
), 0);
4789 static void init_unused_rings(struct drm_device
*dev
)
4792 init_unused_ring(dev
, PRB1_BASE
);
4793 init_unused_ring(dev
, SRB0_BASE
);
4794 init_unused_ring(dev
, SRB1_BASE
);
4795 init_unused_ring(dev
, SRB2_BASE
);
4796 init_unused_ring(dev
, SRB3_BASE
);
4797 } else if (IS_GEN2(dev
)) {
4798 init_unused_ring(dev
, SRB0_BASE
);
4799 init_unused_ring(dev
, SRB1_BASE
);
4800 } else if (IS_GEN3(dev
)) {
4801 init_unused_ring(dev
, PRB1_BASE
);
4802 init_unused_ring(dev
, PRB2_BASE
);
4806 int i915_gem_init_rings(struct drm_device
*dev
)
4808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4811 ret
= intel_init_render_ring_buffer(dev
);
4816 ret
= intel_init_bsd_ring_buffer(dev
);
4818 goto cleanup_render_ring
;
4821 if (intel_enable_blt(dev
)) {
4822 ret
= intel_init_blt_ring_buffer(dev
);
4824 goto cleanup_bsd_ring
;
4827 if (HAS_VEBOX(dev
)) {
4828 ret
= intel_init_vebox_ring_buffer(dev
);
4830 goto cleanup_blt_ring
;
4833 if (HAS_BSD2(dev
)) {
4834 ret
= intel_init_bsd2_ring_buffer(dev
);
4836 goto cleanup_vebox_ring
;
4839 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4841 goto cleanup_bsd2_ring
;
4846 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4848 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4850 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4852 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4853 cleanup_render_ring
:
4854 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4860 i915_gem_init_hw(struct drm_device
*dev
)
4862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4863 struct intel_engine_cs
*ring
;
4866 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4869 /* Double layer security blanket, see i915_gem_init() */
4870 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4872 if (dev_priv
->ellc_size
)
4873 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4875 if (IS_HASWELL(dev
))
4876 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4877 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4879 if (HAS_PCH_NOP(dev
)) {
4880 if (IS_IVYBRIDGE(dev
)) {
4881 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4882 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4883 I915_WRITE(GEN7_MSG_CTL
, temp
);
4884 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4885 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4886 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4887 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4891 i915_gem_init_swizzling(dev
);
4894 * At least 830 can leave some of the unused rings
4895 * "active" (ie. head != tail) after resume which
4896 * will prevent c3 entry. Makes sure all unused rings
4899 init_unused_rings(dev
);
4901 for_each_ring(ring
, dev_priv
, i
) {
4902 ret
= ring
->init_hw(ring
);
4907 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4908 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4910 ret
= i915_ppgtt_init_hw(dev
);
4911 if (ret
&& ret
!= -EIO
) {
4912 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4913 i915_gem_cleanup_ringbuffer(dev
);
4916 ret
= i915_gem_context_enable(dev_priv
);
4917 if (ret
&& ret
!= -EIO
) {
4918 DRM_ERROR("Context enable failed %d\n", ret
);
4919 i915_gem_cleanup_ringbuffer(dev
);
4925 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4929 int i915_gem_init(struct drm_device
*dev
)
4931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4934 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4935 i915
.enable_execlists
);
4937 mutex_lock(&dev
->struct_mutex
);
4939 if (IS_VALLEYVIEW(dev
)) {
4940 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4941 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4942 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4943 VLV_GTLC_ALLOWWAKEACK
), 10))
4944 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4947 if (!i915
.enable_execlists
) {
4948 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4949 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4950 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4951 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4953 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4954 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4955 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4956 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4959 /* This is just a security blanket to placate dragons.
4960 * On some systems, we very sporadically observe that the first TLBs
4961 * used by the CS may be stale, despite us poking the TLB reset. If
4962 * we hold the forcewake during initialisation these problems
4963 * just magically go away.
4965 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4967 ret
= i915_gem_init_userptr(dev
);
4971 i915_gem_init_global_gtt(dev
);
4973 ret
= i915_gem_context_init(dev
);
4977 ret
= dev_priv
->gt
.init_rings(dev
);
4981 ret
= i915_gem_init_hw(dev
);
4983 /* Allow ring initialisation to fail by marking the GPU as
4984 * wedged. But we only want to do this where the GPU is angry,
4985 * for all other failure, such as an allocation failure, bail.
4987 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4988 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4993 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4994 mutex_unlock(&dev
->struct_mutex
);
5000 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 struct intel_engine_cs
*ring
;
5006 for_each_ring(ring
, dev_priv
, i
)
5007 dev_priv
->gt
.cleanup_ring(ring
);
5011 init_ring_lists(struct intel_engine_cs
*ring
)
5013 INIT_LIST_HEAD(&ring
->active_list
);
5014 INIT_LIST_HEAD(&ring
->request_list
);
5017 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5018 struct i915_address_space
*vm
)
5020 if (!i915_is_ggtt(vm
))
5021 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5022 vm
->dev
= dev_priv
->dev
;
5023 INIT_LIST_HEAD(&vm
->active_list
);
5024 INIT_LIST_HEAD(&vm
->inactive_list
);
5025 INIT_LIST_HEAD(&vm
->global_link
);
5026 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5030 i915_gem_load(struct drm_device
*dev
)
5032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5036 kmem_cache_create("i915_gem_object",
5037 sizeof(struct drm_i915_gem_object
), 0,
5041 kmem_cache_create("i915_gem_vma",
5042 sizeof(struct i915_vma
), 0,
5045 dev_priv
->requests
=
5046 kmem_cache_create("i915_gem_request",
5047 sizeof(struct drm_i915_gem_request
), 0,
5051 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5052 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5054 INIT_LIST_HEAD(&dev_priv
->context_list
);
5055 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5056 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5057 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5058 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5059 init_ring_lists(&dev_priv
->ring
[i
]);
5060 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5061 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5062 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5063 i915_gem_retire_work_handler
);
5064 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5065 i915_gem_idle_work_handler
);
5066 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5068 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5070 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5071 dev_priv
->num_fence_regs
= 32;
5072 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5073 dev_priv
->num_fence_regs
= 16;
5075 dev_priv
->num_fence_regs
= 8;
5077 if (intel_vgpu_active(dev
))
5078 dev_priv
->num_fence_regs
=
5079 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5081 /* Initialize fence registers to zero */
5082 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5083 i915_gem_restore_fences(dev
);
5085 i915_gem_detect_bit_6_swizzle(dev
);
5086 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5088 dev_priv
->mm
.interruptible
= true;
5090 i915_gem_shrinker_init(dev_priv
);
5092 mutex_init(&dev_priv
->fb_tracking
.lock
);
5095 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5097 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5099 /* Clean up our request list when the client is going away, so that
5100 * later retire_requests won't dereference our soon-to-be-gone
5103 spin_lock(&file_priv
->mm
.lock
);
5104 while (!list_empty(&file_priv
->mm
.request_list
)) {
5105 struct drm_i915_gem_request
*request
;
5107 request
= list_first_entry(&file_priv
->mm
.request_list
,
5108 struct drm_i915_gem_request
,
5110 list_del(&request
->client_list
);
5111 request
->file_priv
= NULL
;
5113 spin_unlock(&file_priv
->mm
.lock
);
5115 if (!list_empty(&file_priv
->rps_boost
)) {
5116 mutex_lock(&to_i915(dev
)->rps
.hw_lock
);
5117 list_del(&file_priv
->rps_boost
);
5118 mutex_unlock(&to_i915(dev
)->rps
.hw_lock
);
5122 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5124 struct drm_i915_file_private
*file_priv
;
5127 DRM_DEBUG_DRIVER("\n");
5129 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5133 file
->driver_priv
= file_priv
;
5134 file_priv
->dev_priv
= dev
->dev_private
;
5135 file_priv
->file
= file
;
5136 INIT_LIST_HEAD(&file_priv
->rps_boost
);
5138 spin_lock_init(&file_priv
->mm
.lock
);
5139 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5141 ret
= i915_gem_context_open(dev
, file
);
5149 * i915_gem_track_fb - update frontbuffer tracking
5150 * old: current GEM buffer for the frontbuffer slots
5151 * new: new GEM buffer for the frontbuffer slots
5152 * frontbuffer_bits: bitmask of frontbuffer slots
5154 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5155 * from @old and setting them in @new. Both @old and @new can be NULL.
5157 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5158 struct drm_i915_gem_object
*new,
5159 unsigned frontbuffer_bits
)
5162 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5163 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5164 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5168 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5169 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5170 new->frontbuffer_bits
|= frontbuffer_bits
;
5174 /* All the new VM stuff */
5176 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5177 struct i915_address_space
*vm
)
5179 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5180 struct i915_vma
*vma
;
5182 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5184 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5185 if (i915_is_ggtt(vma
->vm
) &&
5186 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5189 return vma
->node
.start
;
5192 WARN(1, "%s vma for this object not found.\n",
5193 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5198 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5199 const struct i915_ggtt_view
*view
)
5201 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5202 struct i915_vma
*vma
;
5204 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5205 if (vma
->vm
== ggtt
&&
5206 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5207 return vma
->node
.start
;
5209 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5213 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5214 struct i915_address_space
*vm
)
5216 struct i915_vma
*vma
;
5218 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5219 if (i915_is_ggtt(vma
->vm
) &&
5220 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5222 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5229 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5230 const struct i915_ggtt_view
*view
)
5232 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5233 struct i915_vma
*vma
;
5235 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5236 if (vma
->vm
== ggtt
&&
5237 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5238 drm_mm_node_allocated(&vma
->node
))
5244 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5246 struct i915_vma
*vma
;
5248 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5249 if (drm_mm_node_allocated(&vma
->node
))
5255 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5256 struct i915_address_space
*vm
)
5258 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5259 struct i915_vma
*vma
;
5261 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5263 BUG_ON(list_empty(&o
->vma_list
));
5265 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5266 if (i915_is_ggtt(vma
->vm
) &&
5267 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5270 return vma
->node
.size
;
5275 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5277 struct i915_vma
*vma
;
5278 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5279 if (vma
->pin_count
> 0)