2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
46 static int i915_gem_object_get_page_list(struct drm_gem_object
*obj
);
47 static void i915_gem_object_free_page_list(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
, bool write
);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
53 static int i915_gem_evict_something(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
61 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
64 (start
& (PAGE_SIZE
- 1)) != 0 ||
65 (end
& (PAGE_SIZE
- 1)) != 0) {
69 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
72 dev
->gtt_total
= (uint32_t) (end
- start
);
78 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
79 struct drm_file
*file_priv
)
81 struct drm_i915_gem_init
*args
= data
;
84 mutex_lock(&dev
->struct_mutex
);
85 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
86 mutex_unlock(&dev
->struct_mutex
);
92 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
93 struct drm_file
*file_priv
)
95 struct drm_i915_gem_get_aperture
*args
= data
;
97 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
100 args
->aper_size
= dev
->gtt_total
;
101 args
->aper_available_size
= (args
->aper_size
-
102 atomic_read(&dev
->pin_memory
));
109 * Creates a new mm object and returns a handle to it.
112 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
113 struct drm_file
*file_priv
)
115 struct drm_i915_gem_create
*args
= data
;
116 struct drm_gem_object
*obj
;
119 args
->size
= roundup(args
->size
, PAGE_SIZE
);
121 /* Allocate the new object */
122 obj
= drm_gem_object_alloc(dev
, args
->size
);
126 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
127 mutex_lock(&dev
->struct_mutex
);
128 drm_gem_object_handle_unreference(obj
);
129 mutex_unlock(&dev
->struct_mutex
);
134 args
->handle
= handle
;
140 * Reads data from the object referenced by handle.
142 * On error, the contents of *data are undefined.
145 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file_priv
)
148 struct drm_i915_gem_pread
*args
= data
;
149 struct drm_gem_object
*obj
;
150 struct drm_i915_gem_object
*obj_priv
;
155 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
158 obj_priv
= obj
->driver_private
;
160 /* Bounds check source.
162 * XXX: This could use review for overflow issues...
164 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
165 args
->offset
+ args
->size
> obj
->size
) {
166 drm_gem_object_unreference(obj
);
170 mutex_lock(&dev
->struct_mutex
);
172 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
175 drm_gem_object_unreference(obj
);
176 mutex_unlock(&dev
->struct_mutex
);
180 offset
= args
->offset
;
182 read
= vfs_read(obj
->filp
, (char __user
*)(uintptr_t)args
->data_ptr
,
183 args
->size
, &offset
);
184 if (read
!= args
->size
) {
185 drm_gem_object_unreference(obj
);
186 mutex_unlock(&dev
->struct_mutex
);
193 drm_gem_object_unreference(obj
);
194 mutex_unlock(&dev
->struct_mutex
);
199 /* This is the fast write path which cannot handle
200 * page faults in the source data
204 fast_user_write(struct io_mapping
*mapping
,
205 loff_t page_base
, int page_offset
,
206 char __user
*user_data
,
210 unsigned long unwritten
;
212 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
213 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
215 io_mapping_unmap_atomic(vaddr_atomic
);
221 /* Here's the write path which can sleep for
226 slow_user_write(struct io_mapping
*mapping
,
227 loff_t page_base
, int page_offset
,
228 char __user
*user_data
,
232 unsigned long unwritten
;
234 vaddr
= io_mapping_map_wc(mapping
, page_base
);
237 unwritten
= __copy_from_user(vaddr
+ page_offset
,
239 io_mapping_unmap(vaddr
);
246 i915_gem_gtt_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
247 struct drm_i915_gem_pwrite
*args
,
248 struct drm_file
*file_priv
)
250 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
251 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
253 loff_t offset
, page_base
;
254 char __user
*user_data
;
255 int page_offset
, page_length
;
258 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
260 if (!access_ok(VERIFY_READ
, user_data
, remain
))
264 mutex_lock(&dev
->struct_mutex
);
265 ret
= i915_gem_object_pin(obj
, 0);
267 mutex_unlock(&dev
->struct_mutex
);
270 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
274 obj_priv
= obj
->driver_private
;
275 offset
= obj_priv
->gtt_offset
+ args
->offset
;
279 /* Operation in this page
281 * page_base = page offset within aperture
282 * page_offset = offset within page
283 * page_length = bytes to copy for this page
285 page_base
= (offset
& ~(PAGE_SIZE
-1));
286 page_offset
= offset
& (PAGE_SIZE
-1);
287 page_length
= remain
;
288 if ((page_offset
+ remain
) > PAGE_SIZE
)
289 page_length
= PAGE_SIZE
- page_offset
;
291 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
292 page_offset
, user_data
, page_length
);
294 /* If we get a fault while copying data, then (presumably) our
295 * source page isn't available. In this case, use the
296 * non-atomic function
299 ret
= slow_user_write (dev_priv
->mm
.gtt_mapping
,
300 page_base
, page_offset
,
301 user_data
, page_length
);
306 remain
-= page_length
;
307 user_data
+= page_length
;
308 offset
+= page_length
;
312 i915_gem_object_unpin(obj
);
313 mutex_unlock(&dev
->struct_mutex
);
319 i915_gem_shmem_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
320 struct drm_i915_gem_pwrite
*args
,
321 struct drm_file
*file_priv
)
327 mutex_lock(&dev
->struct_mutex
);
329 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
331 mutex_unlock(&dev
->struct_mutex
);
335 offset
= args
->offset
;
337 written
= vfs_write(obj
->filp
,
338 (char __user
*)(uintptr_t) args
->data_ptr
,
339 args
->size
, &offset
);
340 if (written
!= args
->size
) {
341 mutex_unlock(&dev
->struct_mutex
);
348 mutex_unlock(&dev
->struct_mutex
);
354 * Writes data to the object referenced by handle.
356 * On error, the contents of the buffer that were to be modified are undefined.
359 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
360 struct drm_file
*file_priv
)
362 struct drm_i915_gem_pwrite
*args
= data
;
363 struct drm_gem_object
*obj
;
364 struct drm_i915_gem_object
*obj_priv
;
367 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
370 obj_priv
= obj
->driver_private
;
372 /* Bounds check destination.
374 * XXX: This could use review for overflow issues...
376 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
377 args
->offset
+ args
->size
> obj
->size
) {
378 drm_gem_object_unreference(obj
);
382 /* We can only do the GTT pwrite on untiled buffers, as otherwise
383 * it would end up going through the fenced access, and we'll get
384 * different detiling behavior between reading and writing.
385 * pread/pwrite currently are reading and writing from the CPU
386 * perspective, requiring manual detiling by the client.
388 if (obj_priv
->phys_obj
)
389 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
390 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
392 ret
= i915_gem_gtt_pwrite(dev
, obj
, args
, file_priv
);
394 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file_priv
);
398 DRM_INFO("pwrite failed %d\n", ret
);
401 drm_gem_object_unreference(obj
);
407 * Called when user space prepares to use an object with the CPU, either
408 * through the mmap ioctl's mapping or a GTT mapping.
411 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
412 struct drm_file
*file_priv
)
414 struct drm_i915_gem_set_domain
*args
= data
;
415 struct drm_gem_object
*obj
;
416 uint32_t read_domains
= args
->read_domains
;
417 uint32_t write_domain
= args
->write_domain
;
420 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
423 /* Only handle setting domains to types used by the CPU. */
424 if (write_domain
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
427 if (read_domains
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
430 /* Having something in the write domain implies it's in the read
431 * domain, and only that read domain. Enforce that in the request.
433 if (write_domain
!= 0 && read_domains
!= write_domain
)
436 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
440 mutex_lock(&dev
->struct_mutex
);
442 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
443 obj
, obj
->size
, read_domains
, write_domain
);
445 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
446 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
448 /* Silently promote "you're not bound, there was nothing to do"
449 * to success, since the client was just asking us to
450 * make sure everything was done.
455 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
458 drm_gem_object_unreference(obj
);
459 mutex_unlock(&dev
->struct_mutex
);
464 * Called when user space has done writes to this buffer
467 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
468 struct drm_file
*file_priv
)
470 struct drm_i915_gem_sw_finish
*args
= data
;
471 struct drm_gem_object
*obj
;
472 struct drm_i915_gem_object
*obj_priv
;
475 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
478 mutex_lock(&dev
->struct_mutex
);
479 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
481 mutex_unlock(&dev
->struct_mutex
);
486 DRM_INFO("%s: sw_finish %d (%p %d)\n",
487 __func__
, args
->handle
, obj
, obj
->size
);
489 obj_priv
= obj
->driver_private
;
491 /* Pinned buffers may be scanout, so flush the cache */
492 if (obj_priv
->pin_count
)
493 i915_gem_object_flush_cpu_write_domain(obj
);
495 drm_gem_object_unreference(obj
);
496 mutex_unlock(&dev
->struct_mutex
);
501 * Maps the contents of an object, returning the address it is mapped
504 * While the mapping holds a reference on the contents of the object, it doesn't
505 * imply a ref on the object itself.
508 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
509 struct drm_file
*file_priv
)
511 struct drm_i915_gem_mmap
*args
= data
;
512 struct drm_gem_object
*obj
;
516 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
519 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
523 offset
= args
->offset
;
525 down_write(¤t
->mm
->mmap_sem
);
526 addr
= do_mmap(obj
->filp
, 0, args
->size
,
527 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
529 up_write(¤t
->mm
->mmap_sem
);
530 mutex_lock(&dev
->struct_mutex
);
531 drm_gem_object_unreference(obj
);
532 mutex_unlock(&dev
->struct_mutex
);
533 if (IS_ERR((void *)addr
))
536 args
->addr_ptr
= (uint64_t) addr
;
542 * i915_gem_fault - fault a page into the GTT
543 * vma: VMA in question
546 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
547 * from userspace. The fault handler takes care of binding the object to
548 * the GTT (if needed), allocating and programming a fence register (again,
549 * only if needed based on whether the old reg is still valid or the object
550 * is tiled) and inserting a new PTE into the faulting process.
552 * Note that the faulting process may involve evicting existing objects
553 * from the GTT and/or fence registers to make room. So performance may
554 * suffer if the GTT working set is large or there are few fence registers
557 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
559 struct drm_gem_object
*obj
= vma
->vm_private_data
;
560 struct drm_device
*dev
= obj
->dev
;
561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
562 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
566 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
568 /* We don't use vmf->pgoff since that has the fake offset */
569 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
572 /* Now bind it into the GTT if needed */
573 mutex_lock(&dev
->struct_mutex
);
574 if (!obj_priv
->gtt_space
) {
575 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
577 mutex_unlock(&dev
->struct_mutex
);
578 return VM_FAULT_SIGBUS
;
580 list_add(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
583 /* Need a new fence register? */
584 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
585 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
586 ret
= i915_gem_object_get_fence_reg(obj
, write
);
588 mutex_unlock(&dev
->struct_mutex
);
589 return VM_FAULT_SIGBUS
;
593 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
596 /* Finally, remap it using the new GTT offset */
597 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
599 mutex_unlock(&dev
->struct_mutex
);
606 return VM_FAULT_SIGBUS
;
608 return VM_FAULT_NOPAGE
;
613 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
614 * @obj: obj in question
616 * GEM memory mapping works by handing back to userspace a fake mmap offset
617 * it can use in a subsequent mmap(2) call. The DRM core code then looks
618 * up the object based on the offset and sets up the various memory mapping
621 * This routine allocates and attaches a fake offset for @obj.
624 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
626 struct drm_device
*dev
= obj
->dev
;
627 struct drm_gem_mm
*mm
= dev
->mm_private
;
628 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
629 struct drm_map_list
*list
;
633 /* Set the object up for mmap'ing */
634 list
= &obj
->map_list
;
635 list
->map
= drm_calloc(1, sizeof(struct drm_map_list
),
641 map
->type
= _DRM_GEM
;
642 map
->size
= obj
->size
;
645 /* Get a DRM GEM mmap offset allocated... */
646 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
647 obj
->size
/ PAGE_SIZE
, 0, 0);
648 if (!list
->file_offset_node
) {
649 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
654 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
655 obj
->size
/ PAGE_SIZE
, 0);
656 if (!list
->file_offset_node
) {
661 list
->hash
.key
= list
->file_offset_node
->start
;
662 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
663 DRM_ERROR("failed to add to map hash\n");
667 /* By now we should be all set, any drm_mmap request on the offset
668 * below will get to our mmap & fault handler */
669 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
674 drm_mm_put_block(list
->file_offset_node
);
676 drm_free(list
->map
, sizeof(struct drm_map_list
), DRM_MEM_DRIVER
);
682 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
684 struct drm_device
*dev
= obj
->dev
;
685 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
686 struct drm_gem_mm
*mm
= dev
->mm_private
;
687 struct drm_map_list
*list
;
689 list
= &obj
->map_list
;
690 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
692 if (list
->file_offset_node
) {
693 drm_mm_put_block(list
->file_offset_node
);
694 list
->file_offset_node
= NULL
;
698 drm_free(list
->map
, sizeof(struct drm_map
), DRM_MEM_DRIVER
);
702 obj_priv
->mmap_offset
= 0;
706 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
707 * @obj: object to check
709 * Return the required GTT alignment for an object, taking into account
710 * potential fence register mapping if needed.
713 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
715 struct drm_device
*dev
= obj
->dev
;
716 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
720 * Minimum alignment is 4k (GTT page size), but might be greater
721 * if a fence register is needed for the object.
723 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
727 * Previous chips need to be aligned to the size of the smallest
728 * fence register that can contain the object.
735 for (i
= start
; i
< obj
->size
; i
<<= 1)
742 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
744 * @data: GTT mapping ioctl data
745 * @file_priv: GEM object info
747 * Simply returns the fake offset to userspace so it can mmap it.
748 * The mmap call will end up in drm_gem_mmap(), which will set things
749 * up so we can get faults in the handler above.
751 * The fault handler will take care of binding the object into the GTT
752 * (since it may have been evicted to make room for something), allocating
753 * a fence register, and mapping the appropriate aperture address into
757 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
758 struct drm_file
*file_priv
)
760 struct drm_i915_gem_mmap_gtt
*args
= data
;
761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
762 struct drm_gem_object
*obj
;
763 struct drm_i915_gem_object
*obj_priv
;
766 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
769 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
773 mutex_lock(&dev
->struct_mutex
);
775 obj_priv
= obj
->driver_private
;
777 if (!obj_priv
->mmap_offset
) {
778 ret
= i915_gem_create_mmap_offset(obj
);
780 drm_gem_object_unreference(obj
);
781 mutex_unlock(&dev
->struct_mutex
);
786 args
->offset
= obj_priv
->mmap_offset
;
788 obj_priv
->gtt_alignment
= i915_gem_get_gtt_alignment(obj
);
790 /* Make sure the alignment is correct for fence regs etc */
791 if (obj_priv
->agp_mem
&&
792 (obj_priv
->gtt_offset
& (obj_priv
->gtt_alignment
- 1))) {
793 drm_gem_object_unreference(obj
);
794 mutex_unlock(&dev
->struct_mutex
);
799 * Pull it into the GTT so that we have a page list (makes the
800 * initial fault faster and any subsequent flushing possible).
802 if (!obj_priv
->agp_mem
) {
803 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
805 drm_gem_object_unreference(obj
);
806 mutex_unlock(&dev
->struct_mutex
);
809 list_add(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
812 drm_gem_object_unreference(obj
);
813 mutex_unlock(&dev
->struct_mutex
);
819 i915_gem_object_free_page_list(struct drm_gem_object
*obj
)
821 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
822 int page_count
= obj
->size
/ PAGE_SIZE
;
825 if (obj_priv
->page_list
== NULL
)
829 for (i
= 0; i
< page_count
; i
++)
830 if (obj_priv
->page_list
[i
] != NULL
) {
832 set_page_dirty(obj_priv
->page_list
[i
]);
833 mark_page_accessed(obj_priv
->page_list
[i
]);
834 page_cache_release(obj_priv
->page_list
[i
]);
838 drm_free(obj_priv
->page_list
,
839 page_count
* sizeof(struct page
*),
841 obj_priv
->page_list
= NULL
;
845 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
847 struct drm_device
*dev
= obj
->dev
;
848 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
849 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
851 /* Add a reference if we're newly entering the active list. */
852 if (!obj_priv
->active
) {
853 drm_gem_object_reference(obj
);
854 obj_priv
->active
= 1;
856 /* Move from whatever list we were on to the tail of execution. */
857 list_move_tail(&obj_priv
->list
,
858 &dev_priv
->mm
.active_list
);
859 obj_priv
->last_rendering_seqno
= seqno
;
863 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
865 struct drm_device
*dev
= obj
->dev
;
866 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
867 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
869 BUG_ON(!obj_priv
->active
);
870 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
871 obj_priv
->last_rendering_seqno
= 0;
875 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
877 struct drm_device
*dev
= obj
->dev
;
878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
879 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
881 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
882 if (obj_priv
->pin_count
!= 0)
883 list_del_init(&obj_priv
->list
);
885 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
887 obj_priv
->last_rendering_seqno
= 0;
888 if (obj_priv
->active
) {
889 obj_priv
->active
= 0;
890 drm_gem_object_unreference(obj
);
892 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
896 * Creates a new sequence number, emitting a write of it to the status page
897 * plus an interrupt, which will trigger i915_user_interrupt_handler.
899 * Must be called with struct_lock held.
901 * Returned sequence numbers are nonzero on success.
904 i915_add_request(struct drm_device
*dev
, uint32_t flush_domains
)
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
907 struct drm_i915_gem_request
*request
;
912 request
= drm_calloc(1, sizeof(*request
), DRM_MEM_DRIVER
);
916 /* Grab the seqno we're going to make this request be, and bump the
917 * next (skipping 0 so it can be the reserved no-seqno value).
919 seqno
= dev_priv
->mm
.next_gem_seqno
;
920 dev_priv
->mm
.next_gem_seqno
++;
921 if (dev_priv
->mm
.next_gem_seqno
== 0)
922 dev_priv
->mm
.next_gem_seqno
++;
925 OUT_RING(MI_STORE_DWORD_INDEX
);
926 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
929 OUT_RING(MI_USER_INTERRUPT
);
932 DRM_DEBUG("%d\n", seqno
);
934 request
->seqno
= seqno
;
935 request
->emitted_jiffies
= jiffies
;
936 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
937 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
939 /* Associate any objects on the flushing list matching the write
940 * domain we're flushing with our flush.
942 if (flush_domains
!= 0) {
943 struct drm_i915_gem_object
*obj_priv
, *next
;
945 list_for_each_entry_safe(obj_priv
, next
,
946 &dev_priv
->mm
.flushing_list
, list
) {
947 struct drm_gem_object
*obj
= obj_priv
->obj
;
949 if ((obj
->write_domain
& flush_domains
) ==
951 obj
->write_domain
= 0;
952 i915_gem_object_move_to_active(obj
, seqno
);
958 if (was_empty
&& !dev_priv
->mm
.suspended
)
959 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
964 * Command execution barrier
966 * Ensures that all commands in the ring are finished
967 * before signalling the CPU
970 i915_retire_commands(struct drm_device
*dev
)
972 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
973 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
974 uint32_t flush_domains
= 0;
977 /* The sampler always gets flushed on i965 (sigh) */
979 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
982 OUT_RING(0); /* noop */
984 return flush_domains
;
988 * Moves buffers associated only with the given active seqno from the active
989 * to inactive list, potentially freeing them.
992 i915_gem_retire_request(struct drm_device
*dev
,
993 struct drm_i915_gem_request
*request
)
995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
997 /* Move any buffers on the active list that are no longer referenced
998 * by the ringbuffer to the flushing/inactive lists as appropriate.
1000 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1001 struct drm_gem_object
*obj
;
1002 struct drm_i915_gem_object
*obj_priv
;
1004 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1005 struct drm_i915_gem_object
,
1007 obj
= obj_priv
->obj
;
1009 /* If the seqno being retired doesn't match the oldest in the
1010 * list, then the oldest in the list must still be newer than
1013 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1017 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018 __func__
, request
->seqno
, obj
);
1021 if (obj
->write_domain
!= 0)
1022 i915_gem_object_move_to_flushing(obj
);
1024 i915_gem_object_move_to_inactive(obj
);
1029 * Returns true if seq1 is later than seq2.
1032 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1034 return (int32_t)(seq1
- seq2
) >= 0;
1038 i915_get_gem_seqno(struct drm_device
*dev
)
1040 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1042 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1046 * This function clears the request list as sequence numbers are passed.
1049 i915_gem_retire_requests(struct drm_device
*dev
)
1051 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1054 if (!dev_priv
->hw_status_page
)
1057 seqno
= i915_get_gem_seqno(dev
);
1059 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1060 struct drm_i915_gem_request
*request
;
1061 uint32_t retiring_seqno
;
1063 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1064 struct drm_i915_gem_request
,
1066 retiring_seqno
= request
->seqno
;
1068 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1069 dev_priv
->mm
.wedged
) {
1070 i915_gem_retire_request(dev
, request
);
1072 list_del(&request
->list
);
1073 drm_free(request
, sizeof(*request
), DRM_MEM_DRIVER
);
1080 i915_gem_retire_work_handler(struct work_struct
*work
)
1082 drm_i915_private_t
*dev_priv
;
1083 struct drm_device
*dev
;
1085 dev_priv
= container_of(work
, drm_i915_private_t
,
1086 mm
.retire_work
.work
);
1087 dev
= dev_priv
->dev
;
1089 mutex_lock(&dev
->struct_mutex
);
1090 i915_gem_retire_requests(dev
);
1091 if (!dev_priv
->mm
.suspended
&&
1092 !list_empty(&dev_priv
->mm
.request_list
))
1093 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
1094 mutex_unlock(&dev
->struct_mutex
);
1098 * Waits for a sequence number to be signaled, and cleans up the
1099 * request and object lists appropriately for that event.
1102 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1104 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1109 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1110 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1111 i915_user_irq_get(dev
);
1112 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1113 i915_seqno_passed(i915_get_gem_seqno(dev
),
1115 dev_priv
->mm
.wedged
);
1116 i915_user_irq_put(dev
);
1117 dev_priv
->mm
.waiting_gem_seqno
= 0;
1119 if (dev_priv
->mm
.wedged
)
1122 if (ret
&& ret
!= -ERESTARTSYS
)
1123 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1124 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1126 /* Directly dispatch request retiring. While we have the work queue
1127 * to handle this, the waiter on a request often wants an associated
1128 * buffer to have made it to the inactive list, and we would need
1129 * a separate wait queue to handle that.
1132 i915_gem_retire_requests(dev
);
1138 i915_gem_flush(struct drm_device
*dev
,
1139 uint32_t invalidate_domains
,
1140 uint32_t flush_domains
)
1142 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1147 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1148 invalidate_domains
, flush_domains
);
1151 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1152 drm_agp_chipset_flush(dev
);
1154 if ((invalidate_domains
| flush_domains
) & ~(I915_GEM_DOMAIN_CPU
|
1155 I915_GEM_DOMAIN_GTT
)) {
1157 * read/write caches:
1159 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1160 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1161 * also flushed at 2d versus 3d pipeline switches.
1165 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1166 * MI_READ_FLUSH is set, and is always flushed on 965.
1168 * I915_GEM_DOMAIN_COMMAND may not exist?
1170 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1171 * invalidated when MI_EXE_FLUSH is set.
1173 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1174 * invalidated with every MI_FLUSH.
1178 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1179 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1180 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1181 * are flushed at any MI_FLUSH.
1184 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1185 if ((invalidate_domains
|flush_domains
) &
1186 I915_GEM_DOMAIN_RENDER
)
1187 cmd
&= ~MI_NO_WRITE_FLUSH
;
1188 if (!IS_I965G(dev
)) {
1190 * On the 965, the sampler cache always gets flushed
1191 * and this bit is reserved.
1193 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1194 cmd
|= MI_READ_FLUSH
;
1196 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1197 cmd
|= MI_EXE_FLUSH
;
1200 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1204 OUT_RING(0); /* noop */
1210 * Ensures that all rendering to the object has completed and the object is
1211 * safe to unbind from the GTT or access from the CPU.
1214 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1216 struct drm_device
*dev
= obj
->dev
;
1217 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1220 /* This function only exists to support waiting for existing rendering,
1221 * not for emitting required flushes.
1223 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1225 /* If there is rendering queued on the buffer being evicted, wait for
1228 if (obj_priv
->active
) {
1230 DRM_INFO("%s: object %p wait for seqno %08x\n",
1231 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1233 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1242 * Unbinds an object from the GTT aperture.
1245 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1247 struct drm_device
*dev
= obj
->dev
;
1248 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1253 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1254 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1256 if (obj_priv
->gtt_space
== NULL
)
1259 if (obj_priv
->pin_count
!= 0) {
1260 DRM_ERROR("Attempting to unbind pinned buffer\n");
1264 /* Move the object to the CPU domain to ensure that
1265 * any possible CPU writes while it's not in the GTT
1266 * are flushed when we go to remap it. This will
1267 * also ensure that all pending GPU writes are finished
1270 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1272 if (ret
!= -ERESTARTSYS
)
1273 DRM_ERROR("set_domain failed: %d\n", ret
);
1277 if (obj_priv
->agp_mem
!= NULL
) {
1278 drm_unbind_agp(obj_priv
->agp_mem
);
1279 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1280 obj_priv
->agp_mem
= NULL
;
1283 BUG_ON(obj_priv
->active
);
1285 /* blow away mappings if mapped through GTT */
1286 offset
= ((loff_t
) obj
->map_list
.hash
.key
) << PAGE_SHIFT
;
1287 if (dev
->dev_mapping
)
1288 unmap_mapping_range(dev
->dev_mapping
, offset
, obj
->size
, 1);
1290 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1291 i915_gem_clear_fence_reg(obj
);
1293 i915_gem_object_free_page_list(obj
);
1295 if (obj_priv
->gtt_space
) {
1296 atomic_dec(&dev
->gtt_count
);
1297 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1299 drm_mm_put_block(obj_priv
->gtt_space
);
1300 obj_priv
->gtt_space
= NULL
;
1303 /* Remove ourselves from the LRU list if present. */
1304 if (!list_empty(&obj_priv
->list
))
1305 list_del_init(&obj_priv
->list
);
1311 i915_gem_evict_something(struct drm_device
*dev
)
1313 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1314 struct drm_gem_object
*obj
;
1315 struct drm_i915_gem_object
*obj_priv
;
1319 /* If there's an inactive buffer available now, grab it
1322 if (!list_empty(&dev_priv
->mm
.inactive_list
)) {
1323 obj_priv
= list_first_entry(&dev_priv
->mm
.inactive_list
,
1324 struct drm_i915_gem_object
,
1326 obj
= obj_priv
->obj
;
1327 BUG_ON(obj_priv
->pin_count
!= 0);
1329 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
1331 BUG_ON(obj_priv
->active
);
1333 /* Wait on the rendering and unbind the buffer. */
1334 ret
= i915_gem_object_unbind(obj
);
1338 /* If we didn't get anything, but the ring is still processing
1339 * things, wait for one of those things to finish and hopefully
1340 * leave us a buffer to evict.
1342 if (!list_empty(&dev_priv
->mm
.request_list
)) {
1343 struct drm_i915_gem_request
*request
;
1345 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1346 struct drm_i915_gem_request
,
1349 ret
= i915_wait_request(dev
, request
->seqno
);
1353 /* if waiting caused an object to become inactive,
1354 * then loop around and wait for it. Otherwise, we
1355 * assume that waiting freed and unbound something,
1356 * so there should now be some space in the GTT
1358 if (!list_empty(&dev_priv
->mm
.inactive_list
))
1363 /* If we didn't have anything on the request list but there
1364 * are buffers awaiting a flush, emit one and try again.
1365 * When we wait on it, those buffers waiting for that flush
1366 * will get moved to inactive.
1368 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1369 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1370 struct drm_i915_gem_object
,
1372 obj
= obj_priv
->obj
;
1377 i915_add_request(dev
, obj
->write_domain
);
1383 DRM_ERROR("inactive empty %d request empty %d "
1384 "flushing empty %d\n",
1385 list_empty(&dev_priv
->mm
.inactive_list
),
1386 list_empty(&dev_priv
->mm
.request_list
),
1387 list_empty(&dev_priv
->mm
.flushing_list
));
1388 /* If we didn't do any of the above, there's nothing to be done
1389 * and we just can't fit it in.
1397 i915_gem_evict_everything(struct drm_device
*dev
)
1402 ret
= i915_gem_evict_something(dev
);
1412 i915_gem_object_get_page_list(struct drm_gem_object
*obj
)
1414 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1416 struct address_space
*mapping
;
1417 struct inode
*inode
;
1421 if (obj_priv
->page_list
)
1424 /* Get the list of pages out of our struct file. They'll be pinned
1425 * at this point until we release them.
1427 page_count
= obj
->size
/ PAGE_SIZE
;
1428 BUG_ON(obj_priv
->page_list
!= NULL
);
1429 obj_priv
->page_list
= drm_calloc(page_count
, sizeof(struct page
*),
1431 if (obj_priv
->page_list
== NULL
) {
1432 DRM_ERROR("Faled to allocate page list\n");
1436 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1437 mapping
= inode
->i_mapping
;
1438 for (i
= 0; i
< page_count
; i
++) {
1439 page
= read_mapping_page(mapping
, i
, NULL
);
1441 ret
= PTR_ERR(page
);
1442 DRM_ERROR("read_mapping_page failed: %d\n", ret
);
1443 i915_gem_object_free_page_list(obj
);
1446 obj_priv
->page_list
[i
] = page
;
1451 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1453 struct drm_gem_object
*obj
= reg
->obj
;
1454 struct drm_device
*dev
= obj
->dev
;
1455 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1456 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1457 int regnum
= obj_priv
->fence_reg
;
1460 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
1462 val
|= obj_priv
->gtt_offset
& 0xfffff000;
1463 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
1464 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1465 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
1466 val
|= I965_FENCE_REG_VALID
;
1468 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
1471 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1473 struct drm_gem_object
*obj
= reg
->obj
;
1474 struct drm_device
*dev
= obj
->dev
;
1475 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1476 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1477 int regnum
= obj_priv
->fence_reg
;
1482 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
1483 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
1484 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1485 __func__
, obj_priv
->gtt_offset
, obj
->size
);
1489 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
1490 HAS_128_BYTE_Y_TILING(dev
))
1495 /* Note: pitch better be a power of two tile widths */
1496 pitch_val
= obj_priv
->stride
/ tile_width
;
1497 pitch_val
= ffs(pitch_val
) - 1;
1499 val
= obj_priv
->gtt_offset
;
1500 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1501 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
1502 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
1503 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
1504 val
|= I830_FENCE_REG_VALID
;
1506 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
1509 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1511 struct drm_gem_object
*obj
= reg
->obj
;
1512 struct drm_device
*dev
= obj
->dev
;
1513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1514 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1515 int regnum
= obj_priv
->fence_reg
;
1519 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
1520 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
1521 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1522 __func__
, obj_priv
->gtt_offset
);
1526 pitch_val
= (obj_priv
->stride
/ 128) - 1;
1528 val
= obj_priv
->gtt_offset
;
1529 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1530 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
1531 val
|= I830_FENCE_SIZE_BITS(obj
->size
);
1532 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
1533 val
|= I830_FENCE_REG_VALID
;
1535 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
1540 * i915_gem_object_get_fence_reg - set up a fence reg for an object
1541 * @obj: object to map through a fence reg
1542 * @write: object is about to be written
1544 * When mapping objects through the GTT, userspace wants to be able to write
1545 * to them without having to worry about swizzling if the object is tiled.
1547 * This function walks the fence regs looking for a free one for @obj,
1548 * stealing one if it can't find any.
1550 * It then sets up the reg based on the object's properties: address, pitch
1551 * and tiling format.
1554 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
, bool write
)
1556 struct drm_device
*dev
= obj
->dev
;
1557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1558 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1559 struct drm_i915_fence_reg
*reg
= NULL
;
1562 switch (obj_priv
->tiling_mode
) {
1563 case I915_TILING_NONE
:
1564 WARN(1, "allocating a fence for non-tiled object?\n");
1567 if (!obj_priv
->stride
)
1569 WARN((obj_priv
->stride
& (512 - 1)),
1570 "object 0x%08x is X tiled but has non-512B pitch\n",
1571 obj_priv
->gtt_offset
);
1574 if (!obj_priv
->stride
)
1576 WARN((obj_priv
->stride
& (128 - 1)),
1577 "object 0x%08x is Y tiled but has non-128B pitch\n",
1578 obj_priv
->gtt_offset
);
1582 /* First try to find a free reg */
1583 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
1584 reg
= &dev_priv
->fence_regs
[i
];
1589 /* None available, try to steal one or wait for a user to finish */
1590 if (i
== dev_priv
->num_fence_regs
) {
1591 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
1595 /* Could try to use LRU here instead... */
1596 for (i
= dev_priv
->fence_reg_start
;
1597 i
< dev_priv
->num_fence_regs
; i
++) {
1598 reg
= &dev_priv
->fence_regs
[i
];
1599 old_obj_priv
= reg
->obj
->driver_private
;
1600 if (!old_obj_priv
->pin_count
)
1605 * Now things get ugly... we have to wait for one of the
1606 * objects to finish before trying again.
1608 if (i
== dev_priv
->num_fence_regs
) {
1609 ret
= i915_gem_object_set_to_gtt_domain(reg
->obj
, 0);
1611 WARN(ret
!= -ERESTARTSYS
,
1612 "switch to GTT domain failed: %d\n", ret
);
1619 * Zap this virtual mapping so we can set up a fence again
1620 * for this object next time we need it.
1622 offset
= ((loff_t
) reg
->obj
->map_list
.hash
.key
) << PAGE_SHIFT
;
1623 if (dev
->dev_mapping
)
1624 unmap_mapping_range(dev
->dev_mapping
, offset
,
1626 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
1629 obj_priv
->fence_reg
= i
;
1633 i965_write_fence_reg(reg
);
1634 else if (IS_I9XX(dev
))
1635 i915_write_fence_reg(reg
);
1637 i830_write_fence_reg(reg
);
1643 * i915_gem_clear_fence_reg - clear out fence register info
1644 * @obj: object to clear
1646 * Zeroes out the fence register itself and clears out the associated
1647 * data structures in dev_priv and obj_priv.
1650 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
1652 struct drm_device
*dev
= obj
->dev
;
1653 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1654 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1657 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
1659 I915_WRITE(FENCE_REG_830_0
+ (obj_priv
->fence_reg
* 4), 0);
1661 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
1662 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
1666 * Finds free space in the GTT aperture and binds the object there.
1669 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
1671 struct drm_device
*dev
= obj
->dev
;
1672 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1673 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1674 struct drm_mm_node
*free_space
;
1675 int page_count
, ret
;
1677 if (dev_priv
->mm
.suspended
)
1680 alignment
= i915_gem_get_gtt_alignment(obj
);
1681 if (alignment
& (PAGE_SIZE
- 1)) {
1682 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
1687 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
1688 obj
->size
, alignment
, 0);
1689 if (free_space
!= NULL
) {
1690 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
1692 if (obj_priv
->gtt_space
!= NULL
) {
1693 obj_priv
->gtt_space
->private = obj
;
1694 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
1697 if (obj_priv
->gtt_space
== NULL
) {
1698 /* If the gtt is empty and we're still having trouble
1699 * fitting our object in, we're out of memory.
1702 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
1704 if (list_empty(&dev_priv
->mm
.inactive_list
) &&
1705 list_empty(&dev_priv
->mm
.flushing_list
) &&
1706 list_empty(&dev_priv
->mm
.active_list
)) {
1707 DRM_ERROR("GTT full, but LRU list empty\n");
1711 ret
= i915_gem_evict_something(dev
);
1713 if (ret
!= -ERESTARTSYS
)
1714 DRM_ERROR("Failed to evict a buffer %d\n", ret
);
1721 DRM_INFO("Binding object of size %d at 0x%08x\n",
1722 obj
->size
, obj_priv
->gtt_offset
);
1724 ret
= i915_gem_object_get_page_list(obj
);
1726 drm_mm_put_block(obj_priv
->gtt_space
);
1727 obj_priv
->gtt_space
= NULL
;
1731 page_count
= obj
->size
/ PAGE_SIZE
;
1732 /* Create an AGP memory structure pointing at our pages, and bind it
1735 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
1736 obj_priv
->page_list
,
1738 obj_priv
->gtt_offset
,
1739 obj_priv
->agp_type
);
1740 if (obj_priv
->agp_mem
== NULL
) {
1741 i915_gem_object_free_page_list(obj
);
1742 drm_mm_put_block(obj_priv
->gtt_space
);
1743 obj_priv
->gtt_space
= NULL
;
1746 atomic_inc(&dev
->gtt_count
);
1747 atomic_add(obj
->size
, &dev
->gtt_memory
);
1749 /* Assert that the object is not currently in any GPU domain. As it
1750 * wasn't in the GTT, there shouldn't be any way it could have been in
1753 BUG_ON(obj
->read_domains
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1754 BUG_ON(obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1760 i915_gem_clflush_object(struct drm_gem_object
*obj
)
1762 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1764 /* If we don't have a page list set up, then we're not pinned
1765 * to GPU, and we can ignore the cache flush because it'll happen
1766 * again at bind time.
1768 if (obj_priv
->page_list
== NULL
)
1771 drm_clflush_pages(obj_priv
->page_list
, obj
->size
/ PAGE_SIZE
);
1774 /** Flushes any GPU write domain for the object if it's dirty. */
1776 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
1778 struct drm_device
*dev
= obj
->dev
;
1781 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
1784 /* Queue the GPU write cache flushing we need. */
1785 i915_gem_flush(dev
, 0, obj
->write_domain
);
1786 seqno
= i915_add_request(dev
, obj
->write_domain
);
1787 obj
->write_domain
= 0;
1788 i915_gem_object_move_to_active(obj
, seqno
);
1791 /** Flushes the GTT write domain for the object if it's dirty. */
1793 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
1795 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
1798 /* No actual flushing is required for the GTT write domain. Writes
1799 * to it immediately go to main memory as far as we know, so there's
1800 * no chipset flush. It also doesn't land in render cache.
1802 obj
->write_domain
= 0;
1805 /** Flushes the CPU write domain for the object if it's dirty. */
1807 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
1809 struct drm_device
*dev
= obj
->dev
;
1811 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
1814 i915_gem_clflush_object(obj
);
1815 drm_agp_chipset_flush(dev
);
1816 obj
->write_domain
= 0;
1820 * Moves a single object to the GTT read, and possibly write domain.
1822 * This function returns when the move is complete, including waiting on
1826 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
1828 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1831 /* Not valid to be called on unbound objects. */
1832 if (obj_priv
->gtt_space
== NULL
)
1835 i915_gem_object_flush_gpu_write_domain(obj
);
1836 /* Wait on any GPU rendering and flushing to occur. */
1837 ret
= i915_gem_object_wait_rendering(obj
);
1841 /* If we're writing through the GTT domain, then CPU and GPU caches
1842 * will need to be invalidated at next use.
1845 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
1847 i915_gem_object_flush_cpu_write_domain(obj
);
1849 /* It should now be out of any other write domains, and we can update
1850 * the domain values for our changes.
1852 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
1853 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
1855 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
1856 obj_priv
->dirty
= 1;
1863 * Moves a single object to the CPU read, and possibly write domain.
1865 * This function returns when the move is complete, including waiting on
1869 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
1871 struct drm_device
*dev
= obj
->dev
;
1874 i915_gem_object_flush_gpu_write_domain(obj
);
1875 /* Wait on any GPU rendering and flushing to occur. */
1876 ret
= i915_gem_object_wait_rendering(obj
);
1880 i915_gem_object_flush_gtt_write_domain(obj
);
1882 /* If we have a partially-valid cache of the object in the CPU,
1883 * finish invalidating it and free the per-page flags.
1885 i915_gem_object_set_to_full_cpu_read_domain(obj
);
1887 /* Flush the CPU cache if it's still invalid. */
1888 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
1889 i915_gem_clflush_object(obj
);
1890 drm_agp_chipset_flush(dev
);
1892 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
1895 /* It should now be out of any other write domains, and we can update
1896 * the domain values for our changes.
1898 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
1900 /* If we're writing through the CPU, then the GPU read domains will
1901 * need to be invalidated at next use.
1904 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
1905 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
1912 * Set the next domain for the specified object. This
1913 * may not actually perform the necessary flushing/invaliding though,
1914 * as that may want to be batched with other set_domain operations
1916 * This is (we hope) the only really tricky part of gem. The goal
1917 * is fairly simple -- track which caches hold bits of the object
1918 * and make sure they remain coherent. A few concrete examples may
1919 * help to explain how it works. For shorthand, we use the notation
1920 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1921 * a pair of read and write domain masks.
1923 * Case 1: the batch buffer
1929 * 5. Unmapped from GTT
1932 * Let's take these a step at a time
1935 * Pages allocated from the kernel may still have
1936 * cache contents, so we set them to (CPU, CPU) always.
1937 * 2. Written by CPU (using pwrite)
1938 * The pwrite function calls set_domain (CPU, CPU) and
1939 * this function does nothing (as nothing changes)
1941 * This function asserts that the object is not
1942 * currently in any GPU-based read or write domains
1944 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1945 * As write_domain is zero, this function adds in the
1946 * current read domains (CPU+COMMAND, 0).
1947 * flush_domains is set to CPU.
1948 * invalidate_domains is set to COMMAND
1949 * clflush is run to get data out of the CPU caches
1950 * then i915_dev_set_domain calls i915_gem_flush to
1951 * emit an MI_FLUSH and drm_agp_chipset_flush
1952 * 5. Unmapped from GTT
1953 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1954 * flush_domains and invalidate_domains end up both zero
1955 * so no flushing/invalidating happens
1959 * Case 2: The shared render buffer
1963 * 3. Read/written by GPU
1964 * 4. set_domain to (CPU,CPU)
1965 * 5. Read/written by CPU
1966 * 6. Read/written by GPU
1969 * Same as last example, (CPU, CPU)
1971 * Nothing changes (assertions find that it is not in the GPU)
1972 * 3. Read/written by GPU
1973 * execbuffer calls set_domain (RENDER, RENDER)
1974 * flush_domains gets CPU
1975 * invalidate_domains gets GPU
1977 * MI_FLUSH and drm_agp_chipset_flush
1978 * 4. set_domain (CPU, CPU)
1979 * flush_domains gets GPU
1980 * invalidate_domains gets CPU
1981 * wait_rendering (obj) to make sure all drawing is complete.
1982 * This will include an MI_FLUSH to get the data from GPU
1984 * clflush (obj) to invalidate the CPU cache
1985 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1986 * 5. Read/written by CPU
1987 * cache lines are loaded and dirtied
1988 * 6. Read written by GPU
1989 * Same as last GPU access
1991 * Case 3: The constant buffer
1996 * 4. Updated (written) by CPU again
2005 * flush_domains = CPU
2006 * invalidate_domains = RENDER
2009 * drm_agp_chipset_flush
2010 * 4. Updated (written) by CPU again
2012 * flush_domains = 0 (no previous write domain)
2013 * invalidate_domains = 0 (no new read domains)
2016 * flush_domains = CPU
2017 * invalidate_domains = RENDER
2020 * drm_agp_chipset_flush
2023 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2025 struct drm_device
*dev
= obj
->dev
;
2026 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2027 uint32_t invalidate_domains
= 0;
2028 uint32_t flush_domains
= 0;
2030 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2031 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2034 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2036 obj
->read_domains
, obj
->pending_read_domains
,
2037 obj
->write_domain
, obj
->pending_write_domain
);
2040 * If the object isn't moving to a new write domain,
2041 * let the object stay in multiple read domains
2043 if (obj
->pending_write_domain
== 0)
2044 obj
->pending_read_domains
|= obj
->read_domains
;
2046 obj_priv
->dirty
= 1;
2049 * Flush the current write domain if
2050 * the new read domains don't match. Invalidate
2051 * any read domains which differ from the old
2054 if (obj
->write_domain
&&
2055 obj
->write_domain
!= obj
->pending_read_domains
) {
2056 flush_domains
|= obj
->write_domain
;
2057 invalidate_domains
|=
2058 obj
->pending_read_domains
& ~obj
->write_domain
;
2061 * Invalidate any read caches which may have
2062 * stale data. That is, any new read domains.
2064 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2065 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2067 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2068 __func__
, flush_domains
, invalidate_domains
);
2070 i915_gem_clflush_object(obj
);
2073 /* The actual obj->write_domain will be updated with
2074 * pending_write_domain after we emit the accumulated flush for all
2075 * of our domain changes in execbuffers (which clears objects'
2076 * write_domains). So if we have a current write domain that we
2077 * aren't changing, set pending_write_domain to that.
2079 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
2080 obj
->pending_write_domain
= obj
->write_domain
;
2081 obj
->read_domains
= obj
->pending_read_domains
;
2083 dev
->invalidate_domains
|= invalidate_domains
;
2084 dev
->flush_domains
|= flush_domains
;
2086 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2088 obj
->read_domains
, obj
->write_domain
,
2089 dev
->invalidate_domains
, dev
->flush_domains
);
2094 * Moves the object from a partially CPU read to a full one.
2096 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2097 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2100 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
2102 struct drm_device
*dev
= obj
->dev
;
2103 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2105 if (!obj_priv
->page_cpu_valid
)
2108 /* If we're partially in the CPU read domain, finish moving it in.
2110 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
2113 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
2114 if (obj_priv
->page_cpu_valid
[i
])
2116 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
2118 drm_agp_chipset_flush(dev
);
2121 /* Free the page_cpu_valid mappings which are now stale, whether
2122 * or not we've got I915_GEM_DOMAIN_CPU.
2124 drm_free(obj_priv
->page_cpu_valid
, obj
->size
/ PAGE_SIZE
,
2126 obj_priv
->page_cpu_valid
= NULL
;
2130 * Set the CPU read domain on a range of the object.
2132 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2133 * not entirely valid. The page_cpu_valid member of the object flags which
2134 * pages have been flushed, and will be respected by
2135 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2136 * of the whole object.
2138 * This function returns when the move is complete, including waiting on
2142 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
2143 uint64_t offset
, uint64_t size
)
2145 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2148 if (offset
== 0 && size
== obj
->size
)
2149 return i915_gem_object_set_to_cpu_domain(obj
, 0);
2151 i915_gem_object_flush_gpu_write_domain(obj
);
2152 /* Wait on any GPU rendering and flushing to occur. */
2153 ret
= i915_gem_object_wait_rendering(obj
);
2156 i915_gem_object_flush_gtt_write_domain(obj
);
2158 /* If we're already fully in the CPU read domain, we're done. */
2159 if (obj_priv
->page_cpu_valid
== NULL
&&
2160 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
2163 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2164 * newly adding I915_GEM_DOMAIN_CPU
2166 if (obj_priv
->page_cpu_valid
== NULL
) {
2167 obj_priv
->page_cpu_valid
= drm_calloc(1, obj
->size
/ PAGE_SIZE
,
2169 if (obj_priv
->page_cpu_valid
== NULL
)
2171 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
2172 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
2174 /* Flush the cache on any pages that are still invalid from the CPU's
2177 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
2179 if (obj_priv
->page_cpu_valid
[i
])
2182 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
2184 obj_priv
->page_cpu_valid
[i
] = 1;
2187 /* It should now be out of any other write domains, and we can update
2188 * the domain values for our changes.
2190 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2192 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2198 * Pin an object to the GTT and evaluate the relocations landing in it.
2201 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
2202 struct drm_file
*file_priv
,
2203 struct drm_i915_gem_exec_object
*entry
)
2205 struct drm_device
*dev
= obj
->dev
;
2206 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2207 struct drm_i915_gem_relocation_entry reloc
;
2208 struct drm_i915_gem_relocation_entry __user
*relocs
;
2209 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2211 void __iomem
*reloc_page
;
2213 /* Choose the GTT offset for our buffer and put it there. */
2214 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
2218 entry
->offset
= obj_priv
->gtt_offset
;
2220 relocs
= (struct drm_i915_gem_relocation_entry __user
*)
2221 (uintptr_t) entry
->relocs_ptr
;
2222 /* Apply the relocations, using the GTT aperture to avoid cache
2223 * flushing requirements.
2225 for (i
= 0; i
< entry
->relocation_count
; i
++) {
2226 struct drm_gem_object
*target_obj
;
2227 struct drm_i915_gem_object
*target_obj_priv
;
2228 uint32_t reloc_val
, reloc_offset
;
2229 uint32_t __iomem
*reloc_entry
;
2231 ret
= copy_from_user(&reloc
, relocs
+ i
, sizeof(reloc
));
2233 i915_gem_object_unpin(obj
);
2237 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
2238 reloc
.target_handle
);
2239 if (target_obj
== NULL
) {
2240 i915_gem_object_unpin(obj
);
2243 target_obj_priv
= target_obj
->driver_private
;
2245 /* The target buffer should have appeared before us in the
2246 * exec_object list, so it should have a GTT space bound by now.
2248 if (target_obj_priv
->gtt_space
== NULL
) {
2249 DRM_ERROR("No GTT space found for object %d\n",
2250 reloc
.target_handle
);
2251 drm_gem_object_unreference(target_obj
);
2252 i915_gem_object_unpin(obj
);
2256 if (reloc
.offset
> obj
->size
- 4) {
2257 DRM_ERROR("Relocation beyond object bounds: "
2258 "obj %p target %d offset %d size %d.\n",
2259 obj
, reloc
.target_handle
,
2260 (int) reloc
.offset
, (int) obj
->size
);
2261 drm_gem_object_unreference(target_obj
);
2262 i915_gem_object_unpin(obj
);
2265 if (reloc
.offset
& 3) {
2266 DRM_ERROR("Relocation not 4-byte aligned: "
2267 "obj %p target %d offset %d.\n",
2268 obj
, reloc
.target_handle
,
2269 (int) reloc
.offset
);
2270 drm_gem_object_unreference(target_obj
);
2271 i915_gem_object_unpin(obj
);
2275 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
2276 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
2277 DRM_ERROR("reloc with read/write CPU domains: "
2278 "obj %p target %d offset %d "
2279 "read %08x write %08x",
2280 obj
, reloc
.target_handle
,
2283 reloc
.write_domain
);
2284 drm_gem_object_unreference(target_obj
);
2285 i915_gem_object_unpin(obj
);
2289 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
2290 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
2291 DRM_ERROR("Write domain conflict: "
2292 "obj %p target %d offset %d "
2293 "new %08x old %08x\n",
2294 obj
, reloc
.target_handle
,
2297 target_obj
->pending_write_domain
);
2298 drm_gem_object_unreference(target_obj
);
2299 i915_gem_object_unpin(obj
);
2304 DRM_INFO("%s: obj %p offset %08x target %d "
2305 "read %08x write %08x gtt %08x "
2306 "presumed %08x delta %08x\n",
2310 (int) reloc
.target_handle
,
2311 (int) reloc
.read_domains
,
2312 (int) reloc
.write_domain
,
2313 (int) target_obj_priv
->gtt_offset
,
2314 (int) reloc
.presumed_offset
,
2318 target_obj
->pending_read_domains
|= reloc
.read_domains
;
2319 target_obj
->pending_write_domain
|= reloc
.write_domain
;
2321 /* If the relocation already has the right value in it, no
2322 * more work needs to be done.
2324 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
2325 drm_gem_object_unreference(target_obj
);
2329 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
2331 drm_gem_object_unreference(target_obj
);
2332 i915_gem_object_unpin(obj
);
2336 /* Map the page containing the relocation we're going to
2339 reloc_offset
= obj_priv
->gtt_offset
+ reloc
.offset
;
2340 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
2343 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
2344 (reloc_offset
& (PAGE_SIZE
- 1)));
2345 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
.delta
;
2348 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2349 obj
, (unsigned int) reloc
.offset
,
2350 readl(reloc_entry
), reloc_val
);
2352 writel(reloc_val
, reloc_entry
);
2353 io_mapping_unmap_atomic(reloc_page
);
2355 /* Write the updated presumed offset for this entry back out
2358 reloc
.presumed_offset
= target_obj_priv
->gtt_offset
;
2359 ret
= copy_to_user(relocs
+ i
, &reloc
, sizeof(reloc
));
2361 drm_gem_object_unreference(target_obj
);
2362 i915_gem_object_unpin(obj
);
2366 drm_gem_object_unreference(target_obj
);
2371 i915_gem_dump_object(obj
, 128, __func__
, ~0);
2376 /** Dispatch a batchbuffer to the ring
2379 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
2380 struct drm_i915_gem_execbuffer
*exec
,
2381 uint64_t exec_offset
)
2383 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2384 struct drm_clip_rect __user
*boxes
= (struct drm_clip_rect __user
*)
2385 (uintptr_t) exec
->cliprects_ptr
;
2386 int nbox
= exec
->num_cliprects
;
2388 uint32_t exec_start
, exec_len
;
2391 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
2392 exec_len
= (uint32_t) exec
->batch_len
;
2394 if ((exec_start
| exec_len
) & 0x7) {
2395 DRM_ERROR("alignment\n");
2402 count
= nbox
? nbox
: 1;
2404 for (i
= 0; i
< count
; i
++) {
2406 int ret
= i915_emit_box(dev
, boxes
, i
,
2407 exec
->DR1
, exec
->DR4
);
2412 if (IS_I830(dev
) || IS_845G(dev
)) {
2414 OUT_RING(MI_BATCH_BUFFER
);
2415 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
2416 OUT_RING(exec_start
+ exec_len
- 4);
2421 if (IS_I965G(dev
)) {
2422 OUT_RING(MI_BATCH_BUFFER_START
|
2424 MI_BATCH_NON_SECURE_I965
);
2425 OUT_RING(exec_start
);
2427 OUT_RING(MI_BATCH_BUFFER_START
|
2429 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
2435 /* XXX breadcrumb */
2439 /* Throttle our rendering by waiting until the ring has completed our requests
2440 * emitted over 20 msec ago.
2442 * This should get us reasonable parallelism between CPU and GPU but also
2443 * relatively low latency when blocking on a particular request to finish.
2446 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
2448 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
2452 mutex_lock(&dev
->struct_mutex
);
2453 seqno
= i915_file_priv
->mm
.last_gem_throttle_seqno
;
2454 i915_file_priv
->mm
.last_gem_throttle_seqno
=
2455 i915_file_priv
->mm
.last_gem_seqno
;
2457 ret
= i915_wait_request(dev
, seqno
);
2458 mutex_unlock(&dev
->struct_mutex
);
2463 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2464 struct drm_file
*file_priv
)
2466 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2467 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
2468 struct drm_i915_gem_execbuffer
*args
= data
;
2469 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
2470 struct drm_gem_object
**object_list
= NULL
;
2471 struct drm_gem_object
*batch_obj
;
2472 struct drm_i915_gem_object
*obj_priv
;
2473 int ret
, i
, pinned
= 0;
2474 uint64_t exec_offset
;
2475 uint32_t seqno
, flush_domains
;
2479 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2480 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
2483 if (args
->buffer_count
< 1) {
2484 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
2487 /* Copy in the exec list from userland */
2488 exec_list
= drm_calloc(sizeof(*exec_list
), args
->buffer_count
,
2490 object_list
= drm_calloc(sizeof(*object_list
), args
->buffer_count
,
2492 if (exec_list
== NULL
|| object_list
== NULL
) {
2493 DRM_ERROR("Failed to allocate exec or object list "
2495 args
->buffer_count
);
2499 ret
= copy_from_user(exec_list
,
2500 (struct drm_i915_relocation_entry __user
*)
2501 (uintptr_t) args
->buffers_ptr
,
2502 sizeof(*exec_list
) * args
->buffer_count
);
2504 DRM_ERROR("copy %d exec entries failed %d\n",
2505 args
->buffer_count
, ret
);
2509 mutex_lock(&dev
->struct_mutex
);
2511 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2513 if (dev_priv
->mm
.wedged
) {
2514 DRM_ERROR("Execbuf while wedged\n");
2515 mutex_unlock(&dev
->struct_mutex
);
2520 if (dev_priv
->mm
.suspended
) {
2521 DRM_ERROR("Execbuf while VT-switched.\n");
2522 mutex_unlock(&dev
->struct_mutex
);
2527 /* Look up object handles */
2528 for (i
= 0; i
< args
->buffer_count
; i
++) {
2529 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
2530 exec_list
[i
].handle
);
2531 if (object_list
[i
] == NULL
) {
2532 DRM_ERROR("Invalid object handle %d at index %d\n",
2533 exec_list
[i
].handle
, i
);
2538 obj_priv
= object_list
[i
]->driver_private
;
2539 if (obj_priv
->in_execbuffer
) {
2540 DRM_ERROR("Object %p appears more than once in object list\n",
2545 obj_priv
->in_execbuffer
= true;
2548 /* Pin and relocate */
2549 for (pin_tries
= 0; ; pin_tries
++) {
2551 for (i
= 0; i
< args
->buffer_count
; i
++) {
2552 object_list
[i
]->pending_read_domains
= 0;
2553 object_list
[i
]->pending_write_domain
= 0;
2554 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
2565 /* error other than GTT full, or we've already tried again */
2566 if (ret
!= -ENOMEM
|| pin_tries
>= 1) {
2567 if (ret
!= -ERESTARTSYS
)
2568 DRM_ERROR("Failed to pin buffers %d\n", ret
);
2572 /* unpin all of our buffers */
2573 for (i
= 0; i
< pinned
; i
++)
2574 i915_gem_object_unpin(object_list
[i
]);
2577 /* evict everyone we can from the aperture */
2578 ret
= i915_gem_evict_everything(dev
);
2583 /* Set the pending read domains for the batch buffer to COMMAND */
2584 batch_obj
= object_list
[args
->buffer_count
-1];
2585 batch_obj
->pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
2586 batch_obj
->pending_write_domain
= 0;
2588 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2590 /* Zero the global flush/invalidate flags. These
2591 * will be modified as new domains are computed
2594 dev
->invalidate_domains
= 0;
2595 dev
->flush_domains
= 0;
2597 for (i
= 0; i
< args
->buffer_count
; i
++) {
2598 struct drm_gem_object
*obj
= object_list
[i
];
2600 /* Compute new gpu domains and update invalidate/flush */
2601 i915_gem_object_set_to_gpu_domain(obj
);
2604 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2606 if (dev
->invalidate_domains
| dev
->flush_domains
) {
2608 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2610 dev
->invalidate_domains
,
2611 dev
->flush_domains
);
2614 dev
->invalidate_domains
,
2615 dev
->flush_domains
);
2616 if (dev
->flush_domains
)
2617 (void)i915_add_request(dev
, dev
->flush_domains
);
2620 for (i
= 0; i
< args
->buffer_count
; i
++) {
2621 struct drm_gem_object
*obj
= object_list
[i
];
2623 obj
->write_domain
= obj
->pending_write_domain
;
2626 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2629 for (i
= 0; i
< args
->buffer_count
; i
++) {
2630 i915_gem_object_check_coherency(object_list
[i
],
2631 exec_list
[i
].handle
);
2635 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
2638 i915_gem_dump_object(object_list
[args
->buffer_count
- 1],
2644 /* Exec the batchbuffer */
2645 ret
= i915_dispatch_gem_execbuffer(dev
, args
, exec_offset
);
2647 DRM_ERROR("dispatch failed %d\n", ret
);
2652 * Ensure that the commands in the batch buffer are
2653 * finished before the interrupt fires
2655 flush_domains
= i915_retire_commands(dev
);
2657 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2660 * Get a seqno representing the execution of the current buffer,
2661 * which we can wait on. We would like to mitigate these interrupts,
2662 * likely by only creating seqnos occasionally (so that we have
2663 * *some* interrupts representing completion of buffers that we can
2664 * wait on when trying to clear up gtt space).
2666 seqno
= i915_add_request(dev
, flush_domains
);
2668 i915_file_priv
->mm
.last_gem_seqno
= seqno
;
2669 for (i
= 0; i
< args
->buffer_count
; i
++) {
2670 struct drm_gem_object
*obj
= object_list
[i
];
2672 i915_gem_object_move_to_active(obj
, seqno
);
2674 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
2678 i915_dump_lru(dev
, __func__
);
2681 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2684 for (i
= 0; i
< pinned
; i
++)
2685 i915_gem_object_unpin(object_list
[i
]);
2687 for (i
= 0; i
< args
->buffer_count
; i
++) {
2688 if (object_list
[i
]) {
2689 obj_priv
= object_list
[i
]->driver_private
;
2690 obj_priv
->in_execbuffer
= false;
2692 drm_gem_object_unreference(object_list
[i
]);
2695 mutex_unlock(&dev
->struct_mutex
);
2698 /* Copy the new buffer offsets back to the user's exec list. */
2699 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
2700 (uintptr_t) args
->buffers_ptr
,
2702 sizeof(*exec_list
) * args
->buffer_count
);
2704 DRM_ERROR("failed to copy %d exec entries "
2705 "back to user (%d)\n",
2706 args
->buffer_count
, ret
);
2710 drm_free(object_list
, sizeof(*object_list
) * args
->buffer_count
,
2712 drm_free(exec_list
, sizeof(*exec_list
) * args
->buffer_count
,
2719 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
2721 struct drm_device
*dev
= obj
->dev
;
2722 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2725 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2726 if (obj_priv
->gtt_space
== NULL
) {
2727 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
2729 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
2730 DRM_ERROR("Failure to bind: %d", ret
);
2734 * Pre-965 chips need a fence register set up in order to
2735 * properly handle tiled surfaces.
2737 if (!IS_I965G(dev
) &&
2738 obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
2739 obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2740 i915_gem_object_get_fence_reg(obj
, true);
2742 obj_priv
->pin_count
++;
2744 /* If the object is not active and not pending a flush,
2745 * remove it from the inactive list
2747 if (obj_priv
->pin_count
== 1) {
2748 atomic_inc(&dev
->pin_count
);
2749 atomic_add(obj
->size
, &dev
->pin_memory
);
2750 if (!obj_priv
->active
&&
2751 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2752 I915_GEM_DOMAIN_GTT
)) == 0 &&
2753 !list_empty(&obj_priv
->list
))
2754 list_del_init(&obj_priv
->list
);
2756 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2762 i915_gem_object_unpin(struct drm_gem_object
*obj
)
2764 struct drm_device
*dev
= obj
->dev
;
2765 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2766 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2768 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2769 obj_priv
->pin_count
--;
2770 BUG_ON(obj_priv
->pin_count
< 0);
2771 BUG_ON(obj_priv
->gtt_space
== NULL
);
2773 /* If the object is no longer pinned, and is
2774 * neither active nor being flushed, then stick it on
2777 if (obj_priv
->pin_count
== 0) {
2778 if (!obj_priv
->active
&&
2779 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2780 I915_GEM_DOMAIN_GTT
)) == 0)
2781 list_move_tail(&obj_priv
->list
,
2782 &dev_priv
->mm
.inactive_list
);
2783 atomic_dec(&dev
->pin_count
);
2784 atomic_sub(obj
->size
, &dev
->pin_memory
);
2786 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2790 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2791 struct drm_file
*file_priv
)
2793 struct drm_i915_gem_pin
*args
= data
;
2794 struct drm_gem_object
*obj
;
2795 struct drm_i915_gem_object
*obj_priv
;
2798 mutex_lock(&dev
->struct_mutex
);
2800 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2802 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2804 mutex_unlock(&dev
->struct_mutex
);
2807 obj_priv
= obj
->driver_private
;
2809 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
2810 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2812 drm_gem_object_unreference(obj
);
2813 mutex_unlock(&dev
->struct_mutex
);
2817 obj_priv
->user_pin_count
++;
2818 obj_priv
->pin_filp
= file_priv
;
2819 if (obj_priv
->user_pin_count
== 1) {
2820 ret
= i915_gem_object_pin(obj
, args
->alignment
);
2822 drm_gem_object_unreference(obj
);
2823 mutex_unlock(&dev
->struct_mutex
);
2828 /* XXX - flush the CPU caches for pinned objects
2829 * as the X server doesn't manage domains yet
2831 i915_gem_object_flush_cpu_write_domain(obj
);
2832 args
->offset
= obj_priv
->gtt_offset
;
2833 drm_gem_object_unreference(obj
);
2834 mutex_unlock(&dev
->struct_mutex
);
2840 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2841 struct drm_file
*file_priv
)
2843 struct drm_i915_gem_pin
*args
= data
;
2844 struct drm_gem_object
*obj
;
2845 struct drm_i915_gem_object
*obj_priv
;
2847 mutex_lock(&dev
->struct_mutex
);
2849 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2851 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2853 mutex_unlock(&dev
->struct_mutex
);
2857 obj_priv
= obj
->driver_private
;
2858 if (obj_priv
->pin_filp
!= file_priv
) {
2859 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2861 drm_gem_object_unreference(obj
);
2862 mutex_unlock(&dev
->struct_mutex
);
2865 obj_priv
->user_pin_count
--;
2866 if (obj_priv
->user_pin_count
== 0) {
2867 obj_priv
->pin_filp
= NULL
;
2868 i915_gem_object_unpin(obj
);
2871 drm_gem_object_unreference(obj
);
2872 mutex_unlock(&dev
->struct_mutex
);
2877 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2878 struct drm_file
*file_priv
)
2880 struct drm_i915_gem_busy
*args
= data
;
2881 struct drm_gem_object
*obj
;
2882 struct drm_i915_gem_object
*obj_priv
;
2884 mutex_lock(&dev
->struct_mutex
);
2885 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2887 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2889 mutex_unlock(&dev
->struct_mutex
);
2893 /* Update the active list for the hardware's current position.
2894 * Otherwise this only updates on a delayed timer or when irqs are
2895 * actually unmasked, and our working set ends up being larger than
2898 i915_gem_retire_requests(dev
);
2900 obj_priv
= obj
->driver_private
;
2901 /* Don't count being on the flushing list against the object being
2902 * done. Otherwise, a buffer left on the flushing list but not getting
2903 * flushed (because nobody's flushing that domain) won't ever return
2904 * unbusy and get reused by libdrm's bo cache. The other expected
2905 * consumer of this interface, OpenGL's occlusion queries, also specs
2906 * that the objects get unbusy "eventually" without any interference.
2908 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
2910 drm_gem_object_unreference(obj
);
2911 mutex_unlock(&dev
->struct_mutex
);
2916 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2917 struct drm_file
*file_priv
)
2919 return i915_gem_ring_throttle(dev
, file_priv
);
2922 int i915_gem_init_object(struct drm_gem_object
*obj
)
2924 struct drm_i915_gem_object
*obj_priv
;
2926 obj_priv
= drm_calloc(1, sizeof(*obj_priv
), DRM_MEM_DRIVER
);
2927 if (obj_priv
== NULL
)
2931 * We've just allocated pages from the kernel,
2932 * so they've just been written by the CPU with
2933 * zeros. They'll need to be clflushed before we
2934 * use them with the GPU.
2936 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2937 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2939 obj_priv
->agp_type
= AGP_USER_MEMORY
;
2941 obj
->driver_private
= obj_priv
;
2942 obj_priv
->obj
= obj
;
2943 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2944 INIT_LIST_HEAD(&obj_priv
->list
);
2949 void i915_gem_free_object(struct drm_gem_object
*obj
)
2951 struct drm_device
*dev
= obj
->dev
;
2952 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2954 while (obj_priv
->pin_count
> 0)
2955 i915_gem_object_unpin(obj
);
2957 if (obj_priv
->phys_obj
)
2958 i915_gem_detach_phys_object(dev
, obj
);
2960 i915_gem_object_unbind(obj
);
2962 i915_gem_free_mmap_offset(obj
);
2964 drm_free(obj_priv
->page_cpu_valid
, 1, DRM_MEM_DRIVER
);
2965 drm_free(obj
->driver_private
, 1, DRM_MEM_DRIVER
);
2968 /** Unbinds all objects that are on the given buffer list. */
2970 i915_gem_evict_from_list(struct drm_device
*dev
, struct list_head
*head
)
2972 struct drm_gem_object
*obj
;
2973 struct drm_i915_gem_object
*obj_priv
;
2976 while (!list_empty(head
)) {
2977 obj_priv
= list_first_entry(head
,
2978 struct drm_i915_gem_object
,
2980 obj
= obj_priv
->obj
;
2982 if (obj_priv
->pin_count
!= 0) {
2983 DRM_ERROR("Pinned object in unbind list\n");
2984 mutex_unlock(&dev
->struct_mutex
);
2988 ret
= i915_gem_object_unbind(obj
);
2990 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2992 mutex_unlock(&dev
->struct_mutex
);
3002 i915_gem_idle(struct drm_device
*dev
)
3004 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3005 uint32_t seqno
, cur_seqno
, last_seqno
;
3008 mutex_lock(&dev
->struct_mutex
);
3010 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
3011 mutex_unlock(&dev
->struct_mutex
);
3015 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3016 * We need to replace this with a semaphore, or something.
3018 dev_priv
->mm
.suspended
= 1;
3020 /* Cancel the retire work handler, wait for it to finish if running
3022 mutex_unlock(&dev
->struct_mutex
);
3023 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3024 mutex_lock(&dev
->struct_mutex
);
3026 i915_kernel_lost_context(dev
);
3028 /* Flush the GPU along with all non-CPU write domains
3030 i915_gem_flush(dev
, ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
),
3031 ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
3032 seqno
= i915_add_request(dev
, ~I915_GEM_DOMAIN_CPU
);
3035 mutex_unlock(&dev
->struct_mutex
);
3039 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
3043 cur_seqno
= i915_get_gem_seqno(dev
);
3044 if (i915_seqno_passed(cur_seqno
, seqno
))
3046 if (last_seqno
== cur_seqno
) {
3047 if (stuck
++ > 100) {
3048 DRM_ERROR("hardware wedged\n");
3049 dev_priv
->mm
.wedged
= 1;
3050 DRM_WAKEUP(&dev_priv
->irq_queue
);
3055 last_seqno
= cur_seqno
;
3057 dev_priv
->mm
.waiting_gem_seqno
= 0;
3059 i915_gem_retire_requests(dev
);
3061 if (!dev_priv
->mm
.wedged
) {
3062 /* Active and flushing should now be empty as we've
3063 * waited for a sequence higher than any pending execbuffer
3065 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
3066 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3067 /* Request should now be empty as we've also waited
3068 * for the last request in the list
3070 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
3073 /* Empty the active and flushing lists to inactive. If there's
3074 * anything left at this point, it means that we're wedged and
3075 * nothing good's going to happen by leaving them there. So strip
3076 * the GPU domains and just stuff them onto inactive.
3078 while (!list_empty(&dev_priv
->mm
.active_list
)) {
3079 struct drm_i915_gem_object
*obj_priv
;
3081 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
3082 struct drm_i915_gem_object
,
3084 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3085 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3088 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
3089 struct drm_i915_gem_object
*obj_priv
;
3091 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
3092 struct drm_i915_gem_object
,
3094 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3095 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3099 /* Move all inactive buffers out of the GTT. */
3100 ret
= i915_gem_evict_from_list(dev
, &dev_priv
->mm
.inactive_list
);
3101 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3103 mutex_unlock(&dev
->struct_mutex
);
3107 i915_gem_cleanup_ringbuffer(dev
);
3108 mutex_unlock(&dev
->struct_mutex
);
3114 i915_gem_init_hws(struct drm_device
*dev
)
3116 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3117 struct drm_gem_object
*obj
;
3118 struct drm_i915_gem_object
*obj_priv
;
3121 /* If we need a physical address for the status page, it's already
3122 * initialized at driver load time.
3124 if (!I915_NEED_GFX_HWS(dev
))
3127 obj
= drm_gem_object_alloc(dev
, 4096);
3129 DRM_ERROR("Failed to allocate status page\n");
3132 obj_priv
= obj
->driver_private
;
3133 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
3135 ret
= i915_gem_object_pin(obj
, 4096);
3137 drm_gem_object_unreference(obj
);
3141 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
3143 dev_priv
->hw_status_page
= kmap(obj_priv
->page_list
[0]);
3144 if (dev_priv
->hw_status_page
== NULL
) {
3145 DRM_ERROR("Failed to map status page.\n");
3146 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
3147 i915_gem_object_unpin(obj
);
3148 drm_gem_object_unreference(obj
);
3151 dev_priv
->hws_obj
= obj
;
3152 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
3153 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
3154 I915_READ(HWS_PGA
); /* posting read */
3155 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
3161 i915_gem_cleanup_hws(struct drm_device
*dev
)
3163 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3164 struct drm_gem_object
*obj
;
3165 struct drm_i915_gem_object
*obj_priv
;
3167 if (dev_priv
->hws_obj
== NULL
)
3170 obj
= dev_priv
->hws_obj
;
3171 obj_priv
= obj
->driver_private
;
3173 kunmap(obj_priv
->page_list
[0]);
3174 i915_gem_object_unpin(obj
);
3175 drm_gem_object_unreference(obj
);
3176 dev_priv
->hws_obj
= NULL
;
3178 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
3179 dev_priv
->hw_status_page
= NULL
;
3181 /* Write high address into HWS_PGA when disabling. */
3182 I915_WRITE(HWS_PGA
, 0x1ffff000);
3186 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3188 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3189 struct drm_gem_object
*obj
;
3190 struct drm_i915_gem_object
*obj_priv
;
3191 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
3195 ret
= i915_gem_init_hws(dev
);
3199 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
3201 DRM_ERROR("Failed to allocate ringbuffer\n");
3202 i915_gem_cleanup_hws(dev
);
3205 obj_priv
= obj
->driver_private
;
3207 ret
= i915_gem_object_pin(obj
, 4096);
3209 drm_gem_object_unreference(obj
);
3210 i915_gem_cleanup_hws(dev
);
3214 /* Set up the kernel mapping for the ring. */
3215 ring
->Size
= obj
->size
;
3216 ring
->tail_mask
= obj
->size
- 1;
3218 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
3219 ring
->map
.size
= obj
->size
;
3221 ring
->map
.flags
= 0;
3224 drm_core_ioremap_wc(&ring
->map
, dev
);
3225 if (ring
->map
.handle
== NULL
) {
3226 DRM_ERROR("Failed to map ringbuffer.\n");
3227 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
3228 i915_gem_object_unpin(obj
);
3229 drm_gem_object_unreference(obj
);
3230 i915_gem_cleanup_hws(dev
);
3233 ring
->ring_obj
= obj
;
3234 ring
->virtual_start
= ring
->map
.handle
;
3236 /* Stop the ring if it's running. */
3237 I915_WRITE(PRB0_CTL
, 0);
3238 I915_WRITE(PRB0_TAIL
, 0);
3239 I915_WRITE(PRB0_HEAD
, 0);
3241 /* Initialize the ring. */
3242 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
3243 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3245 /* G45 ring initialization fails to reset head to zero */
3247 DRM_ERROR("Ring head not reset to zero "
3248 "ctl %08x head %08x tail %08x start %08x\n",
3249 I915_READ(PRB0_CTL
),
3250 I915_READ(PRB0_HEAD
),
3251 I915_READ(PRB0_TAIL
),
3252 I915_READ(PRB0_START
));
3253 I915_WRITE(PRB0_HEAD
, 0);
3255 DRM_ERROR("Ring head forced to zero "
3256 "ctl %08x head %08x tail %08x start %08x\n",
3257 I915_READ(PRB0_CTL
),
3258 I915_READ(PRB0_HEAD
),
3259 I915_READ(PRB0_TAIL
),
3260 I915_READ(PRB0_START
));
3263 I915_WRITE(PRB0_CTL
,
3264 ((obj
->size
- 4096) & RING_NR_PAGES
) |
3268 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3270 /* If the head is still not zero, the ring is dead */
3272 DRM_ERROR("Ring initialization failed "
3273 "ctl %08x head %08x tail %08x start %08x\n",
3274 I915_READ(PRB0_CTL
),
3275 I915_READ(PRB0_HEAD
),
3276 I915_READ(PRB0_TAIL
),
3277 I915_READ(PRB0_START
));
3281 /* Update our cache of the ring state */
3282 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3283 i915_kernel_lost_context(dev
);
3285 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3286 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
3287 ring
->space
= ring
->head
- (ring
->tail
+ 8);
3288 if (ring
->space
< 0)
3289 ring
->space
+= ring
->Size
;
3296 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3298 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3300 if (dev_priv
->ring
.ring_obj
== NULL
)
3303 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
3305 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
3306 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
3307 dev_priv
->ring
.ring_obj
= NULL
;
3308 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
3310 i915_gem_cleanup_hws(dev
);
3314 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3315 struct drm_file
*file_priv
)
3317 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3320 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3323 if (dev_priv
->mm
.wedged
) {
3324 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3325 dev_priv
->mm
.wedged
= 0;
3328 mutex_lock(&dev
->struct_mutex
);
3329 dev_priv
->mm
.suspended
= 0;
3331 ret
= i915_gem_init_ringbuffer(dev
);
3335 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3336 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3337 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3338 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
3339 mutex_unlock(&dev
->struct_mutex
);
3341 drm_irq_install(dev
);
3347 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3348 struct drm_file
*file_priv
)
3352 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3355 ret
= i915_gem_idle(dev
);
3356 drm_irq_uninstall(dev
);
3362 i915_gem_lastclose(struct drm_device
*dev
)
3366 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3369 ret
= i915_gem_idle(dev
);
3371 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3375 i915_gem_load(struct drm_device
*dev
)
3377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3379 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3380 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3381 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3382 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
3383 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3384 i915_gem_retire_work_handler
);
3385 dev_priv
->mm
.next_gem_seqno
= 1;
3387 /* Old X drivers will take 0-2 for front, back, depth buffers */
3388 dev_priv
->fence_reg_start
= 3;
3390 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3391 dev_priv
->num_fence_regs
= 16;
3393 dev_priv
->num_fence_regs
= 8;
3395 i915_gem_detect_bit_6_swizzle(dev
);
3399 * Create a physically contiguous memory object for this object
3400 * e.g. for cursor + overlay regs
3402 int i915_gem_init_phys_object(struct drm_device
*dev
,
3405 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3406 struct drm_i915_gem_phys_object
*phys_obj
;
3409 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3412 phys_obj
= drm_calloc(1, sizeof(struct drm_i915_gem_phys_object
), DRM_MEM_DRIVER
);
3418 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0, 0xffffffff);
3419 if (!phys_obj
->handle
) {
3424 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3427 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3431 drm_free(phys_obj
, sizeof(struct drm_i915_gem_phys_object
), DRM_MEM_DRIVER
);
3435 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3437 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3438 struct drm_i915_gem_phys_object
*phys_obj
;
3440 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3443 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3444 if (phys_obj
->cur_obj
) {
3445 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3449 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3451 drm_pci_free(dev
, phys_obj
->handle
);
3453 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3456 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3460 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3461 i915_gem_free_phys_object(dev
, i
);
3464 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3465 struct drm_gem_object
*obj
)
3467 struct drm_i915_gem_object
*obj_priv
;
3472 obj_priv
= obj
->driver_private
;
3473 if (!obj_priv
->phys_obj
)
3476 ret
= i915_gem_object_get_page_list(obj
);
3480 page_count
= obj
->size
/ PAGE_SIZE
;
3482 for (i
= 0; i
< page_count
; i
++) {
3483 char *dst
= kmap_atomic(obj_priv
->page_list
[i
], KM_USER0
);
3484 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3486 memcpy(dst
, src
, PAGE_SIZE
);
3487 kunmap_atomic(dst
, KM_USER0
);
3489 drm_clflush_pages(obj_priv
->page_list
, page_count
);
3490 drm_agp_chipset_flush(dev
);
3492 obj_priv
->phys_obj
->cur_obj
= NULL
;
3493 obj_priv
->phys_obj
= NULL
;
3497 i915_gem_attach_phys_object(struct drm_device
*dev
,
3498 struct drm_gem_object
*obj
, int id
)
3500 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3501 struct drm_i915_gem_object
*obj_priv
;
3506 if (id
> I915_MAX_PHYS_OBJECT
)
3509 obj_priv
= obj
->driver_private
;
3511 if (obj_priv
->phys_obj
) {
3512 if (obj_priv
->phys_obj
->id
== id
)
3514 i915_gem_detach_phys_object(dev
, obj
);
3518 /* create a new object */
3519 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3520 ret
= i915_gem_init_phys_object(dev
, id
,
3523 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
3528 /* bind to the object */
3529 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3530 obj_priv
->phys_obj
->cur_obj
= obj
;
3532 ret
= i915_gem_object_get_page_list(obj
);
3534 DRM_ERROR("failed to get page list\n");
3538 page_count
= obj
->size
/ PAGE_SIZE
;
3540 for (i
= 0; i
< page_count
; i
++) {
3541 char *src
= kmap_atomic(obj_priv
->page_list
[i
], KM_USER0
);
3542 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3544 memcpy(dst
, src
, PAGE_SIZE
);
3545 kunmap_atomic(src
, KM_USER0
);
3554 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
3555 struct drm_i915_gem_pwrite
*args
,
3556 struct drm_file
*file_priv
)
3558 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3561 char __user
*user_data
;
3563 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3564 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
3566 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr
, args
->size
);
3567 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
3571 drm_agp_chipset_flush(dev
);