2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
46 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
47 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
49 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
50 static int i915_gem_evict_something(struct drm_device
*dev
);
51 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
52 struct drm_i915_gem_pwrite
*args
,
53 struct drm_file
*file_priv
);
55 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
58 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
61 (start
& (PAGE_SIZE
- 1)) != 0 ||
62 (end
& (PAGE_SIZE
- 1)) != 0) {
66 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
69 dev
->gtt_total
= (uint32_t) (end
- start
);
75 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
76 struct drm_file
*file_priv
)
78 struct drm_i915_gem_init
*args
= data
;
81 mutex_lock(&dev
->struct_mutex
);
82 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
83 mutex_unlock(&dev
->struct_mutex
);
89 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
90 struct drm_file
*file_priv
)
92 struct drm_i915_gem_get_aperture
*args
= data
;
94 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
97 args
->aper_size
= dev
->gtt_total
;
98 args
->aper_available_size
= (args
->aper_size
-
99 atomic_read(&dev
->pin_memory
));
106 * Creates a new mm object and returns a handle to it.
109 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
110 struct drm_file
*file_priv
)
112 struct drm_i915_gem_create
*args
= data
;
113 struct drm_gem_object
*obj
;
116 args
->size
= roundup(args
->size
, PAGE_SIZE
);
118 /* Allocate the new object */
119 obj
= drm_gem_object_alloc(dev
, args
->size
);
123 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
124 mutex_lock(&dev
->struct_mutex
);
125 drm_gem_object_handle_unreference(obj
);
126 mutex_unlock(&dev
->struct_mutex
);
131 args
->handle
= handle
;
137 fast_shmem_read(struct page
**pages
,
138 loff_t page_base
, int page_offset
,
145 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
148 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
149 kunmap_atomic(vaddr
, KM_USER0
);
157 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
159 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
160 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
162 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
163 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
167 slow_shmem_copy(struct page
*dst_page
,
169 struct page
*src_page
,
173 char *dst_vaddr
, *src_vaddr
;
175 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
176 if (dst_vaddr
== NULL
)
179 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
180 if (src_vaddr
== NULL
) {
181 kunmap_atomic(dst_vaddr
, KM_USER0
);
185 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
187 kunmap_atomic(src_vaddr
, KM_USER1
);
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
194 slow_shmem_bit17_copy(struct page
*gpu_page
,
196 struct page
*cpu_page
,
201 char *gpu_vaddr
, *cpu_vaddr
;
203 /* Use the unswizzled path if this page isn't affected. */
204 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
206 return slow_shmem_copy(cpu_page
, cpu_offset
,
207 gpu_page
, gpu_offset
, length
);
209 return slow_shmem_copy(gpu_page
, gpu_offset
,
210 cpu_page
, cpu_offset
, length
);
213 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
214 if (gpu_vaddr
== NULL
)
217 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
218 if (cpu_vaddr
== NULL
) {
219 kunmap_atomic(gpu_vaddr
, KM_USER0
);
223 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
224 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
228 int this_length
= min(cacheline_end
- gpu_offset
, length
);
229 int swizzled_gpu_offset
= gpu_offset
^ 64;
232 memcpy(cpu_vaddr
+ cpu_offset
,
233 gpu_vaddr
+ swizzled_gpu_offset
,
236 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
237 cpu_vaddr
+ cpu_offset
,
240 cpu_offset
+= this_length
;
241 gpu_offset
+= this_length
;
242 length
-= this_length
;
245 kunmap_atomic(cpu_vaddr
, KM_USER1
);
246 kunmap_atomic(gpu_vaddr
, KM_USER0
);
252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
257 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
258 struct drm_i915_gem_pread
*args
,
259 struct drm_file
*file_priv
)
261 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
263 loff_t offset
, page_base
;
264 char __user
*user_data
;
265 int page_offset
, page_length
;
268 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
271 mutex_lock(&dev
->struct_mutex
);
273 ret
= i915_gem_object_get_pages(obj
);
277 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
282 obj_priv
= obj
->driver_private
;
283 offset
= args
->offset
;
286 /* Operation in this page
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
292 page_base
= (offset
& ~(PAGE_SIZE
-1));
293 page_offset
= offset
& (PAGE_SIZE
-1);
294 page_length
= remain
;
295 if ((page_offset
+ remain
) > PAGE_SIZE
)
296 page_length
= PAGE_SIZE
- page_offset
;
298 ret
= fast_shmem_read(obj_priv
->pages
,
299 page_base
, page_offset
,
300 user_data
, page_length
);
304 remain
-= page_length
;
305 user_data
+= page_length
;
306 offset
+= page_length
;
310 i915_gem_object_put_pages(obj
);
312 mutex_unlock(&dev
->struct_mutex
);
318 * This is the fallback shmem pread path, which allocates temporary storage
319 * in kernel space to copy_to_user into outside of the struct_mutex, so we
320 * can copy out of the object's backing pages while holding the struct mutex
321 * and not take page faults.
324 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
325 struct drm_i915_gem_pread
*args
,
326 struct drm_file
*file_priv
)
328 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
329 struct mm_struct
*mm
= current
->mm
;
330 struct page
**user_pages
;
332 loff_t offset
, pinned_pages
, i
;
333 loff_t first_data_page
, last_data_page
, num_pages
;
334 int shmem_page_index
, shmem_page_offset
;
335 int data_page_index
, data_page_offset
;
338 uint64_t data_ptr
= args
->data_ptr
;
339 int do_bit17_swizzling
;
343 /* Pin the user pages containing the data. We can't fault while
344 * holding the struct mutex, yet we want to hold it while
345 * dereferencing the user data.
347 first_data_page
= data_ptr
/ PAGE_SIZE
;
348 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
349 num_pages
= last_data_page
- first_data_page
+ 1;
351 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
352 if (user_pages
== NULL
)
355 down_read(&mm
->mmap_sem
);
356 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
357 num_pages
, 1, 0, user_pages
, NULL
);
358 up_read(&mm
->mmap_sem
);
359 if (pinned_pages
< num_pages
) {
361 goto fail_put_user_pages
;
364 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
366 mutex_lock(&dev
->struct_mutex
);
368 ret
= i915_gem_object_get_pages(obj
);
372 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
377 obj_priv
= obj
->driver_private
;
378 offset
= args
->offset
;
381 /* Operation in this page
383 * shmem_page_index = page number within shmem file
384 * shmem_page_offset = offset within page in shmem file
385 * data_page_index = page number in get_user_pages return
386 * data_page_offset = offset with data_page_index page.
387 * page_length = bytes to copy for this page
389 shmem_page_index
= offset
/ PAGE_SIZE
;
390 shmem_page_offset
= offset
& ~PAGE_MASK
;
391 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
392 data_page_offset
= data_ptr
& ~PAGE_MASK
;
394 page_length
= remain
;
395 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
396 page_length
= PAGE_SIZE
- shmem_page_offset
;
397 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
398 page_length
= PAGE_SIZE
- data_page_offset
;
400 if (do_bit17_swizzling
) {
401 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
403 user_pages
[data_page_index
],
408 ret
= slow_shmem_copy(user_pages
[data_page_index
],
410 obj_priv
->pages
[shmem_page_index
],
417 remain
-= page_length
;
418 data_ptr
+= page_length
;
419 offset
+= page_length
;
423 i915_gem_object_put_pages(obj
);
425 mutex_unlock(&dev
->struct_mutex
);
427 for (i
= 0; i
< pinned_pages
; i
++) {
428 SetPageDirty(user_pages
[i
]);
429 page_cache_release(user_pages
[i
]);
431 drm_free_large(user_pages
);
437 * Reads data from the object referenced by handle.
439 * On error, the contents of *data are undefined.
442 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
443 struct drm_file
*file_priv
)
445 struct drm_i915_gem_pread
*args
= data
;
446 struct drm_gem_object
*obj
;
447 struct drm_i915_gem_object
*obj_priv
;
450 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
453 obj_priv
= obj
->driver_private
;
455 /* Bounds check source.
457 * XXX: This could use review for overflow issues...
459 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
460 args
->offset
+ args
->size
> obj
->size
) {
461 drm_gem_object_unreference(obj
);
465 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
466 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
468 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
470 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
474 drm_gem_object_unreference(obj
);
479 /* This is the fast write path which cannot handle
480 * page faults in the source data
484 fast_user_write(struct io_mapping
*mapping
,
485 loff_t page_base
, int page_offset
,
486 char __user
*user_data
,
490 unsigned long unwritten
;
492 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
493 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
495 io_mapping_unmap_atomic(vaddr_atomic
);
501 /* Here's the write path which can sleep for
506 slow_kernel_write(struct io_mapping
*mapping
,
507 loff_t gtt_base
, int gtt_offset
,
508 struct page
*user_page
, int user_offset
,
511 char *src_vaddr
, *dst_vaddr
;
512 unsigned long unwritten
;
514 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
515 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
516 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
517 src_vaddr
+ user_offset
,
519 kunmap_atomic(src_vaddr
, KM_USER1
);
520 io_mapping_unmap_atomic(dst_vaddr
);
527 fast_shmem_write(struct page
**pages
,
528 loff_t page_base
, int page_offset
,
533 unsigned long unwritten
;
535 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
538 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
539 kunmap_atomic(vaddr
, KM_USER0
);
547 * This is the fast pwrite path, where we copy the data directly from the
548 * user into the GTT, uncached.
551 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
552 struct drm_i915_gem_pwrite
*args
,
553 struct drm_file
*file_priv
)
555 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
556 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
558 loff_t offset
, page_base
;
559 char __user
*user_data
;
560 int page_offset
, page_length
;
563 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
565 if (!access_ok(VERIFY_READ
, user_data
, remain
))
569 mutex_lock(&dev
->struct_mutex
);
570 ret
= i915_gem_object_pin(obj
, 0);
572 mutex_unlock(&dev
->struct_mutex
);
575 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
579 obj_priv
= obj
->driver_private
;
580 offset
= obj_priv
->gtt_offset
+ args
->offset
;
583 /* Operation in this page
585 * page_base = page offset within aperture
586 * page_offset = offset within page
587 * page_length = bytes to copy for this page
589 page_base
= (offset
& ~(PAGE_SIZE
-1));
590 page_offset
= offset
& (PAGE_SIZE
-1);
591 page_length
= remain
;
592 if ((page_offset
+ remain
) > PAGE_SIZE
)
593 page_length
= PAGE_SIZE
- page_offset
;
595 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
596 page_offset
, user_data
, page_length
);
598 /* If we get a fault while copying data, then (presumably) our
599 * source page isn't available. Return the error and we'll
600 * retry in the slow path.
605 remain
-= page_length
;
606 user_data
+= page_length
;
607 offset
+= page_length
;
611 i915_gem_object_unpin(obj
);
612 mutex_unlock(&dev
->struct_mutex
);
618 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
619 * the memory and maps it using kmap_atomic for copying.
621 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
622 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
625 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
626 struct drm_i915_gem_pwrite
*args
,
627 struct drm_file
*file_priv
)
629 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
630 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
632 loff_t gtt_page_base
, offset
;
633 loff_t first_data_page
, last_data_page
, num_pages
;
634 loff_t pinned_pages
, i
;
635 struct page
**user_pages
;
636 struct mm_struct
*mm
= current
->mm
;
637 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
639 uint64_t data_ptr
= args
->data_ptr
;
643 /* Pin the user pages containing the data. We can't fault while
644 * holding the struct mutex, and all of the pwrite implementations
645 * want to hold it while dereferencing the user data.
647 first_data_page
= data_ptr
/ PAGE_SIZE
;
648 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
649 num_pages
= last_data_page
- first_data_page
+ 1;
651 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
652 if (user_pages
== NULL
)
655 down_read(&mm
->mmap_sem
);
656 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
657 num_pages
, 0, 0, user_pages
, NULL
);
658 up_read(&mm
->mmap_sem
);
659 if (pinned_pages
< num_pages
) {
661 goto out_unpin_pages
;
664 mutex_lock(&dev
->struct_mutex
);
665 ret
= i915_gem_object_pin(obj
, 0);
669 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
671 goto out_unpin_object
;
673 obj_priv
= obj
->driver_private
;
674 offset
= obj_priv
->gtt_offset
+ args
->offset
;
677 /* Operation in this page
679 * gtt_page_base = page offset within aperture
680 * gtt_page_offset = offset within page in aperture
681 * data_page_index = page number in get_user_pages return
682 * data_page_offset = offset with data_page_index page.
683 * page_length = bytes to copy for this page
685 gtt_page_base
= offset
& PAGE_MASK
;
686 gtt_page_offset
= offset
& ~PAGE_MASK
;
687 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
688 data_page_offset
= data_ptr
& ~PAGE_MASK
;
690 page_length
= remain
;
691 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
692 page_length
= PAGE_SIZE
- gtt_page_offset
;
693 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
694 page_length
= PAGE_SIZE
- data_page_offset
;
696 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
697 gtt_page_base
, gtt_page_offset
,
698 user_pages
[data_page_index
],
702 /* If we get a fault while copying data, then (presumably) our
703 * source page isn't available. Return the error and we'll
704 * retry in the slow path.
707 goto out_unpin_object
;
709 remain
-= page_length
;
710 offset
+= page_length
;
711 data_ptr
+= page_length
;
715 i915_gem_object_unpin(obj
);
717 mutex_unlock(&dev
->struct_mutex
);
719 for (i
= 0; i
< pinned_pages
; i
++)
720 page_cache_release(user_pages
[i
]);
721 drm_free_large(user_pages
);
727 * This is the fast shmem pwrite path, which attempts to directly
728 * copy_from_user into the kmapped pages backing the object.
731 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
732 struct drm_i915_gem_pwrite
*args
,
733 struct drm_file
*file_priv
)
735 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
737 loff_t offset
, page_base
;
738 char __user
*user_data
;
739 int page_offset
, page_length
;
742 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
745 mutex_lock(&dev
->struct_mutex
);
747 ret
= i915_gem_object_get_pages(obj
);
751 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
755 obj_priv
= obj
->driver_private
;
756 offset
= args
->offset
;
760 /* Operation in this page
762 * page_base = page offset within aperture
763 * page_offset = offset within page
764 * page_length = bytes to copy for this page
766 page_base
= (offset
& ~(PAGE_SIZE
-1));
767 page_offset
= offset
& (PAGE_SIZE
-1);
768 page_length
= remain
;
769 if ((page_offset
+ remain
) > PAGE_SIZE
)
770 page_length
= PAGE_SIZE
- page_offset
;
772 ret
= fast_shmem_write(obj_priv
->pages
,
773 page_base
, page_offset
,
774 user_data
, page_length
);
778 remain
-= page_length
;
779 user_data
+= page_length
;
780 offset
+= page_length
;
784 i915_gem_object_put_pages(obj
);
786 mutex_unlock(&dev
->struct_mutex
);
792 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
793 * the memory and maps it using kmap_atomic for copying.
795 * This avoids taking mmap_sem for faulting on the user's address while the
796 * struct_mutex is held.
799 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
800 struct drm_i915_gem_pwrite
*args
,
801 struct drm_file
*file_priv
)
803 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
804 struct mm_struct
*mm
= current
->mm
;
805 struct page
**user_pages
;
807 loff_t offset
, pinned_pages
, i
;
808 loff_t first_data_page
, last_data_page
, num_pages
;
809 int shmem_page_index
, shmem_page_offset
;
810 int data_page_index
, data_page_offset
;
813 uint64_t data_ptr
= args
->data_ptr
;
814 int do_bit17_swizzling
;
818 /* Pin the user pages containing the data. We can't fault while
819 * holding the struct mutex, and all of the pwrite implementations
820 * want to hold it while dereferencing the user data.
822 first_data_page
= data_ptr
/ PAGE_SIZE
;
823 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
824 num_pages
= last_data_page
- first_data_page
+ 1;
826 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
827 if (user_pages
== NULL
)
830 down_read(&mm
->mmap_sem
);
831 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
832 num_pages
, 0, 0, user_pages
, NULL
);
833 up_read(&mm
->mmap_sem
);
834 if (pinned_pages
< num_pages
) {
836 goto fail_put_user_pages
;
839 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
841 mutex_lock(&dev
->struct_mutex
);
843 ret
= i915_gem_object_get_pages(obj
);
847 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
851 obj_priv
= obj
->driver_private
;
852 offset
= args
->offset
;
856 /* Operation in this page
858 * shmem_page_index = page number within shmem file
859 * shmem_page_offset = offset within page in shmem file
860 * data_page_index = page number in get_user_pages return
861 * data_page_offset = offset with data_page_index page.
862 * page_length = bytes to copy for this page
864 shmem_page_index
= offset
/ PAGE_SIZE
;
865 shmem_page_offset
= offset
& ~PAGE_MASK
;
866 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
867 data_page_offset
= data_ptr
& ~PAGE_MASK
;
869 page_length
= remain
;
870 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
871 page_length
= PAGE_SIZE
- shmem_page_offset
;
872 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
873 page_length
= PAGE_SIZE
- data_page_offset
;
875 if (do_bit17_swizzling
) {
876 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
878 user_pages
[data_page_index
],
883 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
885 user_pages
[data_page_index
],
892 remain
-= page_length
;
893 data_ptr
+= page_length
;
894 offset
+= page_length
;
898 i915_gem_object_put_pages(obj
);
900 mutex_unlock(&dev
->struct_mutex
);
902 for (i
= 0; i
< pinned_pages
; i
++)
903 page_cache_release(user_pages
[i
]);
904 drm_free_large(user_pages
);
910 * Writes data to the object referenced by handle.
912 * On error, the contents of the buffer that were to be modified are undefined.
915 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
916 struct drm_file
*file_priv
)
918 struct drm_i915_gem_pwrite
*args
= data
;
919 struct drm_gem_object
*obj
;
920 struct drm_i915_gem_object
*obj_priv
;
923 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
926 obj_priv
= obj
->driver_private
;
928 /* Bounds check destination.
930 * XXX: This could use review for overflow issues...
932 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
933 args
->offset
+ args
->size
> obj
->size
) {
934 drm_gem_object_unreference(obj
);
938 /* We can only do the GTT pwrite on untiled buffers, as otherwise
939 * it would end up going through the fenced access, and we'll get
940 * different detiling behavior between reading and writing.
941 * pread/pwrite currently are reading and writing from the CPU
942 * perspective, requiring manual detiling by the client.
944 if (obj_priv
->phys_obj
)
945 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
946 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
947 dev
->gtt_total
!= 0) {
948 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
949 if (ret
== -EFAULT
) {
950 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
953 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
954 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
956 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
957 if (ret
== -EFAULT
) {
958 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
965 DRM_INFO("pwrite failed %d\n", ret
);
968 drm_gem_object_unreference(obj
);
974 * Called when user space prepares to use an object with the CPU, either
975 * through the mmap ioctl's mapping or a GTT mapping.
978 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
979 struct drm_file
*file_priv
)
981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
982 struct drm_i915_gem_set_domain
*args
= data
;
983 struct drm_gem_object
*obj
;
984 uint32_t read_domains
= args
->read_domains
;
985 uint32_t write_domain
= args
->write_domain
;
988 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
991 /* Only handle setting domains to types used by the CPU. */
992 if (write_domain
& I915_GEM_GPU_DOMAINS
)
995 if (read_domains
& I915_GEM_GPU_DOMAINS
)
998 /* Having something in the write domain implies it's in the read
999 * domain, and only that read domain. Enforce that in the request.
1001 if (write_domain
!= 0 && read_domains
!= write_domain
)
1004 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1008 mutex_lock(&dev
->struct_mutex
);
1010 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1011 obj
, obj
->size
, read_domains
, write_domain
);
1013 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1014 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1016 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1018 /* Update the LRU on the fence for the CPU access that's
1021 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1022 list_move_tail(&obj_priv
->fence_list
,
1023 &dev_priv
->mm
.fence_list
);
1026 /* Silently promote "you're not bound, there was nothing to do"
1027 * to success, since the client was just asking us to
1028 * make sure everything was done.
1033 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1036 drm_gem_object_unreference(obj
);
1037 mutex_unlock(&dev
->struct_mutex
);
1042 * Called when user space has done writes to this buffer
1045 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file_priv
)
1048 struct drm_i915_gem_sw_finish
*args
= data
;
1049 struct drm_gem_object
*obj
;
1050 struct drm_i915_gem_object
*obj_priv
;
1053 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1056 mutex_lock(&dev
->struct_mutex
);
1057 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1059 mutex_unlock(&dev
->struct_mutex
);
1064 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1065 __func__
, args
->handle
, obj
, obj
->size
);
1067 obj_priv
= obj
->driver_private
;
1069 /* Pinned buffers may be scanout, so flush the cache */
1070 if (obj_priv
->pin_count
)
1071 i915_gem_object_flush_cpu_write_domain(obj
);
1073 drm_gem_object_unreference(obj
);
1074 mutex_unlock(&dev
->struct_mutex
);
1079 * Maps the contents of an object, returning the address it is mapped
1082 * While the mapping holds a reference on the contents of the object, it doesn't
1083 * imply a ref on the object itself.
1086 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1087 struct drm_file
*file_priv
)
1089 struct drm_i915_gem_mmap
*args
= data
;
1090 struct drm_gem_object
*obj
;
1094 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1097 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1101 offset
= args
->offset
;
1103 down_write(¤t
->mm
->mmap_sem
);
1104 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1105 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1107 up_write(¤t
->mm
->mmap_sem
);
1108 mutex_lock(&dev
->struct_mutex
);
1109 drm_gem_object_unreference(obj
);
1110 mutex_unlock(&dev
->struct_mutex
);
1111 if (IS_ERR((void *)addr
))
1114 args
->addr_ptr
= (uint64_t) addr
;
1120 * i915_gem_fault - fault a page into the GTT
1121 * vma: VMA in question
1124 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1125 * from userspace. The fault handler takes care of binding the object to
1126 * the GTT (if needed), allocating and programming a fence register (again,
1127 * only if needed based on whether the old reg is still valid or the object
1128 * is tiled) and inserting a new PTE into the faulting process.
1130 * Note that the faulting process may involve evicting existing objects
1131 * from the GTT and/or fence registers to make room. So performance may
1132 * suffer if the GTT working set is large or there are few fence registers
1135 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1137 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1138 struct drm_device
*dev
= obj
->dev
;
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1140 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1141 pgoff_t page_offset
;
1144 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1146 /* We don't use vmf->pgoff since that has the fake offset */
1147 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1150 /* Now bind it into the GTT if needed */
1151 mutex_lock(&dev
->struct_mutex
);
1152 if (!obj_priv
->gtt_space
) {
1153 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
1155 mutex_unlock(&dev
->struct_mutex
);
1156 return VM_FAULT_SIGBUS
;
1159 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1161 mutex_unlock(&dev
->struct_mutex
);
1162 return VM_FAULT_SIGBUS
;
1165 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1168 /* Need a new fence register? */
1169 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1170 ret
= i915_gem_object_get_fence_reg(obj
);
1172 mutex_unlock(&dev
->struct_mutex
);
1173 return VM_FAULT_SIGBUS
;
1177 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1180 /* Finally, remap it using the new GTT offset */
1181 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1183 mutex_unlock(&dev
->struct_mutex
);
1188 return VM_FAULT_OOM
;
1191 return VM_FAULT_SIGBUS
;
1193 return VM_FAULT_NOPAGE
;
1198 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1199 * @obj: obj in question
1201 * GEM memory mapping works by handing back to userspace a fake mmap offset
1202 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1203 * up the object based on the offset and sets up the various memory mapping
1206 * This routine allocates and attaches a fake offset for @obj.
1209 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1211 struct drm_device
*dev
= obj
->dev
;
1212 struct drm_gem_mm
*mm
= dev
->mm_private
;
1213 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1214 struct drm_map_list
*list
;
1215 struct drm_local_map
*map
;
1218 /* Set the object up for mmap'ing */
1219 list
= &obj
->map_list
;
1220 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1225 map
->type
= _DRM_GEM
;
1226 map
->size
= obj
->size
;
1229 /* Get a DRM GEM mmap offset allocated... */
1230 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1231 obj
->size
/ PAGE_SIZE
, 0, 0);
1232 if (!list
->file_offset_node
) {
1233 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1238 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1239 obj
->size
/ PAGE_SIZE
, 0);
1240 if (!list
->file_offset_node
) {
1245 list
->hash
.key
= list
->file_offset_node
->start
;
1246 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1247 DRM_ERROR("failed to add to map hash\n");
1251 /* By now we should be all set, any drm_mmap request on the offset
1252 * below will get to our mmap & fault handler */
1253 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1258 drm_mm_put_block(list
->file_offset_node
);
1266 * i915_gem_release_mmap - remove physical page mappings
1267 * @obj: obj in question
1269 * Preserve the reservation of the mmaping with the DRM core code, but
1270 * relinquish ownership of the pages back to the system.
1272 * It is vital that we remove the page mapping if we have mapped a tiled
1273 * object through the GTT and then lose the fence register due to
1274 * resource pressure. Similarly if the object has been moved out of the
1275 * aperture, than pages mapped into userspace must be revoked. Removing the
1276 * mapping will then trigger a page fault on the next user access, allowing
1277 * fixup by i915_gem_fault().
1280 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1282 struct drm_device
*dev
= obj
->dev
;
1283 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1285 if (dev
->dev_mapping
)
1286 unmap_mapping_range(dev
->dev_mapping
,
1287 obj_priv
->mmap_offset
, obj
->size
, 1);
1291 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1293 struct drm_device
*dev
= obj
->dev
;
1294 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1295 struct drm_gem_mm
*mm
= dev
->mm_private
;
1296 struct drm_map_list
*list
;
1298 list
= &obj
->map_list
;
1299 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1301 if (list
->file_offset_node
) {
1302 drm_mm_put_block(list
->file_offset_node
);
1303 list
->file_offset_node
= NULL
;
1311 obj_priv
->mmap_offset
= 0;
1315 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1316 * @obj: object to check
1318 * Return the required GTT alignment for an object, taking into account
1319 * potential fence register mapping if needed.
1322 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1324 struct drm_device
*dev
= obj
->dev
;
1325 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1329 * Minimum alignment is 4k (GTT page size), but might be greater
1330 * if a fence register is needed for the object.
1332 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1336 * Previous chips need to be aligned to the size of the smallest
1337 * fence register that can contain the object.
1344 for (i
= start
; i
< obj
->size
; i
<<= 1)
1351 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1353 * @data: GTT mapping ioctl data
1354 * @file_priv: GEM object info
1356 * Simply returns the fake offset to userspace so it can mmap it.
1357 * The mmap call will end up in drm_gem_mmap(), which will set things
1358 * up so we can get faults in the handler above.
1360 * The fault handler will take care of binding the object into the GTT
1361 * (since it may have been evicted to make room for something), allocating
1362 * a fence register, and mapping the appropriate aperture address into
1366 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1367 struct drm_file
*file_priv
)
1369 struct drm_i915_gem_mmap_gtt
*args
= data
;
1370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1371 struct drm_gem_object
*obj
;
1372 struct drm_i915_gem_object
*obj_priv
;
1375 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1378 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1382 mutex_lock(&dev
->struct_mutex
);
1384 obj_priv
= obj
->driver_private
;
1386 if (!obj_priv
->mmap_offset
) {
1387 ret
= i915_gem_create_mmap_offset(obj
);
1389 drm_gem_object_unreference(obj
);
1390 mutex_unlock(&dev
->struct_mutex
);
1395 args
->offset
= obj_priv
->mmap_offset
;
1397 obj_priv
->gtt_alignment
= i915_gem_get_gtt_alignment(obj
);
1399 /* Make sure the alignment is correct for fence regs etc */
1400 if (obj_priv
->agp_mem
&&
1401 (obj_priv
->gtt_offset
& (obj_priv
->gtt_alignment
- 1))) {
1402 drm_gem_object_unreference(obj
);
1403 mutex_unlock(&dev
->struct_mutex
);
1408 * Pull it into the GTT so that we have a page list (makes the
1409 * initial fault faster and any subsequent flushing possible).
1411 if (!obj_priv
->agp_mem
) {
1412 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
1414 drm_gem_object_unreference(obj
);
1415 mutex_unlock(&dev
->struct_mutex
);
1418 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1421 drm_gem_object_unreference(obj
);
1422 mutex_unlock(&dev
->struct_mutex
);
1428 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1430 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1431 int page_count
= obj
->size
/ PAGE_SIZE
;
1434 BUG_ON(obj_priv
->pages_refcount
== 0);
1436 if (--obj_priv
->pages_refcount
!= 0)
1439 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1440 i915_gem_object_save_bit_17_swizzle(obj
);
1442 for (i
= 0; i
< page_count
; i
++)
1443 if (obj_priv
->pages
[i
] != NULL
) {
1444 if (obj_priv
->dirty
)
1445 set_page_dirty(obj_priv
->pages
[i
]);
1446 mark_page_accessed(obj_priv
->pages
[i
]);
1447 page_cache_release(obj_priv
->pages
[i
]);
1449 obj_priv
->dirty
= 0;
1451 drm_free_large(obj_priv
->pages
);
1452 obj_priv
->pages
= NULL
;
1456 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1458 struct drm_device
*dev
= obj
->dev
;
1459 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1460 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1462 /* Add a reference if we're newly entering the active list. */
1463 if (!obj_priv
->active
) {
1464 drm_gem_object_reference(obj
);
1465 obj_priv
->active
= 1;
1467 /* Move from whatever list we were on to the tail of execution. */
1468 spin_lock(&dev_priv
->mm
.active_list_lock
);
1469 list_move_tail(&obj_priv
->list
,
1470 &dev_priv
->mm
.active_list
);
1471 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1472 obj_priv
->last_rendering_seqno
= seqno
;
1476 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1478 struct drm_device
*dev
= obj
->dev
;
1479 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1480 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1482 BUG_ON(!obj_priv
->active
);
1483 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1484 obj_priv
->last_rendering_seqno
= 0;
1488 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1490 struct drm_device
*dev
= obj
->dev
;
1491 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1492 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1494 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1495 if (obj_priv
->pin_count
!= 0)
1496 list_del_init(&obj_priv
->list
);
1498 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1500 obj_priv
->last_rendering_seqno
= 0;
1501 if (obj_priv
->active
) {
1502 obj_priv
->active
= 0;
1503 drm_gem_object_unreference(obj
);
1505 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1509 * Creates a new sequence number, emitting a write of it to the status page
1510 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1512 * Must be called with struct_lock held.
1514 * Returned sequence numbers are nonzero on success.
1517 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1518 uint32_t flush_domains
)
1520 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1521 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1522 struct drm_i915_gem_request
*request
;
1527 if (file_priv
!= NULL
)
1528 i915_file_priv
= file_priv
->driver_priv
;
1530 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1531 if (request
== NULL
)
1534 /* Grab the seqno we're going to make this request be, and bump the
1535 * next (skipping 0 so it can be the reserved no-seqno value).
1537 seqno
= dev_priv
->mm
.next_gem_seqno
;
1538 dev_priv
->mm
.next_gem_seqno
++;
1539 if (dev_priv
->mm
.next_gem_seqno
== 0)
1540 dev_priv
->mm
.next_gem_seqno
++;
1543 OUT_RING(MI_STORE_DWORD_INDEX
);
1544 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1547 OUT_RING(MI_USER_INTERRUPT
);
1550 DRM_DEBUG("%d\n", seqno
);
1552 request
->seqno
= seqno
;
1553 request
->emitted_jiffies
= jiffies
;
1554 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1555 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1556 if (i915_file_priv
) {
1557 list_add_tail(&request
->client_list
,
1558 &i915_file_priv
->mm
.request_list
);
1560 INIT_LIST_HEAD(&request
->client_list
);
1563 /* Associate any objects on the flushing list matching the write
1564 * domain we're flushing with our flush.
1566 if (flush_domains
!= 0) {
1567 struct drm_i915_gem_object
*obj_priv
, *next
;
1569 list_for_each_entry_safe(obj_priv
, next
,
1570 &dev_priv
->mm
.flushing_list
, list
) {
1571 struct drm_gem_object
*obj
= obj_priv
->obj
;
1573 if ((obj
->write_domain
& flush_domains
) ==
1574 obj
->write_domain
) {
1575 obj
->write_domain
= 0;
1576 i915_gem_object_move_to_active(obj
, seqno
);
1582 if (was_empty
&& !dev_priv
->mm
.suspended
)
1583 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1588 * Command execution barrier
1590 * Ensures that all commands in the ring are finished
1591 * before signalling the CPU
1594 i915_retire_commands(struct drm_device
*dev
)
1596 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1597 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1598 uint32_t flush_domains
= 0;
1601 /* The sampler always gets flushed on i965 (sigh) */
1603 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1606 OUT_RING(0); /* noop */
1608 return flush_domains
;
1612 * Moves buffers associated only with the given active seqno from the active
1613 * to inactive list, potentially freeing them.
1616 i915_gem_retire_request(struct drm_device
*dev
,
1617 struct drm_i915_gem_request
*request
)
1619 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1621 /* Move any buffers on the active list that are no longer referenced
1622 * by the ringbuffer to the flushing/inactive lists as appropriate.
1624 spin_lock(&dev_priv
->mm
.active_list_lock
);
1625 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1626 struct drm_gem_object
*obj
;
1627 struct drm_i915_gem_object
*obj_priv
;
1629 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1630 struct drm_i915_gem_object
,
1632 obj
= obj_priv
->obj
;
1634 /* If the seqno being retired doesn't match the oldest in the
1635 * list, then the oldest in the list must still be newer than
1638 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1642 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1643 __func__
, request
->seqno
, obj
);
1646 if (obj
->write_domain
!= 0)
1647 i915_gem_object_move_to_flushing(obj
);
1649 /* Take a reference on the object so it won't be
1650 * freed while the spinlock is held. The list
1651 * protection for this spinlock is safe when breaking
1652 * the lock like this since the next thing we do
1653 * is just get the head of the list again.
1655 drm_gem_object_reference(obj
);
1656 i915_gem_object_move_to_inactive(obj
);
1657 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1658 drm_gem_object_unreference(obj
);
1659 spin_lock(&dev_priv
->mm
.active_list_lock
);
1663 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1667 * Returns true if seq1 is later than seq2.
1670 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1672 return (int32_t)(seq1
- seq2
) >= 0;
1676 i915_get_gem_seqno(struct drm_device
*dev
)
1678 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1680 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1684 * This function clears the request list as sequence numbers are passed.
1687 i915_gem_retire_requests(struct drm_device
*dev
)
1689 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1692 if (!dev_priv
->hw_status_page
)
1695 seqno
= i915_get_gem_seqno(dev
);
1697 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1698 struct drm_i915_gem_request
*request
;
1699 uint32_t retiring_seqno
;
1701 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1702 struct drm_i915_gem_request
,
1704 retiring_seqno
= request
->seqno
;
1706 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1707 dev_priv
->mm
.wedged
) {
1708 i915_gem_retire_request(dev
, request
);
1710 list_del(&request
->list
);
1711 list_del(&request
->client_list
);
1719 i915_gem_retire_work_handler(struct work_struct
*work
)
1721 drm_i915_private_t
*dev_priv
;
1722 struct drm_device
*dev
;
1724 dev_priv
= container_of(work
, drm_i915_private_t
,
1725 mm
.retire_work
.work
);
1726 dev
= dev_priv
->dev
;
1728 mutex_lock(&dev
->struct_mutex
);
1729 i915_gem_retire_requests(dev
);
1730 if (!dev_priv
->mm
.suspended
&&
1731 !list_empty(&dev_priv
->mm
.request_list
))
1732 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1733 mutex_unlock(&dev
->struct_mutex
);
1737 * Waits for a sequence number to be signaled, and cleans up the
1738 * request and object lists appropriately for that event.
1741 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1749 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1751 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1753 ier
= I915_READ(IER
);
1755 DRM_ERROR("something (likely vbetool) disabled "
1756 "interrupts, re-enabling\n");
1757 i915_driver_irq_preinstall(dev
);
1758 i915_driver_irq_postinstall(dev
);
1761 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1762 i915_user_irq_get(dev
);
1763 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1764 i915_seqno_passed(i915_get_gem_seqno(dev
),
1766 dev_priv
->mm
.wedged
);
1767 i915_user_irq_put(dev
);
1768 dev_priv
->mm
.waiting_gem_seqno
= 0;
1770 if (dev_priv
->mm
.wedged
)
1773 if (ret
&& ret
!= -ERESTARTSYS
)
1774 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1775 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1777 /* Directly dispatch request retiring. While we have the work queue
1778 * to handle this, the waiter on a request often wants an associated
1779 * buffer to have made it to the inactive list, and we would need
1780 * a separate wait queue to handle that.
1783 i915_gem_retire_requests(dev
);
1789 i915_gem_flush(struct drm_device
*dev
,
1790 uint32_t invalidate_domains
,
1791 uint32_t flush_domains
)
1793 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1798 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1799 invalidate_domains
, flush_domains
);
1802 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1803 drm_agp_chipset_flush(dev
);
1805 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1807 * read/write caches:
1809 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1810 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1811 * also flushed at 2d versus 3d pipeline switches.
1815 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1816 * MI_READ_FLUSH is set, and is always flushed on 965.
1818 * I915_GEM_DOMAIN_COMMAND may not exist?
1820 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1821 * invalidated when MI_EXE_FLUSH is set.
1823 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1824 * invalidated with every MI_FLUSH.
1828 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1829 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1830 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1831 * are flushed at any MI_FLUSH.
1834 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1835 if ((invalidate_domains
|flush_domains
) &
1836 I915_GEM_DOMAIN_RENDER
)
1837 cmd
&= ~MI_NO_WRITE_FLUSH
;
1838 if (!IS_I965G(dev
)) {
1840 * On the 965, the sampler cache always gets flushed
1841 * and this bit is reserved.
1843 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1844 cmd
|= MI_READ_FLUSH
;
1846 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1847 cmd
|= MI_EXE_FLUSH
;
1850 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1854 OUT_RING(0); /* noop */
1860 * Ensures that all rendering to the object has completed and the object is
1861 * safe to unbind from the GTT or access from the CPU.
1864 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1866 struct drm_device
*dev
= obj
->dev
;
1867 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1870 /* This function only exists to support waiting for existing rendering,
1871 * not for emitting required flushes.
1873 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1875 /* If there is rendering queued on the buffer being evicted, wait for
1878 if (obj_priv
->active
) {
1880 DRM_INFO("%s: object %p wait for seqno %08x\n",
1881 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1883 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1892 * Unbinds an object from the GTT aperture.
1895 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1897 struct drm_device
*dev
= obj
->dev
;
1898 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1902 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1903 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1905 if (obj_priv
->gtt_space
== NULL
)
1908 if (obj_priv
->pin_count
!= 0) {
1909 DRM_ERROR("Attempting to unbind pinned buffer\n");
1913 /* Move the object to the CPU domain to ensure that
1914 * any possible CPU writes while it's not in the GTT
1915 * are flushed when we go to remap it. This will
1916 * also ensure that all pending GPU writes are finished
1919 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1921 if (ret
!= -ERESTARTSYS
)
1922 DRM_ERROR("set_domain failed: %d\n", ret
);
1926 if (obj_priv
->agp_mem
!= NULL
) {
1927 drm_unbind_agp(obj_priv
->agp_mem
);
1928 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1929 obj_priv
->agp_mem
= NULL
;
1932 BUG_ON(obj_priv
->active
);
1934 /* blow away mappings if mapped through GTT */
1935 i915_gem_release_mmap(obj
);
1937 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1938 i915_gem_clear_fence_reg(obj
);
1940 i915_gem_object_put_pages(obj
);
1942 if (obj_priv
->gtt_space
) {
1943 atomic_dec(&dev
->gtt_count
);
1944 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1946 drm_mm_put_block(obj_priv
->gtt_space
);
1947 obj_priv
->gtt_space
= NULL
;
1950 /* Remove ourselves from the LRU list if present. */
1951 if (!list_empty(&obj_priv
->list
))
1952 list_del_init(&obj_priv
->list
);
1958 i915_gem_evict_something(struct drm_device
*dev
)
1960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1961 struct drm_gem_object
*obj
;
1962 struct drm_i915_gem_object
*obj_priv
;
1966 /* If there's an inactive buffer available now, grab it
1969 if (!list_empty(&dev_priv
->mm
.inactive_list
)) {
1970 obj_priv
= list_first_entry(&dev_priv
->mm
.inactive_list
,
1971 struct drm_i915_gem_object
,
1973 obj
= obj_priv
->obj
;
1974 BUG_ON(obj_priv
->pin_count
!= 0);
1976 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
1978 BUG_ON(obj_priv
->active
);
1980 /* Wait on the rendering and unbind the buffer. */
1981 ret
= i915_gem_object_unbind(obj
);
1985 /* If we didn't get anything, but the ring is still processing
1986 * things, wait for one of those things to finish and hopefully
1987 * leave us a buffer to evict.
1989 if (!list_empty(&dev_priv
->mm
.request_list
)) {
1990 struct drm_i915_gem_request
*request
;
1992 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1993 struct drm_i915_gem_request
,
1996 ret
= i915_wait_request(dev
, request
->seqno
);
2000 /* if waiting caused an object to become inactive,
2001 * then loop around and wait for it. Otherwise, we
2002 * assume that waiting freed and unbound something,
2003 * so there should now be some space in the GTT
2005 if (!list_empty(&dev_priv
->mm
.inactive_list
))
2010 /* If we didn't have anything on the request list but there
2011 * are buffers awaiting a flush, emit one and try again.
2012 * When we wait on it, those buffers waiting for that flush
2013 * will get moved to inactive.
2015 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2016 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
2017 struct drm_i915_gem_object
,
2019 obj
= obj_priv
->obj
;
2024 i915_add_request(dev
, NULL
, obj
->write_domain
);
2030 DRM_ERROR("inactive empty %d request empty %d "
2031 "flushing empty %d\n",
2032 list_empty(&dev_priv
->mm
.inactive_list
),
2033 list_empty(&dev_priv
->mm
.request_list
),
2034 list_empty(&dev_priv
->mm
.flushing_list
));
2035 /* If we didn't do any of the above, there's nothing to be done
2036 * and we just can't fit it in.
2044 i915_gem_evict_everything(struct drm_device
*dev
)
2049 ret
= i915_gem_evict_something(dev
);
2059 i915_gem_object_get_pages(struct drm_gem_object
*obj
)
2061 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2063 struct address_space
*mapping
;
2064 struct inode
*inode
;
2068 if (obj_priv
->pages_refcount
++ != 0)
2071 /* Get the list of pages out of our struct file. They'll be pinned
2072 * at this point until we release them.
2074 page_count
= obj
->size
/ PAGE_SIZE
;
2075 BUG_ON(obj_priv
->pages
!= NULL
);
2076 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2077 if (obj_priv
->pages
== NULL
) {
2078 DRM_ERROR("Faled to allocate page list\n");
2079 obj_priv
->pages_refcount
--;
2083 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2084 mapping
= inode
->i_mapping
;
2085 for (i
= 0; i
< page_count
; i
++) {
2086 page
= read_mapping_page(mapping
, i
, NULL
);
2088 ret
= PTR_ERR(page
);
2089 DRM_ERROR("read_mapping_page failed: %d\n", ret
);
2090 i915_gem_object_put_pages(obj
);
2093 obj_priv
->pages
[i
] = page
;
2096 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2097 i915_gem_object_do_bit_17_swizzle(obj
);
2102 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2104 struct drm_gem_object
*obj
= reg
->obj
;
2105 struct drm_device
*dev
= obj
->dev
;
2106 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2107 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2108 int regnum
= obj_priv
->fence_reg
;
2111 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2113 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2114 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2115 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2116 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2117 val
|= I965_FENCE_REG_VALID
;
2119 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2122 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2124 struct drm_gem_object
*obj
= reg
->obj
;
2125 struct drm_device
*dev
= obj
->dev
;
2126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2127 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2128 int regnum
= obj_priv
->fence_reg
;
2130 uint32_t fence_reg
, val
;
2133 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2134 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2135 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2136 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2140 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2141 HAS_128_BYTE_Y_TILING(dev
))
2146 /* Note: pitch better be a power of two tile widths */
2147 pitch_val
= obj_priv
->stride
/ tile_width
;
2148 pitch_val
= ffs(pitch_val
) - 1;
2150 val
= obj_priv
->gtt_offset
;
2151 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2152 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2153 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2154 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2155 val
|= I830_FENCE_REG_VALID
;
2158 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2160 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2161 I915_WRITE(fence_reg
, val
);
2164 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2166 struct drm_gem_object
*obj
= reg
->obj
;
2167 struct drm_device
*dev
= obj
->dev
;
2168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2169 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2170 int regnum
= obj_priv
->fence_reg
;
2173 uint32_t fence_size_bits
;
2175 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2176 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2177 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2178 __func__
, obj_priv
->gtt_offset
);
2182 pitch_val
= obj_priv
->stride
/ 128;
2183 pitch_val
= ffs(pitch_val
) - 1;
2184 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2186 val
= obj_priv
->gtt_offset
;
2187 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2188 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2189 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2190 WARN_ON(fence_size_bits
& ~0x00000f00);
2191 val
|= fence_size_bits
;
2192 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2193 val
|= I830_FENCE_REG_VALID
;
2195 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2199 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2200 * @obj: object to map through a fence reg
2202 * When mapping objects through the GTT, userspace wants to be able to write
2203 * to them without having to worry about swizzling if the object is tiled.
2205 * This function walks the fence regs looking for a free one for @obj,
2206 * stealing one if it can't find any.
2208 * It then sets up the reg based on the object's properties: address, pitch
2209 * and tiling format.
2212 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2214 struct drm_device
*dev
= obj
->dev
;
2215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2217 struct drm_i915_fence_reg
*reg
= NULL
;
2218 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2221 /* Just update our place in the LRU if our fence is getting used. */
2222 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2223 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2227 switch (obj_priv
->tiling_mode
) {
2228 case I915_TILING_NONE
:
2229 WARN(1, "allocating a fence for non-tiled object?\n");
2232 if (!obj_priv
->stride
)
2234 WARN((obj_priv
->stride
& (512 - 1)),
2235 "object 0x%08x is X tiled but has non-512B pitch\n",
2236 obj_priv
->gtt_offset
);
2239 if (!obj_priv
->stride
)
2241 WARN((obj_priv
->stride
& (128 - 1)),
2242 "object 0x%08x is Y tiled but has non-128B pitch\n",
2243 obj_priv
->gtt_offset
);
2247 /* First try to find a free reg */
2249 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2250 reg
= &dev_priv
->fence_regs
[i
];
2254 old_obj_priv
= reg
->obj
->driver_private
;
2255 if (!old_obj_priv
->pin_count
)
2259 /* None available, try to steal one or wait for a user to finish */
2260 if (i
== dev_priv
->num_fence_regs
) {
2261 struct drm_gem_object
*old_obj
= NULL
;
2266 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2268 old_obj
= old_obj_priv
->obj
;
2270 reg
= &dev_priv
->fence_regs
[old_obj_priv
->fence_reg
];
2272 if (old_obj_priv
->pin_count
)
2275 /* Take a reference, as otherwise the wait_rendering
2276 * below may cause the object to get freed out from
2279 drm_gem_object_reference(old_obj
);
2281 /* i915 uses fences for GPU access to tiled buffers */
2282 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2285 /* This brings the object to the head of the LRU if it
2286 * had been written to. The only way this should
2287 * result in us waiting longer than the expected
2288 * optimal amount of time is if there was a
2289 * fence-using buffer later that was read-only.
2291 i915_gem_object_flush_gpu_write_domain(old_obj
);
2292 ret
= i915_gem_object_wait_rendering(old_obj
);
2299 * Zap this virtual mapping so we can set up a fence again
2300 * for this object next time we need it.
2302 i915_gem_release_mmap(reg
->obj
);
2303 i
= old_obj_priv
->fence_reg
;
2304 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2305 list_del_init(&old_obj_priv
->fence_list
);
2306 drm_gem_object_unreference(old_obj
);
2309 obj_priv
->fence_reg
= i
;
2310 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2315 i965_write_fence_reg(reg
);
2316 else if (IS_I9XX(dev
))
2317 i915_write_fence_reg(reg
);
2319 i830_write_fence_reg(reg
);
2325 * i915_gem_clear_fence_reg - clear out fence register info
2326 * @obj: object to clear
2328 * Zeroes out the fence register itself and clears out the associated
2329 * data structures in dev_priv and obj_priv.
2332 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2334 struct drm_device
*dev
= obj
->dev
;
2335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2336 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2339 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2343 if (obj_priv
->fence_reg
< 8)
2344 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2346 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2349 I915_WRITE(fence_reg
, 0);
2352 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2353 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2354 list_del_init(&obj_priv
->fence_list
);
2358 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2359 * to the buffer to finish, and then resets the fence register.
2360 * @obj: tiled object holding a fence register.
2362 * Zeroes out the fence register itself and clears out the associated
2363 * data structures in dev_priv and obj_priv.
2366 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2368 struct drm_device
*dev
= obj
->dev
;
2369 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2371 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2374 /* On the i915, GPU access to tiled buffers is via a fence,
2375 * therefore we must wait for any outstanding access to complete
2376 * before clearing the fence.
2378 if (!IS_I965G(dev
)) {
2381 i915_gem_object_flush_gpu_write_domain(obj
);
2382 i915_gem_object_flush_gtt_write_domain(obj
);
2383 ret
= i915_gem_object_wait_rendering(obj
);
2388 i915_gem_clear_fence_reg (obj
);
2394 * Finds free space in the GTT aperture and binds the object there.
2397 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2399 struct drm_device
*dev
= obj
->dev
;
2400 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2401 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2402 struct drm_mm_node
*free_space
;
2403 int page_count
, ret
;
2405 if (dev_priv
->mm
.suspended
)
2408 alignment
= i915_gem_get_gtt_alignment(obj
);
2409 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2410 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2415 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2416 obj
->size
, alignment
, 0);
2417 if (free_space
!= NULL
) {
2418 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2420 if (obj_priv
->gtt_space
!= NULL
) {
2421 obj_priv
->gtt_space
->private = obj
;
2422 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2425 if (obj_priv
->gtt_space
== NULL
) {
2428 /* If the gtt is empty and we're still having trouble
2429 * fitting our object in, we're out of memory.
2432 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2434 spin_lock(&dev_priv
->mm
.active_list_lock
);
2435 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2436 list_empty(&dev_priv
->mm
.flushing_list
) &&
2437 list_empty(&dev_priv
->mm
.active_list
));
2438 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2440 DRM_ERROR("GTT full, but LRU list empty\n");
2444 ret
= i915_gem_evict_something(dev
);
2446 if (ret
!= -ERESTARTSYS
)
2447 DRM_ERROR("Failed to evict a buffer %d\n", ret
);
2454 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2455 obj
->size
, obj_priv
->gtt_offset
);
2457 ret
= i915_gem_object_get_pages(obj
);
2459 drm_mm_put_block(obj_priv
->gtt_space
);
2460 obj_priv
->gtt_space
= NULL
;
2464 page_count
= obj
->size
/ PAGE_SIZE
;
2465 /* Create an AGP memory structure pointing at our pages, and bind it
2468 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2471 obj_priv
->gtt_offset
,
2472 obj_priv
->agp_type
);
2473 if (obj_priv
->agp_mem
== NULL
) {
2474 i915_gem_object_put_pages(obj
);
2475 drm_mm_put_block(obj_priv
->gtt_space
);
2476 obj_priv
->gtt_space
= NULL
;
2479 atomic_inc(&dev
->gtt_count
);
2480 atomic_add(obj
->size
, &dev
->gtt_memory
);
2482 /* Assert that the object is not currently in any GPU domain. As it
2483 * wasn't in the GTT, there shouldn't be any way it could have been in
2486 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2487 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2493 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2495 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2497 /* If we don't have a page list set up, then we're not pinned
2498 * to GPU, and we can ignore the cache flush because it'll happen
2499 * again at bind time.
2501 if (obj_priv
->pages
== NULL
)
2504 /* XXX: The 865 in particular appears to be weird in how it handles
2505 * cache flushing. We haven't figured it out, but the
2506 * clflush+agp_chipset_flush doesn't appear to successfully get the
2507 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2509 if (IS_I865G(obj
->dev
)) {
2514 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2517 /** Flushes any GPU write domain for the object if it's dirty. */
2519 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2521 struct drm_device
*dev
= obj
->dev
;
2524 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2527 /* Queue the GPU write cache flushing we need. */
2528 i915_gem_flush(dev
, 0, obj
->write_domain
);
2529 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2530 obj
->write_domain
= 0;
2531 i915_gem_object_move_to_active(obj
, seqno
);
2534 /** Flushes the GTT write domain for the object if it's dirty. */
2536 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2538 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2541 /* No actual flushing is required for the GTT write domain. Writes
2542 * to it immediately go to main memory as far as we know, so there's
2543 * no chipset flush. It also doesn't land in render cache.
2545 obj
->write_domain
= 0;
2548 /** Flushes the CPU write domain for the object if it's dirty. */
2550 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2552 struct drm_device
*dev
= obj
->dev
;
2554 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2557 i915_gem_clflush_object(obj
);
2558 drm_agp_chipset_flush(dev
);
2559 obj
->write_domain
= 0;
2563 * Moves a single object to the GTT read, and possibly write domain.
2565 * This function returns when the move is complete, including waiting on
2569 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2571 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2574 /* Not valid to be called on unbound objects. */
2575 if (obj_priv
->gtt_space
== NULL
)
2578 i915_gem_object_flush_gpu_write_domain(obj
);
2579 /* Wait on any GPU rendering and flushing to occur. */
2580 ret
= i915_gem_object_wait_rendering(obj
);
2584 /* If we're writing through the GTT domain, then CPU and GPU caches
2585 * will need to be invalidated at next use.
2588 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2590 i915_gem_object_flush_cpu_write_domain(obj
);
2592 /* It should now be out of any other write domains, and we can update
2593 * the domain values for our changes.
2595 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2596 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2598 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2599 obj_priv
->dirty
= 1;
2606 * Moves a single object to the CPU read, and possibly write domain.
2608 * This function returns when the move is complete, including waiting on
2612 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2616 i915_gem_object_flush_gpu_write_domain(obj
);
2617 /* Wait on any GPU rendering and flushing to occur. */
2618 ret
= i915_gem_object_wait_rendering(obj
);
2622 i915_gem_object_flush_gtt_write_domain(obj
);
2624 /* If we have a partially-valid cache of the object in the CPU,
2625 * finish invalidating it and free the per-page flags.
2627 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2629 /* Flush the CPU cache if it's still invalid. */
2630 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2631 i915_gem_clflush_object(obj
);
2633 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2636 /* It should now be out of any other write domains, and we can update
2637 * the domain values for our changes.
2639 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2641 /* If we're writing through the CPU, then the GPU read domains will
2642 * need to be invalidated at next use.
2645 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2646 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2653 * Set the next domain for the specified object. This
2654 * may not actually perform the necessary flushing/invaliding though,
2655 * as that may want to be batched with other set_domain operations
2657 * This is (we hope) the only really tricky part of gem. The goal
2658 * is fairly simple -- track which caches hold bits of the object
2659 * and make sure they remain coherent. A few concrete examples may
2660 * help to explain how it works. For shorthand, we use the notation
2661 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2662 * a pair of read and write domain masks.
2664 * Case 1: the batch buffer
2670 * 5. Unmapped from GTT
2673 * Let's take these a step at a time
2676 * Pages allocated from the kernel may still have
2677 * cache contents, so we set them to (CPU, CPU) always.
2678 * 2. Written by CPU (using pwrite)
2679 * The pwrite function calls set_domain (CPU, CPU) and
2680 * this function does nothing (as nothing changes)
2682 * This function asserts that the object is not
2683 * currently in any GPU-based read or write domains
2685 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2686 * As write_domain is zero, this function adds in the
2687 * current read domains (CPU+COMMAND, 0).
2688 * flush_domains is set to CPU.
2689 * invalidate_domains is set to COMMAND
2690 * clflush is run to get data out of the CPU caches
2691 * then i915_dev_set_domain calls i915_gem_flush to
2692 * emit an MI_FLUSH and drm_agp_chipset_flush
2693 * 5. Unmapped from GTT
2694 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2695 * flush_domains and invalidate_domains end up both zero
2696 * so no flushing/invalidating happens
2700 * Case 2: The shared render buffer
2704 * 3. Read/written by GPU
2705 * 4. set_domain to (CPU,CPU)
2706 * 5. Read/written by CPU
2707 * 6. Read/written by GPU
2710 * Same as last example, (CPU, CPU)
2712 * Nothing changes (assertions find that it is not in the GPU)
2713 * 3. Read/written by GPU
2714 * execbuffer calls set_domain (RENDER, RENDER)
2715 * flush_domains gets CPU
2716 * invalidate_domains gets GPU
2718 * MI_FLUSH and drm_agp_chipset_flush
2719 * 4. set_domain (CPU, CPU)
2720 * flush_domains gets GPU
2721 * invalidate_domains gets CPU
2722 * wait_rendering (obj) to make sure all drawing is complete.
2723 * This will include an MI_FLUSH to get the data from GPU
2725 * clflush (obj) to invalidate the CPU cache
2726 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2727 * 5. Read/written by CPU
2728 * cache lines are loaded and dirtied
2729 * 6. Read written by GPU
2730 * Same as last GPU access
2732 * Case 3: The constant buffer
2737 * 4. Updated (written) by CPU again
2746 * flush_domains = CPU
2747 * invalidate_domains = RENDER
2750 * drm_agp_chipset_flush
2751 * 4. Updated (written) by CPU again
2753 * flush_domains = 0 (no previous write domain)
2754 * invalidate_domains = 0 (no new read domains)
2757 * flush_domains = CPU
2758 * invalidate_domains = RENDER
2761 * drm_agp_chipset_flush
2764 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2766 struct drm_device
*dev
= obj
->dev
;
2767 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2768 uint32_t invalidate_domains
= 0;
2769 uint32_t flush_domains
= 0;
2771 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2772 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2775 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2777 obj
->read_domains
, obj
->pending_read_domains
,
2778 obj
->write_domain
, obj
->pending_write_domain
);
2781 * If the object isn't moving to a new write domain,
2782 * let the object stay in multiple read domains
2784 if (obj
->pending_write_domain
== 0)
2785 obj
->pending_read_domains
|= obj
->read_domains
;
2787 obj_priv
->dirty
= 1;
2790 * Flush the current write domain if
2791 * the new read domains don't match. Invalidate
2792 * any read domains which differ from the old
2795 if (obj
->write_domain
&&
2796 obj
->write_domain
!= obj
->pending_read_domains
) {
2797 flush_domains
|= obj
->write_domain
;
2798 invalidate_domains
|=
2799 obj
->pending_read_domains
& ~obj
->write_domain
;
2802 * Invalidate any read caches which may have
2803 * stale data. That is, any new read domains.
2805 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2806 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2808 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2809 __func__
, flush_domains
, invalidate_domains
);
2811 i915_gem_clflush_object(obj
);
2814 /* The actual obj->write_domain will be updated with
2815 * pending_write_domain after we emit the accumulated flush for all
2816 * of our domain changes in execbuffers (which clears objects'
2817 * write_domains). So if we have a current write domain that we
2818 * aren't changing, set pending_write_domain to that.
2820 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
2821 obj
->pending_write_domain
= obj
->write_domain
;
2822 obj
->read_domains
= obj
->pending_read_domains
;
2824 dev
->invalidate_domains
|= invalidate_domains
;
2825 dev
->flush_domains
|= flush_domains
;
2827 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2829 obj
->read_domains
, obj
->write_domain
,
2830 dev
->invalidate_domains
, dev
->flush_domains
);
2835 * Moves the object from a partially CPU read to a full one.
2837 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2838 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2841 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
2843 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2845 if (!obj_priv
->page_cpu_valid
)
2848 /* If we're partially in the CPU read domain, finish moving it in.
2850 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
2853 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
2854 if (obj_priv
->page_cpu_valid
[i
])
2856 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
2860 /* Free the page_cpu_valid mappings which are now stale, whether
2861 * or not we've got I915_GEM_DOMAIN_CPU.
2863 kfree(obj_priv
->page_cpu_valid
);
2864 obj_priv
->page_cpu_valid
= NULL
;
2868 * Set the CPU read domain on a range of the object.
2870 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2871 * not entirely valid. The page_cpu_valid member of the object flags which
2872 * pages have been flushed, and will be respected by
2873 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2874 * of the whole object.
2876 * This function returns when the move is complete, including waiting on
2880 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
2881 uint64_t offset
, uint64_t size
)
2883 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2886 if (offset
== 0 && size
== obj
->size
)
2887 return i915_gem_object_set_to_cpu_domain(obj
, 0);
2889 i915_gem_object_flush_gpu_write_domain(obj
);
2890 /* Wait on any GPU rendering and flushing to occur. */
2891 ret
= i915_gem_object_wait_rendering(obj
);
2894 i915_gem_object_flush_gtt_write_domain(obj
);
2896 /* If we're already fully in the CPU read domain, we're done. */
2897 if (obj_priv
->page_cpu_valid
== NULL
&&
2898 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
2901 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2902 * newly adding I915_GEM_DOMAIN_CPU
2904 if (obj_priv
->page_cpu_valid
== NULL
) {
2905 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
2907 if (obj_priv
->page_cpu_valid
== NULL
)
2909 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
2910 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
2912 /* Flush the cache on any pages that are still invalid from the CPU's
2915 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
2917 if (obj_priv
->page_cpu_valid
[i
])
2920 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
2922 obj_priv
->page_cpu_valid
[i
] = 1;
2925 /* It should now be out of any other write domains, and we can update
2926 * the domain values for our changes.
2928 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2930 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2936 * Pin an object to the GTT and evaluate the relocations landing in it.
2939 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
2940 struct drm_file
*file_priv
,
2941 struct drm_i915_gem_exec_object
*entry
,
2942 struct drm_i915_gem_relocation_entry
*relocs
)
2944 struct drm_device
*dev
= obj
->dev
;
2945 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2946 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2948 void __iomem
*reloc_page
;
2950 /* Choose the GTT offset for our buffer and put it there. */
2951 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
2955 entry
->offset
= obj_priv
->gtt_offset
;
2957 /* Apply the relocations, using the GTT aperture to avoid cache
2958 * flushing requirements.
2960 for (i
= 0; i
< entry
->relocation_count
; i
++) {
2961 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
2962 struct drm_gem_object
*target_obj
;
2963 struct drm_i915_gem_object
*target_obj_priv
;
2964 uint32_t reloc_val
, reloc_offset
;
2965 uint32_t __iomem
*reloc_entry
;
2967 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
2968 reloc
->target_handle
);
2969 if (target_obj
== NULL
) {
2970 i915_gem_object_unpin(obj
);
2973 target_obj_priv
= target_obj
->driver_private
;
2975 /* The target buffer should have appeared before us in the
2976 * exec_object list, so it should have a GTT space bound by now.
2978 if (target_obj_priv
->gtt_space
== NULL
) {
2979 DRM_ERROR("No GTT space found for object %d\n",
2980 reloc
->target_handle
);
2981 drm_gem_object_unreference(target_obj
);
2982 i915_gem_object_unpin(obj
);
2986 if (reloc
->offset
> obj
->size
- 4) {
2987 DRM_ERROR("Relocation beyond object bounds: "
2988 "obj %p target %d offset %d size %d.\n",
2989 obj
, reloc
->target_handle
,
2990 (int) reloc
->offset
, (int) obj
->size
);
2991 drm_gem_object_unreference(target_obj
);
2992 i915_gem_object_unpin(obj
);
2995 if (reloc
->offset
& 3) {
2996 DRM_ERROR("Relocation not 4-byte aligned: "
2997 "obj %p target %d offset %d.\n",
2998 obj
, reloc
->target_handle
,
2999 (int) reloc
->offset
);
3000 drm_gem_object_unreference(target_obj
);
3001 i915_gem_object_unpin(obj
);
3005 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3006 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3007 DRM_ERROR("reloc with read/write CPU domains: "
3008 "obj %p target %d offset %d "
3009 "read %08x write %08x",
3010 obj
, reloc
->target_handle
,
3011 (int) reloc
->offset
,
3012 reloc
->read_domains
,
3013 reloc
->write_domain
);
3014 drm_gem_object_unreference(target_obj
);
3015 i915_gem_object_unpin(obj
);
3019 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3020 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3021 DRM_ERROR("Write domain conflict: "
3022 "obj %p target %d offset %d "
3023 "new %08x old %08x\n",
3024 obj
, reloc
->target_handle
,
3025 (int) reloc
->offset
,
3026 reloc
->write_domain
,
3027 target_obj
->pending_write_domain
);
3028 drm_gem_object_unreference(target_obj
);
3029 i915_gem_object_unpin(obj
);
3034 DRM_INFO("%s: obj %p offset %08x target %d "
3035 "read %08x write %08x gtt %08x "
3036 "presumed %08x delta %08x\n",
3039 (int) reloc
->offset
,
3040 (int) reloc
->target_handle
,
3041 (int) reloc
->read_domains
,
3042 (int) reloc
->write_domain
,
3043 (int) target_obj_priv
->gtt_offset
,
3044 (int) reloc
->presumed_offset
,
3048 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3049 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3051 /* If the relocation already has the right value in it, no
3052 * more work needs to be done.
3054 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3055 drm_gem_object_unreference(target_obj
);
3059 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3061 drm_gem_object_unreference(target_obj
);
3062 i915_gem_object_unpin(obj
);
3066 /* Map the page containing the relocation we're going to
3069 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3070 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3073 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3074 (reloc_offset
& (PAGE_SIZE
- 1)));
3075 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3078 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3079 obj
, (unsigned int) reloc
->offset
,
3080 readl(reloc_entry
), reloc_val
);
3082 writel(reloc_val
, reloc_entry
);
3083 io_mapping_unmap_atomic(reloc_page
);
3085 /* The updated presumed offset for this entry will be
3086 * copied back out to the user.
3088 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3090 drm_gem_object_unreference(target_obj
);
3095 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3100 /** Dispatch a batchbuffer to the ring
3103 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3104 struct drm_i915_gem_execbuffer
*exec
,
3105 struct drm_clip_rect
*cliprects
,
3106 uint64_t exec_offset
)
3108 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3109 int nbox
= exec
->num_cliprects
;
3111 uint32_t exec_start
, exec_len
;
3114 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3115 exec_len
= (uint32_t) exec
->batch_len
;
3117 count
= nbox
? nbox
: 1;
3119 for (i
= 0; i
< count
; i
++) {
3121 int ret
= i915_emit_box(dev
, cliprects
, i
,
3122 exec
->DR1
, exec
->DR4
);
3127 if (IS_I830(dev
) || IS_845G(dev
)) {
3129 OUT_RING(MI_BATCH_BUFFER
);
3130 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3131 OUT_RING(exec_start
+ exec_len
- 4);
3136 if (IS_I965G(dev
)) {
3137 OUT_RING(MI_BATCH_BUFFER_START
|
3139 MI_BATCH_NON_SECURE_I965
);
3140 OUT_RING(exec_start
);
3142 OUT_RING(MI_BATCH_BUFFER_START
|
3144 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3150 /* XXX breadcrumb */
3154 /* Throttle our rendering by waiting until the ring has completed our requests
3155 * emitted over 20 msec ago.
3157 * Note that if we were to use the current jiffies each time around the loop,
3158 * we wouldn't escape the function with any frames outstanding if the time to
3159 * render a frame was over 20ms.
3161 * This should get us reasonable parallelism between CPU and GPU but also
3162 * relatively low latency when blocking on a particular request to finish.
3165 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3167 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3169 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3171 mutex_lock(&dev
->struct_mutex
);
3172 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3173 struct drm_i915_gem_request
*request
;
3175 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3176 struct drm_i915_gem_request
,
3179 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3182 ret
= i915_wait_request(dev
, request
->seqno
);
3186 mutex_unlock(&dev
->struct_mutex
);
3192 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object
*exec_list
,
3193 uint32_t buffer_count
,
3194 struct drm_i915_gem_relocation_entry
**relocs
)
3196 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3200 for (i
= 0; i
< buffer_count
; i
++) {
3201 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3203 reloc_count
+= exec_list
[i
].relocation_count
;
3206 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3207 if (*relocs
== NULL
)
3210 for (i
= 0; i
< buffer_count
; i
++) {
3211 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3213 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3215 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3217 exec_list
[i
].relocation_count
*
3220 drm_free_large(*relocs
);
3225 reloc_index
+= exec_list
[i
].relocation_count
;
3232 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object
*exec_list
,
3233 uint32_t buffer_count
,
3234 struct drm_i915_gem_relocation_entry
*relocs
)
3236 uint32_t reloc_count
= 0, i
;
3239 for (i
= 0; i
< buffer_count
; i
++) {
3240 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3243 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3245 unwritten
= copy_to_user(user_relocs
,
3246 &relocs
[reloc_count
],
3247 exec_list
[i
].relocation_count
*
3255 reloc_count
+= exec_list
[i
].relocation_count
;
3259 drm_free_large(relocs
);
3265 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer
*exec
,
3266 uint64_t exec_offset
)
3268 uint32_t exec_start
, exec_len
;
3270 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3271 exec_len
= (uint32_t) exec
->batch_len
;
3273 if ((exec_start
| exec_len
) & 0x7)
3283 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3284 struct drm_file
*file_priv
)
3286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3287 struct drm_i915_gem_execbuffer
*args
= data
;
3288 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3289 struct drm_gem_object
**object_list
= NULL
;
3290 struct drm_gem_object
*batch_obj
;
3291 struct drm_i915_gem_object
*obj_priv
;
3292 struct drm_clip_rect
*cliprects
= NULL
;
3293 struct drm_i915_gem_relocation_entry
*relocs
;
3294 int ret
, ret2
, i
, pinned
= 0;
3295 uint64_t exec_offset
;
3296 uint32_t seqno
, flush_domains
, reloc_index
;
3300 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3301 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3304 if (args
->buffer_count
< 1) {
3305 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3308 /* Copy in the exec list from userland */
3309 exec_list
= drm_calloc_large(sizeof(*exec_list
), args
->buffer_count
);
3310 object_list
= drm_calloc_large(sizeof(*object_list
), args
->buffer_count
);
3311 if (exec_list
== NULL
|| object_list
== NULL
) {
3312 DRM_ERROR("Failed to allocate exec or object list "
3314 args
->buffer_count
);
3318 ret
= copy_from_user(exec_list
,
3319 (struct drm_i915_relocation_entry __user
*)
3320 (uintptr_t) args
->buffers_ptr
,
3321 sizeof(*exec_list
) * args
->buffer_count
);
3323 DRM_ERROR("copy %d exec entries failed %d\n",
3324 args
->buffer_count
, ret
);
3328 if (args
->num_cliprects
!= 0) {
3329 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3331 if (cliprects
== NULL
)
3334 ret
= copy_from_user(cliprects
,
3335 (struct drm_clip_rect __user
*)
3336 (uintptr_t) args
->cliprects_ptr
,
3337 sizeof(*cliprects
) * args
->num_cliprects
);
3339 DRM_ERROR("copy %d cliprects failed: %d\n",
3340 args
->num_cliprects
, ret
);
3345 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3350 mutex_lock(&dev
->struct_mutex
);
3352 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3354 if (dev_priv
->mm
.wedged
) {
3355 DRM_ERROR("Execbuf while wedged\n");
3356 mutex_unlock(&dev
->struct_mutex
);
3361 if (dev_priv
->mm
.suspended
) {
3362 DRM_ERROR("Execbuf while VT-switched.\n");
3363 mutex_unlock(&dev
->struct_mutex
);
3368 /* Look up object handles */
3369 for (i
= 0; i
< args
->buffer_count
; i
++) {
3370 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3371 exec_list
[i
].handle
);
3372 if (object_list
[i
] == NULL
) {
3373 DRM_ERROR("Invalid object handle %d at index %d\n",
3374 exec_list
[i
].handle
, i
);
3379 obj_priv
= object_list
[i
]->driver_private
;
3380 if (obj_priv
->in_execbuffer
) {
3381 DRM_ERROR("Object %p appears more than once in object list\n",
3386 obj_priv
->in_execbuffer
= true;
3389 /* Pin and relocate */
3390 for (pin_tries
= 0; ; pin_tries
++) {
3394 for (i
= 0; i
< args
->buffer_count
; i
++) {
3395 object_list
[i
]->pending_read_domains
= 0;
3396 object_list
[i
]->pending_write_domain
= 0;
3397 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3400 &relocs
[reloc_index
]);
3404 reloc_index
+= exec_list
[i
].relocation_count
;
3410 /* error other than GTT full, or we've already tried again */
3411 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3412 if (ret
!= -ERESTARTSYS
)
3413 DRM_ERROR("Failed to pin buffers %d\n", ret
);
3417 /* unpin all of our buffers */
3418 for (i
= 0; i
< pinned
; i
++)
3419 i915_gem_object_unpin(object_list
[i
]);
3422 /* evict everyone we can from the aperture */
3423 ret
= i915_gem_evict_everything(dev
);
3428 /* Set the pending read domains for the batch buffer to COMMAND */
3429 batch_obj
= object_list
[args
->buffer_count
-1];
3430 if (batch_obj
->pending_write_domain
) {
3431 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3435 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3437 /* Sanity check the batch buffer, prior to moving objects */
3438 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3439 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3441 DRM_ERROR("execbuf with invalid offset/length\n");
3445 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3447 /* Zero the global flush/invalidate flags. These
3448 * will be modified as new domains are computed
3451 dev
->invalidate_domains
= 0;
3452 dev
->flush_domains
= 0;
3454 for (i
= 0; i
< args
->buffer_count
; i
++) {
3455 struct drm_gem_object
*obj
= object_list
[i
];
3457 /* Compute new gpu domains and update invalidate/flush */
3458 i915_gem_object_set_to_gpu_domain(obj
);
3461 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3463 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3465 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3467 dev
->invalidate_domains
,
3468 dev
->flush_domains
);
3471 dev
->invalidate_domains
,
3472 dev
->flush_domains
);
3473 if (dev
->flush_domains
)
3474 (void)i915_add_request(dev
, file_priv
,
3475 dev
->flush_domains
);
3478 for (i
= 0; i
< args
->buffer_count
; i
++) {
3479 struct drm_gem_object
*obj
= object_list
[i
];
3481 obj
->write_domain
= obj
->pending_write_domain
;
3484 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3487 for (i
= 0; i
< args
->buffer_count
; i
++) {
3488 i915_gem_object_check_coherency(object_list
[i
],
3489 exec_list
[i
].handle
);
3494 i915_gem_dump_object(batch_obj
,
3500 /* Exec the batchbuffer */
3501 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3503 DRM_ERROR("dispatch failed %d\n", ret
);
3508 * Ensure that the commands in the batch buffer are
3509 * finished before the interrupt fires
3511 flush_domains
= i915_retire_commands(dev
);
3513 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3516 * Get a seqno representing the execution of the current buffer,
3517 * which we can wait on. We would like to mitigate these interrupts,
3518 * likely by only creating seqnos occasionally (so that we have
3519 * *some* interrupts representing completion of buffers that we can
3520 * wait on when trying to clear up gtt space).
3522 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3524 for (i
= 0; i
< args
->buffer_count
; i
++) {
3525 struct drm_gem_object
*obj
= object_list
[i
];
3527 i915_gem_object_move_to_active(obj
, seqno
);
3529 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3533 i915_dump_lru(dev
, __func__
);
3536 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3539 for (i
= 0; i
< pinned
; i
++)
3540 i915_gem_object_unpin(object_list
[i
]);
3542 for (i
= 0; i
< args
->buffer_count
; i
++) {
3543 if (object_list
[i
]) {
3544 obj_priv
= object_list
[i
]->driver_private
;
3545 obj_priv
->in_execbuffer
= false;
3547 drm_gem_object_unreference(object_list
[i
]);
3550 mutex_unlock(&dev
->struct_mutex
);
3553 /* Copy the new buffer offsets back to the user's exec list. */
3554 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3555 (uintptr_t) args
->buffers_ptr
,
3557 sizeof(*exec_list
) * args
->buffer_count
);
3560 DRM_ERROR("failed to copy %d exec entries "
3561 "back to user (%d)\n",
3562 args
->buffer_count
, ret
);
3566 /* Copy the updated relocations out regardless of current error
3567 * state. Failure to update the relocs would mean that the next
3568 * time userland calls execbuf, it would do so with presumed offset
3569 * state that didn't match the actual object state.
3571 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3574 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3581 drm_free_large(object_list
);
3582 drm_free_large(exec_list
);
3589 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3591 struct drm_device
*dev
= obj
->dev
;
3592 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3595 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3596 if (obj_priv
->gtt_space
== NULL
) {
3597 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
3599 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3600 DRM_ERROR("Failure to bind: %d\n", ret
);
3605 * Pre-965 chips need a fence register set up in order to
3606 * properly handle tiled surfaces.
3608 if (!IS_I965G(dev
) && obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
3609 ret
= i915_gem_object_get_fence_reg(obj
);
3611 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3612 DRM_ERROR("Failure to install fence: %d\n",
3617 obj_priv
->pin_count
++;
3619 /* If the object is not active and not pending a flush,
3620 * remove it from the inactive list
3622 if (obj_priv
->pin_count
== 1) {
3623 atomic_inc(&dev
->pin_count
);
3624 atomic_add(obj
->size
, &dev
->pin_memory
);
3625 if (!obj_priv
->active
&&
3626 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
3627 !list_empty(&obj_priv
->list
))
3628 list_del_init(&obj_priv
->list
);
3630 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3636 i915_gem_object_unpin(struct drm_gem_object
*obj
)
3638 struct drm_device
*dev
= obj
->dev
;
3639 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3640 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3642 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3643 obj_priv
->pin_count
--;
3644 BUG_ON(obj_priv
->pin_count
< 0);
3645 BUG_ON(obj_priv
->gtt_space
== NULL
);
3647 /* If the object is no longer pinned, and is
3648 * neither active nor being flushed, then stick it on
3651 if (obj_priv
->pin_count
== 0) {
3652 if (!obj_priv
->active
&&
3653 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
3654 list_move_tail(&obj_priv
->list
,
3655 &dev_priv
->mm
.inactive_list
);
3656 atomic_dec(&dev
->pin_count
);
3657 atomic_sub(obj
->size
, &dev
->pin_memory
);
3659 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3663 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3664 struct drm_file
*file_priv
)
3666 struct drm_i915_gem_pin
*args
= data
;
3667 struct drm_gem_object
*obj
;
3668 struct drm_i915_gem_object
*obj_priv
;
3671 mutex_lock(&dev
->struct_mutex
);
3673 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3675 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3677 mutex_unlock(&dev
->struct_mutex
);
3680 obj_priv
= obj
->driver_private
;
3682 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
3683 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3685 drm_gem_object_unreference(obj
);
3686 mutex_unlock(&dev
->struct_mutex
);
3690 obj_priv
->user_pin_count
++;
3691 obj_priv
->pin_filp
= file_priv
;
3692 if (obj_priv
->user_pin_count
== 1) {
3693 ret
= i915_gem_object_pin(obj
, args
->alignment
);
3695 drm_gem_object_unreference(obj
);
3696 mutex_unlock(&dev
->struct_mutex
);
3701 /* XXX - flush the CPU caches for pinned objects
3702 * as the X server doesn't manage domains yet
3704 i915_gem_object_flush_cpu_write_domain(obj
);
3705 args
->offset
= obj_priv
->gtt_offset
;
3706 drm_gem_object_unreference(obj
);
3707 mutex_unlock(&dev
->struct_mutex
);
3713 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3714 struct drm_file
*file_priv
)
3716 struct drm_i915_gem_pin
*args
= data
;
3717 struct drm_gem_object
*obj
;
3718 struct drm_i915_gem_object
*obj_priv
;
3720 mutex_lock(&dev
->struct_mutex
);
3722 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3724 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3726 mutex_unlock(&dev
->struct_mutex
);
3730 obj_priv
= obj
->driver_private
;
3731 if (obj_priv
->pin_filp
!= file_priv
) {
3732 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3734 drm_gem_object_unreference(obj
);
3735 mutex_unlock(&dev
->struct_mutex
);
3738 obj_priv
->user_pin_count
--;
3739 if (obj_priv
->user_pin_count
== 0) {
3740 obj_priv
->pin_filp
= NULL
;
3741 i915_gem_object_unpin(obj
);
3744 drm_gem_object_unreference(obj
);
3745 mutex_unlock(&dev
->struct_mutex
);
3750 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3751 struct drm_file
*file_priv
)
3753 struct drm_i915_gem_busy
*args
= data
;
3754 struct drm_gem_object
*obj
;
3755 struct drm_i915_gem_object
*obj_priv
;
3757 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3759 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3764 mutex_lock(&dev
->struct_mutex
);
3765 /* Update the active list for the hardware's current position.
3766 * Otherwise this only updates on a delayed timer or when irqs are
3767 * actually unmasked, and our working set ends up being larger than
3770 i915_gem_retire_requests(dev
);
3772 obj_priv
= obj
->driver_private
;
3773 /* Don't count being on the flushing list against the object being
3774 * done. Otherwise, a buffer left on the flushing list but not getting
3775 * flushed (because nobody's flushing that domain) won't ever return
3776 * unbusy and get reused by libdrm's bo cache. The other expected
3777 * consumer of this interface, OpenGL's occlusion queries, also specs
3778 * that the objects get unbusy "eventually" without any interference.
3780 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
3782 drm_gem_object_unreference(obj
);
3783 mutex_unlock(&dev
->struct_mutex
);
3788 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3789 struct drm_file
*file_priv
)
3791 return i915_gem_ring_throttle(dev
, file_priv
);
3794 int i915_gem_init_object(struct drm_gem_object
*obj
)
3796 struct drm_i915_gem_object
*obj_priv
;
3798 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
3799 if (obj_priv
== NULL
)
3803 * We've just allocated pages from the kernel,
3804 * so they've just been written by the CPU with
3805 * zeros. They'll need to be clflushed before we
3806 * use them with the GPU.
3808 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3809 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3811 obj_priv
->agp_type
= AGP_USER_MEMORY
;
3813 obj
->driver_private
= obj_priv
;
3814 obj_priv
->obj
= obj
;
3815 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
3816 INIT_LIST_HEAD(&obj_priv
->list
);
3817 INIT_LIST_HEAD(&obj_priv
->fence_list
);
3822 void i915_gem_free_object(struct drm_gem_object
*obj
)
3824 struct drm_device
*dev
= obj
->dev
;
3825 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3827 while (obj_priv
->pin_count
> 0)
3828 i915_gem_object_unpin(obj
);
3830 if (obj_priv
->phys_obj
)
3831 i915_gem_detach_phys_object(dev
, obj
);
3833 i915_gem_object_unbind(obj
);
3835 i915_gem_free_mmap_offset(obj
);
3837 kfree(obj_priv
->page_cpu_valid
);
3838 kfree(obj_priv
->bit_17
);
3839 kfree(obj
->driver_private
);
3842 /** Unbinds all objects that are on the given buffer list. */
3844 i915_gem_evict_from_list(struct drm_device
*dev
, struct list_head
*head
)
3846 struct drm_gem_object
*obj
;
3847 struct drm_i915_gem_object
*obj_priv
;
3850 while (!list_empty(head
)) {
3851 obj_priv
= list_first_entry(head
,
3852 struct drm_i915_gem_object
,
3854 obj
= obj_priv
->obj
;
3856 if (obj_priv
->pin_count
!= 0) {
3857 DRM_ERROR("Pinned object in unbind list\n");
3858 mutex_unlock(&dev
->struct_mutex
);
3862 ret
= i915_gem_object_unbind(obj
);
3864 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3866 mutex_unlock(&dev
->struct_mutex
);
3876 i915_gem_idle(struct drm_device
*dev
)
3878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3879 uint32_t seqno
, cur_seqno
, last_seqno
;
3882 mutex_lock(&dev
->struct_mutex
);
3884 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
3885 mutex_unlock(&dev
->struct_mutex
);
3889 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3890 * We need to replace this with a semaphore, or something.
3892 dev_priv
->mm
.suspended
= 1;
3894 /* Cancel the retire work handler, wait for it to finish if running
3896 mutex_unlock(&dev
->struct_mutex
);
3897 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3898 mutex_lock(&dev
->struct_mutex
);
3900 i915_kernel_lost_context(dev
);
3902 /* Flush the GPU along with all non-CPU write domains
3904 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
3905 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
3908 mutex_unlock(&dev
->struct_mutex
);
3912 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
3916 cur_seqno
= i915_get_gem_seqno(dev
);
3917 if (i915_seqno_passed(cur_seqno
, seqno
))
3919 if (last_seqno
== cur_seqno
) {
3920 if (stuck
++ > 100) {
3921 DRM_ERROR("hardware wedged\n");
3922 dev_priv
->mm
.wedged
= 1;
3923 DRM_WAKEUP(&dev_priv
->irq_queue
);
3928 last_seqno
= cur_seqno
;
3930 dev_priv
->mm
.waiting_gem_seqno
= 0;
3932 i915_gem_retire_requests(dev
);
3934 spin_lock(&dev_priv
->mm
.active_list_lock
);
3935 if (!dev_priv
->mm
.wedged
) {
3936 /* Active and flushing should now be empty as we've
3937 * waited for a sequence higher than any pending execbuffer
3939 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
3940 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3941 /* Request should now be empty as we've also waited
3942 * for the last request in the list
3944 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
3947 /* Empty the active and flushing lists to inactive. If there's
3948 * anything left at this point, it means that we're wedged and
3949 * nothing good's going to happen by leaving them there. So strip
3950 * the GPU domains and just stuff them onto inactive.
3952 while (!list_empty(&dev_priv
->mm
.active_list
)) {
3953 struct drm_i915_gem_object
*obj_priv
;
3955 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
3956 struct drm_i915_gem_object
,
3958 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3959 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3961 spin_unlock(&dev_priv
->mm
.active_list_lock
);
3963 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
3964 struct drm_i915_gem_object
*obj_priv
;
3966 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
3967 struct drm_i915_gem_object
,
3969 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3970 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3974 /* Move all inactive buffers out of the GTT. */
3975 ret
= i915_gem_evict_from_list(dev
, &dev_priv
->mm
.inactive_list
);
3976 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3978 mutex_unlock(&dev
->struct_mutex
);
3982 i915_gem_cleanup_ringbuffer(dev
);
3983 mutex_unlock(&dev
->struct_mutex
);
3989 i915_gem_init_hws(struct drm_device
*dev
)
3991 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3992 struct drm_gem_object
*obj
;
3993 struct drm_i915_gem_object
*obj_priv
;
3996 /* If we need a physical address for the status page, it's already
3997 * initialized at driver load time.
3999 if (!I915_NEED_GFX_HWS(dev
))
4002 obj
= drm_gem_object_alloc(dev
, 4096);
4004 DRM_ERROR("Failed to allocate status page\n");
4007 obj_priv
= obj
->driver_private
;
4008 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4010 ret
= i915_gem_object_pin(obj
, 4096);
4012 drm_gem_object_unreference(obj
);
4016 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4018 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4019 if (dev_priv
->hw_status_page
== NULL
) {
4020 DRM_ERROR("Failed to map status page.\n");
4021 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4022 i915_gem_object_unpin(obj
);
4023 drm_gem_object_unreference(obj
);
4026 dev_priv
->hws_obj
= obj
;
4027 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4028 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4029 I915_READ(HWS_PGA
); /* posting read */
4030 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4036 i915_gem_cleanup_hws(struct drm_device
*dev
)
4038 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4039 struct drm_gem_object
*obj
;
4040 struct drm_i915_gem_object
*obj_priv
;
4042 if (dev_priv
->hws_obj
== NULL
)
4045 obj
= dev_priv
->hws_obj
;
4046 obj_priv
= obj
->driver_private
;
4048 kunmap(obj_priv
->pages
[0]);
4049 i915_gem_object_unpin(obj
);
4050 drm_gem_object_unreference(obj
);
4051 dev_priv
->hws_obj
= NULL
;
4053 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4054 dev_priv
->hw_status_page
= NULL
;
4056 /* Write high address into HWS_PGA when disabling. */
4057 I915_WRITE(HWS_PGA
, 0x1ffff000);
4061 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4064 struct drm_gem_object
*obj
;
4065 struct drm_i915_gem_object
*obj_priv
;
4066 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4070 ret
= i915_gem_init_hws(dev
);
4074 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4076 DRM_ERROR("Failed to allocate ringbuffer\n");
4077 i915_gem_cleanup_hws(dev
);
4080 obj_priv
= obj
->driver_private
;
4082 ret
= i915_gem_object_pin(obj
, 4096);
4084 drm_gem_object_unreference(obj
);
4085 i915_gem_cleanup_hws(dev
);
4089 /* Set up the kernel mapping for the ring. */
4090 ring
->Size
= obj
->size
;
4091 ring
->tail_mask
= obj
->size
- 1;
4093 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4094 ring
->map
.size
= obj
->size
;
4096 ring
->map
.flags
= 0;
4099 drm_core_ioremap_wc(&ring
->map
, dev
);
4100 if (ring
->map
.handle
== NULL
) {
4101 DRM_ERROR("Failed to map ringbuffer.\n");
4102 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4103 i915_gem_object_unpin(obj
);
4104 drm_gem_object_unreference(obj
);
4105 i915_gem_cleanup_hws(dev
);
4108 ring
->ring_obj
= obj
;
4109 ring
->virtual_start
= ring
->map
.handle
;
4111 /* Stop the ring if it's running. */
4112 I915_WRITE(PRB0_CTL
, 0);
4113 I915_WRITE(PRB0_TAIL
, 0);
4114 I915_WRITE(PRB0_HEAD
, 0);
4116 /* Initialize the ring. */
4117 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4118 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4120 /* G45 ring initialization fails to reset head to zero */
4122 DRM_ERROR("Ring head not reset to zero "
4123 "ctl %08x head %08x tail %08x start %08x\n",
4124 I915_READ(PRB0_CTL
),
4125 I915_READ(PRB0_HEAD
),
4126 I915_READ(PRB0_TAIL
),
4127 I915_READ(PRB0_START
));
4128 I915_WRITE(PRB0_HEAD
, 0);
4130 DRM_ERROR("Ring head forced to zero "
4131 "ctl %08x head %08x tail %08x start %08x\n",
4132 I915_READ(PRB0_CTL
),
4133 I915_READ(PRB0_HEAD
),
4134 I915_READ(PRB0_TAIL
),
4135 I915_READ(PRB0_START
));
4138 I915_WRITE(PRB0_CTL
,
4139 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4143 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4145 /* If the head is still not zero, the ring is dead */
4147 DRM_ERROR("Ring initialization failed "
4148 "ctl %08x head %08x tail %08x start %08x\n",
4149 I915_READ(PRB0_CTL
),
4150 I915_READ(PRB0_HEAD
),
4151 I915_READ(PRB0_TAIL
),
4152 I915_READ(PRB0_START
));
4156 /* Update our cache of the ring state */
4157 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4158 i915_kernel_lost_context(dev
);
4160 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4161 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4162 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4163 if (ring
->space
< 0)
4164 ring
->space
+= ring
->Size
;
4171 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4173 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4175 if (dev_priv
->ring
.ring_obj
== NULL
)
4178 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4180 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4181 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4182 dev_priv
->ring
.ring_obj
= NULL
;
4183 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4185 i915_gem_cleanup_hws(dev
);
4189 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4190 struct drm_file
*file_priv
)
4192 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4195 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4198 if (dev_priv
->mm
.wedged
) {
4199 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4200 dev_priv
->mm
.wedged
= 0;
4203 mutex_lock(&dev
->struct_mutex
);
4204 dev_priv
->mm
.suspended
= 0;
4206 ret
= i915_gem_init_ringbuffer(dev
);
4208 mutex_unlock(&dev
->struct_mutex
);
4212 spin_lock(&dev_priv
->mm
.active_list_lock
);
4213 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4214 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4216 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4217 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4218 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4219 mutex_unlock(&dev
->struct_mutex
);
4221 drm_irq_install(dev
);
4227 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4228 struct drm_file
*file_priv
)
4232 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4235 ret
= i915_gem_idle(dev
);
4236 drm_irq_uninstall(dev
);
4242 i915_gem_lastclose(struct drm_device
*dev
)
4246 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4249 ret
= i915_gem_idle(dev
);
4251 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4255 i915_gem_load(struct drm_device
*dev
)
4258 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4260 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4261 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4262 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4263 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4264 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4265 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4266 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4267 i915_gem_retire_work_handler
);
4268 dev_priv
->mm
.next_gem_seqno
= 1;
4270 /* Old X drivers will take 0-2 for front, back, depth buffers */
4271 dev_priv
->fence_reg_start
= 3;
4273 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4274 dev_priv
->num_fence_regs
= 16;
4276 dev_priv
->num_fence_regs
= 8;
4278 /* Initialize fence registers to zero */
4279 if (IS_I965G(dev
)) {
4280 for (i
= 0; i
< 16; i
++)
4281 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4283 for (i
= 0; i
< 8; i
++)
4284 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4285 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4286 for (i
= 0; i
< 8; i
++)
4287 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4290 i915_gem_detect_bit_6_swizzle(dev
);
4294 * Create a physically contiguous memory object for this object
4295 * e.g. for cursor + overlay regs
4297 int i915_gem_init_phys_object(struct drm_device
*dev
,
4300 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4301 struct drm_i915_gem_phys_object
*phys_obj
;
4304 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4307 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4313 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0, 0xffffffff);
4314 if (!phys_obj
->handle
) {
4319 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4322 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4330 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4332 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4333 struct drm_i915_gem_phys_object
*phys_obj
;
4335 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4338 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4339 if (phys_obj
->cur_obj
) {
4340 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4344 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4346 drm_pci_free(dev
, phys_obj
->handle
);
4348 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4351 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4355 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4356 i915_gem_free_phys_object(dev
, i
);
4359 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4360 struct drm_gem_object
*obj
)
4362 struct drm_i915_gem_object
*obj_priv
;
4367 obj_priv
= obj
->driver_private
;
4368 if (!obj_priv
->phys_obj
)
4371 ret
= i915_gem_object_get_pages(obj
);
4375 page_count
= obj
->size
/ PAGE_SIZE
;
4377 for (i
= 0; i
< page_count
; i
++) {
4378 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4379 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4381 memcpy(dst
, src
, PAGE_SIZE
);
4382 kunmap_atomic(dst
, KM_USER0
);
4384 drm_clflush_pages(obj_priv
->pages
, page_count
);
4385 drm_agp_chipset_flush(dev
);
4387 i915_gem_object_put_pages(obj
);
4389 obj_priv
->phys_obj
->cur_obj
= NULL
;
4390 obj_priv
->phys_obj
= NULL
;
4394 i915_gem_attach_phys_object(struct drm_device
*dev
,
4395 struct drm_gem_object
*obj
, int id
)
4397 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4398 struct drm_i915_gem_object
*obj_priv
;
4403 if (id
> I915_MAX_PHYS_OBJECT
)
4406 obj_priv
= obj
->driver_private
;
4408 if (obj_priv
->phys_obj
) {
4409 if (obj_priv
->phys_obj
->id
== id
)
4411 i915_gem_detach_phys_object(dev
, obj
);
4415 /* create a new object */
4416 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4417 ret
= i915_gem_init_phys_object(dev
, id
,
4420 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4425 /* bind to the object */
4426 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4427 obj_priv
->phys_obj
->cur_obj
= obj
;
4429 ret
= i915_gem_object_get_pages(obj
);
4431 DRM_ERROR("failed to get page list\n");
4435 page_count
= obj
->size
/ PAGE_SIZE
;
4437 for (i
= 0; i
< page_count
; i
++) {
4438 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4439 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4441 memcpy(dst
, src
, PAGE_SIZE
);
4442 kunmap_atomic(src
, KM_USER0
);
4445 i915_gem_object_put_pages(obj
);
4453 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4454 struct drm_i915_gem_pwrite
*args
,
4455 struct drm_file
*file_priv
)
4457 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4460 char __user
*user_data
;
4462 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4463 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4465 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4466 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4470 drm_agp_chipset_flush(dev
);
4474 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4476 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4478 /* Clean up our request list when the client is going away, so that
4479 * later retire_requests won't dereference our soon-to-be-gone
4482 mutex_lock(&dev
->struct_mutex
);
4483 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4484 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4485 mutex_unlock(&dev
->struct_mutex
);