2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
61 return obj
->pin_display
;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
68 spin_lock(&dev_priv
->mm
.object_stat_lock
);
69 dev_priv
->mm
.object_count
++;
70 dev_priv
->mm
.object_memory
+= size
;
71 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
74 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
77 spin_lock(&dev_priv
->mm
.object_stat_lock
);
78 dev_priv
->mm
.object_count
--;
79 dev_priv
->mm
.object_memory
-= size
;
80 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
84 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret
< 0) {
112 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
125 WARN_ON(i915_verify_lists(dev
));
130 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
131 struct drm_file
*file
)
133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
134 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
135 struct drm_i915_gem_get_aperture
*args
= data
;
136 struct i915_vma
*vma
;
140 mutex_lock(&dev
->struct_mutex
);
141 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
143 pinned
+= vma
->node
.size
;
144 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
146 pinned
+= vma
->node
.size
;
147 mutex_unlock(&dev
->struct_mutex
);
149 args
->aper_size
= ggtt
->base
.total
;
150 args
->aper_available_size
= args
->aper_size
- pinned
;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
158 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
159 char *vaddr
= obj
->phys_handle
->vaddr
;
161 struct scatterlist
*sg
;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
167 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
171 page
= shmem_read_mapping_page(mapping
, i
);
173 return PTR_ERR(page
);
175 src
= kmap_atomic(page
);
176 memcpy(vaddr
, src
, PAGE_SIZE
);
177 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 page_cache_release(page
);
184 i915_gem_chipset_flush(obj
->base
.dev
);
186 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
190 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
197 sg
->length
= obj
->base
.size
;
199 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
200 sg_dma_len(sg
) = obj
->base
.size
;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
211 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
213 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret
!= -EIO
);
219 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
222 if (obj
->madv
== I915_MADV_DONTNEED
)
226 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
227 char *vaddr
= obj
->phys_handle
->vaddr
;
230 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
234 page
= shmem_read_mapping_page(mapping
, i
);
238 dst
= kmap_atomic(page
);
239 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
240 memcpy(dst
, vaddr
, PAGE_SIZE
);
243 set_page_dirty(page
);
244 if (obj
->madv
== I915_MADV_WILLNEED
)
245 mark_page_accessed(page
);
246 page_cache_release(page
);
252 sg_free_table(obj
->pages
);
257 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
259 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
263 .get_pages
= i915_gem_object_get_pages_phys
,
264 .put_pages
= i915_gem_object_put_pages_phys
,
265 .release
= i915_gem_object_release_phys
,
269 drop_pages(struct drm_i915_gem_object
*obj
)
271 struct i915_vma
*vma
, *next
;
274 drm_gem_object_reference(&obj
->base
);
275 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
276 if (i915_vma_unbind(vma
))
279 ret
= i915_gem_object_put_pages(obj
);
280 drm_gem_object_unreference(&obj
->base
);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
289 drm_dma_handle_t
*phys
;
292 if (obj
->phys_handle
) {
293 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
299 if (obj
->madv
!= I915_MADV_WILLNEED
)
302 if (obj
->base
.filp
== NULL
)
305 ret
= drop_pages(obj
);
309 /* create a new object */
310 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
314 obj
->phys_handle
= phys
;
315 obj
->ops
= &i915_gem_phys_ops
;
317 return i915_gem_object_get_pages(obj
);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
322 struct drm_i915_gem_pwrite
*args
,
323 struct drm_file
*file_priv
)
325 struct drm_device
*dev
= obj
->base
.dev
;
326 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
327 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret
= i915_gem_object_wait_rendering(obj
, false);
337 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
338 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
339 unsigned long unwritten
;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev
->struct_mutex
);
346 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
347 mutex_lock(&dev
->struct_mutex
);
354 drm_clflush_virt_range(vaddr
, args
->size
);
355 i915_gem_chipset_flush(dev
);
358 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
362 void *i915_gem_object_alloc(struct drm_device
*dev
)
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
368 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
370 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
371 kmem_cache_free(dev_priv
->objects
, obj
);
375 i915_gem_create(struct drm_file
*file
,
376 struct drm_device
*dev
,
380 struct drm_i915_gem_object
*obj
;
384 size
= roundup(size
, PAGE_SIZE
);
388 /* Allocate the new object */
389 obj
= i915_gem_alloc_object(dev
, size
);
393 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj
->base
);
404 i915_gem_dumb_create(struct drm_file
*file
,
405 struct drm_device
*dev
,
406 struct drm_mode_create_dumb
*args
)
408 /* have to work out size/pitch and return them */
409 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
410 args
->size
= args
->pitch
* args
->height
;
411 return i915_gem_create(file
, dev
,
412 args
->size
, &args
->handle
);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
420 struct drm_file
*file
)
422 struct drm_i915_gem_create
*args
= data
;
424 return i915_gem_create(file
, dev
,
425 args
->size
, &args
->handle
);
429 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
430 const char *gpu_vaddr
, int gpu_offset
,
433 int ret
, cpu_offset
= 0;
436 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
437 int this_length
= min(cacheline_end
- gpu_offset
, length
);
438 int swizzled_gpu_offset
= gpu_offset
^ 64;
440 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
441 gpu_vaddr
+ swizzled_gpu_offset
,
446 cpu_offset
+= this_length
;
447 gpu_offset
+= this_length
;
448 length
-= this_length
;
455 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
456 const char __user
*cpu_vaddr
,
459 int ret
, cpu_offset
= 0;
462 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
463 int this_length
= min(cacheline_end
- gpu_offset
, length
);
464 int swizzled_gpu_offset
= gpu_offset
^ 64;
466 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
467 cpu_vaddr
+ cpu_offset
,
472 cpu_offset
+= this_length
;
473 gpu_offset
+= this_length
;
474 length
-= this_length
;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
492 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
495 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
502 ret
= i915_gem_object_wait_rendering(obj
, true);
507 ret
= i915_gem_object_get_pages(obj
);
511 i915_gem_object_pin_pages(obj
);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
521 char __user
*user_data
,
522 bool page_do_bit17_swizzling
, bool needs_clflush
)
527 if (unlikely(page_do_bit17_swizzling
))
530 vaddr
= kmap_atomic(page
);
532 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
534 ret
= __copy_to_user_inatomic(user_data
,
535 vaddr
+ shmem_page_offset
,
537 kunmap_atomic(vaddr
);
539 return ret
? -EFAULT
: 0;
543 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
546 if (unlikely(swizzled
)) {
547 unsigned long start
= (unsigned long) addr
;
548 unsigned long end
= (unsigned long) addr
+ length
;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start
= round_down(start
, 128);
555 end
= round_up(end
, 128);
557 drm_clflush_virt_range((void *)start
, end
- start
);
559 drm_clflush_virt_range(addr
, length
);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
568 char __user
*user_data
,
569 bool page_do_bit17_swizzling
, bool needs_clflush
)
576 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
578 page_do_bit17_swizzling
);
580 if (page_do_bit17_swizzling
)
581 ret
= __copy_to_user_swizzled(user_data
,
582 vaddr
, shmem_page_offset
,
585 ret
= __copy_to_user(user_data
,
586 vaddr
+ shmem_page_offset
,
590 return ret
? - EFAULT
: 0;
594 i915_gem_shmem_pread(struct drm_device
*dev
,
595 struct drm_i915_gem_object
*obj
,
596 struct drm_i915_gem_pread
*args
,
597 struct drm_file
*file
)
599 char __user
*user_data
;
602 int shmem_page_offset
, page_length
, ret
= 0;
603 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
605 int needs_clflush
= 0;
606 struct sg_page_iter sg_iter
;
608 user_data
= to_user_ptr(args
->data_ptr
);
611 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
613 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
617 offset
= args
->offset
;
619 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
620 offset
>> PAGE_SHIFT
) {
621 struct page
*page
= sg_page_iter_page(&sg_iter
);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset
= offset_in_page(offset
);
632 page_length
= remain
;
633 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
634 page_length
= PAGE_SIZE
- shmem_page_offset
;
636 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
637 (page_to_phys(page
) & (1 << 17)) != 0;
639 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
640 user_data
, page_do_bit17_swizzling
,
645 mutex_unlock(&dev
->struct_mutex
);
647 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
648 ret
= fault_in_multipages_writeable(user_data
, remain
);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
661 mutex_lock(&dev
->struct_mutex
);
667 remain
-= page_length
;
668 user_data
+= page_length
;
669 offset
+= page_length
;
673 i915_gem_object_unpin_pages(obj
);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
685 struct drm_file
*file
)
687 struct drm_i915_gem_pread
*args
= data
;
688 struct drm_i915_gem_object
*obj
;
694 if (!access_ok(VERIFY_WRITE
,
695 to_user_ptr(args
->data_ptr
),
699 ret
= i915_mutex_lock_interruptible(dev
);
703 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
704 if (&obj
->base
== NULL
) {
709 /* Bounds check source. */
710 if (args
->offset
> obj
->base
.size
||
711 args
->size
> obj
->base
.size
- args
->offset
) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj
->base
.filp
) {
724 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
726 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
729 drm_gem_object_unreference(&obj
->base
);
731 mutex_unlock(&dev
->struct_mutex
);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping
*mapping
,
741 loff_t page_base
, int page_offset
,
742 char __user
*user_data
,
745 void __iomem
*vaddr_atomic
;
747 unsigned long unwritten
;
749 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
752 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
754 io_mapping_unmap_atomic(vaddr_atomic
);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
764 struct drm_i915_gem_object
*obj
,
765 struct drm_i915_gem_pwrite
*args
,
766 struct drm_file
*file
)
768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
769 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
771 loff_t offset
, page_base
;
772 char __user
*user_data
;
773 int page_offset
, page_length
, ret
;
775 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
779 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
783 ret
= i915_gem_object_put_fence(obj
);
787 user_data
= to_user_ptr(args
->data_ptr
);
790 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
792 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
795 /* Operation in this page
797 * page_base = page offset within aperture
798 * page_offset = offset within page
799 * page_length = bytes to copy for this page
801 page_base
= offset
& PAGE_MASK
;
802 page_offset
= offset_in_page(offset
);
803 page_length
= remain
;
804 if ((page_offset
+ remain
) > PAGE_SIZE
)
805 page_length
= PAGE_SIZE
- page_offset
;
807 /* If we get a fault while copying data, then (presumably) our
808 * source page isn't available. Return the error and we'll
809 * retry in the slow path.
811 if (fast_user_write(ggtt
->mappable
, page_base
,
812 page_offset
, user_data
, page_length
)) {
817 remain
-= page_length
;
818 user_data
+= page_length
;
819 offset
+= page_length
;
823 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
825 i915_gem_object_ggtt_unpin(obj
);
830 /* Per-page copy function for the shmem pwrite fastpath.
831 * Flushes invalid cachelines before writing to the target if
832 * needs_clflush_before is set and flushes out any written cachelines after
833 * writing if needs_clflush is set. */
835 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
836 char __user
*user_data
,
837 bool page_do_bit17_swizzling
,
838 bool needs_clflush_before
,
839 bool needs_clflush_after
)
844 if (unlikely(page_do_bit17_swizzling
))
847 vaddr
= kmap_atomic(page
);
848 if (needs_clflush_before
)
849 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
851 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
852 user_data
, page_length
);
853 if (needs_clflush_after
)
854 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
856 kunmap_atomic(vaddr
);
858 return ret
? -EFAULT
: 0;
861 /* Only difference to the fast-path function is that this can handle bit17
862 * and uses non-atomic copy and kmap functions. */
864 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
865 char __user
*user_data
,
866 bool page_do_bit17_swizzling
,
867 bool needs_clflush_before
,
868 bool needs_clflush_after
)
874 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
875 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
877 page_do_bit17_swizzling
);
878 if (page_do_bit17_swizzling
)
879 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
883 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
886 if (needs_clflush_after
)
887 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
889 page_do_bit17_swizzling
);
892 return ret
? -EFAULT
: 0;
896 i915_gem_shmem_pwrite(struct drm_device
*dev
,
897 struct drm_i915_gem_object
*obj
,
898 struct drm_i915_gem_pwrite
*args
,
899 struct drm_file
*file
)
903 char __user
*user_data
;
904 int shmem_page_offset
, page_length
, ret
= 0;
905 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
906 int hit_slowpath
= 0;
907 int needs_clflush_after
= 0;
908 int needs_clflush_before
= 0;
909 struct sg_page_iter sg_iter
;
911 user_data
= to_user_ptr(args
->data_ptr
);
914 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
916 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
917 /* If we're not in the cpu write domain, set ourself into the gtt
918 * write domain and manually flush cachelines (if required). This
919 * optimizes for the case when the gpu will use the data
920 * right away and we therefore have to clflush anyway. */
921 needs_clflush_after
= cpu_write_needs_clflush(obj
);
922 ret
= i915_gem_object_wait_rendering(obj
, false);
926 /* Same trick applies to invalidate partially written cachelines read
928 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
929 needs_clflush_before
=
930 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
932 ret
= i915_gem_object_get_pages(obj
);
936 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
938 i915_gem_object_pin_pages(obj
);
940 offset
= args
->offset
;
943 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
944 offset
>> PAGE_SHIFT
) {
945 struct page
*page
= sg_page_iter_page(&sg_iter
);
946 int partial_cacheline_write
;
951 /* Operation in this page
953 * shmem_page_offset = offset within page in shmem file
954 * page_length = bytes to copy for this page
956 shmem_page_offset
= offset_in_page(offset
);
958 page_length
= remain
;
959 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
960 page_length
= PAGE_SIZE
- shmem_page_offset
;
962 /* If we don't overwrite a cacheline completely we need to be
963 * careful to have up-to-date data by first clflushing. Don't
964 * overcomplicate things and flush the entire patch. */
965 partial_cacheline_write
= needs_clflush_before
&&
966 ((shmem_page_offset
| page_length
)
967 & (boot_cpu_data
.x86_clflush_size
- 1));
969 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
970 (page_to_phys(page
) & (1 << 17)) != 0;
972 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
973 user_data
, page_do_bit17_swizzling
,
974 partial_cacheline_write
,
975 needs_clflush_after
);
980 mutex_unlock(&dev
->struct_mutex
);
981 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
982 user_data
, page_do_bit17_swizzling
,
983 partial_cacheline_write
,
984 needs_clflush_after
);
986 mutex_lock(&dev
->struct_mutex
);
992 remain
-= page_length
;
993 user_data
+= page_length
;
994 offset
+= page_length
;
998 i915_gem_object_unpin_pages(obj
);
1002 * Fixup: Flush cpu caches in case we didn't flush the dirty
1003 * cachelines in-line while writing and the object moved
1004 * out of the cpu write domain while we've dropped the lock.
1006 if (!needs_clflush_after
&&
1007 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1008 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1009 needs_clflush_after
= true;
1013 if (needs_clflush_after
)
1014 i915_gem_chipset_flush(dev
);
1016 obj
->cache_dirty
= true;
1018 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1023 * Writes data to the object referenced by handle.
1025 * On error, the contents of the buffer that were to be modified are undefined.
1028 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1029 struct drm_file
*file
)
1031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1032 struct drm_i915_gem_pwrite
*args
= data
;
1033 struct drm_i915_gem_object
*obj
;
1036 if (args
->size
== 0)
1039 if (!access_ok(VERIFY_READ
,
1040 to_user_ptr(args
->data_ptr
),
1044 if (likely(!i915
.prefault_disable
)) {
1045 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1051 intel_runtime_pm_get(dev_priv
);
1053 ret
= i915_mutex_lock_interruptible(dev
);
1057 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1058 if (&obj
->base
== NULL
) {
1063 /* Bounds check destination. */
1064 if (args
->offset
> obj
->base
.size
||
1065 args
->size
> obj
->base
.size
- args
->offset
) {
1070 /* prime objects have no backing filp to GEM pread/pwrite
1073 if (!obj
->base
.filp
) {
1078 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1081 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1082 * it would end up going through the fenced access, and we'll get
1083 * different detiling behavior between reading and writing.
1084 * pread/pwrite currently are reading and writing from the CPU
1085 * perspective, requiring manual detiling by the client.
1087 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1088 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1089 cpu_write_needs_clflush(obj
)) {
1090 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1091 /* Note that the gtt paths might fail with non-page-backed user
1092 * pointers (e.g. gtt mappings when moving data between
1093 * textures). Fallback to the shmem path in that case. */
1096 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1097 if (obj
->phys_handle
)
1098 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1100 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1104 drm_gem_object_unreference(&obj
->base
);
1106 mutex_unlock(&dev
->struct_mutex
);
1108 intel_runtime_pm_put(dev_priv
);
1114 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1117 if (i915_reset_in_progress(error
)) {
1118 /* Non-interruptible callers can't handle -EAGAIN, hence return
1119 * -EIO unconditionally for these. */
1123 /* Recovery complete, but the reset failed ... */
1124 if (i915_terminally_wedged(error
))
1128 * Check if GPU Reset is in progress - we need intel_ring_begin
1129 * to work properly to reinit the hw state while the gpu is
1130 * still marked as reset-in-progress. Handle this with a flag.
1132 if (!error
->reload_in_reset
)
1139 static void fake_irq(unsigned long data
)
1141 wake_up_process((struct task_struct
*)data
);
1144 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1145 struct intel_engine_cs
*engine
)
1147 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1150 static unsigned long local_clock_us(unsigned *cpu
)
1154 /* Cheaply and approximately convert from nanoseconds to microseconds.
1155 * The result and subsequent calculations are also defined in the same
1156 * approximate microseconds units. The principal source of timing
1157 * error here is from the simple truncation.
1159 * Note that local_clock() is only defined wrt to the current CPU;
1160 * the comparisons are no longer valid if we switch CPUs. Instead of
1161 * blocking preemption for the entire busywait, we can detect the CPU
1162 * switch and use that as indicator of system load and a reason to
1163 * stop busywaiting, see busywait_stop().
1166 t
= local_clock() >> 10;
1172 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1176 if (time_after(local_clock_us(&this_cpu
), timeout
))
1179 return this_cpu
!= cpu
;
1182 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1184 unsigned long timeout
;
1187 /* When waiting for high frequency requests, e.g. during synchronous
1188 * rendering split between the CPU and GPU, the finite amount of time
1189 * required to set up the irq and wait upon it limits the response
1190 * rate. By busywaiting on the request completion for a short while we
1191 * can service the high frequency waits as quick as possible. However,
1192 * if it is a slow request, we want to sleep as quickly as possible.
1193 * The tradeoff between waiting and sleeping is roughly the time it
1194 * takes to sleep on a request, on the order of a microsecond.
1197 if (req
->engine
->irq_refcount
)
1200 /* Only spin if we know the GPU is processing this request */
1201 if (!i915_gem_request_started(req
, true))
1204 timeout
= local_clock_us(&cpu
) + 5;
1205 while (!need_resched()) {
1206 if (i915_gem_request_completed(req
, true))
1209 if (signal_pending_state(state
, current
))
1212 if (busywait_stop(timeout
, cpu
))
1215 cpu_relax_lowlatency();
1218 if (i915_gem_request_completed(req
, false))
1225 * __i915_wait_request - wait until execution of request has finished
1227 * @reset_counter: reset sequence associated with the given request
1228 * @interruptible: do an interruptible wait (normally yes)
1229 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1231 * Note: It is of utmost importance that the passed in seqno and reset_counter
1232 * values have been read by the caller in an smp safe manner. Where read-side
1233 * locks are involved, it is sufficient to read the reset_counter before
1234 * unlocking the lock that protects the seqno. For lockless tricks, the
1235 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1238 * Returns 0 if the request was found within the alloted time. Else returns the
1239 * errno with remaining time filled in timeout argument.
1241 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1242 unsigned reset_counter
,
1245 struct intel_rps_client
*rps
)
1247 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1248 struct drm_device
*dev
= engine
->dev
;
1249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1250 const bool irq_test_in_progress
=
1251 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1252 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1254 unsigned long timeout_expire
;
1255 s64 before
= 0; /* Only to silence a compiler warning. */
1258 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1260 if (list_empty(&req
->list
))
1263 if (i915_gem_request_completed(req
, true))
1268 if (WARN_ON(*timeout
< 0))
1274 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1277 * Record current time in case interrupted by signal, or wedged.
1279 before
= ktime_get_raw_ns();
1282 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1283 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1285 trace_i915_gem_request_wait_begin(req
);
1287 /* Optimistic spin for the next jiffie before touching IRQs */
1288 ret
= __i915_spin_request(req
, state
);
1292 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1298 struct timer_list timer
;
1300 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1302 /* We need to check whether any gpu reset happened in between
1303 * the caller grabbing the seqno and now ... */
1304 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1305 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1306 * is truely gone. */
1307 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1313 if (i915_gem_request_completed(req
, false)) {
1318 if (signal_pending_state(state
, current
)) {
1323 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1328 timer
.function
= NULL
;
1329 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1330 unsigned long expire
;
1332 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1333 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1334 mod_timer(&timer
, expire
);
1339 if (timer
.function
) {
1340 del_singleshot_timer_sync(&timer
);
1341 destroy_timer_on_stack(&timer
);
1344 if (!irq_test_in_progress
)
1345 engine
->irq_put(engine
);
1347 finish_wait(&engine
->irq_queue
, &wait
);
1350 trace_i915_gem_request_wait_end(req
);
1353 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1355 *timeout
= tres
< 0 ? 0 : tres
;
1358 * Apparently ktime isn't accurate enough and occasionally has a
1359 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1360 * things up to make the test happy. We allow up to 1 jiffy.
1362 * This is a regrssion from the timespec->ktime conversion.
1364 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1371 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1372 struct drm_file
*file
)
1374 struct drm_i915_file_private
*file_priv
;
1376 WARN_ON(!req
|| !file
|| req
->file_priv
);
1384 file_priv
= file
->driver_priv
;
1386 spin_lock(&file_priv
->mm
.lock
);
1387 req
->file_priv
= file_priv
;
1388 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1389 spin_unlock(&file_priv
->mm
.lock
);
1391 req
->pid
= get_pid(task_pid(current
));
1397 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1399 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1404 spin_lock(&file_priv
->mm
.lock
);
1405 list_del(&request
->client_list
);
1406 request
->file_priv
= NULL
;
1407 spin_unlock(&file_priv
->mm
.lock
);
1409 put_pid(request
->pid
);
1410 request
->pid
= NULL
;
1413 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1415 trace_i915_gem_request_retire(request
);
1417 /* We know the GPU must have read the request to have
1418 * sent us the seqno + interrupt, so use the position
1419 * of tail of the request to update the last known position
1422 * Note this requires that we are always called in request
1425 request
->ringbuf
->last_retired_head
= request
->postfix
;
1427 list_del_init(&request
->list
);
1428 i915_gem_request_remove_from_client(request
);
1430 i915_gem_request_unreference(request
);
1434 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1436 struct intel_engine_cs
*engine
= req
->engine
;
1437 struct drm_i915_gem_request
*tmp
;
1439 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1441 if (list_empty(&req
->list
))
1445 tmp
= list_first_entry(&engine
->request_list
,
1446 typeof(*tmp
), list
);
1448 i915_gem_request_retire(tmp
);
1449 } while (tmp
!= req
);
1451 WARN_ON(i915_verify_lists(engine
->dev
));
1455 * Waits for a request to be signaled, and cleans up the
1456 * request and object lists appropriately for that event.
1459 i915_wait_request(struct drm_i915_gem_request
*req
)
1461 struct drm_device
*dev
;
1462 struct drm_i915_private
*dev_priv
;
1466 BUG_ON(req
== NULL
);
1468 dev
= req
->engine
->dev
;
1469 dev_priv
= dev
->dev_private
;
1470 interruptible
= dev_priv
->mm
.interruptible
;
1472 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1474 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1478 ret
= __i915_wait_request(req
,
1479 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1480 interruptible
, NULL
, NULL
);
1484 __i915_gem_request_retire__upto(req
);
1489 * Ensures that all rendering to the object has completed and the object is
1490 * safe to unbind from the GTT or access from the CPU.
1493 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1502 if (obj
->last_write_req
!= NULL
) {
1503 ret
= i915_wait_request(obj
->last_write_req
);
1507 i
= obj
->last_write_req
->engine
->id
;
1508 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1509 i915_gem_object_retire__read(obj
, i
);
1511 i915_gem_object_retire__write(obj
);
1514 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1515 if (obj
->last_read_req
[i
] == NULL
)
1518 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1522 i915_gem_object_retire__read(obj
, i
);
1524 RQ_BUG_ON(obj
->active
);
1531 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1532 struct drm_i915_gem_request
*req
)
1534 int ring
= req
->engine
->id
;
1536 if (obj
->last_read_req
[ring
] == req
)
1537 i915_gem_object_retire__read(obj
, ring
);
1538 else if (obj
->last_write_req
== req
)
1539 i915_gem_object_retire__write(obj
);
1541 __i915_gem_request_retire__upto(req
);
1544 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1545 * as the object state may change during this call.
1547 static __must_check
int
1548 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1549 struct intel_rps_client
*rps
,
1552 struct drm_device
*dev
= obj
->base
.dev
;
1553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1555 unsigned reset_counter
;
1558 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1559 BUG_ON(!dev_priv
->mm
.interruptible
);
1564 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1568 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1571 struct drm_i915_gem_request
*req
;
1573 req
= obj
->last_write_req
;
1577 requests
[n
++] = i915_gem_request_reference(req
);
1579 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1580 struct drm_i915_gem_request
*req
;
1582 req
= obj
->last_read_req
[i
];
1586 requests
[n
++] = i915_gem_request_reference(req
);
1590 mutex_unlock(&dev
->struct_mutex
);
1591 for (i
= 0; ret
== 0 && i
< n
; i
++)
1592 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1594 mutex_lock(&dev
->struct_mutex
);
1596 for (i
= 0; i
< n
; i
++) {
1598 i915_gem_object_retire_request(obj
, requests
[i
]);
1599 i915_gem_request_unreference(requests
[i
]);
1605 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1607 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1612 * Called when user space prepares to use an object with the CPU, either
1613 * through the mmap ioctl's mapping or a GTT mapping.
1616 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1617 struct drm_file
*file
)
1619 struct drm_i915_gem_set_domain
*args
= data
;
1620 struct drm_i915_gem_object
*obj
;
1621 uint32_t read_domains
= args
->read_domains
;
1622 uint32_t write_domain
= args
->write_domain
;
1625 /* Only handle setting domains to types used by the CPU. */
1626 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1629 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1632 /* Having something in the write domain implies it's in the read
1633 * domain, and only that read domain. Enforce that in the request.
1635 if (write_domain
!= 0 && read_domains
!= write_domain
)
1638 ret
= i915_mutex_lock_interruptible(dev
);
1642 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1643 if (&obj
->base
== NULL
) {
1648 /* Try to flush the object off the GPU without holding the lock.
1649 * We will repeat the flush holding the lock in the normal manner
1650 * to catch cases where we are gazumped.
1652 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1653 to_rps_client(file
),
1658 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1659 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1661 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1663 if (write_domain
!= 0)
1664 intel_fb_obj_invalidate(obj
,
1665 write_domain
== I915_GEM_DOMAIN_GTT
?
1666 ORIGIN_GTT
: ORIGIN_CPU
);
1669 drm_gem_object_unreference(&obj
->base
);
1671 mutex_unlock(&dev
->struct_mutex
);
1676 * Called when user space has done writes to this buffer
1679 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1680 struct drm_file
*file
)
1682 struct drm_i915_gem_sw_finish
*args
= data
;
1683 struct drm_i915_gem_object
*obj
;
1686 ret
= i915_mutex_lock_interruptible(dev
);
1690 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1691 if (&obj
->base
== NULL
) {
1696 /* Pinned buffers may be scanout, so flush the cache */
1697 if (obj
->pin_display
)
1698 i915_gem_object_flush_cpu_write_domain(obj
);
1700 drm_gem_object_unreference(&obj
->base
);
1702 mutex_unlock(&dev
->struct_mutex
);
1707 * Maps the contents of an object, returning the address it is mapped
1710 * While the mapping holds a reference on the contents of the object, it doesn't
1711 * imply a ref on the object itself.
1715 * DRM driver writers who look a this function as an example for how to do GEM
1716 * mmap support, please don't implement mmap support like here. The modern way
1717 * to implement DRM mmap support is with an mmap offset ioctl (like
1718 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1719 * That way debug tooling like valgrind will understand what's going on, hiding
1720 * the mmap call in a driver private ioctl will break that. The i915 driver only
1721 * does cpu mmaps this way because we didn't know better.
1724 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1725 struct drm_file
*file
)
1727 struct drm_i915_gem_mmap
*args
= data
;
1728 struct drm_gem_object
*obj
;
1731 if (args
->flags
& ~(I915_MMAP_WC
))
1734 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1737 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1741 /* prime objects have no backing filp to GEM mmap
1745 drm_gem_object_unreference_unlocked(obj
);
1749 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1750 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1752 if (args
->flags
& I915_MMAP_WC
) {
1753 struct mm_struct
*mm
= current
->mm
;
1754 struct vm_area_struct
*vma
;
1756 down_write(&mm
->mmap_sem
);
1757 vma
= find_vma(mm
, addr
);
1760 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1763 up_write(&mm
->mmap_sem
);
1765 drm_gem_object_unreference_unlocked(obj
);
1766 if (IS_ERR((void *)addr
))
1769 args
->addr_ptr
= (uint64_t) addr
;
1775 * i915_gem_fault - fault a page into the GTT
1776 * @vma: VMA in question
1779 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1780 * from userspace. The fault handler takes care of binding the object to
1781 * the GTT (if needed), allocating and programming a fence register (again,
1782 * only if needed based on whether the old reg is still valid or the object
1783 * is tiled) and inserting a new PTE into the faulting process.
1785 * Note that the faulting process may involve evicting existing objects
1786 * from the GTT and/or fence registers to make room. So performance may
1787 * suffer if the GTT working set is large or there are few fence registers
1790 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1792 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1793 struct drm_device
*dev
= obj
->base
.dev
;
1794 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1795 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1796 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1797 pgoff_t page_offset
;
1800 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1802 intel_runtime_pm_get(dev_priv
);
1804 /* We don't use vmf->pgoff since that has the fake offset */
1805 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1808 ret
= i915_mutex_lock_interruptible(dev
);
1812 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1814 /* Try to flush the object off the GPU first without holding the lock.
1815 * Upon reacquiring the lock, we will perform our sanity checks and then
1816 * repeat the flush holding the lock in the normal manner to catch cases
1817 * where we are gazumped.
1819 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1823 /* Access to snoopable pages through the GTT is incoherent. */
1824 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1829 /* Use a partial view if the object is bigger than the aperture. */
1830 if (obj
->base
.size
>= ggtt
->mappable_end
&&
1831 obj
->tiling_mode
== I915_TILING_NONE
) {
1832 static const unsigned int chunk_size
= 256; // 1 MiB
1834 memset(&view
, 0, sizeof(view
));
1835 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1836 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1837 view
.params
.partial
.size
=
1840 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1841 view
.params
.partial
.offset
);
1844 /* Now pin it into the GTT if needed */
1845 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1849 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1853 ret
= i915_gem_object_get_fence(obj
);
1857 /* Finally, remap it using the new GTT offset */
1858 pfn
= ggtt
->mappable_base
+
1859 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1862 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1863 /* Overriding existing pages in partial view does not cause
1864 * us any trouble as TLBs are still valid because the fault
1865 * is due to userspace losing part of the mapping or never
1866 * having accessed it before (at this partials' range).
1868 unsigned long base
= vma
->vm_start
+
1869 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1872 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1873 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1878 obj
->fault_mappable
= true;
1880 if (!obj
->fault_mappable
) {
1881 unsigned long size
= min_t(unsigned long,
1882 vma
->vm_end
- vma
->vm_start
,
1886 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1887 ret
= vm_insert_pfn(vma
,
1888 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1894 obj
->fault_mappable
= true;
1896 ret
= vm_insert_pfn(vma
,
1897 (unsigned long)vmf
->virtual_address
,
1901 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1903 mutex_unlock(&dev
->struct_mutex
);
1908 * We eat errors when the gpu is terminally wedged to avoid
1909 * userspace unduly crashing (gl has no provisions for mmaps to
1910 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1911 * and so needs to be reported.
1913 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1914 ret
= VM_FAULT_SIGBUS
;
1919 * EAGAIN means the gpu is hung and we'll wait for the error
1920 * handler to reset everything when re-faulting in
1921 * i915_mutex_lock_interruptible.
1928 * EBUSY is ok: this just means that another thread
1929 * already did the job.
1931 ret
= VM_FAULT_NOPAGE
;
1938 ret
= VM_FAULT_SIGBUS
;
1941 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1942 ret
= VM_FAULT_SIGBUS
;
1946 intel_runtime_pm_put(dev_priv
);
1951 * i915_gem_release_mmap - remove physical page mappings
1952 * @obj: obj in question
1954 * Preserve the reservation of the mmapping with the DRM core code, but
1955 * relinquish ownership of the pages back to the system.
1957 * It is vital that we remove the page mapping if we have mapped a tiled
1958 * object through the GTT and then lose the fence register due to
1959 * resource pressure. Similarly if the object has been moved out of the
1960 * aperture, than pages mapped into userspace must be revoked. Removing the
1961 * mapping will then trigger a page fault on the next user access, allowing
1962 * fixup by i915_gem_fault().
1965 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1967 if (!obj
->fault_mappable
)
1970 drm_vma_node_unmap(&obj
->base
.vma_node
,
1971 obj
->base
.dev
->anon_inode
->i_mapping
);
1972 obj
->fault_mappable
= false;
1976 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1978 struct drm_i915_gem_object
*obj
;
1980 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1981 i915_gem_release_mmap(obj
);
1985 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1989 if (INTEL_INFO(dev
)->gen
>= 4 ||
1990 tiling_mode
== I915_TILING_NONE
)
1993 /* Previous chips need a power-of-two fence region when tiling */
1994 if (INTEL_INFO(dev
)->gen
== 3)
1995 gtt_size
= 1024*1024;
1997 gtt_size
= 512*1024;
1999 while (gtt_size
< size
)
2006 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2007 * @obj: object to check
2009 * Return the required GTT alignment for an object, taking into account
2010 * potential fence register mapping.
2013 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2014 int tiling_mode
, bool fenced
)
2017 * Minimum alignment is 4k (GTT page size), but might be greater
2018 * if a fence register is needed for the object.
2020 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2021 tiling_mode
== I915_TILING_NONE
)
2025 * Previous chips need to be aligned to the size of the smallest
2026 * fence register that can contain the object.
2028 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2031 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2033 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2036 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2039 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2041 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2045 /* Badly fragmented mmap space? The only way we can recover
2046 * space is by destroying unwanted objects. We can't randomly release
2047 * mmap_offsets as userspace expects them to be persistent for the
2048 * lifetime of the objects. The closest we can is to release the
2049 * offsets on purgeable objects by truncating it and marking it purged,
2050 * which prevents userspace from ever using that object again.
2052 i915_gem_shrink(dev_priv
,
2053 obj
->base
.size
>> PAGE_SHIFT
,
2055 I915_SHRINK_UNBOUND
|
2056 I915_SHRINK_PURGEABLE
);
2057 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2061 i915_gem_shrink_all(dev_priv
);
2062 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2064 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2069 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2071 drm_gem_free_mmap_offset(&obj
->base
);
2075 i915_gem_mmap_gtt(struct drm_file
*file
,
2076 struct drm_device
*dev
,
2080 struct drm_i915_gem_object
*obj
;
2083 ret
= i915_mutex_lock_interruptible(dev
);
2087 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2088 if (&obj
->base
== NULL
) {
2093 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2094 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2099 ret
= i915_gem_object_create_mmap_offset(obj
);
2103 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2106 drm_gem_object_unreference(&obj
->base
);
2108 mutex_unlock(&dev
->struct_mutex
);
2113 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2115 * @data: GTT mapping ioctl data
2116 * @file: GEM object info
2118 * Simply returns the fake offset to userspace so it can mmap it.
2119 * The mmap call will end up in drm_gem_mmap(), which will set things
2120 * up so we can get faults in the handler above.
2122 * The fault handler will take care of binding the object into the GTT
2123 * (since it may have been evicted to make room for something), allocating
2124 * a fence register, and mapping the appropriate aperture address into
2128 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2129 struct drm_file
*file
)
2131 struct drm_i915_gem_mmap_gtt
*args
= data
;
2133 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2136 /* Immediately discard the backing storage */
2138 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2140 i915_gem_object_free_mmap_offset(obj
);
2142 if (obj
->base
.filp
== NULL
)
2145 /* Our goal here is to return as much of the memory as
2146 * is possible back to the system as we are called from OOM.
2147 * To do this we must instruct the shmfs to drop all of its
2148 * backing pages, *now*.
2150 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2151 obj
->madv
= __I915_MADV_PURGED
;
2154 /* Try to discard unwanted pages */
2156 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2158 struct address_space
*mapping
;
2160 switch (obj
->madv
) {
2161 case I915_MADV_DONTNEED
:
2162 i915_gem_object_truncate(obj
);
2163 case __I915_MADV_PURGED
:
2167 if (obj
->base
.filp
== NULL
)
2170 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2171 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2175 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2177 struct sg_page_iter sg_iter
;
2180 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2182 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2184 /* In the event of a disaster, abandon all caches and
2185 * hope for the best.
2187 WARN_ON(ret
!= -EIO
);
2188 i915_gem_clflush_object(obj
, true);
2189 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2192 i915_gem_gtt_finish_object(obj
);
2194 if (i915_gem_object_needs_bit17_swizzle(obj
))
2195 i915_gem_object_save_bit_17_swizzle(obj
);
2197 if (obj
->madv
== I915_MADV_DONTNEED
)
2200 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2201 struct page
*page
= sg_page_iter_page(&sg_iter
);
2204 set_page_dirty(page
);
2206 if (obj
->madv
== I915_MADV_WILLNEED
)
2207 mark_page_accessed(page
);
2209 page_cache_release(page
);
2213 sg_free_table(obj
->pages
);
2218 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2220 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2222 if (obj
->pages
== NULL
)
2225 if (obj
->pages_pin_count
)
2228 BUG_ON(i915_gem_obj_bound_any(obj
));
2230 /* ->put_pages might need to allocate memory for the bit17 swizzle
2231 * array, hence protect them from being reaped by removing them from gtt
2233 list_del(&obj
->global_list
);
2236 if (is_vmalloc_addr(obj
->mapping
))
2237 vunmap(obj
->mapping
);
2239 kunmap(kmap_to_page(obj
->mapping
));
2240 obj
->mapping
= NULL
;
2243 ops
->put_pages(obj
);
2246 i915_gem_object_invalidate(obj
);
2252 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2254 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2256 struct address_space
*mapping
;
2257 struct sg_table
*st
;
2258 struct scatterlist
*sg
;
2259 struct sg_page_iter sg_iter
;
2261 unsigned long last_pfn
= 0; /* suppress gcc warning */
2265 /* Assert that the object is not currently in any GPU domain. As it
2266 * wasn't in the GTT, there shouldn't be any way it could have been in
2269 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2270 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2272 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2276 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2277 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2282 /* Get the list of pages out of our struct file. They'll be pinned
2283 * at this point until we release them.
2285 * Fail silently without starting the shrinker
2287 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2288 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2289 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2292 for (i
= 0; i
< page_count
; i
++) {
2293 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2295 i915_gem_shrink(dev_priv
,
2298 I915_SHRINK_UNBOUND
|
2299 I915_SHRINK_PURGEABLE
);
2300 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2303 /* We've tried hard to allocate the memory by reaping
2304 * our own buffer, now let the real VM do its job and
2305 * go down in flames if truly OOM.
2307 i915_gem_shrink_all(dev_priv
);
2308 page
= shmem_read_mapping_page(mapping
, i
);
2310 ret
= PTR_ERR(page
);
2314 #ifdef CONFIG_SWIOTLB
2315 if (swiotlb_nr_tbl()) {
2317 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2322 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2326 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2328 sg
->length
+= PAGE_SIZE
;
2330 last_pfn
= page_to_pfn(page
);
2332 /* Check that the i965g/gm workaround works. */
2333 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2335 #ifdef CONFIG_SWIOTLB
2336 if (!swiotlb_nr_tbl())
2341 ret
= i915_gem_gtt_prepare_object(obj
);
2345 if (i915_gem_object_needs_bit17_swizzle(obj
))
2346 i915_gem_object_do_bit_17_swizzle(obj
);
2348 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2349 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2350 i915_gem_object_pin_pages(obj
);
2356 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2357 page_cache_release(sg_page_iter_page(&sg_iter
));
2361 /* shmemfs first checks if there is enough memory to allocate the page
2362 * and reports ENOSPC should there be insufficient, along with the usual
2363 * ENOMEM for a genuine allocation failure.
2365 * We use ENOSPC in our driver to mean that we have run out of aperture
2366 * space and so want to translate the error from shmemfs back to our
2367 * usual understanding of ENOMEM.
2375 /* Ensure that the associated pages are gathered from the backing storage
2376 * and pinned into our object. i915_gem_object_get_pages() may be called
2377 * multiple times before they are released by a single call to
2378 * i915_gem_object_put_pages() - once the pages are no longer referenced
2379 * either as a result of memory pressure (reaping pages under the shrinker)
2380 * or as the object is itself released.
2383 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2385 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2386 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2392 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2393 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2397 BUG_ON(obj
->pages_pin_count
);
2399 ret
= ops
->get_pages(obj
);
2403 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2405 obj
->get_page
.sg
= obj
->pages
->sgl
;
2406 obj
->get_page
.last
= 0;
2411 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2415 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2417 ret
= i915_gem_object_get_pages(obj
);
2419 return ERR_PTR(ret
);
2421 i915_gem_object_pin_pages(obj
);
2423 if (obj
->mapping
== NULL
) {
2424 struct page
**pages
;
2427 if (obj
->base
.size
== PAGE_SIZE
)
2428 obj
->mapping
= kmap(sg_page(obj
->pages
->sgl
));
2430 pages
= drm_malloc_gfp(obj
->base
.size
>> PAGE_SHIFT
,
2433 if (pages
!= NULL
) {
2434 struct sg_page_iter sg_iter
;
2438 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
,
2439 obj
->pages
->nents
, 0)
2440 pages
[n
++] = sg_page_iter_page(&sg_iter
);
2442 obj
->mapping
= vmap(pages
, n
, 0, PAGE_KERNEL
);
2443 drm_free_large(pages
);
2445 if (obj
->mapping
== NULL
) {
2446 i915_gem_object_unpin_pages(obj
);
2447 return ERR_PTR(-ENOMEM
);
2451 return obj
->mapping
;
2454 void i915_vma_move_to_active(struct i915_vma
*vma
,
2455 struct drm_i915_gem_request
*req
)
2457 struct drm_i915_gem_object
*obj
= vma
->obj
;
2458 struct intel_engine_cs
*engine
;
2460 engine
= i915_gem_request_get_engine(req
);
2462 /* Add a reference if we're newly entering the active list. */
2463 if (obj
->active
== 0)
2464 drm_gem_object_reference(&obj
->base
);
2465 obj
->active
|= intel_engine_flag(engine
);
2467 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2468 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2470 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2474 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2476 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2477 RQ_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2479 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2480 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2484 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2486 struct i915_vma
*vma
;
2488 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2489 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2491 list_del_init(&obj
->engine_list
[ring
]);
2492 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2494 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2495 i915_gem_object_retire__write(obj
);
2497 obj
->active
&= ~(1 << ring
);
2501 /* Bump our place on the bound list to keep it roughly in LRU order
2502 * so that we don't steal from recently used but inactive objects
2503 * (unless we are forced to ofc!)
2505 list_move_tail(&obj
->global_list
,
2506 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2508 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2509 if (!list_empty(&vma
->vm_link
))
2510 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2513 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2514 drm_gem_object_unreference(&obj
->base
);
2518 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 struct intel_engine_cs
*engine
;
2524 /* Carefully retire all requests without writing to the rings */
2525 for_each_engine(engine
, dev_priv
) {
2526 ret
= intel_engine_idle(engine
);
2530 i915_gem_retire_requests(dev
);
2532 /* Finally reset hw state */
2533 for_each_engine(engine
, dev_priv
)
2534 intel_ring_init_seqno(engine
, seqno
);
2539 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 /* HWS page needs to be set less than what we
2548 * will inject to ring
2550 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2554 /* Carefully set the last_seqno value so that wrap
2555 * detection still works
2557 dev_priv
->next_seqno
= seqno
;
2558 dev_priv
->last_seqno
= seqno
- 1;
2559 if (dev_priv
->last_seqno
== 0)
2560 dev_priv
->last_seqno
--;
2566 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2570 /* reserve 0 for non-seqno */
2571 if (dev_priv
->next_seqno
== 0) {
2572 int ret
= i915_gem_init_seqno(dev
, 0);
2576 dev_priv
->next_seqno
= 1;
2579 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2584 * NB: This function is not allowed to fail. Doing so would mean the the
2585 * request is not being tracked for completion but the work itself is
2586 * going to happen on the hardware. This would be a Bad Thing(tm).
2588 void __i915_add_request(struct drm_i915_gem_request
*request
,
2589 struct drm_i915_gem_object
*obj
,
2592 struct intel_engine_cs
*engine
;
2593 struct drm_i915_private
*dev_priv
;
2594 struct intel_ringbuffer
*ringbuf
;
2598 if (WARN_ON(request
== NULL
))
2601 engine
= request
->engine
;
2602 dev_priv
= request
->i915
;
2603 ringbuf
= request
->ringbuf
;
2606 * To ensure that this call will not fail, space for its emissions
2607 * should already have been reserved in the ring buffer. Let the ring
2608 * know that it is time to use that space up.
2610 intel_ring_reserved_space_use(ringbuf
);
2612 request_start
= intel_ring_get_tail(ringbuf
);
2614 * Emit any outstanding flushes - execbuf can fail to emit the flush
2615 * after having emitted the batchbuffer command. Hence we need to fix
2616 * things up similar to emitting the lazy request. The difference here
2617 * is that the flush _must_ happen before the next request, no matter
2621 if (i915
.enable_execlists
)
2622 ret
= logical_ring_flush_all_caches(request
);
2624 ret
= intel_ring_flush_all_caches(request
);
2625 /* Not allowed to fail! */
2626 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2629 trace_i915_gem_request_add(request
);
2631 request
->head
= request_start
;
2633 /* Whilst this request exists, batch_obj will be on the
2634 * active_list, and so will hold the active reference. Only when this
2635 * request is retired will the the batch_obj be moved onto the
2636 * inactive_list and lose its active reference. Hence we do not need
2637 * to explicitly hold another reference here.
2639 request
->batch_obj
= obj
;
2641 /* Seal the request and mark it as pending execution. Note that
2642 * we may inspect this state, without holding any locks, during
2643 * hangcheck. Hence we apply the barrier to ensure that we do not
2644 * see a more recent value in the hws than we are tracking.
2646 request
->emitted_jiffies
= jiffies
;
2647 request
->previous_seqno
= engine
->last_submitted_seqno
;
2648 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2649 list_add_tail(&request
->list
, &engine
->request_list
);
2651 /* Record the position of the start of the request so that
2652 * should we detect the updated seqno part-way through the
2653 * GPU processing the request, we never over-estimate the
2654 * position of the head.
2656 request
->postfix
= intel_ring_get_tail(ringbuf
);
2658 if (i915
.enable_execlists
)
2659 ret
= engine
->emit_request(request
);
2661 ret
= engine
->add_request(request
);
2663 request
->tail
= intel_ring_get_tail(ringbuf
);
2665 /* Not allowed to fail! */
2666 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2668 i915_queue_hangcheck(engine
->dev
);
2670 queue_delayed_work(dev_priv
->wq
,
2671 &dev_priv
->mm
.retire_work
,
2672 round_jiffies_up_relative(HZ
));
2673 intel_mark_busy(dev_priv
->dev
);
2675 /* Sanity check that the reserved size was large enough. */
2676 intel_ring_reserved_space_end(ringbuf
);
2679 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2680 const struct intel_context
*ctx
)
2682 unsigned long elapsed
;
2684 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2686 if (ctx
->hang_stats
.banned
)
2689 if (ctx
->hang_stats
.ban_period_seconds
&&
2690 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2691 if (!i915_gem_context_is_default(ctx
)) {
2692 DRM_DEBUG("context hanging too fast, banning!\n");
2694 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2695 if (i915_stop_ring_allow_warn(dev_priv
))
2696 DRM_ERROR("gpu hanging too fast, banning!\n");
2704 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2705 struct intel_context
*ctx
,
2708 struct i915_ctx_hang_stats
*hs
;
2713 hs
= &ctx
->hang_stats
;
2716 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2718 hs
->guilty_ts
= get_seconds();
2720 hs
->batch_pending
++;
2724 void i915_gem_request_free(struct kref
*req_ref
)
2726 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2728 struct intel_context
*ctx
= req
->ctx
;
2731 i915_gem_request_remove_from_client(req
);
2734 if (i915
.enable_execlists
&& ctx
!= req
->i915
->kernel_context
)
2735 intel_lr_context_unpin(ctx
, req
->engine
);
2737 i915_gem_context_unreference(ctx
);
2740 kmem_cache_free(req
->i915
->requests
, req
);
2744 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2745 struct intel_context
*ctx
,
2746 struct drm_i915_gem_request
**req_out
)
2748 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
2749 struct drm_i915_gem_request
*req
;
2757 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2761 ret
= i915_gem_get_seqno(engine
->dev
, &req
->seqno
);
2765 kref_init(&req
->ref
);
2766 req
->i915
= dev_priv
;
2767 req
->engine
= engine
;
2769 i915_gem_context_reference(req
->ctx
);
2771 if (i915
.enable_execlists
)
2772 ret
= intel_logical_ring_alloc_request_extras(req
);
2774 ret
= intel_ring_alloc_request_extras(req
);
2776 i915_gem_context_unreference(req
->ctx
);
2781 * Reserve space in the ring buffer for all the commands required to
2782 * eventually emit this request. This is to guarantee that the
2783 * i915_add_request() call can't fail. Note that the reserve may need
2784 * to be redone if the request is not actually submitted straight
2785 * away, e.g. because a GPU scheduler has deferred it.
2787 if (i915
.enable_execlists
)
2788 ret
= intel_logical_ring_reserve_space(req
);
2790 ret
= intel_ring_reserve_space(req
);
2793 * At this point, the request is fully allocated even if not
2794 * fully prepared. Thus it can be cleaned up using the proper
2797 i915_gem_request_cancel(req
);
2805 kmem_cache_free(dev_priv
->requests
, req
);
2810 * i915_gem_request_alloc - allocate a request structure
2812 * @engine: engine that we wish to issue the request on.
2813 * @ctx: context that the request will be associated with.
2814 * This can be NULL if the request is not directly related to
2815 * any specific user context, in which case this function will
2816 * choose an appropriate context to use.
2818 * Returns a pointer to the allocated request if successful,
2819 * or an error code if not.
2821 struct drm_i915_gem_request
*
2822 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2823 struct intel_context
*ctx
)
2825 struct drm_i915_gem_request
*req
;
2829 ctx
= to_i915(engine
->dev
)->kernel_context
;
2830 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
2831 return err
? ERR_PTR(err
) : req
;
2834 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2836 intel_ring_reserved_space_cancel(req
->ringbuf
);
2838 i915_gem_request_unreference(req
);
2841 struct drm_i915_gem_request
*
2842 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2844 struct drm_i915_gem_request
*request
;
2846 list_for_each_entry(request
, &engine
->request_list
, list
) {
2847 if (i915_gem_request_completed(request
, false))
2856 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
2857 struct intel_engine_cs
*engine
)
2859 struct drm_i915_gem_request
*request
;
2862 request
= i915_gem_find_active_request(engine
);
2864 if (request
== NULL
)
2867 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2869 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2871 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
2872 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2875 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
2876 struct intel_engine_cs
*engine
)
2878 struct intel_ringbuffer
*buffer
;
2880 while (!list_empty(&engine
->active_list
)) {
2881 struct drm_i915_gem_object
*obj
;
2883 obj
= list_first_entry(&engine
->active_list
,
2884 struct drm_i915_gem_object
,
2885 engine_list
[engine
->id
]);
2887 i915_gem_object_retire__read(obj
, engine
->id
);
2891 * Clear the execlists queue up before freeing the requests, as those
2892 * are the ones that keep the context and ringbuffer backing objects
2896 if (i915
.enable_execlists
) {
2897 /* Ensure irq handler finishes or is cancelled. */
2898 tasklet_kill(&engine
->irq_tasklet
);
2900 spin_lock_bh(&engine
->execlist_lock
);
2901 /* list_splice_tail_init checks for empty lists */
2902 list_splice_tail_init(&engine
->execlist_queue
,
2903 &engine
->execlist_retired_req_list
);
2904 spin_unlock_bh(&engine
->execlist_lock
);
2906 intel_execlists_retire_requests(engine
);
2910 * We must free the requests after all the corresponding objects have
2911 * been moved off active lists. Which is the same order as the normal
2912 * retire_requests function does. This is important if object hold
2913 * implicit references on things like e.g. ppgtt address spaces through
2916 while (!list_empty(&engine
->request_list
)) {
2917 struct drm_i915_gem_request
*request
;
2919 request
= list_first_entry(&engine
->request_list
,
2920 struct drm_i915_gem_request
,
2923 i915_gem_request_retire(request
);
2926 /* Having flushed all requests from all queues, we know that all
2927 * ringbuffers must now be empty. However, since we do not reclaim
2928 * all space when retiring the request (to prevent HEADs colliding
2929 * with rapid ringbuffer wraparound) the amount of available space
2930 * upon reset is less than when we start. Do one more pass over
2931 * all the ringbuffers to reset last_retired_head.
2933 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
2934 buffer
->last_retired_head
= buffer
->tail
;
2935 intel_ring_update_space(buffer
);
2938 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
2941 void i915_gem_reset(struct drm_device
*dev
)
2943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2944 struct intel_engine_cs
*engine
;
2947 * Before we free the objects from the requests, we need to inspect
2948 * them for finding the guilty party. As the requests only borrow
2949 * their reference to the objects, the inspection must be done first.
2951 for_each_engine(engine
, dev_priv
)
2952 i915_gem_reset_engine_status(dev_priv
, engine
);
2954 for_each_engine(engine
, dev_priv
)
2955 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
2957 i915_gem_context_reset(dev
);
2959 i915_gem_restore_fences(dev
);
2961 WARN_ON(i915_verify_lists(dev
));
2965 * This function clears the request list as sequence numbers are passed.
2968 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
2970 WARN_ON(i915_verify_lists(engine
->dev
));
2972 /* Retire requests first as we use it above for the early return.
2973 * If we retire requests last, we may use a later seqno and so clear
2974 * the requests lists without clearing the active list, leading to
2977 while (!list_empty(&engine
->request_list
)) {
2978 struct drm_i915_gem_request
*request
;
2980 request
= list_first_entry(&engine
->request_list
,
2981 struct drm_i915_gem_request
,
2984 if (!i915_gem_request_completed(request
, true))
2987 i915_gem_request_retire(request
);
2990 /* Move any buffers on the active list that are no longer referenced
2991 * by the ringbuffer to the flushing/inactive lists as appropriate,
2992 * before we free the context associated with the requests.
2994 while (!list_empty(&engine
->active_list
)) {
2995 struct drm_i915_gem_object
*obj
;
2997 obj
= list_first_entry(&engine
->active_list
,
2998 struct drm_i915_gem_object
,
2999 engine_list
[engine
->id
]);
3001 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
3004 i915_gem_object_retire__read(obj
, engine
->id
);
3007 if (unlikely(engine
->trace_irq_req
&&
3008 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
3009 engine
->irq_put(engine
);
3010 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3013 WARN_ON(i915_verify_lists(engine
->dev
));
3017 i915_gem_retire_requests(struct drm_device
*dev
)
3019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3020 struct intel_engine_cs
*engine
;
3023 for_each_engine(engine
, dev_priv
) {
3024 i915_gem_retire_requests_ring(engine
);
3025 idle
&= list_empty(&engine
->request_list
);
3026 if (i915
.enable_execlists
) {
3027 spin_lock_bh(&engine
->execlist_lock
);
3028 idle
&= list_empty(&engine
->execlist_queue
);
3029 spin_unlock_bh(&engine
->execlist_lock
);
3031 intel_execlists_retire_requests(engine
);
3036 mod_delayed_work(dev_priv
->wq
,
3037 &dev_priv
->mm
.idle_work
,
3038 msecs_to_jiffies(100));
3044 i915_gem_retire_work_handler(struct work_struct
*work
)
3046 struct drm_i915_private
*dev_priv
=
3047 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3048 struct drm_device
*dev
= dev_priv
->dev
;
3051 /* Come back later if the device is busy... */
3053 if (mutex_trylock(&dev
->struct_mutex
)) {
3054 idle
= i915_gem_retire_requests(dev
);
3055 mutex_unlock(&dev
->struct_mutex
);
3058 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3059 round_jiffies_up_relative(HZ
));
3063 i915_gem_idle_work_handler(struct work_struct
*work
)
3065 struct drm_i915_private
*dev_priv
=
3066 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3067 struct drm_device
*dev
= dev_priv
->dev
;
3068 struct intel_engine_cs
*engine
;
3070 for_each_engine(engine
, dev_priv
)
3071 if (!list_empty(&engine
->request_list
))
3074 /* we probably should sync with hangcheck here, using cancel_work_sync.
3075 * Also locking seems to be fubar here, engine->request_list is protected
3076 * by dev->struct_mutex. */
3078 intel_mark_idle(dev
);
3080 if (mutex_trylock(&dev
->struct_mutex
)) {
3081 for_each_engine(engine
, dev_priv
)
3082 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3084 mutex_unlock(&dev
->struct_mutex
);
3089 * Ensures that an object will eventually get non-busy by flushing any required
3090 * write domains, emitting any outstanding lazy request and retiring and
3091 * completed requests.
3094 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3101 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3102 struct drm_i915_gem_request
*req
;
3104 req
= obj
->last_read_req
[i
];
3108 if (list_empty(&req
->list
))
3111 if (i915_gem_request_completed(req
, true)) {
3112 __i915_gem_request_retire__upto(req
);
3114 i915_gem_object_retire__read(obj
, i
);
3122 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3123 * @DRM_IOCTL_ARGS: standard ioctl arguments
3125 * Returns 0 if successful, else an error is returned with the remaining time in
3126 * the timeout parameter.
3127 * -ETIME: object is still busy after timeout
3128 * -ERESTARTSYS: signal interrupted the wait
3129 * -ENONENT: object doesn't exist
3130 * Also possible, but rare:
3131 * -EAGAIN: GPU wedged
3133 * -ENODEV: Internal IRQ fail
3134 * -E?: The add request failed
3136 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3137 * non-zero timeout parameter the wait ioctl will wait for the given number of
3138 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3139 * without holding struct_mutex the object may become re-busied before this
3140 * function completes. A similar but shorter * race condition exists in the busy
3144 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3147 struct drm_i915_gem_wait
*args
= data
;
3148 struct drm_i915_gem_object
*obj
;
3149 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3150 unsigned reset_counter
;
3154 if (args
->flags
!= 0)
3157 ret
= i915_mutex_lock_interruptible(dev
);
3161 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3162 if (&obj
->base
== NULL
) {
3163 mutex_unlock(&dev
->struct_mutex
);
3167 /* Need to make sure the object gets inactive eventually. */
3168 ret
= i915_gem_object_flush_active(obj
);
3175 /* Do this after OLR check to make sure we make forward progress polling
3176 * on this IOCTL with a timeout == 0 (like busy ioctl)
3178 if (args
->timeout_ns
== 0) {
3183 drm_gem_object_unreference(&obj
->base
);
3184 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3186 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3187 if (obj
->last_read_req
[i
] == NULL
)
3190 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3193 mutex_unlock(&dev
->struct_mutex
);
3195 for (i
= 0; i
< n
; i
++) {
3197 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3198 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3199 to_rps_client(file
));
3200 i915_gem_request_unreference__unlocked(req
[i
]);
3205 drm_gem_object_unreference(&obj
->base
);
3206 mutex_unlock(&dev
->struct_mutex
);
3211 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3212 struct intel_engine_cs
*to
,
3213 struct drm_i915_gem_request
*from_req
,
3214 struct drm_i915_gem_request
**to_req
)
3216 struct intel_engine_cs
*from
;
3219 from
= i915_gem_request_get_engine(from_req
);
3223 if (i915_gem_request_completed(from_req
, true))
3226 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3227 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3228 ret
= __i915_wait_request(from_req
,
3229 atomic_read(&i915
->gpu_error
.reset_counter
),
3230 i915
->mm
.interruptible
,
3232 &i915
->rps
.semaphores
);
3236 i915_gem_object_retire_request(obj
, from_req
);
3238 int idx
= intel_ring_sync_index(from
, to
);
3239 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3243 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3246 if (*to_req
== NULL
) {
3247 struct drm_i915_gem_request
*req
;
3249 req
= i915_gem_request_alloc(to
, NULL
);
3251 return PTR_ERR(req
);
3256 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3257 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3261 /* We use last_read_req because sync_to()
3262 * might have just caused seqno wrap under
3265 from
->semaphore
.sync_seqno
[idx
] =
3266 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3273 * i915_gem_object_sync - sync an object to a ring.
3275 * @obj: object which may be in use on another ring.
3276 * @to: ring we wish to use the object on. May be NULL.
3277 * @to_req: request we wish to use the object for. See below.
3278 * This will be allocated and returned if a request is
3279 * required but not passed in.
3281 * This code is meant to abstract object synchronization with the GPU.
3282 * Calling with NULL implies synchronizing the object with the CPU
3283 * rather than a particular GPU ring. Conceptually we serialise writes
3284 * between engines inside the GPU. We only allow one engine to write
3285 * into a buffer at any time, but multiple readers. To ensure each has
3286 * a coherent view of memory, we must:
3288 * - If there is an outstanding write request to the object, the new
3289 * request must wait for it to complete (either CPU or in hw, requests
3290 * on the same ring will be naturally ordered).
3292 * - If we are a write request (pending_write_domain is set), the new
3293 * request must wait for outstanding read requests to complete.
3295 * For CPU synchronisation (NULL to) no request is required. For syncing with
3296 * rings to_req must be non-NULL. However, a request does not have to be
3297 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3298 * request will be allocated automatically and returned through *to_req. Note
3299 * that it is not guaranteed that commands will be emitted (because the system
3300 * might already be idle). Hence there is no need to create a request that
3301 * might never have any work submitted. Note further that if a request is
3302 * returned in *to_req, it is the responsibility of the caller to submit
3303 * that request (after potentially adding more work to it).
3305 * Returns 0 if successful, else propagates up the lower layer error.
3308 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3309 struct intel_engine_cs
*to
,
3310 struct drm_i915_gem_request
**to_req
)
3312 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3313 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3320 return i915_gem_object_wait_rendering(obj
, readonly
);
3324 if (obj
->last_write_req
)
3325 req
[n
++] = obj
->last_write_req
;
3327 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3328 if (obj
->last_read_req
[i
])
3329 req
[n
++] = obj
->last_read_req
[i
];
3331 for (i
= 0; i
< n
; i
++) {
3332 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3340 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3342 u32 old_write_domain
, old_read_domains
;
3344 /* Force a pagefault for domain tracking on next user access */
3345 i915_gem_release_mmap(obj
);
3347 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3350 /* Wait for any direct GTT access to complete */
3353 old_read_domains
= obj
->base
.read_domains
;
3354 old_write_domain
= obj
->base
.write_domain
;
3356 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3357 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3359 trace_i915_gem_object_change_domain(obj
,
3364 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3366 struct drm_i915_gem_object
*obj
= vma
->obj
;
3367 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3370 if (list_empty(&vma
->obj_link
))
3373 if (!drm_mm_node_allocated(&vma
->node
)) {
3374 i915_gem_vma_destroy(vma
);
3381 BUG_ON(obj
->pages
== NULL
);
3384 ret
= i915_gem_object_wait_rendering(obj
, false);
3389 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3390 i915_gem_object_finish_gtt(obj
);
3392 /* release the fence reg _after_ flushing */
3393 ret
= i915_gem_object_put_fence(obj
);
3398 trace_i915_vma_unbind(vma
);
3400 vma
->vm
->unbind_vma(vma
);
3403 list_del_init(&vma
->vm_link
);
3405 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3406 obj
->map_and_fenceable
= false;
3407 } else if (vma
->ggtt_view
.pages
) {
3408 sg_free_table(vma
->ggtt_view
.pages
);
3409 kfree(vma
->ggtt_view
.pages
);
3411 vma
->ggtt_view
.pages
= NULL
;
3414 drm_mm_remove_node(&vma
->node
);
3415 i915_gem_vma_destroy(vma
);
3417 /* Since the unbound list is global, only move to that list if
3418 * no more VMAs exist. */
3419 if (list_empty(&obj
->vma_list
))
3420 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3422 /* And finally now the object is completely decoupled from this vma,
3423 * we can drop its hold on the backing storage and allow it to be
3424 * reaped by the shrinker.
3426 i915_gem_object_unpin_pages(obj
);
3431 int i915_vma_unbind(struct i915_vma
*vma
)
3433 return __i915_vma_unbind(vma
, true);
3436 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3438 return __i915_vma_unbind(vma
, false);
3441 int i915_gpu_idle(struct drm_device
*dev
)
3443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3444 struct intel_engine_cs
*engine
;
3447 /* Flush everything onto the inactive list. */
3448 for_each_engine(engine
, dev_priv
) {
3449 if (!i915
.enable_execlists
) {
3450 struct drm_i915_gem_request
*req
;
3452 req
= i915_gem_request_alloc(engine
, NULL
);
3454 return PTR_ERR(req
);
3456 ret
= i915_switch_context(req
);
3458 i915_gem_request_cancel(req
);
3462 i915_add_request_no_flush(req
);
3465 ret
= intel_engine_idle(engine
);
3470 WARN_ON(i915_verify_lists(dev
));
3474 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3475 unsigned long cache_level
)
3477 struct drm_mm_node
*gtt_space
= &vma
->node
;
3478 struct drm_mm_node
*other
;
3481 * On some machines we have to be careful when putting differing types
3482 * of snoopable memory together to avoid the prefetcher crossing memory
3483 * domains and dying. During vm initialisation, we decide whether or not
3484 * these constraints apply and set the drm_mm.color_adjust
3487 if (vma
->vm
->mm
.color_adjust
== NULL
)
3490 if (!drm_mm_node_allocated(gtt_space
))
3493 if (list_empty(>t_space
->node_list
))
3496 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3497 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3500 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3501 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3508 * Finds free space in the GTT aperture and binds the object or a view of it
3511 static struct i915_vma
*
3512 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3513 struct i915_address_space
*vm
,
3514 const struct i915_ggtt_view
*ggtt_view
,
3518 struct drm_device
*dev
= obj
->base
.dev
;
3519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3520 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3521 u32 fence_alignment
, unfenced_alignment
;
3522 u32 search_flag
, alloc_flag
;
3524 u64 size
, fence_size
;
3525 struct i915_vma
*vma
;
3528 if (i915_is_ggtt(vm
)) {
3531 if (WARN_ON(!ggtt_view
))
3532 return ERR_PTR(-EINVAL
);
3534 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3536 fence_size
= i915_gem_get_gtt_size(dev
,
3539 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3543 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3547 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3549 fence_size
= i915_gem_get_gtt_size(dev
,
3552 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3556 unfenced_alignment
=
3557 i915_gem_get_gtt_alignment(dev
,
3561 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3564 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3566 if (flags
& PIN_MAPPABLE
)
3567 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3568 if (flags
& PIN_ZONE_4G
)
3569 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3572 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3574 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3575 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3576 ggtt_view
? ggtt_view
->type
: 0,
3578 return ERR_PTR(-EINVAL
);
3581 /* If binding the object/GGTT view requires more space than the entire
3582 * aperture has, reject it early before evicting everything in a vain
3583 * attempt to find space.
3586 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3587 ggtt_view
? ggtt_view
->type
: 0,
3589 flags
& PIN_MAPPABLE
? "mappable" : "total",
3591 return ERR_PTR(-E2BIG
);
3594 ret
= i915_gem_object_get_pages(obj
);
3596 return ERR_PTR(ret
);
3598 i915_gem_object_pin_pages(obj
);
3600 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3601 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3606 if (flags
& PIN_OFFSET_FIXED
) {
3607 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3609 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3613 vma
->node
.start
= offset
;
3614 vma
->node
.size
= size
;
3615 vma
->node
.color
= obj
->cache_level
;
3616 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3618 ret
= i915_gem_evict_for_vma(vma
);
3620 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3625 if (flags
& PIN_HIGH
) {
3626 search_flag
= DRM_MM_SEARCH_BELOW
;
3627 alloc_flag
= DRM_MM_CREATE_TOP
;
3629 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3630 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3634 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3641 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3651 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3653 goto err_remove_node
;
3656 trace_i915_vma_bind(vma
, flags
);
3657 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3659 goto err_remove_node
;
3661 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3662 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3667 drm_mm_remove_node(&vma
->node
);
3669 i915_gem_vma_destroy(vma
);
3672 i915_gem_object_unpin_pages(obj
);
3677 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3680 /* If we don't have a page list set up, then we're not pinned
3681 * to GPU, and we can ignore the cache flush because it'll happen
3682 * again at bind time.
3684 if (obj
->pages
== NULL
)
3688 * Stolen memory is always coherent with the GPU as it is explicitly
3689 * marked as wc by the system, or the system is cache-coherent.
3691 if (obj
->stolen
|| obj
->phys_handle
)
3694 /* If the GPU is snooping the contents of the CPU cache,
3695 * we do not need to manually clear the CPU cache lines. However,
3696 * the caches are only snooped when the render cache is
3697 * flushed/invalidated. As we always have to emit invalidations
3698 * and flushes when moving into and out of the RENDER domain, correct
3699 * snooping behaviour occurs naturally as the result of our domain
3702 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3703 obj
->cache_dirty
= true;
3707 trace_i915_gem_object_clflush(obj
);
3708 drm_clflush_sg(obj
->pages
);
3709 obj
->cache_dirty
= false;
3714 /** Flushes the GTT write domain for the object if it's dirty. */
3716 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3718 uint32_t old_write_domain
;
3720 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3723 /* No actual flushing is required for the GTT write domain. Writes
3724 * to it immediately go to main memory as far as we know, so there's
3725 * no chipset flush. It also doesn't land in render cache.
3727 * However, we do have to enforce the order so that all writes through
3728 * the GTT land before any writes to the device, such as updates to
3733 old_write_domain
= obj
->base
.write_domain
;
3734 obj
->base
.write_domain
= 0;
3736 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3738 trace_i915_gem_object_change_domain(obj
,
3739 obj
->base
.read_domains
,
3743 /** Flushes the CPU write domain for the object if it's dirty. */
3745 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3747 uint32_t old_write_domain
;
3749 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3752 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3753 i915_gem_chipset_flush(obj
->base
.dev
);
3755 old_write_domain
= obj
->base
.write_domain
;
3756 obj
->base
.write_domain
= 0;
3758 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3760 trace_i915_gem_object_change_domain(obj
,
3761 obj
->base
.read_domains
,
3766 * Moves a single object to the GTT read, and possibly write domain.
3768 * This function returns when the move is complete, including waiting on
3772 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3774 struct drm_device
*dev
= obj
->base
.dev
;
3775 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3776 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3777 uint32_t old_write_domain
, old_read_domains
;
3778 struct i915_vma
*vma
;
3781 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3784 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3788 /* Flush and acquire obj->pages so that we are coherent through
3789 * direct access in memory with previous cached writes through
3790 * shmemfs and that our cache domain tracking remains valid.
3791 * For example, if the obj->filp was moved to swap without us
3792 * being notified and releasing the pages, we would mistakenly
3793 * continue to assume that the obj remained out of the CPU cached
3796 ret
= i915_gem_object_get_pages(obj
);
3800 i915_gem_object_flush_cpu_write_domain(obj
);
3802 /* Serialise direct access to this object with the barriers for
3803 * coherent writes from the GPU, by effectively invalidating the
3804 * GTT domain upon first access.
3806 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3809 old_write_domain
= obj
->base
.write_domain
;
3810 old_read_domains
= obj
->base
.read_domains
;
3812 /* It should now be out of any other write domains, and we can update
3813 * the domain values for our changes.
3815 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3816 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3818 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3819 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3823 trace_i915_gem_object_change_domain(obj
,
3827 /* And bump the LRU for this access */
3828 vma
= i915_gem_obj_to_ggtt(obj
);
3829 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3830 list_move_tail(&vma
->vm_link
,
3831 &ggtt
->base
.inactive_list
);
3837 * Changes the cache-level of an object across all VMA.
3839 * After this function returns, the object will be in the new cache-level
3840 * across all GTT and the contents of the backing storage will be coherent,
3841 * with respect to the new cache-level. In order to keep the backing storage
3842 * coherent for all users, we only allow a single cache level to be set
3843 * globally on the object and prevent it from being changed whilst the
3844 * hardware is reading from the object. That is if the object is currently
3845 * on the scanout it will be set to uncached (or equivalent display
3846 * cache coherency) and all non-MOCS GPU access will also be uncached so
3847 * that all direct access to the scanout remains coherent.
3849 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3850 enum i915_cache_level cache_level
)
3852 struct drm_device
*dev
= obj
->base
.dev
;
3853 struct i915_vma
*vma
, *next
;
3857 if (obj
->cache_level
== cache_level
)
3860 /* Inspect the list of currently bound VMA and unbind any that would
3861 * be invalid given the new cache-level. This is principally to
3862 * catch the issue of the CS prefetch crossing page boundaries and
3863 * reading an invalid PTE on older architectures.
3865 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
3866 if (!drm_mm_node_allocated(&vma
->node
))
3869 if (vma
->pin_count
) {
3870 DRM_DEBUG("can not change the cache level of pinned objects\n");
3874 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3875 ret
= i915_vma_unbind(vma
);
3882 /* We can reuse the existing drm_mm nodes but need to change the
3883 * cache-level on the PTE. We could simply unbind them all and
3884 * rebind with the correct cache-level on next use. However since
3885 * we already have a valid slot, dma mapping, pages etc, we may as
3886 * rewrite the PTE in the belief that doing so tramples upon less
3887 * state and so involves less work.
3890 /* Before we change the PTE, the GPU must not be accessing it.
3891 * If we wait upon the object, we know that all the bound
3892 * VMA are no longer active.
3894 ret
= i915_gem_object_wait_rendering(obj
, false);
3898 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3899 /* Access to snoopable pages through the GTT is
3900 * incoherent and on some machines causes a hard
3901 * lockup. Relinquish the CPU mmaping to force
3902 * userspace to refault in the pages and we can
3903 * then double check if the GTT mapping is still
3904 * valid for that pointer access.
3906 i915_gem_release_mmap(obj
);
3908 /* As we no longer need a fence for GTT access,
3909 * we can relinquish it now (and so prevent having
3910 * to steal a fence from someone else on the next
3911 * fence request). Note GPU activity would have
3912 * dropped the fence as all snoopable access is
3913 * supposed to be linear.
3915 ret
= i915_gem_object_put_fence(obj
);
3919 /* We either have incoherent backing store and
3920 * so no GTT access or the architecture is fully
3921 * coherent. In such cases, existing GTT mmaps
3922 * ignore the cache bit in the PTE and we can
3923 * rewrite it without confusing the GPU or having
3924 * to force userspace to fault back in its mmaps.
3928 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3929 if (!drm_mm_node_allocated(&vma
->node
))
3932 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3938 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3939 vma
->node
.color
= cache_level
;
3940 obj
->cache_level
= cache_level
;
3943 /* Flush the dirty CPU caches to the backing storage so that the
3944 * object is now coherent at its new cache level (with respect
3945 * to the access domain).
3947 if (obj
->cache_dirty
&&
3948 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3949 cpu_write_needs_clflush(obj
)) {
3950 if (i915_gem_clflush_object(obj
, true))
3951 i915_gem_chipset_flush(obj
->base
.dev
);
3957 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3958 struct drm_file
*file
)
3960 struct drm_i915_gem_caching
*args
= data
;
3961 struct drm_i915_gem_object
*obj
;
3963 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3964 if (&obj
->base
== NULL
)
3967 switch (obj
->cache_level
) {
3968 case I915_CACHE_LLC
:
3969 case I915_CACHE_L3_LLC
:
3970 args
->caching
= I915_CACHING_CACHED
;
3974 args
->caching
= I915_CACHING_DISPLAY
;
3978 args
->caching
= I915_CACHING_NONE
;
3982 drm_gem_object_unreference_unlocked(&obj
->base
);
3986 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3987 struct drm_file
*file
)
3989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3990 struct drm_i915_gem_caching
*args
= data
;
3991 struct drm_i915_gem_object
*obj
;
3992 enum i915_cache_level level
;
3995 switch (args
->caching
) {
3996 case I915_CACHING_NONE
:
3997 level
= I915_CACHE_NONE
;
3999 case I915_CACHING_CACHED
:
4001 * Due to a HW issue on BXT A stepping, GPU stores via a
4002 * snooped mapping may leave stale data in a corresponding CPU
4003 * cacheline, whereas normally such cachelines would get
4006 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
4009 level
= I915_CACHE_LLC
;
4011 case I915_CACHING_DISPLAY
:
4012 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4018 intel_runtime_pm_get(dev_priv
);
4020 ret
= i915_mutex_lock_interruptible(dev
);
4024 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4025 if (&obj
->base
== NULL
) {
4030 ret
= i915_gem_object_set_cache_level(obj
, level
);
4032 drm_gem_object_unreference(&obj
->base
);
4034 mutex_unlock(&dev
->struct_mutex
);
4036 intel_runtime_pm_put(dev_priv
);
4042 * Prepare buffer for display plane (scanout, cursors, etc).
4043 * Can be called from an uninterruptible phase (modesetting) and allows
4044 * any flushes to be pipelined (for pageflips).
4047 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4049 const struct i915_ggtt_view
*view
)
4051 u32 old_read_domains
, old_write_domain
;
4054 /* Mark the pin_display early so that we account for the
4055 * display coherency whilst setting up the cache domains.
4059 /* The display engine is not coherent with the LLC cache on gen6. As
4060 * a result, we make sure that the pinning that is about to occur is
4061 * done with uncached PTEs. This is lowest common denominator for all
4064 * However for gen6+, we could do better by using the GFDT bit instead
4065 * of uncaching, which would allow us to flush all the LLC-cached data
4066 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4068 ret
= i915_gem_object_set_cache_level(obj
,
4069 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4071 goto err_unpin_display
;
4073 /* As the user may map the buffer once pinned in the display plane
4074 * (e.g. libkms for the bootup splash), we have to ensure that we
4075 * always use map_and_fenceable for all scanout buffers.
4077 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4078 view
->type
== I915_GGTT_VIEW_NORMAL
?
4081 goto err_unpin_display
;
4083 i915_gem_object_flush_cpu_write_domain(obj
);
4085 old_write_domain
= obj
->base
.write_domain
;
4086 old_read_domains
= obj
->base
.read_domains
;
4088 /* It should now be out of any other write domains, and we can update
4089 * the domain values for our changes.
4091 obj
->base
.write_domain
= 0;
4092 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4094 trace_i915_gem_object_change_domain(obj
,
4106 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4107 const struct i915_ggtt_view
*view
)
4109 if (WARN_ON(obj
->pin_display
== 0))
4112 i915_gem_object_ggtt_unpin_view(obj
, view
);
4118 * Moves a single object to the CPU read, and possibly write domain.
4120 * This function returns when the move is complete, including waiting on
4124 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4126 uint32_t old_write_domain
, old_read_domains
;
4129 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4132 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4136 i915_gem_object_flush_gtt_write_domain(obj
);
4138 old_write_domain
= obj
->base
.write_domain
;
4139 old_read_domains
= obj
->base
.read_domains
;
4141 /* Flush the CPU cache if it's still invalid. */
4142 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4143 i915_gem_clflush_object(obj
, false);
4145 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4148 /* It should now be out of any other write domains, and we can update
4149 * the domain values for our changes.
4151 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4153 /* If we're writing through the CPU, then the GPU read domains will
4154 * need to be invalidated at next use.
4157 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4158 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4161 trace_i915_gem_object_change_domain(obj
,
4168 /* Throttle our rendering by waiting until the ring has completed our requests
4169 * emitted over 20 msec ago.
4171 * Note that if we were to use the current jiffies each time around the loop,
4172 * we wouldn't escape the function with any frames outstanding if the time to
4173 * render a frame was over 20ms.
4175 * This should get us reasonable parallelism between CPU and GPU but also
4176 * relatively low latency when blocking on a particular request to finish.
4179 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4182 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4183 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4184 struct drm_i915_gem_request
*request
, *target
= NULL
;
4185 unsigned reset_counter
;
4188 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4192 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4196 spin_lock(&file_priv
->mm
.lock
);
4197 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4198 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4202 * Note that the request might not have been submitted yet.
4203 * In which case emitted_jiffies will be zero.
4205 if (!request
->emitted_jiffies
)
4210 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4212 i915_gem_request_reference(target
);
4213 spin_unlock(&file_priv
->mm
.lock
);
4218 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4220 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4222 i915_gem_request_unreference__unlocked(target
);
4228 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4230 struct drm_i915_gem_object
*obj
= vma
->obj
;
4233 vma
->node
.start
& (alignment
- 1))
4236 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4239 if (flags
& PIN_OFFSET_BIAS
&&
4240 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4243 if (flags
& PIN_OFFSET_FIXED
&&
4244 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4250 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4252 struct drm_i915_gem_object
*obj
= vma
->obj
;
4253 bool mappable
, fenceable
;
4254 u32 fence_size
, fence_alignment
;
4256 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4259 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4264 fenceable
= (vma
->node
.size
== fence_size
&&
4265 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4267 mappable
= (vma
->node
.start
+ fence_size
<=
4268 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4270 obj
->map_and_fenceable
= mappable
&& fenceable
;
4274 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4275 struct i915_address_space
*vm
,
4276 const struct i915_ggtt_view
*ggtt_view
,
4280 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4281 struct i915_vma
*vma
;
4285 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4288 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4291 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4294 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4297 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4298 i915_gem_obj_to_vma(obj
, vm
);
4301 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4304 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4305 WARN(vma
->pin_count
,
4306 "bo is already pinned in %s with incorrect alignment:"
4307 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4308 " obj->map_and_fenceable=%d\n",
4309 ggtt_view
? "ggtt" : "ppgtt",
4310 upper_32_bits(vma
->node
.start
),
4311 lower_32_bits(vma
->node
.start
),
4313 !!(flags
& PIN_MAPPABLE
),
4314 obj
->map_and_fenceable
);
4315 ret
= i915_vma_unbind(vma
);
4323 bound
= vma
? vma
->bound
: 0;
4324 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4325 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4328 return PTR_ERR(vma
);
4330 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4335 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4336 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4337 __i915_vma_set_map_and_fenceable(vma
);
4338 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4346 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4347 struct i915_address_space
*vm
,
4351 return i915_gem_object_do_pin(obj
, vm
,
4352 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4357 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4358 const struct i915_ggtt_view
*view
,
4362 struct drm_device
*dev
= obj
->base
.dev
;
4363 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4364 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4368 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4369 alignment
, flags
| PIN_GLOBAL
);
4373 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4374 const struct i915_ggtt_view
*view
)
4376 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4379 WARN_ON(vma
->pin_count
== 0);
4380 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4386 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4387 struct drm_file
*file
)
4389 struct drm_i915_gem_busy
*args
= data
;
4390 struct drm_i915_gem_object
*obj
;
4393 ret
= i915_mutex_lock_interruptible(dev
);
4397 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4398 if (&obj
->base
== NULL
) {
4403 /* Count all active objects as busy, even if they are currently not used
4404 * by the gpu. Users of this interface expect objects to eventually
4405 * become non-busy without any further actions, therefore emit any
4406 * necessary flushes here.
4408 ret
= i915_gem_object_flush_active(obj
);
4416 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4417 struct drm_i915_gem_request
*req
;
4419 req
= obj
->last_read_req
[i
];
4421 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4423 if (obj
->last_write_req
)
4424 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4428 drm_gem_object_unreference(&obj
->base
);
4430 mutex_unlock(&dev
->struct_mutex
);
4435 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4436 struct drm_file
*file_priv
)
4438 return i915_gem_ring_throttle(dev
, file_priv
);
4442 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4443 struct drm_file
*file_priv
)
4445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4446 struct drm_i915_gem_madvise
*args
= data
;
4447 struct drm_i915_gem_object
*obj
;
4450 switch (args
->madv
) {
4451 case I915_MADV_DONTNEED
:
4452 case I915_MADV_WILLNEED
:
4458 ret
= i915_mutex_lock_interruptible(dev
);
4462 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4463 if (&obj
->base
== NULL
) {
4468 if (i915_gem_obj_is_pinned(obj
)) {
4474 obj
->tiling_mode
!= I915_TILING_NONE
&&
4475 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4476 if (obj
->madv
== I915_MADV_WILLNEED
)
4477 i915_gem_object_unpin_pages(obj
);
4478 if (args
->madv
== I915_MADV_WILLNEED
)
4479 i915_gem_object_pin_pages(obj
);
4482 if (obj
->madv
!= __I915_MADV_PURGED
)
4483 obj
->madv
= args
->madv
;
4485 /* if the object is no longer attached, discard its backing storage */
4486 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4487 i915_gem_object_truncate(obj
);
4489 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4492 drm_gem_object_unreference(&obj
->base
);
4494 mutex_unlock(&dev
->struct_mutex
);
4498 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4499 const struct drm_i915_gem_object_ops
*ops
)
4503 INIT_LIST_HEAD(&obj
->global_list
);
4504 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4505 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4506 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4507 INIT_LIST_HEAD(&obj
->vma_list
);
4508 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4512 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4513 obj
->madv
= I915_MADV_WILLNEED
;
4515 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4518 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4519 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4520 .get_pages
= i915_gem_object_get_pages_gtt
,
4521 .put_pages
= i915_gem_object_put_pages_gtt
,
4524 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4527 struct drm_i915_gem_object
*obj
;
4528 struct address_space
*mapping
;
4531 obj
= i915_gem_object_alloc(dev
);
4535 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4536 i915_gem_object_free(obj
);
4540 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4541 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4542 /* 965gm cannot relocate objects above 4GiB. */
4543 mask
&= ~__GFP_HIGHMEM
;
4544 mask
|= __GFP_DMA32
;
4547 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4548 mapping_set_gfp_mask(mapping
, mask
);
4550 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4552 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4553 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4556 /* On some devices, we can have the GPU use the LLC (the CPU
4557 * cache) for about a 10% performance improvement
4558 * compared to uncached. Graphics requests other than
4559 * display scanout are coherent with the CPU in
4560 * accessing this cache. This means in this mode we
4561 * don't need to clflush on the CPU side, and on the
4562 * GPU side we only need to flush internal caches to
4563 * get data visible to the CPU.
4565 * However, we maintain the display planes as UC, and so
4566 * need to rebind when first used as such.
4568 obj
->cache_level
= I915_CACHE_LLC
;
4570 obj
->cache_level
= I915_CACHE_NONE
;
4572 trace_i915_gem_object_create(obj
);
4577 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4579 /* If we are the last user of the backing storage (be it shmemfs
4580 * pages or stolen etc), we know that the pages are going to be
4581 * immediately released. In this case, we can then skip copying
4582 * back the contents from the GPU.
4585 if (obj
->madv
!= I915_MADV_WILLNEED
)
4588 if (obj
->base
.filp
== NULL
)
4591 /* At first glance, this looks racy, but then again so would be
4592 * userspace racing mmap against close. However, the first external
4593 * reference to the filp can only be obtained through the
4594 * i915_gem_mmap_ioctl() which safeguards us against the user
4595 * acquiring such a reference whilst we are in the middle of
4596 * freeing the object.
4598 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4601 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4603 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4604 struct drm_device
*dev
= obj
->base
.dev
;
4605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4606 struct i915_vma
*vma
, *next
;
4608 intel_runtime_pm_get(dev_priv
);
4610 trace_i915_gem_object_destroy(obj
);
4612 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4616 ret
= i915_vma_unbind(vma
);
4617 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4618 bool was_interruptible
;
4620 was_interruptible
= dev_priv
->mm
.interruptible
;
4621 dev_priv
->mm
.interruptible
= false;
4623 WARN_ON(i915_vma_unbind(vma
));
4625 dev_priv
->mm
.interruptible
= was_interruptible
;
4629 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4630 * before progressing. */
4632 i915_gem_object_unpin_pages(obj
);
4634 WARN_ON(obj
->frontbuffer_bits
);
4636 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4637 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4638 obj
->tiling_mode
!= I915_TILING_NONE
)
4639 i915_gem_object_unpin_pages(obj
);
4641 if (WARN_ON(obj
->pages_pin_count
))
4642 obj
->pages_pin_count
= 0;
4643 if (discard_backing_storage(obj
))
4644 obj
->madv
= I915_MADV_DONTNEED
;
4645 i915_gem_object_put_pages(obj
);
4646 i915_gem_object_free_mmap_offset(obj
);
4650 if (obj
->base
.import_attach
)
4651 drm_prime_gem_destroy(&obj
->base
, NULL
);
4653 if (obj
->ops
->release
)
4654 obj
->ops
->release(obj
);
4656 drm_gem_object_release(&obj
->base
);
4657 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4660 i915_gem_object_free(obj
);
4662 intel_runtime_pm_put(dev_priv
);
4665 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4666 struct i915_address_space
*vm
)
4668 struct i915_vma
*vma
;
4669 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4670 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4677 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4678 const struct i915_ggtt_view
*view
)
4680 struct drm_device
*dev
= obj
->base
.dev
;
4681 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4682 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4683 struct i915_vma
*vma
;
4687 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4688 if (vma
->vm
== &ggtt
->base
&&
4689 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4694 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4696 WARN_ON(vma
->node
.allocated
);
4698 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4699 if (!list_empty(&vma
->exec_list
))
4703 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4705 list_del(&vma
->obj_link
);
4707 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4711 i915_gem_stop_engines(struct drm_device
*dev
)
4713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4714 struct intel_engine_cs
*engine
;
4716 for_each_engine(engine
, dev_priv
)
4717 dev_priv
->gt
.stop_engine(engine
);
4721 i915_gem_suspend(struct drm_device
*dev
)
4723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4726 mutex_lock(&dev
->struct_mutex
);
4727 ret
= i915_gpu_idle(dev
);
4731 i915_gem_retire_requests(dev
);
4733 i915_gem_stop_engines(dev
);
4734 mutex_unlock(&dev
->struct_mutex
);
4736 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4737 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4738 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4740 /* Assert that we sucessfully flushed all the work and
4741 * reset the GPU back to its idle, low power state.
4743 WARN_ON(dev_priv
->mm
.busy
);
4748 mutex_unlock(&dev
->struct_mutex
);
4752 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4754 struct intel_engine_cs
*engine
= req
->engine
;
4755 struct drm_device
*dev
= engine
->dev
;
4756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4757 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4760 if (!HAS_L3_DPF(dev
) || !remap_info
)
4763 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4768 * Note: We do not worry about the concurrent register cacheline hang
4769 * here because no other code should access these registers other than
4770 * at initialization time.
4772 for (i
= 0; i
< GEN7_L3LOG_SIZE
/ 4; i
++) {
4773 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
4774 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
4775 intel_ring_emit(engine
, remap_info
[i
]);
4778 intel_ring_advance(engine
);
4783 void i915_gem_init_swizzling(struct drm_device
*dev
)
4785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4787 if (INTEL_INFO(dev
)->gen
< 5 ||
4788 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4791 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4792 DISP_TILE_SURFACE_SWIZZLING
);
4797 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4799 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4800 else if (IS_GEN7(dev
))
4801 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4802 else if (IS_GEN8(dev
))
4803 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4808 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4812 I915_WRITE(RING_CTL(base
), 0);
4813 I915_WRITE(RING_HEAD(base
), 0);
4814 I915_WRITE(RING_TAIL(base
), 0);
4815 I915_WRITE(RING_START(base
), 0);
4818 static void init_unused_rings(struct drm_device
*dev
)
4821 init_unused_ring(dev
, PRB1_BASE
);
4822 init_unused_ring(dev
, SRB0_BASE
);
4823 init_unused_ring(dev
, SRB1_BASE
);
4824 init_unused_ring(dev
, SRB2_BASE
);
4825 init_unused_ring(dev
, SRB3_BASE
);
4826 } else if (IS_GEN2(dev
)) {
4827 init_unused_ring(dev
, SRB0_BASE
);
4828 init_unused_ring(dev
, SRB1_BASE
);
4829 } else if (IS_GEN3(dev
)) {
4830 init_unused_ring(dev
, PRB1_BASE
);
4831 init_unused_ring(dev
, PRB2_BASE
);
4835 int i915_gem_init_engines(struct drm_device
*dev
)
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4840 ret
= intel_init_render_ring_buffer(dev
);
4845 ret
= intel_init_bsd_ring_buffer(dev
);
4847 goto cleanup_render_ring
;
4851 ret
= intel_init_blt_ring_buffer(dev
);
4853 goto cleanup_bsd_ring
;
4856 if (HAS_VEBOX(dev
)) {
4857 ret
= intel_init_vebox_ring_buffer(dev
);
4859 goto cleanup_blt_ring
;
4862 if (HAS_BSD2(dev
)) {
4863 ret
= intel_init_bsd2_ring_buffer(dev
);
4865 goto cleanup_vebox_ring
;
4871 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
4873 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
4875 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
4876 cleanup_render_ring
:
4877 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
4883 i915_gem_init_hw(struct drm_device
*dev
)
4885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4886 struct intel_engine_cs
*engine
;
4889 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4892 /* Double layer security blanket, see i915_gem_init() */
4893 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4895 if (dev_priv
->ellc_size
)
4896 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4898 if (IS_HASWELL(dev
))
4899 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4900 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4902 if (HAS_PCH_NOP(dev
)) {
4903 if (IS_IVYBRIDGE(dev
)) {
4904 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4905 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4906 I915_WRITE(GEN7_MSG_CTL
, temp
);
4907 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4908 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4909 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4910 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4914 i915_gem_init_swizzling(dev
);
4917 * At least 830 can leave some of the unused rings
4918 * "active" (ie. head != tail) after resume which
4919 * will prevent c3 entry. Makes sure all unused rings
4922 init_unused_rings(dev
);
4924 BUG_ON(!dev_priv
->kernel_context
);
4926 ret
= i915_ppgtt_init_hw(dev
);
4928 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4932 /* Need to do basic initialisation of all rings first: */
4933 for_each_engine(engine
, dev_priv
) {
4934 ret
= engine
->init_hw(engine
);
4939 /* We can't enable contexts until all firmware is loaded */
4940 if (HAS_GUC_UCODE(dev
)) {
4941 ret
= intel_guc_ucode_load(dev
);
4943 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4950 * Increment the next seqno by 0x100 so we have a visible break
4951 * on re-initialisation
4953 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4957 /* Now it is safe to go back round and do everything else: */
4958 for_each_engine(engine
, dev_priv
) {
4959 struct drm_i915_gem_request
*req
;
4961 req
= i915_gem_request_alloc(engine
, NULL
);
4964 i915_gem_cleanup_engines(dev
);
4968 if (engine
->id
== RCS
) {
4969 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
4970 i915_gem_l3_remap(req
, j
);
4973 ret
= i915_ppgtt_init_ring(req
);
4974 if (ret
&& ret
!= -EIO
) {
4975 DRM_ERROR("PPGTT enable %s failed %d\n",
4977 i915_gem_request_cancel(req
);
4978 i915_gem_cleanup_engines(dev
);
4982 ret
= i915_gem_context_enable(req
);
4983 if (ret
&& ret
!= -EIO
) {
4984 DRM_ERROR("Context enable %s failed %d\n",
4986 i915_gem_request_cancel(req
);
4987 i915_gem_cleanup_engines(dev
);
4991 i915_add_request_no_flush(req
);
4995 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4999 int i915_gem_init(struct drm_device
*dev
)
5001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5004 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5005 i915
.enable_execlists
);
5007 mutex_lock(&dev
->struct_mutex
);
5009 if (!i915
.enable_execlists
) {
5010 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5011 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
5012 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
5013 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
5015 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5016 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
5017 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
5018 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
5021 /* This is just a security blanket to placate dragons.
5022 * On some systems, we very sporadically observe that the first TLBs
5023 * used by the CS may be stale, despite us poking the TLB reset. If
5024 * we hold the forcewake during initialisation these problems
5025 * just magically go away.
5027 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5029 ret
= i915_gem_init_userptr(dev
);
5033 i915_gem_init_ggtt(dev
);
5035 ret
= i915_gem_context_init(dev
);
5039 ret
= dev_priv
->gt
.init_engines(dev
);
5043 ret
= i915_gem_init_hw(dev
);
5045 /* Allow ring initialisation to fail by marking the GPU as
5046 * wedged. But we only want to do this where the GPU is angry,
5047 * for all other failure, such as an allocation failure, bail.
5049 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5050 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5055 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5056 mutex_unlock(&dev
->struct_mutex
);
5062 i915_gem_cleanup_engines(struct drm_device
*dev
)
5064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 struct intel_engine_cs
*engine
;
5067 for_each_engine(engine
, dev_priv
)
5068 dev_priv
->gt
.cleanup_engine(engine
);
5070 if (i915
.enable_execlists
)
5072 * Neither the BIOS, ourselves or any other kernel
5073 * expects the system to be in execlists mode on startup,
5074 * so we need to reset the GPU back to legacy mode.
5076 intel_gpu_reset(dev
, ALL_ENGINES
);
5080 init_engine_lists(struct intel_engine_cs
*engine
)
5082 INIT_LIST_HEAD(&engine
->active_list
);
5083 INIT_LIST_HEAD(&engine
->request_list
);
5087 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5089 struct drm_device
*dev
= dev_priv
->dev
;
5091 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5092 !IS_CHERRYVIEW(dev_priv
))
5093 dev_priv
->num_fence_regs
= 32;
5094 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5095 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5096 dev_priv
->num_fence_regs
= 16;
5098 dev_priv
->num_fence_regs
= 8;
5100 if (intel_vgpu_active(dev
))
5101 dev_priv
->num_fence_regs
=
5102 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5104 /* Initialize fence registers to zero */
5105 i915_gem_restore_fences(dev
);
5107 i915_gem_detect_bit_6_swizzle(dev
);
5111 i915_gem_load_init(struct drm_device
*dev
)
5113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5117 kmem_cache_create("i915_gem_object",
5118 sizeof(struct drm_i915_gem_object
), 0,
5122 kmem_cache_create("i915_gem_vma",
5123 sizeof(struct i915_vma
), 0,
5126 dev_priv
->requests
=
5127 kmem_cache_create("i915_gem_request",
5128 sizeof(struct drm_i915_gem_request
), 0,
5132 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5133 INIT_LIST_HEAD(&dev_priv
->context_list
);
5134 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5135 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5136 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5137 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5138 init_engine_lists(&dev_priv
->engine
[i
]);
5139 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5140 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5141 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5142 i915_gem_retire_work_handler
);
5143 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5144 i915_gem_idle_work_handler
);
5145 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5147 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5150 * Set initial sequence number for requests.
5151 * Using this number allows the wraparound to happen early,
5152 * catching any obvious problems.
5154 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5155 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5157 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5159 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5161 dev_priv
->mm
.interruptible
= true;
5163 mutex_init(&dev_priv
->fb_tracking
.lock
);
5166 void i915_gem_load_cleanup(struct drm_device
*dev
)
5168 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5170 kmem_cache_destroy(dev_priv
->requests
);
5171 kmem_cache_destroy(dev_priv
->vmas
);
5172 kmem_cache_destroy(dev_priv
->objects
);
5175 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5177 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5179 /* Clean up our request list when the client is going away, so that
5180 * later retire_requests won't dereference our soon-to-be-gone
5183 spin_lock(&file_priv
->mm
.lock
);
5184 while (!list_empty(&file_priv
->mm
.request_list
)) {
5185 struct drm_i915_gem_request
*request
;
5187 request
= list_first_entry(&file_priv
->mm
.request_list
,
5188 struct drm_i915_gem_request
,
5190 list_del(&request
->client_list
);
5191 request
->file_priv
= NULL
;
5193 spin_unlock(&file_priv
->mm
.lock
);
5195 if (!list_empty(&file_priv
->rps
.link
)) {
5196 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5197 list_del(&file_priv
->rps
.link
);
5198 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5202 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5204 struct drm_i915_file_private
*file_priv
;
5207 DRM_DEBUG_DRIVER("\n");
5209 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5213 file
->driver_priv
= file_priv
;
5214 file_priv
->dev_priv
= dev
->dev_private
;
5215 file_priv
->file
= file
;
5216 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5218 spin_lock_init(&file_priv
->mm
.lock
);
5219 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5221 file_priv
->bsd_ring
= -1;
5223 ret
= i915_gem_context_open(dev
, file
);
5231 * i915_gem_track_fb - update frontbuffer tracking
5232 * @old: current GEM buffer for the frontbuffer slots
5233 * @new: new GEM buffer for the frontbuffer slots
5234 * @frontbuffer_bits: bitmask of frontbuffer slots
5236 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5237 * from @old and setting them in @new. Both @old and @new can be NULL.
5239 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5240 struct drm_i915_gem_object
*new,
5241 unsigned frontbuffer_bits
)
5244 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5245 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5246 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5250 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5251 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5252 new->frontbuffer_bits
|= frontbuffer_bits
;
5256 /* All the new VM stuff */
5257 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5258 struct i915_address_space
*vm
)
5260 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5261 struct i915_vma
*vma
;
5263 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5265 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5267 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5270 return vma
->node
.start
;
5273 WARN(1, "%s vma for this object not found.\n",
5274 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5278 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5279 const struct i915_ggtt_view
*view
)
5281 struct drm_i915_private
*dev_priv
= to_i915(o
->base
.dev
);
5282 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5283 struct i915_vma
*vma
;
5285 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5286 if (vma
->vm
== &ggtt
->base
&&
5287 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5288 return vma
->node
.start
;
5290 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5294 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5295 struct i915_address_space
*vm
)
5297 struct i915_vma
*vma
;
5299 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5301 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5303 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5310 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5311 const struct i915_ggtt_view
*view
)
5313 struct drm_i915_private
*dev_priv
= to_i915(o
->base
.dev
);
5314 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5315 struct i915_vma
*vma
;
5317 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5318 if (vma
->vm
== &ggtt
->base
&&
5319 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5320 drm_mm_node_allocated(&vma
->node
))
5326 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5328 struct i915_vma
*vma
;
5330 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5331 if (drm_mm_node_allocated(&vma
->node
))
5337 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5338 struct i915_address_space
*vm
)
5340 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5341 struct i915_vma
*vma
;
5343 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5345 BUG_ON(list_empty(&o
->vma_list
));
5347 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5349 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5352 return vma
->node
.size
;
5357 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5359 struct i915_vma
*vma
;
5360 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5361 if (vma
->pin_count
> 0)
5367 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5369 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5373 /* Only default objects have per-page dirty tracking */
5374 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5377 page
= i915_gem_object_get_page(obj
, n
);
5378 set_page_dirty(page
);
5382 /* Allocate a new GEM object and fill it with the supplied data */
5383 struct drm_i915_gem_object
*
5384 i915_gem_object_create_from_data(struct drm_device
*dev
,
5385 const void *data
, size_t size
)
5387 struct drm_i915_gem_object
*obj
;
5388 struct sg_table
*sg
;
5392 obj
= i915_gem_alloc_object(dev
, round_up(size
, PAGE_SIZE
));
5393 if (IS_ERR_OR_NULL(obj
))
5396 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5400 ret
= i915_gem_object_get_pages(obj
);
5404 i915_gem_object_pin_pages(obj
);
5406 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5407 obj
->dirty
= 1; /* Backing store is now out of date */
5408 i915_gem_object_unpin_pages(obj
);
5410 if (WARN_ON(bytes
!= size
)) {
5411 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5419 drm_gem_object_unreference(&obj
->base
);
5420 return ERR_PTR(ret
);