2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->error_completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
167 args
->gtt_end
, args
->gtt_end
);
168 mutex_unlock(&dev
->struct_mutex
);
174 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
175 struct drm_file
*file
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_gem_get_aperture
*args
= data
;
179 struct drm_i915_gem_object
*obj
;
183 mutex_lock(&dev
->struct_mutex
);
184 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
186 pinned
+= obj
->gtt_space
->size
;
187 mutex_unlock(&dev
->struct_mutex
);
189 args
->aper_size
= dev_priv
->mm
.gtt_total
;
190 args
->aper_available_size
= args
->aper_size
- pinned
;
195 void *i915_gem_object_alloc(struct drm_device
*dev
)
197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
198 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
201 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
203 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
204 kmem_cache_free(dev_priv
->slab
, obj
);
208 i915_gem_create(struct drm_file
*file
,
209 struct drm_device
*dev
,
213 struct drm_i915_gem_object
*obj
;
217 size
= roundup(size
, PAGE_SIZE
);
221 /* Allocate the new object */
222 obj
= i915_gem_alloc_object(dev
, size
);
226 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
228 drm_gem_object_release(&obj
->base
);
229 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
230 i915_gem_object_free(obj
);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference(&obj
->base
);
236 trace_i915_gem_object_create(obj
);
243 i915_gem_dumb_create(struct drm_file
*file
,
244 struct drm_device
*dev
,
245 struct drm_mode_create_dumb
*args
)
247 /* have to work out size/pitch and return them */
248 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
249 args
->size
= args
->pitch
* args
->height
;
250 return i915_gem_create(file
, dev
,
251 args
->size
, &args
->handle
);
254 int i915_gem_dumb_destroy(struct drm_file
*file
,
255 struct drm_device
*dev
,
258 return drm_gem_handle_delete(file
, handle
);
262 * Creates a new mm object and returns a handle to it.
265 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
266 struct drm_file
*file
)
268 struct drm_i915_gem_create
*args
= data
;
270 return i915_gem_create(file
, dev
,
271 args
->size
, &args
->handle
);
275 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
276 const char *gpu_vaddr
, int gpu_offset
,
279 int ret
, cpu_offset
= 0;
282 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
283 int this_length
= min(cacheline_end
- gpu_offset
, length
);
284 int swizzled_gpu_offset
= gpu_offset
^ 64;
286 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
287 gpu_vaddr
+ swizzled_gpu_offset
,
292 cpu_offset
+= this_length
;
293 gpu_offset
+= this_length
;
294 length
-= this_length
;
301 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
302 const char __user
*cpu_vaddr
,
305 int ret
, cpu_offset
= 0;
308 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
309 int this_length
= min(cacheline_end
- gpu_offset
, length
);
310 int swizzled_gpu_offset
= gpu_offset
^ 64;
312 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
313 cpu_vaddr
+ cpu_offset
,
318 cpu_offset
+= this_length
;
319 gpu_offset
+= this_length
;
320 length
-= this_length
;
326 /* Per-page copy function for the shmem pread fastpath.
327 * Flushes invalid cachelines before reading the target if
328 * needs_clflush is set. */
330 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
331 char __user
*user_data
,
332 bool page_do_bit17_swizzling
, bool needs_clflush
)
337 if (unlikely(page_do_bit17_swizzling
))
340 vaddr
= kmap_atomic(page
);
342 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
344 ret
= __copy_to_user_inatomic(user_data
,
345 vaddr
+ shmem_page_offset
,
347 kunmap_atomic(vaddr
);
349 return ret
? -EFAULT
: 0;
353 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
356 if (unlikely(swizzled
)) {
357 unsigned long start
= (unsigned long) addr
;
358 unsigned long end
= (unsigned long) addr
+ length
;
360 /* For swizzling simply ensure that we always flush both
361 * channels. Lame, but simple and it works. Swizzled
362 * pwrite/pread is far from a hotpath - current userspace
363 * doesn't use it at all. */
364 start
= round_down(start
, 128);
365 end
= round_up(end
, 128);
367 drm_clflush_virt_range((void *)start
, end
- start
);
369 drm_clflush_virt_range(addr
, length
);
374 /* Only difference to the fast-path function is that this can handle bit17
375 * and uses non-atomic copy and kmap functions. */
377 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
378 char __user
*user_data
,
379 bool page_do_bit17_swizzling
, bool needs_clflush
)
386 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
388 page_do_bit17_swizzling
);
390 if (page_do_bit17_swizzling
)
391 ret
= __copy_to_user_swizzled(user_data
,
392 vaddr
, shmem_page_offset
,
395 ret
= __copy_to_user(user_data
,
396 vaddr
+ shmem_page_offset
,
400 return ret
? - EFAULT
: 0;
404 i915_gem_shmem_pread(struct drm_device
*dev
,
405 struct drm_i915_gem_object
*obj
,
406 struct drm_i915_gem_pread
*args
,
407 struct drm_file
*file
)
409 char __user
*user_data
;
412 int shmem_page_offset
, page_length
, ret
= 0;
413 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
415 int needs_clflush
= 0;
416 struct scatterlist
*sg
;
419 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
422 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
424 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
425 /* If we're not in the cpu read domain, set ourself into the gtt
426 * read domain and manually flush cachelines (if required). This
427 * optimizes for the case when the gpu will dirty the data
428 * anyway again before the next pread happens. */
429 if (obj
->cache_level
== I915_CACHE_NONE
)
431 if (obj
->gtt_space
) {
432 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
438 ret
= i915_gem_object_get_pages(obj
);
442 i915_gem_object_pin_pages(obj
);
444 offset
= args
->offset
;
446 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
449 if (i
< offset
>> PAGE_SHIFT
)
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset
= offset_in_page(offset
);
461 page_length
= remain
;
462 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
463 page_length
= PAGE_SIZE
- shmem_page_offset
;
466 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
467 (page_to_phys(page
) & (1 << 17)) != 0;
469 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
470 user_data
, page_do_bit17_swizzling
,
475 mutex_unlock(&dev
->struct_mutex
);
478 ret
= fault_in_multipages_writeable(user_data
, remain
);
479 /* Userspace is tricking us, but we've already clobbered
480 * its pages with the prefault and promised to write the
481 * data up to the first fault. Hence ignore any errors
482 * and just continue. */
487 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
488 user_data
, page_do_bit17_swizzling
,
491 mutex_lock(&dev
->struct_mutex
);
494 mark_page_accessed(page
);
499 remain
-= page_length
;
500 user_data
+= page_length
;
501 offset
+= page_length
;
505 i915_gem_object_unpin_pages(obj
);
511 * Reads data from the object referenced by handle.
513 * On error, the contents of *data are undefined.
516 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
517 struct drm_file
*file
)
519 struct drm_i915_gem_pread
*args
= data
;
520 struct drm_i915_gem_object
*obj
;
526 if (!access_ok(VERIFY_WRITE
,
527 (char __user
*)(uintptr_t)args
->data_ptr
,
531 ret
= i915_mutex_lock_interruptible(dev
);
535 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
536 if (&obj
->base
== NULL
) {
541 /* Bounds check source. */
542 if (args
->offset
> obj
->base
.size
||
543 args
->size
> obj
->base
.size
- args
->offset
) {
548 /* prime objects have no backing filp to GEM pread/pwrite
551 if (!obj
->base
.filp
) {
556 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
558 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
561 drm_gem_object_unreference(&obj
->base
);
563 mutex_unlock(&dev
->struct_mutex
);
567 /* This is the fast write path which cannot handle
568 * page faults in the source data
572 fast_user_write(struct io_mapping
*mapping
,
573 loff_t page_base
, int page_offset
,
574 char __user
*user_data
,
577 void __iomem
*vaddr_atomic
;
579 unsigned long unwritten
;
581 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
582 /* We can use the cpu mem copy function because this is X86. */
583 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
584 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
586 io_mapping_unmap_atomic(vaddr_atomic
);
591 * This is the fast pwrite path, where we copy the data directly from the
592 * user into the GTT, uncached.
595 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
596 struct drm_i915_gem_object
*obj
,
597 struct drm_i915_gem_pwrite
*args
,
598 struct drm_file
*file
)
600 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
602 loff_t offset
, page_base
;
603 char __user
*user_data
;
604 int page_offset
, page_length
, ret
;
606 ret
= i915_gem_object_pin(obj
, 0, true, true);
610 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
614 ret
= i915_gem_object_put_fence(obj
);
618 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
621 offset
= obj
->gtt_offset
+ args
->offset
;
624 /* Operation in this page
626 * page_base = page offset within aperture
627 * page_offset = offset within page
628 * page_length = bytes to copy for this page
630 page_base
= offset
& PAGE_MASK
;
631 page_offset
= offset_in_page(offset
);
632 page_length
= remain
;
633 if ((page_offset
+ remain
) > PAGE_SIZE
)
634 page_length
= PAGE_SIZE
- page_offset
;
636 /* If we get a fault while copying data, then (presumably) our
637 * source page isn't available. Return the error and we'll
638 * retry in the slow path.
640 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
641 page_offset
, user_data
, page_length
)) {
646 remain
-= page_length
;
647 user_data
+= page_length
;
648 offset
+= page_length
;
652 i915_gem_object_unpin(obj
);
657 /* Per-page copy function for the shmem pwrite fastpath.
658 * Flushes invalid cachelines before writing to the target if
659 * needs_clflush_before is set and flushes out any written cachelines after
660 * writing if needs_clflush is set. */
662 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
663 char __user
*user_data
,
664 bool page_do_bit17_swizzling
,
665 bool needs_clflush_before
,
666 bool needs_clflush_after
)
671 if (unlikely(page_do_bit17_swizzling
))
674 vaddr
= kmap_atomic(page
);
675 if (needs_clflush_before
)
676 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
678 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
681 if (needs_clflush_after
)
682 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
684 kunmap_atomic(vaddr
);
686 return ret
? -EFAULT
: 0;
689 /* Only difference to the fast-path function is that this can handle bit17
690 * and uses non-atomic copy and kmap functions. */
692 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
693 char __user
*user_data
,
694 bool page_do_bit17_swizzling
,
695 bool needs_clflush_before
,
696 bool needs_clflush_after
)
702 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
703 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
705 page_do_bit17_swizzling
);
706 if (page_do_bit17_swizzling
)
707 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
711 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
714 if (needs_clflush_after
)
715 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
717 page_do_bit17_swizzling
);
720 return ret
? -EFAULT
: 0;
724 i915_gem_shmem_pwrite(struct drm_device
*dev
,
725 struct drm_i915_gem_object
*obj
,
726 struct drm_i915_gem_pwrite
*args
,
727 struct drm_file
*file
)
731 char __user
*user_data
;
732 int shmem_page_offset
, page_length
, ret
= 0;
733 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
734 int hit_slowpath
= 0;
735 int needs_clflush_after
= 0;
736 int needs_clflush_before
= 0;
738 struct scatterlist
*sg
;
740 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
743 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
745 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
746 /* If we're not in the cpu write domain, set ourself into the gtt
747 * write domain and manually flush cachelines (if required). This
748 * optimizes for the case when the gpu will use the data
749 * right away and we therefore have to clflush anyway. */
750 if (obj
->cache_level
== I915_CACHE_NONE
)
751 needs_clflush_after
= 1;
752 if (obj
->gtt_space
) {
753 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
758 /* Same trick applies for invalidate partially written cachelines before
760 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
761 && obj
->cache_level
== I915_CACHE_NONE
)
762 needs_clflush_before
= 1;
764 ret
= i915_gem_object_get_pages(obj
);
768 i915_gem_object_pin_pages(obj
);
770 offset
= args
->offset
;
773 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
775 int partial_cacheline_write
;
777 if (i
< offset
>> PAGE_SHIFT
)
783 /* Operation in this page
785 * shmem_page_offset = offset within page in shmem file
786 * page_length = bytes to copy for this page
788 shmem_page_offset
= offset_in_page(offset
);
790 page_length
= remain
;
791 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
792 page_length
= PAGE_SIZE
- shmem_page_offset
;
794 /* If we don't overwrite a cacheline completely we need to be
795 * careful to have up-to-date data by first clflushing. Don't
796 * overcomplicate things and flush the entire patch. */
797 partial_cacheline_write
= needs_clflush_before
&&
798 ((shmem_page_offset
| page_length
)
799 & (boot_cpu_data
.x86_clflush_size
- 1));
802 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
803 (page_to_phys(page
) & (1 << 17)) != 0;
805 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
806 user_data
, page_do_bit17_swizzling
,
807 partial_cacheline_write
,
808 needs_clflush_after
);
813 mutex_unlock(&dev
->struct_mutex
);
814 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
815 user_data
, page_do_bit17_swizzling
,
816 partial_cacheline_write
,
817 needs_clflush_after
);
819 mutex_lock(&dev
->struct_mutex
);
822 set_page_dirty(page
);
823 mark_page_accessed(page
);
828 remain
-= page_length
;
829 user_data
+= page_length
;
830 offset
+= page_length
;
834 i915_gem_object_unpin_pages(obj
);
838 * Fixup: Flush cpu caches in case we didn't flush the dirty
839 * cachelines in-line while writing and the object moved
840 * out of the cpu write domain while we've dropped the lock.
842 if (!needs_clflush_after
&&
843 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
844 i915_gem_clflush_object(obj
);
845 i915_gem_chipset_flush(dev
);
849 if (needs_clflush_after
)
850 i915_gem_chipset_flush(dev
);
856 * Writes data to the object referenced by handle.
858 * On error, the contents of the buffer that were to be modified are undefined.
861 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
862 struct drm_file
*file
)
864 struct drm_i915_gem_pwrite
*args
= data
;
865 struct drm_i915_gem_object
*obj
;
871 if (!access_ok(VERIFY_READ
,
872 (char __user
*)(uintptr_t)args
->data_ptr
,
876 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
881 ret
= i915_mutex_lock_interruptible(dev
);
885 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
886 if (&obj
->base
== NULL
) {
891 /* Bounds check destination. */
892 if (args
->offset
> obj
->base
.size
||
893 args
->size
> obj
->base
.size
- args
->offset
) {
898 /* prime objects have no backing filp to GEM pread/pwrite
901 if (!obj
->base
.filp
) {
906 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
909 /* We can only do the GTT pwrite on untiled buffers, as otherwise
910 * it would end up going through the fenced access, and we'll get
911 * different detiling behavior between reading and writing.
912 * pread/pwrite currently are reading and writing from the CPU
913 * perspective, requiring manual detiling by the client.
916 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
920 if (obj
->cache_level
== I915_CACHE_NONE
&&
921 obj
->tiling_mode
== I915_TILING_NONE
&&
922 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
923 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
924 /* Note that the gtt paths might fail with non-page-backed user
925 * pointers (e.g. gtt mappings when moving data between
926 * textures). Fallback to the shmem path in that case. */
929 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
930 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
933 drm_gem_object_unreference(&obj
->base
);
935 mutex_unlock(&dev
->struct_mutex
);
940 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
943 if (atomic_read(&dev_priv
->mm
.wedged
)) {
944 struct completion
*x
= &dev_priv
->error_completion
;
945 bool recovery_complete
;
948 /* Give the error handler a chance to run. */
949 spin_lock_irqsave(&x
->wait
.lock
, flags
);
950 recovery_complete
= x
->done
> 0;
951 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but still wedged means reset failure. */
959 if (recovery_complete
)
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
977 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
980 if (seqno
== ring
->outstanding_lazy_request
)
981 ret
= i915_add_request(ring
, NULL
, NULL
);
987 * __wait_seqno - wait until execution of seqno has finished
988 * @ring: the ring expected to report seqno
990 * @interruptible: do an interruptible wait (normally yes)
991 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
993 * Returns 0 if the seqno was found within the alloted time. Else returns the
994 * errno with remaining time filled in timeout argument.
996 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
997 bool interruptible
, struct timespec
*timeout
)
999 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1000 struct timespec before
, now
, wait_time
={1,0};
1001 unsigned long timeout_jiffies
;
1003 bool wait_forever
= true;
1006 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1009 trace_i915_gem_request_wait_begin(ring
, seqno
);
1011 if (timeout
!= NULL
) {
1012 wait_time
= *timeout
;
1013 wait_forever
= false;
1016 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1018 if (WARN_ON(!ring
->irq_get(ring
)))
1021 /* Record current time in case interrupted by signal, or wedged * */
1022 getrawmonotonic(&before
);
1025 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026 atomic_read(&dev_priv->mm.wedged))
1029 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1033 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1036 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1039 } while (end
== 0 && wait_forever
);
1041 getrawmonotonic(&now
);
1043 ring
->irq_put(ring
);
1044 trace_i915_gem_request_wait_end(ring
, seqno
);
1048 struct timespec sleep_time
= timespec_sub(now
, before
);
1049 *timeout
= timespec_sub(*timeout
, sleep_time
);
1054 case -EAGAIN
: /* Wedged */
1055 case -ERESTARTSYS
: /* Signal */
1057 case 0: /* Timeout */
1059 set_normalized_timespec(timeout
, 0, 0);
1061 default: /* Completed */
1062 WARN_ON(end
< 0); /* We're not aware of other errors */
1068 * Waits for a sequence number to be signaled, and cleans up the
1069 * request and object lists appropriately for that event.
1072 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1074 struct drm_device
*dev
= ring
->dev
;
1075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1076 bool interruptible
= dev_priv
->mm
.interruptible
;
1079 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1082 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1086 ret
= i915_gem_check_olr(ring
, seqno
);
1090 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check
int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1101 struct intel_ring_buffer
*ring
= obj
->ring
;
1105 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1109 ret
= i915_wait_seqno(ring
, seqno
);
1113 i915_gem_retire_requests_ring(ring
);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj
->last_write_seqno
&&
1119 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1120 obj
->last_write_seqno
= 0;
1121 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check
int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1134 struct drm_device
*dev
= obj
->base
.dev
;
1135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1136 struct intel_ring_buffer
*ring
= obj
->ring
;
1140 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1141 BUG_ON(!dev_priv
->mm
.interruptible
);
1143 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1147 ret
= i915_gem_check_wedge(dev_priv
, true);
1151 ret
= i915_gem_check_olr(ring
, seqno
);
1155 mutex_unlock(&dev
->struct_mutex
);
1156 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1157 mutex_lock(&dev
->struct_mutex
);
1159 i915_gem_retire_requests_ring(ring
);
1161 /* Manually manage the write flush as we may have not yet
1162 * retired the buffer.
1164 if (obj
->last_write_seqno
&&
1165 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1166 obj
->last_write_seqno
= 0;
1167 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1179 struct drm_file
*file
)
1181 struct drm_i915_gem_set_domain
*args
= data
;
1182 struct drm_i915_gem_object
*obj
;
1183 uint32_t read_domains
= args
->read_domains
;
1184 uint32_t write_domain
= args
->write_domain
;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1191 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain
!= 0 && read_domains
!= write_domain
)
1200 ret
= i915_mutex_lock_interruptible(dev
);
1204 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1205 if (&obj
->base
== NULL
) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1218 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1219 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1232 drm_gem_object_unreference(&obj
->base
);
1234 mutex_unlock(&dev
->struct_mutex
);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1243 struct drm_file
*file
)
1245 struct drm_i915_gem_sw_finish
*args
= data
;
1246 struct drm_i915_gem_object
*obj
;
1249 ret
= i915_mutex_lock_interruptible(dev
);
1253 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1254 if (&obj
->base
== NULL
) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj
);
1263 drm_gem_object_unreference(&obj
->base
);
1265 mutex_unlock(&dev
->struct_mutex
);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1278 struct drm_file
*file
)
1280 struct drm_i915_gem_mmap
*args
= data
;
1281 struct drm_gem_object
*obj
;
1284 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj
);
1296 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1297 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1299 drm_gem_object_unreference_unlocked(obj
);
1300 if (IS_ERR((void *)addr
))
1303 args
->addr_ptr
= (uint64_t) addr
;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1326 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1327 struct drm_device
*dev
= obj
->base
.dev
;
1328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1329 pgoff_t page_offset
;
1332 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1338 ret
= i915_mutex_lock_interruptible(dev
);
1342 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1350 /* Now bind it into the GTT if needed */
1351 ret
= i915_gem_object_pin(obj
, 0, true, false);
1355 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1359 ret
= i915_gem_object_get_fence(obj
);
1363 obj
->fault_mappable
= true;
1365 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1368 /* Finally, remap it using the new GTT offset */
1369 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1371 i915_gem_object_unpin(obj
);
1373 mutex_unlock(&dev
->struct_mutex
);
1377 /* If this -EIO is due to a gpu hang, give the reset code a
1378 * chance to clean up the mess. Otherwise return the proper
1380 if (!atomic_read(&dev_priv
->mm
.wedged
))
1381 return VM_FAULT_SIGBUS
;
1383 /* Give the error handler a chance to run and move the
1384 * objects off the GPU active list. Next time we service the
1385 * fault, we should be able to transition the page into the
1386 * GTT without touching the GPU (and so avoid further
1387 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1388 * with coherency, just lost writes.
1396 * EBUSY is ok: this just means that another thread
1397 * already did the job.
1399 return VM_FAULT_NOPAGE
;
1401 return VM_FAULT_OOM
;
1403 return VM_FAULT_SIGBUS
;
1405 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1406 return VM_FAULT_SIGBUS
;
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1427 if (!obj
->fault_mappable
)
1430 if (obj
->base
.dev
->dev_mapping
)
1431 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1432 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1435 obj
->fault_mappable
= false;
1439 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1443 if (INTEL_INFO(dev
)->gen
>= 4 ||
1444 tiling_mode
== I915_TILING_NONE
)
1447 /* Previous chips need a power-of-two fence region when tiling */
1448 if (INTEL_INFO(dev
)->gen
== 3)
1449 gtt_size
= 1024*1024;
1451 gtt_size
= 512*1024;
1453 while (gtt_size
< size
)
1460 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1461 * @obj: object to check
1463 * Return the required GTT alignment for an object, taking into account
1464 * potential fence register mapping.
1467 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev
)->gen
>= 4 ||
1476 tiling_mode
== I915_TILING_NONE
)
1480 * Previous chips need to be aligned to the size of the smallest
1481 * fence register that can contain the object.
1483 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1487 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1490 * @size: size of the object
1491 * @tiling_mode: tiling mode of the object
1493 * Return the required GTT alignment for an object, only taking into account
1494 * unfenced tiled surface requirements.
1497 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1502 * Minimum alignment is 4k (GTT page size) for sane hw.
1504 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1505 tiling_mode
== I915_TILING_NONE
)
1508 /* Previous hardware however needs to be aligned to a power-of-two
1509 * tile height. The simplest method for determining this is to reuse
1510 * the power-of-tile object size.
1512 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1515 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1517 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1520 if (obj
->base
.map_list
.map
)
1523 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1527 /* Badly fragmented mmap space? The only way we can recover
1528 * space is by destroying unwanted objects. We can't randomly release
1529 * mmap_offsets as userspace expects them to be persistent for the
1530 * lifetime of the objects. The closest we can is to release the
1531 * offsets on purgeable objects by truncating it and marking it purged,
1532 * which prevents userspace from ever using that object again.
1534 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1535 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1539 i915_gem_shrink_all(dev_priv
);
1540 return drm_gem_create_mmap_offset(&obj
->base
);
1543 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1545 if (!obj
->base
.map_list
.map
)
1548 drm_gem_free_mmap_offset(&obj
->base
);
1552 i915_gem_mmap_gtt(struct drm_file
*file
,
1553 struct drm_device
*dev
,
1557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1558 struct drm_i915_gem_object
*obj
;
1561 ret
= i915_mutex_lock_interruptible(dev
);
1565 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1566 if (&obj
->base
== NULL
) {
1571 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1576 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1577 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1582 ret
= i915_gem_object_create_mmap_offset(obj
);
1586 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1589 drm_gem_object_unreference(&obj
->base
);
1591 mutex_unlock(&dev
->struct_mutex
);
1596 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1598 * @data: GTT mapping ioctl data
1599 * @file: GEM object info
1601 * Simply returns the fake offset to userspace so it can mmap it.
1602 * The mmap call will end up in drm_gem_mmap(), which will set things
1603 * up so we can get faults in the handler above.
1605 * The fault handler will take care of binding the object into the GTT
1606 * (since it may have been evicted to make room for something), allocating
1607 * a fence register, and mapping the appropriate aperture address into
1611 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1612 struct drm_file
*file
)
1614 struct drm_i915_gem_mmap_gtt
*args
= data
;
1616 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1619 /* Immediately discard the backing storage */
1621 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1623 struct inode
*inode
;
1625 i915_gem_object_free_mmap_offset(obj
);
1627 if (obj
->base
.filp
== NULL
)
1630 /* Our goal here is to return as much of the memory as
1631 * is possible back to the system as we are called from OOM.
1632 * To do this we must instruct the shmfs to drop all of its
1633 * backing pages, *now*.
1635 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1636 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1638 obj
->madv
= __I915_MADV_PURGED
;
1642 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1644 return obj
->madv
== I915_MADV_DONTNEED
;
1648 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1650 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1651 struct scatterlist
*sg
;
1654 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1656 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1658 /* In the event of a disaster, abandon all caches and
1659 * hope for the best.
1661 WARN_ON(ret
!= -EIO
);
1662 i915_gem_clflush_object(obj
);
1663 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1666 if (i915_gem_object_needs_bit17_swizzle(obj
))
1667 i915_gem_object_save_bit_17_swizzle(obj
);
1669 if (obj
->madv
== I915_MADV_DONTNEED
)
1672 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1673 struct page
*page
= sg_page(sg
);
1676 set_page_dirty(page
);
1678 if (obj
->madv
== I915_MADV_WILLNEED
)
1679 mark_page_accessed(page
);
1681 page_cache_release(page
);
1685 sg_free_table(obj
->pages
);
1690 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1692 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1694 if (obj
->pages
== NULL
)
1697 BUG_ON(obj
->gtt_space
);
1699 if (obj
->pages_pin_count
)
1702 ops
->put_pages(obj
);
1705 list_del(&obj
->gtt_list
);
1706 if (i915_gem_object_is_purgeable(obj
))
1707 i915_gem_object_truncate(obj
);
1713 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1715 struct drm_i915_gem_object
*obj
, *next
;
1718 list_for_each_entry_safe(obj
, next
,
1719 &dev_priv
->mm
.unbound_list
,
1721 if (i915_gem_object_is_purgeable(obj
) &&
1722 i915_gem_object_put_pages(obj
) == 0) {
1723 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1724 if (count
>= target
)
1729 list_for_each_entry_safe(obj
, next
,
1730 &dev_priv
->mm
.inactive_list
,
1732 if (i915_gem_object_is_purgeable(obj
) &&
1733 i915_gem_object_unbind(obj
) == 0 &&
1734 i915_gem_object_put_pages(obj
) == 0) {
1735 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1736 if (count
>= target
)
1745 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1747 struct drm_i915_gem_object
*obj
, *next
;
1749 i915_gem_evict_everything(dev_priv
->dev
);
1751 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1752 i915_gem_object_put_pages(obj
);
1756 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1758 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1760 struct address_space
*mapping
;
1761 struct sg_table
*st
;
1762 struct scatterlist
*sg
;
1766 /* Assert that the object is not currently in any GPU domain. As it
1767 * wasn't in the GTT, there shouldn't be any way it could have been in
1770 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1771 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1773 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1777 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1778 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1784 /* Get the list of pages out of our struct file. They'll be pinned
1785 * at this point until we release them.
1787 * Fail silently without starting the shrinker
1789 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1790 gfp
= mapping_gfp_mask(mapping
);
1791 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1792 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1793 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1794 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1796 i915_gem_purge(dev_priv
, page_count
);
1797 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1800 /* We've tried hard to allocate the memory by reaping
1801 * our own buffer, now let the real VM do its job and
1802 * go down in flames if truly OOM.
1804 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
);
1805 gfp
|= __GFP_IO
| __GFP_WAIT
;
1807 i915_gem_shrink_all(dev_priv
);
1808 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1812 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1813 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1816 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1821 if (i915_gem_object_needs_bit17_swizzle(obj
))
1822 i915_gem_object_do_bit_17_swizzle(obj
);
1827 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1828 page_cache_release(sg_page(sg
));
1831 return PTR_ERR(page
);
1834 /* Ensure that the associated pages are gathered from the backing storage
1835 * and pinned into our object. i915_gem_object_get_pages() may be called
1836 * multiple times before they are released by a single call to
1837 * i915_gem_object_put_pages() - once the pages are no longer referenced
1838 * either as a result of memory pressure (reaping pages under the shrinker)
1839 * or as the object is itself released.
1842 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1844 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1845 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1851 BUG_ON(obj
->pages_pin_count
);
1853 ret
= ops
->get_pages(obj
);
1857 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1862 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1863 struct intel_ring_buffer
*ring
)
1865 struct drm_device
*dev
= obj
->base
.dev
;
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 u32 seqno
= intel_ring_get_seqno(ring
);
1869 BUG_ON(ring
== NULL
);
1872 /* Add a reference if we're newly entering the active list. */
1874 drm_gem_object_reference(&obj
->base
);
1878 /* Move from whatever list we were on to the tail of execution. */
1879 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1880 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1882 obj
->last_read_seqno
= seqno
;
1884 if (obj
->fenced_gpu_access
) {
1885 obj
->last_fenced_seqno
= seqno
;
1887 /* Bump MRU to take account of the delayed flush */
1888 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1889 struct drm_i915_fence_reg
*reg
;
1891 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1892 list_move_tail(®
->lru_list
,
1893 &dev_priv
->mm
.fence_list
);
1899 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1901 struct drm_device
*dev
= obj
->base
.dev
;
1902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1904 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1905 BUG_ON(!obj
->active
);
1907 if (obj
->pin_count
) /* are we a framebuffer? */
1908 intel_mark_fb_idle(obj
);
1910 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1912 list_del_init(&obj
->ring_list
);
1915 obj
->last_read_seqno
= 0;
1916 obj
->last_write_seqno
= 0;
1917 obj
->base
.write_domain
= 0;
1919 obj
->last_fenced_seqno
= 0;
1920 obj
->fenced_gpu_access
= false;
1923 drm_gem_object_unreference(&obj
->base
);
1925 WARN_ON(i915_verify_lists(dev
));
1929 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 struct intel_ring_buffer
*ring
;
1935 /* Carefully retire all requests without writing to the rings */
1936 for_each_ring(ring
, dev_priv
, i
) {
1937 ret
= intel_ring_idle(ring
);
1941 i915_gem_retire_requests(dev
);
1943 /* Finally reset hw state */
1944 for_each_ring(ring
, dev_priv
, i
) {
1945 intel_ring_init_seqno(ring
, seqno
);
1947 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1948 ring
->sync_seqno
[j
] = 0;
1954 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1962 /* HWS page needs to be set less than what we
1963 * will inject to ring
1965 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1969 /* Carefully set the last_seqno value so that wrap
1970 * detection still works
1972 dev_priv
->next_seqno
= seqno
;
1973 dev_priv
->last_seqno
= seqno
- 1;
1974 if (dev_priv
->last_seqno
== 0)
1975 dev_priv
->last_seqno
--;
1981 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1985 /* reserve 0 for non-seqno */
1986 if (dev_priv
->next_seqno
== 0) {
1987 int ret
= i915_gem_init_seqno(dev
, 0);
1991 dev_priv
->next_seqno
= 1;
1994 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
1999 i915_add_request(struct intel_ring_buffer
*ring
,
2000 struct drm_file
*file
,
2003 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2004 struct drm_i915_gem_request
*request
;
2005 u32 request_ring_position
;
2010 * Emit any outstanding flushes - execbuf can fail to emit the flush
2011 * after having emitted the batchbuffer command. Hence we need to fix
2012 * things up similar to emitting the lazy request. The difference here
2013 * is that the flush _must_ happen before the next request, no matter
2016 ret
= intel_ring_flush_all_caches(ring
);
2020 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2021 if (request
== NULL
)
2025 /* Record the position of the start of the request so that
2026 * should we detect the updated seqno part-way through the
2027 * GPU processing the request, we never over-estimate the
2028 * position of the head.
2030 request_ring_position
= intel_ring_get_tail(ring
);
2032 ret
= ring
->add_request(ring
);
2038 request
->seqno
= intel_ring_get_seqno(ring
);
2039 request
->ring
= ring
;
2040 request
->tail
= request_ring_position
;
2041 request
->emitted_jiffies
= jiffies
;
2042 was_empty
= list_empty(&ring
->request_list
);
2043 list_add_tail(&request
->list
, &ring
->request_list
);
2044 request
->file_priv
= NULL
;
2047 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2049 spin_lock(&file_priv
->mm
.lock
);
2050 request
->file_priv
= file_priv
;
2051 list_add_tail(&request
->client_list
,
2052 &file_priv
->mm
.request_list
);
2053 spin_unlock(&file_priv
->mm
.lock
);
2056 trace_i915_gem_request_add(ring
, request
->seqno
);
2057 ring
->outstanding_lazy_request
= 0;
2059 if (!dev_priv
->mm
.suspended
) {
2060 if (i915_enable_hangcheck
) {
2061 mod_timer(&dev_priv
->hangcheck_timer
,
2062 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2065 queue_delayed_work(dev_priv
->wq
,
2066 &dev_priv
->mm
.retire_work
,
2067 round_jiffies_up_relative(HZ
));
2068 intel_mark_busy(dev_priv
->dev
);
2073 *out_seqno
= request
->seqno
;
2078 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2080 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2085 spin_lock(&file_priv
->mm
.lock
);
2086 if (request
->file_priv
) {
2087 list_del(&request
->client_list
);
2088 request
->file_priv
= NULL
;
2090 spin_unlock(&file_priv
->mm
.lock
);
2093 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2094 struct intel_ring_buffer
*ring
)
2096 while (!list_empty(&ring
->request_list
)) {
2097 struct drm_i915_gem_request
*request
;
2099 request
= list_first_entry(&ring
->request_list
,
2100 struct drm_i915_gem_request
,
2103 list_del(&request
->list
);
2104 i915_gem_request_remove_from_client(request
);
2108 while (!list_empty(&ring
->active_list
)) {
2109 struct drm_i915_gem_object
*obj
;
2111 obj
= list_first_entry(&ring
->active_list
,
2112 struct drm_i915_gem_object
,
2115 i915_gem_object_move_to_inactive(obj
);
2119 static void i915_gem_reset_fences(struct drm_device
*dev
)
2121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2124 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2125 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2127 i915_gem_write_fence(dev
, i
, NULL
);
2130 i915_gem_object_fence_lost(reg
->obj
);
2134 INIT_LIST_HEAD(®
->lru_list
);
2137 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2140 void i915_gem_reset(struct drm_device
*dev
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2143 struct drm_i915_gem_object
*obj
;
2144 struct intel_ring_buffer
*ring
;
2147 for_each_ring(ring
, dev_priv
, i
)
2148 i915_gem_reset_ring_lists(dev_priv
, ring
);
2150 /* Move everything out of the GPU domains to ensure we do any
2151 * necessary invalidation upon reuse.
2153 list_for_each_entry(obj
,
2154 &dev_priv
->mm
.inactive_list
,
2157 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2160 /* The fence registers are invalidated so clear them out */
2161 i915_gem_reset_fences(dev
);
2165 * This function clears the request list as sequence numbers are passed.
2168 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2172 if (list_empty(&ring
->request_list
))
2175 WARN_ON(i915_verify_lists(ring
->dev
));
2177 seqno
= ring
->get_seqno(ring
, true);
2179 while (!list_empty(&ring
->request_list
)) {
2180 struct drm_i915_gem_request
*request
;
2182 request
= list_first_entry(&ring
->request_list
,
2183 struct drm_i915_gem_request
,
2186 if (!i915_seqno_passed(seqno
, request
->seqno
))
2189 trace_i915_gem_request_retire(ring
, request
->seqno
);
2190 /* We know the GPU must have read the request to have
2191 * sent us the seqno + interrupt, so use the position
2192 * of tail of the request to update the last known position
2195 ring
->last_retired_head
= request
->tail
;
2197 list_del(&request
->list
);
2198 i915_gem_request_remove_from_client(request
);
2202 /* Move any buffers on the active list that are no longer referenced
2203 * by the ringbuffer to the flushing/inactive lists as appropriate.
2205 while (!list_empty(&ring
->active_list
)) {
2206 struct drm_i915_gem_object
*obj
;
2208 obj
= list_first_entry(&ring
->active_list
,
2209 struct drm_i915_gem_object
,
2212 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2215 i915_gem_object_move_to_inactive(obj
);
2218 if (unlikely(ring
->trace_irq_seqno
&&
2219 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2220 ring
->irq_put(ring
);
2221 ring
->trace_irq_seqno
= 0;
2224 WARN_ON(i915_verify_lists(ring
->dev
));
2228 i915_gem_retire_requests(struct drm_device
*dev
)
2230 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2231 struct intel_ring_buffer
*ring
;
2234 for_each_ring(ring
, dev_priv
, i
)
2235 i915_gem_retire_requests_ring(ring
);
2239 i915_gem_retire_work_handler(struct work_struct
*work
)
2241 drm_i915_private_t
*dev_priv
;
2242 struct drm_device
*dev
;
2243 struct intel_ring_buffer
*ring
;
2247 dev_priv
= container_of(work
, drm_i915_private_t
,
2248 mm
.retire_work
.work
);
2249 dev
= dev_priv
->dev
;
2251 /* Come back later if the device is busy... */
2252 if (!mutex_trylock(&dev
->struct_mutex
)) {
2253 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2254 round_jiffies_up_relative(HZ
));
2258 i915_gem_retire_requests(dev
);
2260 /* Send a periodic flush down the ring so we don't hold onto GEM
2261 * objects indefinitely.
2264 for_each_ring(ring
, dev_priv
, i
) {
2265 if (ring
->gpu_caches_dirty
)
2266 i915_add_request(ring
, NULL
, NULL
);
2268 idle
&= list_empty(&ring
->request_list
);
2271 if (!dev_priv
->mm
.suspended
&& !idle
)
2272 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2273 round_jiffies_up_relative(HZ
));
2275 intel_mark_idle(dev
);
2277 mutex_unlock(&dev
->struct_mutex
);
2281 * Ensures that an object will eventually get non-busy by flushing any required
2282 * write domains, emitting any outstanding lazy request and retiring and
2283 * completed requests.
2286 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2291 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2295 i915_gem_retire_requests_ring(obj
->ring
);
2302 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2303 * @DRM_IOCTL_ARGS: standard ioctl arguments
2305 * Returns 0 if successful, else an error is returned with the remaining time in
2306 * the timeout parameter.
2307 * -ETIME: object is still busy after timeout
2308 * -ERESTARTSYS: signal interrupted the wait
2309 * -ENONENT: object doesn't exist
2310 * Also possible, but rare:
2311 * -EAGAIN: GPU wedged
2313 * -ENODEV: Internal IRQ fail
2314 * -E?: The add request failed
2316 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2317 * non-zero timeout parameter the wait ioctl will wait for the given number of
2318 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2319 * without holding struct_mutex the object may become re-busied before this
2320 * function completes. A similar but shorter * race condition exists in the busy
2324 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2326 struct drm_i915_gem_wait
*args
= data
;
2327 struct drm_i915_gem_object
*obj
;
2328 struct intel_ring_buffer
*ring
= NULL
;
2329 struct timespec timeout_stack
, *timeout
= NULL
;
2333 if (args
->timeout_ns
>= 0) {
2334 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2335 timeout
= &timeout_stack
;
2338 ret
= i915_mutex_lock_interruptible(dev
);
2342 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2343 if (&obj
->base
== NULL
) {
2344 mutex_unlock(&dev
->struct_mutex
);
2348 /* Need to make sure the object gets inactive eventually. */
2349 ret
= i915_gem_object_flush_active(obj
);
2354 seqno
= obj
->last_read_seqno
;
2361 /* Do this after OLR check to make sure we make forward progress polling
2362 * on this IOCTL with a 0 timeout (like busy ioctl)
2364 if (!args
->timeout_ns
) {
2369 drm_gem_object_unreference(&obj
->base
);
2370 mutex_unlock(&dev
->struct_mutex
);
2372 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2374 WARN_ON(!timespec_valid(timeout
));
2375 args
->timeout_ns
= timespec_to_ns(timeout
);
2380 drm_gem_object_unreference(&obj
->base
);
2381 mutex_unlock(&dev
->struct_mutex
);
2386 * i915_gem_object_sync - sync an object to a ring.
2388 * @obj: object which may be in use on another ring.
2389 * @to: ring we wish to use the object on. May be NULL.
2391 * This code is meant to abstract object synchronization with the GPU.
2392 * Calling with NULL implies synchronizing the object with the CPU
2393 * rather than a particular GPU ring.
2395 * Returns 0 if successful, else propagates up the lower layer error.
2398 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2399 struct intel_ring_buffer
*to
)
2401 struct intel_ring_buffer
*from
= obj
->ring
;
2405 if (from
== NULL
|| to
== from
)
2408 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2409 return i915_gem_object_wait_rendering(obj
, false);
2411 idx
= intel_ring_sync_index(from
, to
);
2413 seqno
= obj
->last_read_seqno
;
2414 if (seqno
<= from
->sync_seqno
[idx
])
2417 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2421 ret
= to
->sync_to(to
, from
, seqno
);
2423 /* We use last_read_seqno because sync_to()
2424 * might have just caused seqno wrap under
2427 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2432 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2434 u32 old_write_domain
, old_read_domains
;
2436 /* Act a barrier for all accesses through the GTT */
2439 /* Force a pagefault for domain tracking on next user access */
2440 i915_gem_release_mmap(obj
);
2442 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2445 old_read_domains
= obj
->base
.read_domains
;
2446 old_write_domain
= obj
->base
.write_domain
;
2448 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2449 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2451 trace_i915_gem_object_change_domain(obj
,
2457 * Unbinds an object from the GTT aperture.
2460 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2462 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2465 if (obj
->gtt_space
== NULL
)
2471 BUG_ON(obj
->pages
== NULL
);
2473 ret
= i915_gem_object_finish_gpu(obj
);
2476 /* Continue on if we fail due to EIO, the GPU is hung so we
2477 * should be safe and we need to cleanup or else we might
2478 * cause memory corruption through use-after-free.
2481 i915_gem_object_finish_gtt(obj
);
2483 /* release the fence reg _after_ flushing */
2484 ret
= i915_gem_object_put_fence(obj
);
2488 trace_i915_gem_object_unbind(obj
);
2490 if (obj
->has_global_gtt_mapping
)
2491 i915_gem_gtt_unbind_object(obj
);
2492 if (obj
->has_aliasing_ppgtt_mapping
) {
2493 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2494 obj
->has_aliasing_ppgtt_mapping
= 0;
2496 i915_gem_gtt_finish_object(obj
);
2498 list_del(&obj
->mm_list
);
2499 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2500 /* Avoid an unnecessary call to unbind on rebind. */
2501 obj
->map_and_fenceable
= true;
2503 drm_mm_put_block(obj
->gtt_space
);
2504 obj
->gtt_space
= NULL
;
2505 obj
->gtt_offset
= 0;
2510 int i915_gpu_idle(struct drm_device
*dev
)
2512 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2513 struct intel_ring_buffer
*ring
;
2516 /* Flush everything onto the inactive list. */
2517 for_each_ring(ring
, dev_priv
, i
) {
2518 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2522 ret
= intel_ring_idle(ring
);
2530 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2531 struct drm_i915_gem_object
*obj
)
2533 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2537 u32 size
= obj
->gtt_space
->size
;
2539 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2541 val
|= obj
->gtt_offset
& 0xfffff000;
2542 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2543 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2545 if (obj
->tiling_mode
== I915_TILING_Y
)
2546 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2547 val
|= I965_FENCE_REG_VALID
;
2551 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2552 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2555 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2556 struct drm_i915_gem_object
*obj
)
2558 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2562 u32 size
= obj
->gtt_space
->size
;
2564 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2566 val
|= obj
->gtt_offset
& 0xfffff000;
2567 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2568 if (obj
->tiling_mode
== I915_TILING_Y
)
2569 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2570 val
|= I965_FENCE_REG_VALID
;
2574 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2575 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2578 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2579 struct drm_i915_gem_object
*obj
)
2581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2585 u32 size
= obj
->gtt_space
->size
;
2589 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2590 (size
& -size
) != size
||
2591 (obj
->gtt_offset
& (size
- 1)),
2592 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2593 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2595 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2600 /* Note: pitch better be a power of two tile widths */
2601 pitch_val
= obj
->stride
/ tile_width
;
2602 pitch_val
= ffs(pitch_val
) - 1;
2604 val
= obj
->gtt_offset
;
2605 if (obj
->tiling_mode
== I915_TILING_Y
)
2606 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2607 val
|= I915_FENCE_SIZE_BITS(size
);
2608 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2609 val
|= I830_FENCE_REG_VALID
;
2614 reg
= FENCE_REG_830_0
+ reg
* 4;
2616 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2618 I915_WRITE(reg
, val
);
2622 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2623 struct drm_i915_gem_object
*obj
)
2625 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2629 u32 size
= obj
->gtt_space
->size
;
2632 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2633 (size
& -size
) != size
||
2634 (obj
->gtt_offset
& (size
- 1)),
2635 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2636 obj
->gtt_offset
, size
);
2638 pitch_val
= obj
->stride
/ 128;
2639 pitch_val
= ffs(pitch_val
) - 1;
2641 val
= obj
->gtt_offset
;
2642 if (obj
->tiling_mode
== I915_TILING_Y
)
2643 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2644 val
|= I830_FENCE_SIZE_BITS(size
);
2645 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2646 val
|= I830_FENCE_REG_VALID
;
2650 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2651 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2654 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2655 struct drm_i915_gem_object
*obj
)
2657 switch (INTEL_INFO(dev
)->gen
) {
2659 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2661 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2662 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2663 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2668 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2669 struct drm_i915_fence_reg
*fence
)
2671 return fence
- dev_priv
->fence_regs
;
2674 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2675 struct drm_i915_fence_reg
*fence
,
2678 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2679 int reg
= fence_number(dev_priv
, fence
);
2681 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2684 obj
->fence_reg
= reg
;
2686 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2688 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2690 list_del_init(&fence
->lru_list
);
2695 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2697 if (obj
->last_fenced_seqno
) {
2698 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2702 obj
->last_fenced_seqno
= 0;
2705 /* Ensure that all CPU reads are completed before installing a fence
2706 * and all writes before removing the fence.
2708 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2711 obj
->fenced_gpu_access
= false;
2716 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2718 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2721 ret
= i915_gem_object_flush_fence(obj
);
2725 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2728 i915_gem_object_update_fence(obj
,
2729 &dev_priv
->fence_regs
[obj
->fence_reg
],
2731 i915_gem_object_fence_lost(obj
);
2736 static struct drm_i915_fence_reg
*
2737 i915_find_fence_reg(struct drm_device
*dev
)
2739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2740 struct drm_i915_fence_reg
*reg
, *avail
;
2743 /* First try to find a free reg */
2745 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2746 reg
= &dev_priv
->fence_regs
[i
];
2750 if (!reg
->pin_count
)
2757 /* None available, try to steal one or wait for a user to finish */
2758 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2769 * i915_gem_object_get_fence - set up fencing for an object
2770 * @obj: object to map through a fence reg
2772 * When mapping objects through the GTT, userspace wants to be able to write
2773 * to them without having to worry about swizzling if the object is tiled.
2774 * This function walks the fence regs looking for a free one for @obj,
2775 * stealing one if it can't find any.
2777 * It then sets up the reg based on the object's properties: address, pitch
2778 * and tiling format.
2780 * For an untiled surface, this removes any existing fence.
2783 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2785 struct drm_device
*dev
= obj
->base
.dev
;
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2788 struct drm_i915_fence_reg
*reg
;
2791 /* Have we updated the tiling parameters upon the object and so
2792 * will need to serialise the write to the associated fence register?
2794 if (obj
->fence_dirty
) {
2795 ret
= i915_gem_object_flush_fence(obj
);
2800 /* Just update our place in the LRU if our fence is getting reused. */
2801 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2802 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2803 if (!obj
->fence_dirty
) {
2804 list_move_tail(®
->lru_list
,
2805 &dev_priv
->mm
.fence_list
);
2808 } else if (enable
) {
2809 reg
= i915_find_fence_reg(dev
);
2814 struct drm_i915_gem_object
*old
= reg
->obj
;
2816 ret
= i915_gem_object_flush_fence(old
);
2820 i915_gem_object_fence_lost(old
);
2825 i915_gem_object_update_fence(obj
, reg
, enable
);
2826 obj
->fence_dirty
= false;
2831 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2832 struct drm_mm_node
*gtt_space
,
2833 unsigned long cache_level
)
2835 struct drm_mm_node
*other
;
2837 /* On non-LLC machines we have to be careful when putting differing
2838 * types of snoopable memory together to avoid the prefetcher
2839 * crossing memory domains and dying.
2844 if (gtt_space
== NULL
)
2847 if (list_empty(>t_space
->node_list
))
2850 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2851 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2854 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2855 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2861 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2865 struct drm_i915_gem_object
*obj
;
2868 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2869 if (obj
->gtt_space
== NULL
) {
2870 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2875 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2876 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2877 obj
->gtt_space
->start
,
2878 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2880 obj
->gtt_space
->color
);
2885 if (!i915_gem_valid_gtt_space(dev
,
2887 obj
->cache_level
)) {
2888 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2889 obj
->gtt_space
->start
,
2890 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2902 * Finds free space in the GTT aperture and binds the object there.
2905 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2907 bool map_and_fenceable
,
2910 struct drm_device
*dev
= obj
->base
.dev
;
2911 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2912 struct drm_mm_node
*free_space
;
2913 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2914 bool mappable
, fenceable
;
2917 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2918 DRM_ERROR("Attempting to bind a purgeable object\n");
2922 fence_size
= i915_gem_get_gtt_size(dev
,
2925 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2928 unfenced_alignment
=
2929 i915_gem_get_unfenced_gtt_alignment(dev
,
2934 alignment
= map_and_fenceable
? fence_alignment
:
2936 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2937 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2941 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2943 /* If the object is bigger than the entire aperture, reject it early
2944 * before evicting everything in a vain attempt to find space.
2946 if (obj
->base
.size
>
2947 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2948 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2952 ret
= i915_gem_object_get_pages(obj
);
2956 i915_gem_object_pin_pages(obj
);
2959 if (map_and_fenceable
)
2960 free_space
= drm_mm_search_free_in_range_color(&dev_priv
->mm
.gtt_space
,
2961 size
, alignment
, obj
->cache_level
,
2962 0, dev_priv
->mm
.gtt_mappable_end
,
2965 free_space
= drm_mm_search_free_color(&dev_priv
->mm
.gtt_space
,
2966 size
, alignment
, obj
->cache_level
,
2969 if (free_space
!= NULL
) {
2970 if (map_and_fenceable
)
2972 drm_mm_get_block_range_generic(free_space
,
2973 size
, alignment
, obj
->cache_level
,
2974 0, dev_priv
->mm
.gtt_mappable_end
,
2978 drm_mm_get_block_generic(free_space
,
2979 size
, alignment
, obj
->cache_level
,
2982 if (free_space
== NULL
) {
2983 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2988 i915_gem_object_unpin_pages(obj
);
2994 if (WARN_ON(!i915_gem_valid_gtt_space(dev
,
2996 obj
->cache_level
))) {
2997 i915_gem_object_unpin_pages(obj
);
2998 drm_mm_put_block(free_space
);
3002 ret
= i915_gem_gtt_prepare_object(obj
);
3004 i915_gem_object_unpin_pages(obj
);
3005 drm_mm_put_block(free_space
);
3009 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
3010 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3012 obj
->gtt_space
= free_space
;
3013 obj
->gtt_offset
= free_space
->start
;
3016 free_space
->size
== fence_size
&&
3017 (free_space
->start
& (fence_alignment
- 1)) == 0;
3020 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
3022 obj
->map_and_fenceable
= mappable
&& fenceable
;
3024 i915_gem_object_unpin_pages(obj
);
3025 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3026 i915_gem_verify_gtt(dev
);
3031 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3033 /* If we don't have a page list set up, then we're not pinned
3034 * to GPU, and we can ignore the cache flush because it'll happen
3035 * again at bind time.
3037 if (obj
->pages
== NULL
)
3040 /* If the GPU is snooping the contents of the CPU cache,
3041 * we do not need to manually clear the CPU cache lines. However,
3042 * the caches are only snooped when the render cache is
3043 * flushed/invalidated. As we always have to emit invalidations
3044 * and flushes when moving into and out of the RENDER domain, correct
3045 * snooping behaviour occurs naturally as the result of our domain
3048 if (obj
->cache_level
!= I915_CACHE_NONE
)
3051 trace_i915_gem_object_clflush(obj
);
3053 drm_clflush_sg(obj
->pages
);
3056 /** Flushes the GTT write domain for the object if it's dirty. */
3058 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3060 uint32_t old_write_domain
;
3062 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3065 /* No actual flushing is required for the GTT write domain. Writes
3066 * to it immediately go to main memory as far as we know, so there's
3067 * no chipset flush. It also doesn't land in render cache.
3069 * However, we do have to enforce the order so that all writes through
3070 * the GTT land before any writes to the device, such as updates to
3075 old_write_domain
= obj
->base
.write_domain
;
3076 obj
->base
.write_domain
= 0;
3078 trace_i915_gem_object_change_domain(obj
,
3079 obj
->base
.read_domains
,
3083 /** Flushes the CPU write domain for the object if it's dirty. */
3085 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3087 uint32_t old_write_domain
;
3089 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3092 i915_gem_clflush_object(obj
);
3093 i915_gem_chipset_flush(obj
->base
.dev
);
3094 old_write_domain
= obj
->base
.write_domain
;
3095 obj
->base
.write_domain
= 0;
3097 trace_i915_gem_object_change_domain(obj
,
3098 obj
->base
.read_domains
,
3103 * Moves a single object to the GTT read, and possibly write domain.
3105 * This function returns when the move is complete, including waiting on
3109 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3111 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3112 uint32_t old_write_domain
, old_read_domains
;
3115 /* Not valid to be called on unbound objects. */
3116 if (obj
->gtt_space
== NULL
)
3119 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3122 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3126 i915_gem_object_flush_cpu_write_domain(obj
);
3128 old_write_domain
= obj
->base
.write_domain
;
3129 old_read_domains
= obj
->base
.read_domains
;
3131 /* It should now be out of any other write domains, and we can update
3132 * the domain values for our changes.
3134 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3135 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3137 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3138 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3142 trace_i915_gem_object_change_domain(obj
,
3146 /* And bump the LRU for this access */
3147 if (i915_gem_object_is_inactive(obj
))
3148 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3153 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3154 enum i915_cache_level cache_level
)
3156 struct drm_device
*dev
= obj
->base
.dev
;
3157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3160 if (obj
->cache_level
== cache_level
)
3163 if (obj
->pin_count
) {
3164 DRM_DEBUG("can not change the cache level of pinned objects\n");
3168 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3169 ret
= i915_gem_object_unbind(obj
);
3174 if (obj
->gtt_space
) {
3175 ret
= i915_gem_object_finish_gpu(obj
);
3179 i915_gem_object_finish_gtt(obj
);
3181 /* Before SandyBridge, you could not use tiling or fence
3182 * registers with snooped memory, so relinquish any fences
3183 * currently pointing to our region in the aperture.
3185 if (INTEL_INFO(dev
)->gen
< 6) {
3186 ret
= i915_gem_object_put_fence(obj
);
3191 if (obj
->has_global_gtt_mapping
)
3192 i915_gem_gtt_bind_object(obj
, cache_level
);
3193 if (obj
->has_aliasing_ppgtt_mapping
)
3194 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3197 obj
->gtt_space
->color
= cache_level
;
3200 if (cache_level
== I915_CACHE_NONE
) {
3201 u32 old_read_domains
, old_write_domain
;
3203 /* If we're coming from LLC cached, then we haven't
3204 * actually been tracking whether the data is in the
3205 * CPU cache or not, since we only allow one bit set
3206 * in obj->write_domain and have been skipping the clflushes.
3207 * Just set it to the CPU cache for now.
3209 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3210 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3212 old_read_domains
= obj
->base
.read_domains
;
3213 old_write_domain
= obj
->base
.write_domain
;
3215 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3216 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3218 trace_i915_gem_object_change_domain(obj
,
3223 obj
->cache_level
= cache_level
;
3224 i915_gem_verify_gtt(dev
);
3228 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3229 struct drm_file
*file
)
3231 struct drm_i915_gem_caching
*args
= data
;
3232 struct drm_i915_gem_object
*obj
;
3235 ret
= i915_mutex_lock_interruptible(dev
);
3239 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3240 if (&obj
->base
== NULL
) {
3245 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3247 drm_gem_object_unreference(&obj
->base
);
3249 mutex_unlock(&dev
->struct_mutex
);
3253 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3254 struct drm_file
*file
)
3256 struct drm_i915_gem_caching
*args
= data
;
3257 struct drm_i915_gem_object
*obj
;
3258 enum i915_cache_level level
;
3261 switch (args
->caching
) {
3262 case I915_CACHING_NONE
:
3263 level
= I915_CACHE_NONE
;
3265 case I915_CACHING_CACHED
:
3266 level
= I915_CACHE_LLC
;
3272 ret
= i915_mutex_lock_interruptible(dev
);
3276 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3277 if (&obj
->base
== NULL
) {
3282 ret
= i915_gem_object_set_cache_level(obj
, level
);
3284 drm_gem_object_unreference(&obj
->base
);
3286 mutex_unlock(&dev
->struct_mutex
);
3291 * Prepare buffer for display plane (scanout, cursors, etc).
3292 * Can be called from an uninterruptible phase (modesetting) and allows
3293 * any flushes to be pipelined (for pageflips).
3296 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3298 struct intel_ring_buffer
*pipelined
)
3300 u32 old_read_domains
, old_write_domain
;
3303 if (pipelined
!= obj
->ring
) {
3304 ret
= i915_gem_object_sync(obj
, pipelined
);
3309 /* The display engine is not coherent with the LLC cache on gen6. As
3310 * a result, we make sure that the pinning that is about to occur is
3311 * done with uncached PTEs. This is lowest common denominator for all
3314 * However for gen6+, we could do better by using the GFDT bit instead
3315 * of uncaching, which would allow us to flush all the LLC-cached data
3316 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3318 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3322 /* As the user may map the buffer once pinned in the display plane
3323 * (e.g. libkms for the bootup splash), we have to ensure that we
3324 * always use map_and_fenceable for all scanout buffers.
3326 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3330 i915_gem_object_flush_cpu_write_domain(obj
);
3332 old_write_domain
= obj
->base
.write_domain
;
3333 old_read_domains
= obj
->base
.read_domains
;
3335 /* It should now be out of any other write domains, and we can update
3336 * the domain values for our changes.
3338 obj
->base
.write_domain
= 0;
3339 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3341 trace_i915_gem_object_change_domain(obj
,
3349 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3353 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3356 ret
= i915_gem_object_wait_rendering(obj
, false);
3360 /* Ensure that we invalidate the GPU's caches and TLBs. */
3361 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3366 * Moves a single object to the CPU read, and possibly write domain.
3368 * This function returns when the move is complete, including waiting on
3372 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3374 uint32_t old_write_domain
, old_read_domains
;
3377 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3380 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3384 i915_gem_object_flush_gtt_write_domain(obj
);
3386 old_write_domain
= obj
->base
.write_domain
;
3387 old_read_domains
= obj
->base
.read_domains
;
3389 /* Flush the CPU cache if it's still invalid. */
3390 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3391 i915_gem_clflush_object(obj
);
3393 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3396 /* It should now be out of any other write domains, and we can update
3397 * the domain values for our changes.
3399 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3401 /* If we're writing through the CPU, then the GPU read domains will
3402 * need to be invalidated at next use.
3405 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3406 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3409 trace_i915_gem_object_change_domain(obj
,
3416 /* Throttle our rendering by waiting until the ring has completed our requests
3417 * emitted over 20 msec ago.
3419 * Note that if we were to use the current jiffies each time around the loop,
3420 * we wouldn't escape the function with any frames outstanding if the time to
3421 * render a frame was over 20ms.
3423 * This should get us reasonable parallelism between CPU and GPU but also
3424 * relatively low latency when blocking on a particular request to finish.
3427 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3430 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3431 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3432 struct drm_i915_gem_request
*request
;
3433 struct intel_ring_buffer
*ring
= NULL
;
3437 if (atomic_read(&dev_priv
->mm
.wedged
))
3440 spin_lock(&file_priv
->mm
.lock
);
3441 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3442 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3445 ring
= request
->ring
;
3446 seqno
= request
->seqno
;
3448 spin_unlock(&file_priv
->mm
.lock
);
3453 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3455 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3461 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3463 bool map_and_fenceable
,
3468 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3471 if (obj
->gtt_space
!= NULL
) {
3472 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3473 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3474 WARN(obj
->pin_count
,
3475 "bo is already pinned with incorrect alignment:"
3476 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3477 " obj->map_and_fenceable=%d\n",
3478 obj
->gtt_offset
, alignment
,
3480 obj
->map_and_fenceable
);
3481 ret
= i915_gem_object_unbind(obj
);
3487 if (obj
->gtt_space
== NULL
) {
3488 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3490 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3496 if (!dev_priv
->mm
.aliasing_ppgtt
)
3497 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3500 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3501 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3504 obj
->pin_mappable
|= map_and_fenceable
;
3510 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3512 BUG_ON(obj
->pin_count
== 0);
3513 BUG_ON(obj
->gtt_space
== NULL
);
3515 if (--obj
->pin_count
== 0)
3516 obj
->pin_mappable
= false;
3520 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3521 struct drm_file
*file
)
3523 struct drm_i915_gem_pin
*args
= data
;
3524 struct drm_i915_gem_object
*obj
;
3527 ret
= i915_mutex_lock_interruptible(dev
);
3531 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3532 if (&obj
->base
== NULL
) {
3537 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3538 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3543 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3544 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3550 obj
->user_pin_count
++;
3551 obj
->pin_filp
= file
;
3552 if (obj
->user_pin_count
== 1) {
3553 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3558 /* XXX - flush the CPU caches for pinned objects
3559 * as the X server doesn't manage domains yet
3561 i915_gem_object_flush_cpu_write_domain(obj
);
3562 args
->offset
= obj
->gtt_offset
;
3564 drm_gem_object_unreference(&obj
->base
);
3566 mutex_unlock(&dev
->struct_mutex
);
3571 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3572 struct drm_file
*file
)
3574 struct drm_i915_gem_pin
*args
= data
;
3575 struct drm_i915_gem_object
*obj
;
3578 ret
= i915_mutex_lock_interruptible(dev
);
3582 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3583 if (&obj
->base
== NULL
) {
3588 if (obj
->pin_filp
!= file
) {
3589 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3594 obj
->user_pin_count
--;
3595 if (obj
->user_pin_count
== 0) {
3596 obj
->pin_filp
= NULL
;
3597 i915_gem_object_unpin(obj
);
3601 drm_gem_object_unreference(&obj
->base
);
3603 mutex_unlock(&dev
->struct_mutex
);
3608 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3609 struct drm_file
*file
)
3611 struct drm_i915_gem_busy
*args
= data
;
3612 struct drm_i915_gem_object
*obj
;
3615 ret
= i915_mutex_lock_interruptible(dev
);
3619 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3620 if (&obj
->base
== NULL
) {
3625 /* Count all active objects as busy, even if they are currently not used
3626 * by the gpu. Users of this interface expect objects to eventually
3627 * become non-busy without any further actions, therefore emit any
3628 * necessary flushes here.
3630 ret
= i915_gem_object_flush_active(obj
);
3632 args
->busy
= obj
->active
;
3634 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3635 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3638 drm_gem_object_unreference(&obj
->base
);
3640 mutex_unlock(&dev
->struct_mutex
);
3645 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3646 struct drm_file
*file_priv
)
3648 return i915_gem_ring_throttle(dev
, file_priv
);
3652 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3653 struct drm_file
*file_priv
)
3655 struct drm_i915_gem_madvise
*args
= data
;
3656 struct drm_i915_gem_object
*obj
;
3659 switch (args
->madv
) {
3660 case I915_MADV_DONTNEED
:
3661 case I915_MADV_WILLNEED
:
3667 ret
= i915_mutex_lock_interruptible(dev
);
3671 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3672 if (&obj
->base
== NULL
) {
3677 if (obj
->pin_count
) {
3682 if (obj
->madv
!= __I915_MADV_PURGED
)
3683 obj
->madv
= args
->madv
;
3685 /* if the object is no longer attached, discard its backing storage */
3686 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3687 i915_gem_object_truncate(obj
);
3689 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3692 drm_gem_object_unreference(&obj
->base
);
3694 mutex_unlock(&dev
->struct_mutex
);
3698 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3699 const struct drm_i915_gem_object_ops
*ops
)
3701 INIT_LIST_HEAD(&obj
->mm_list
);
3702 INIT_LIST_HEAD(&obj
->gtt_list
);
3703 INIT_LIST_HEAD(&obj
->ring_list
);
3704 INIT_LIST_HEAD(&obj
->exec_list
);
3708 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3709 obj
->madv
= I915_MADV_WILLNEED
;
3710 /* Avoid an unnecessary call to unbind on the first bind. */
3711 obj
->map_and_fenceable
= true;
3713 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3716 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3717 .get_pages
= i915_gem_object_get_pages_gtt
,
3718 .put_pages
= i915_gem_object_put_pages_gtt
,
3721 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3724 struct drm_i915_gem_object
*obj
;
3725 struct address_space
*mapping
;
3728 obj
= i915_gem_object_alloc(dev
);
3732 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3733 i915_gem_object_free(obj
);
3737 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3738 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3739 /* 965gm cannot relocate objects above 4GiB. */
3740 mask
&= ~__GFP_HIGHMEM
;
3741 mask
|= __GFP_DMA32
;
3744 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3745 mapping_set_gfp_mask(mapping
, mask
);
3747 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3749 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3750 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3753 /* On some devices, we can have the GPU use the LLC (the CPU
3754 * cache) for about a 10% performance improvement
3755 * compared to uncached. Graphics requests other than
3756 * display scanout are coherent with the CPU in
3757 * accessing this cache. This means in this mode we
3758 * don't need to clflush on the CPU side, and on the
3759 * GPU side we only need to flush internal caches to
3760 * get data visible to the CPU.
3762 * However, we maintain the display planes as UC, and so
3763 * need to rebind when first used as such.
3765 obj
->cache_level
= I915_CACHE_LLC
;
3767 obj
->cache_level
= I915_CACHE_NONE
;
3772 int i915_gem_init_object(struct drm_gem_object
*obj
)
3779 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3781 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3782 struct drm_device
*dev
= obj
->base
.dev
;
3783 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3785 trace_i915_gem_object_destroy(obj
);
3788 i915_gem_detach_phys_object(dev
, obj
);
3791 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3792 bool was_interruptible
;
3794 was_interruptible
= dev_priv
->mm
.interruptible
;
3795 dev_priv
->mm
.interruptible
= false;
3797 WARN_ON(i915_gem_object_unbind(obj
));
3799 dev_priv
->mm
.interruptible
= was_interruptible
;
3802 obj
->pages_pin_count
= 0;
3803 i915_gem_object_put_pages(obj
);
3804 i915_gem_object_free_mmap_offset(obj
);
3805 i915_gem_object_release_stolen(obj
);
3809 if (obj
->base
.import_attach
)
3810 drm_prime_gem_destroy(&obj
->base
, NULL
);
3812 drm_gem_object_release(&obj
->base
);
3813 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3816 i915_gem_object_free(obj
);
3820 i915_gem_idle(struct drm_device
*dev
)
3822 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3825 mutex_lock(&dev
->struct_mutex
);
3827 if (dev_priv
->mm
.suspended
) {
3828 mutex_unlock(&dev
->struct_mutex
);
3832 ret
= i915_gpu_idle(dev
);
3834 mutex_unlock(&dev
->struct_mutex
);
3837 i915_gem_retire_requests(dev
);
3839 /* Under UMS, be paranoid and evict. */
3840 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3841 i915_gem_evict_everything(dev
);
3843 i915_gem_reset_fences(dev
);
3845 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3846 * We need to replace this with a semaphore, or something.
3847 * And not confound mm.suspended!
3849 dev_priv
->mm
.suspended
= 1;
3850 del_timer_sync(&dev_priv
->hangcheck_timer
);
3852 i915_kernel_lost_context(dev
);
3853 i915_gem_cleanup_ringbuffer(dev
);
3855 mutex_unlock(&dev
->struct_mutex
);
3857 /* Cancel the retire work handler, which should be idle now. */
3858 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3863 void i915_gem_l3_remap(struct drm_device
*dev
)
3865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3869 if (!IS_IVYBRIDGE(dev
))
3872 if (!dev_priv
->l3_parity
.remap_info
)
3875 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3876 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3877 POSTING_READ(GEN7_MISCCPCTL
);
3879 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3880 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3881 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3882 DRM_DEBUG("0x%x was already programmed to %x\n",
3883 GEN7_L3LOG_BASE
+ i
, remap
);
3884 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3885 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3886 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3889 /* Make sure all the writes land before disabling dop clock gating */
3890 POSTING_READ(GEN7_L3LOG_BASE
);
3892 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3895 void i915_gem_init_swizzling(struct drm_device
*dev
)
3897 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3899 if (INTEL_INFO(dev
)->gen
< 5 ||
3900 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3903 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3904 DISP_TILE_SURFACE_SWIZZLING
);
3909 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3911 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3912 else if (IS_GEN7(dev
))
3913 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3919 intel_enable_blt(struct drm_device
*dev
)
3924 /* The blitter was dysfunctional on early prototypes */
3925 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3926 DRM_INFO("BLT not supported on this pre-production hardware;"
3927 " graphics performance will be degraded.\n");
3935 i915_gem_init_hw(struct drm_device
*dev
)
3937 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3940 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3943 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3944 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3946 i915_gem_l3_remap(dev
);
3948 i915_gem_init_swizzling(dev
);
3950 dev_priv
->next_seqno
= dev_priv
->last_seqno
= (u32
)~0 - 0x1000;
3952 ret
= intel_init_render_ring_buffer(dev
);
3957 ret
= intel_init_bsd_ring_buffer(dev
);
3959 goto cleanup_render_ring
;
3962 if (intel_enable_blt(dev
)) {
3963 ret
= intel_init_blt_ring_buffer(dev
);
3965 goto cleanup_bsd_ring
;
3969 * XXX: There was some w/a described somewhere suggesting loading
3970 * contexts before PPGTT.
3972 i915_gem_context_init(dev
);
3973 i915_gem_init_ppgtt(dev
);
3978 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3979 cleanup_render_ring
:
3980 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3985 intel_enable_ppgtt(struct drm_device
*dev
)
3987 if (i915_enable_ppgtt
>= 0)
3988 return i915_enable_ppgtt
;
3990 #ifdef CONFIG_INTEL_IOMMU
3991 /* Disable ppgtt on SNB if VT-d is on. */
3992 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3999 int i915_gem_init(struct drm_device
*dev
)
4001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4002 unsigned long gtt_size
, mappable_size
;
4005 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
4006 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
4008 mutex_lock(&dev
->struct_mutex
);
4009 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
4010 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4011 * aperture accordingly when using aliasing ppgtt. */
4012 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
4014 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
4016 ret
= i915_gem_init_aliasing_ppgtt(dev
);
4018 mutex_unlock(&dev
->struct_mutex
);
4022 /* Let GEM Manage all of the aperture.
4024 * However, leave one page at the end still bound to the scratch
4025 * page. There are a number of places where the hardware
4026 * apparently prefetches past the end of the object, and we've
4027 * seen multiple hangs with the GPU head pointer stuck in a
4028 * batchbuffer bound at the last page of the aperture. One page
4029 * should be enough to keep any prefetching inside of the
4032 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
4036 ret
= i915_gem_init_hw(dev
);
4037 mutex_unlock(&dev
->struct_mutex
);
4039 i915_gem_cleanup_aliasing_ppgtt(dev
);
4043 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4044 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4045 dev_priv
->dri1
.allow_batchbuffer
= 1;
4050 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4052 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4053 struct intel_ring_buffer
*ring
;
4056 for_each_ring(ring
, dev_priv
, i
)
4057 intel_cleanup_ring_buffer(ring
);
4061 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4062 struct drm_file
*file_priv
)
4064 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4067 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4070 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4071 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4072 atomic_set(&dev_priv
->mm
.wedged
, 0);
4075 mutex_lock(&dev
->struct_mutex
);
4076 dev_priv
->mm
.suspended
= 0;
4078 ret
= i915_gem_init_hw(dev
);
4080 mutex_unlock(&dev
->struct_mutex
);
4084 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4085 mutex_unlock(&dev
->struct_mutex
);
4087 ret
= drm_irq_install(dev
);
4089 goto cleanup_ringbuffer
;
4094 mutex_lock(&dev
->struct_mutex
);
4095 i915_gem_cleanup_ringbuffer(dev
);
4096 dev_priv
->mm
.suspended
= 1;
4097 mutex_unlock(&dev
->struct_mutex
);
4103 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4104 struct drm_file
*file_priv
)
4106 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4109 drm_irq_uninstall(dev
);
4110 return i915_gem_idle(dev
);
4114 i915_gem_lastclose(struct drm_device
*dev
)
4118 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4121 ret
= i915_gem_idle(dev
);
4123 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4127 init_ring_lists(struct intel_ring_buffer
*ring
)
4129 INIT_LIST_HEAD(&ring
->active_list
);
4130 INIT_LIST_HEAD(&ring
->request_list
);
4134 i915_gem_load(struct drm_device
*dev
)
4136 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4140 kmem_cache_create("i915_gem_object",
4141 sizeof(struct drm_i915_gem_object
), 0,
4145 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4146 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4147 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4148 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4149 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4150 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4151 init_ring_lists(&dev_priv
->ring
[i
]);
4152 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4153 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4154 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4155 i915_gem_retire_work_handler
);
4156 init_completion(&dev_priv
->error_completion
);
4158 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4160 I915_WRITE(MI_ARB_STATE
,
4161 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4164 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4166 /* Old X drivers will take 0-2 for front, back, depth buffers */
4167 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4168 dev_priv
->fence_reg_start
= 3;
4170 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4171 dev_priv
->num_fence_regs
= 16;
4173 dev_priv
->num_fence_regs
= 8;
4175 /* Initialize fence registers to zero */
4176 i915_gem_reset_fences(dev
);
4178 i915_gem_detect_bit_6_swizzle(dev
);
4179 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4181 dev_priv
->mm
.interruptible
= true;
4183 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4184 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4185 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4189 * Create a physically contiguous memory object for this object
4190 * e.g. for cursor + overlay regs
4192 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4193 int id
, int size
, int align
)
4195 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4196 struct drm_i915_gem_phys_object
*phys_obj
;
4199 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4202 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4208 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4209 if (!phys_obj
->handle
) {
4214 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4217 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4225 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4228 struct drm_i915_gem_phys_object
*phys_obj
;
4230 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4233 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4234 if (phys_obj
->cur_obj
) {
4235 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4239 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4241 drm_pci_free(dev
, phys_obj
->handle
);
4243 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4246 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4250 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4251 i915_gem_free_phys_object(dev
, i
);
4254 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4255 struct drm_i915_gem_object
*obj
)
4257 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4264 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4266 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4267 for (i
= 0; i
< page_count
; i
++) {
4268 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4269 if (!IS_ERR(page
)) {
4270 char *dst
= kmap_atomic(page
);
4271 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4274 drm_clflush_pages(&page
, 1);
4276 set_page_dirty(page
);
4277 mark_page_accessed(page
);
4278 page_cache_release(page
);
4281 i915_gem_chipset_flush(dev
);
4283 obj
->phys_obj
->cur_obj
= NULL
;
4284 obj
->phys_obj
= NULL
;
4288 i915_gem_attach_phys_object(struct drm_device
*dev
,
4289 struct drm_i915_gem_object
*obj
,
4293 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4294 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4299 if (id
> I915_MAX_PHYS_OBJECT
)
4302 if (obj
->phys_obj
) {
4303 if (obj
->phys_obj
->id
== id
)
4305 i915_gem_detach_phys_object(dev
, obj
);
4308 /* create a new object */
4309 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4310 ret
= i915_gem_init_phys_object(dev
, id
,
4311 obj
->base
.size
, align
);
4313 DRM_ERROR("failed to init phys object %d size: %zu\n",
4314 id
, obj
->base
.size
);
4319 /* bind to the object */
4320 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4321 obj
->phys_obj
->cur_obj
= obj
;
4323 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4325 for (i
= 0; i
< page_count
; i
++) {
4329 page
= shmem_read_mapping_page(mapping
, i
);
4331 return PTR_ERR(page
);
4333 src
= kmap_atomic(page
);
4334 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4335 memcpy(dst
, src
, PAGE_SIZE
);
4338 mark_page_accessed(page
);
4339 page_cache_release(page
);
4346 i915_gem_phys_pwrite(struct drm_device
*dev
,
4347 struct drm_i915_gem_object
*obj
,
4348 struct drm_i915_gem_pwrite
*args
,
4349 struct drm_file
*file_priv
)
4351 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4352 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4355 unsigned long unwritten
;
4357 /* The physical object once assigned is fixed for the lifetime
4358 * of the obj, so we can safely drop the lock and continue
4361 mutex_unlock(&dev
->struct_mutex
);
4362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4363 mutex_lock(&dev
->struct_mutex
);
4368 i915_gem_chipset_flush(dev
);
4372 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4374 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4376 /* Clean up our request list when the client is going away, so that
4377 * later retire_requests won't dereference our soon-to-be-gone
4380 spin_lock(&file_priv
->mm
.lock
);
4381 while (!list_empty(&file_priv
->mm
.request_list
)) {
4382 struct drm_i915_gem_request
*request
;
4384 request
= list_first_entry(&file_priv
->mm
.request_list
,
4385 struct drm_i915_gem_request
,
4387 list_del(&request
->client_list
);
4388 request
->file_priv
= NULL
;
4390 spin_unlock(&file_priv
->mm
.lock
);
4393 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4395 if (!mutex_is_locked(mutex
))
4398 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4399 return mutex
->owner
== task
;
4401 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4407 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4409 struct drm_i915_private
*dev_priv
=
4410 container_of(shrinker
,
4411 struct drm_i915_private
,
4412 mm
.inactive_shrinker
);
4413 struct drm_device
*dev
= dev_priv
->dev
;
4414 struct drm_i915_gem_object
*obj
;
4415 int nr_to_scan
= sc
->nr_to_scan
;
4419 if (!mutex_trylock(&dev
->struct_mutex
)) {
4420 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4427 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4429 i915_gem_shrink_all(dev_priv
);
4433 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4434 if (obj
->pages_pin_count
== 0)
4435 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4436 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4437 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4438 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4441 mutex_unlock(&dev
->struct_mutex
);