2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 static void lut_close(struct i915_gem_context
*ctx
)
98 struct i915_lut_handle
*lut
, *ln
;
99 struct radix_tree_iter iter
;
102 list_for_each_entry_safe(lut
, ln
, &ctx
->handles_list
, ctx_link
) {
103 list_del(&lut
->obj_link
);
104 kmem_cache_free(ctx
->i915
->luts
, lut
);
107 radix_tree_for_each_slot(slot
, &ctx
->handles_vma
, &iter
, 0) {
108 struct i915_vma
*vma
= rcu_dereference_raw(*slot
);
109 struct drm_i915_gem_object
*obj
= vma
->obj
;
111 radix_tree_iter_delete(&ctx
->handles_vma
, &iter
, slot
);
113 if (!i915_vma_is_ggtt(vma
))
116 __i915_gem_object_release_unless_active(obj
);
120 static void i915_gem_context_free(struct i915_gem_context
*ctx
)
124 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
125 GEM_BUG_ON(!i915_gem_context_is_closed(ctx
));
127 i915_ppgtt_put(ctx
->ppgtt
);
129 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
130 struct intel_context
*ce
= &ctx
->engine
[i
];
135 WARN_ON(ce
->pin_count
);
137 intel_ring_free(ce
->ring
);
139 __i915_gem_object_release_unless_active(ce
->state
->obj
);
145 list_del(&ctx
->link
);
147 ida_simple_remove(&ctx
->i915
->contexts
.hw_ida
, ctx
->hw_id
);
151 static void contexts_free(struct drm_i915_private
*i915
)
153 struct llist_node
*freed
= llist_del_all(&i915
->contexts
.free_list
);
154 struct i915_gem_context
*ctx
, *cn
;
156 lockdep_assert_held(&i915
->drm
.struct_mutex
);
158 llist_for_each_entry_safe(ctx
, cn
, freed
, free_link
)
159 i915_gem_context_free(ctx
);
162 static void contexts_free_first(struct drm_i915_private
*i915
)
164 struct i915_gem_context
*ctx
;
165 struct llist_node
*freed
;
167 lockdep_assert_held(&i915
->drm
.struct_mutex
);
169 freed
= llist_del_first(&i915
->contexts
.free_list
);
173 ctx
= container_of(freed
, typeof(*ctx
), free_link
);
174 i915_gem_context_free(ctx
);
177 static void contexts_free_worker(struct work_struct
*work
)
179 struct drm_i915_private
*i915
=
180 container_of(work
, typeof(*i915
), contexts
.free_work
);
182 mutex_lock(&i915
->drm
.struct_mutex
);
184 mutex_unlock(&i915
->drm
.struct_mutex
);
187 void i915_gem_context_release(struct kref
*ref
)
189 struct i915_gem_context
*ctx
= container_of(ref
, typeof(*ctx
), ref
);
190 struct drm_i915_private
*i915
= ctx
->i915
;
192 trace_i915_context_free(ctx
);
193 if (llist_add(&ctx
->free_link
, &i915
->contexts
.free_list
))
194 queue_work(i915
->wq
, &i915
->contexts
.free_work
);
197 static void context_close(struct i915_gem_context
*ctx
)
199 i915_gem_context_set_closed(ctx
);
203 i915_ppgtt_close(&ctx
->ppgtt
->base
);
205 ctx
->file_priv
= ERR_PTR(-EBADF
);
206 i915_gem_context_put(ctx
);
209 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
213 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
214 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
216 /* Contexts are only released when no longer active.
217 * Flush any pending retires to hopefully release some
218 * stale contexts and try again.
220 i915_gem_retire_requests(dev_priv
);
221 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
222 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
231 static u32
default_desc_template(const struct drm_i915_private
*i915
,
232 const struct i915_hw_ppgtt
*ppgtt
)
237 desc
= GEN8_CTX_VALID
| GEN8_CTX_PRIVILEGE
;
239 address_mode
= INTEL_LEGACY_32B_CONTEXT
;
240 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
))
241 address_mode
= INTEL_LEGACY_64B_CONTEXT
;
242 desc
|= address_mode
<< GEN8_CTX_ADDRESSING_MODE_SHIFT
;
245 desc
|= GEN8_CTX_L3LLC_COHERENT
;
247 /* TODO: WaDisableLiteRestore when we start using semaphore
248 * signalling between Command Streamers
249 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
255 static struct i915_gem_context
*
256 __create_hw_context(struct drm_i915_private
*dev_priv
,
257 struct drm_i915_file_private
*file_priv
)
259 struct i915_gem_context
*ctx
;
262 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
264 return ERR_PTR(-ENOMEM
);
266 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
272 kref_init(&ctx
->ref
);
273 list_add_tail(&ctx
->link
, &dev_priv
->contexts
.list
);
274 ctx
->i915
= dev_priv
;
275 ctx
->priority
= I915_PRIORITY_NORMAL
;
277 INIT_RADIX_TREE(&ctx
->handles_vma
, GFP_KERNEL
);
278 INIT_LIST_HEAD(&ctx
->handles_list
);
280 /* Default context will never have a file_priv */
281 ret
= DEFAULT_CONTEXT_HANDLE
;
283 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
284 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
288 ctx
->user_handle
= ret
;
290 ctx
->file_priv
= file_priv
;
292 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
293 ctx
->name
= kasprintf(GFP_KERNEL
, "%s[%d]/%x",
303 /* NB: Mark all slices as needing a remap so that when the context first
304 * loads it will restore whatever remap state already exists. If there
305 * is no remap info, it will be a NOP. */
306 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
308 i915_gem_context_set_bannable(ctx
);
309 ctx
->ring_size
= 4 * PAGE_SIZE
;
311 default_desc_template(dev_priv
, dev_priv
->mm
.aliasing_ppgtt
);
313 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
314 * present or not in use we still need a small bias as ring wraparound
315 * at offset 0 sometimes hangs. No idea why.
317 if (HAS_GUC(dev_priv
) && i915_modparams
.enable_guc_loading
)
318 ctx
->ggtt_offset_bias
= GUC_WOPCM_TOP
;
320 ctx
->ggtt_offset_bias
= I915_GTT_PAGE_SIZE
;
326 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
332 static void __destroy_hw_context(struct i915_gem_context
*ctx
,
333 struct drm_i915_file_private
*file_priv
)
335 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
340 * The default context needs to exist per ring that uses contexts. It stores the
341 * context state of the GPU for applications that don't utilize HW contexts, as
342 * well as an idle case.
344 static struct i915_gem_context
*
345 i915_gem_create_context(struct drm_i915_private
*dev_priv
,
346 struct drm_i915_file_private
*file_priv
)
348 struct i915_gem_context
*ctx
;
350 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
352 /* Reap the most stale context */
353 contexts_free_first(dev_priv
);
355 ctx
= __create_hw_context(dev_priv
, file_priv
);
359 if (USES_FULL_PPGTT(dev_priv
)) {
360 struct i915_hw_ppgtt
*ppgtt
;
362 ppgtt
= i915_ppgtt_create(dev_priv
, file_priv
, ctx
->name
);
364 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
366 __destroy_hw_context(ctx
, file_priv
);
367 return ERR_CAST(ppgtt
);
371 ctx
->desc_template
= default_desc_template(dev_priv
, ppgtt
);
374 trace_i915_context_create(ctx
);
380 * i915_gem_context_create_gvt - create a GVT GEM context
383 * This function is used to create a GVT specific GEM context.
386 * pointer to i915_gem_context on success, error pointer if failed
389 struct i915_gem_context
*
390 i915_gem_context_create_gvt(struct drm_device
*dev
)
392 struct i915_gem_context
*ctx
;
395 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
396 return ERR_PTR(-ENODEV
);
398 ret
= i915_mutex_lock_interruptible(dev
);
402 ctx
= __create_hw_context(to_i915(dev
), NULL
);
406 ctx
->file_priv
= ERR_PTR(-EBADF
);
407 i915_gem_context_set_closed(ctx
); /* not user accessible */
408 i915_gem_context_clear_bannable(ctx
);
409 i915_gem_context_set_force_single_submission(ctx
);
410 if (!i915_modparams
.enable_guc_submission
)
411 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
413 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
415 mutex_unlock(&dev
->struct_mutex
);
419 static struct i915_gem_context
*
420 create_kernel_context(struct drm_i915_private
*i915
, int prio
)
422 struct i915_gem_context
*ctx
;
424 ctx
= i915_gem_create_context(i915
, NULL
);
428 i915_gem_context_clear_bannable(ctx
);
429 ctx
->priority
= prio
;
430 ctx
->ring_size
= PAGE_SIZE
;
432 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
438 destroy_kernel_context(struct i915_gem_context
**ctxp
)
440 struct i915_gem_context
*ctx
;
442 /* Keep the context ref so that we can free it immediately ourselves */
443 ctx
= i915_gem_context_get(fetch_and_zero(ctxp
));
444 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
447 i915_gem_context_free(ctx
);
450 int i915_gem_contexts_init(struct drm_i915_private
*dev_priv
)
452 struct i915_gem_context
*ctx
;
455 GEM_BUG_ON(dev_priv
->kernel_context
);
457 INIT_LIST_HEAD(&dev_priv
->contexts
.list
);
458 INIT_WORK(&dev_priv
->contexts
.free_work
, contexts_free_worker
);
459 init_llist_head(&dev_priv
->contexts
.free_list
);
461 if (intel_vgpu_active(dev_priv
) &&
462 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
463 if (!i915_modparams
.enable_execlists
) {
464 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
469 /* Using the simple ida interface, the max is limited by sizeof(int) */
470 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
471 ida_init(&dev_priv
->contexts
.hw_ida
);
473 /* lowest priority; idle task */
474 ctx
= create_kernel_context(dev_priv
, I915_PRIORITY_MIN
);
476 DRM_ERROR("Failed to create default global context\n");
481 * For easy recognisablity, we want the kernel context to be 0 and then
482 * all user contexts will have non-zero hw_id.
484 GEM_BUG_ON(ctx
->hw_id
);
485 dev_priv
->kernel_context
= ctx
;
487 /* highest priority; preempting task */
488 ctx
= create_kernel_context(dev_priv
, INT_MAX
);
490 DRM_ERROR("Failed to create default preempt context\n");
492 goto err_kernel_context
;
494 dev_priv
->preempt_context
= ctx
;
496 DRM_DEBUG_DRIVER("%s context support initialized\n",
497 dev_priv
->engine
[RCS
]->context_size
? "logical" :
502 destroy_kernel_context(&dev_priv
->kernel_context
);
507 void i915_gem_contexts_lost(struct drm_i915_private
*dev_priv
)
509 struct intel_engine_cs
*engine
;
510 enum intel_engine_id id
;
512 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
514 for_each_engine(engine
, dev_priv
, id
) {
515 engine
->legacy_active_context
= NULL
;
517 if (!engine
->last_retired_context
)
520 engine
->context_unpin(engine
, engine
->last_retired_context
);
521 engine
->last_retired_context
= NULL
;
524 /* Force the GPU state to be restored on enabling */
525 if (!i915_modparams
.enable_execlists
) {
526 struct i915_gem_context
*ctx
;
528 list_for_each_entry(ctx
, &dev_priv
->contexts
.list
, link
) {
529 if (!i915_gem_context_is_default(ctx
))
532 for_each_engine(engine
, dev_priv
, id
)
533 ctx
->engine
[engine
->id
].initialised
= false;
535 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
538 for_each_engine(engine
, dev_priv
, id
) {
539 struct intel_context
*kce
=
540 &dev_priv
->kernel_context
->engine
[engine
->id
];
542 kce
->initialised
= true;
547 void i915_gem_contexts_fini(struct drm_i915_private
*i915
)
549 lockdep_assert_held(&i915
->drm
.struct_mutex
);
551 destroy_kernel_context(&i915
->preempt_context
);
552 destroy_kernel_context(&i915
->kernel_context
);
554 /* Must free all deferred contexts (via flush_workqueue) first */
555 ida_destroy(&i915
->contexts
.hw_ida
);
558 static int context_idr_cleanup(int id
, void *p
, void *data
)
560 struct i915_gem_context
*ctx
= p
;
566 int i915_gem_context_open(struct drm_i915_private
*i915
,
567 struct drm_file
*file
)
569 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
570 struct i915_gem_context
*ctx
;
572 idr_init(&file_priv
->context_idr
);
574 mutex_lock(&i915
->drm
.struct_mutex
);
575 ctx
= i915_gem_create_context(i915
, file_priv
);
576 mutex_unlock(&i915
->drm
.struct_mutex
);
578 idr_destroy(&file_priv
->context_idr
);
582 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
587 void i915_gem_context_close(struct drm_file
*file
)
589 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
591 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
593 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
594 idr_destroy(&file_priv
->context_idr
);
598 mi_set_context(struct drm_i915_gem_request
*req
, u32 flags
)
600 struct drm_i915_private
*dev_priv
= req
->i915
;
601 struct intel_engine_cs
*engine
= req
->engine
;
602 enum intel_engine_id id
;
603 const int num_rings
=
604 /* Use an extended w/a on gen7 if signalling from other rings */
605 (i915_modparams
.semaphores
&& INTEL_GEN(dev_priv
) == 7) ?
606 INTEL_INFO(dev_priv
)->num_rings
- 1 :
611 flags
|= MI_MM_SPACE_GTT
;
612 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
613 /* These flags are for resource streamer on HSW+ */
614 flags
|= HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
;
616 flags
|= MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
;
619 if (INTEL_GEN(dev_priv
) >= 7)
620 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
622 cs
= intel_ring_begin(req
, len
);
626 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
627 if (INTEL_GEN(dev_priv
) >= 7) {
628 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
630 struct intel_engine_cs
*signaller
;
632 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
633 for_each_engine(signaller
, dev_priv
, id
) {
634 if (signaller
== engine
)
637 *cs
++ = i915_mmio_reg_offset(
638 RING_PSMI_CTL(signaller
->mmio_base
));
639 *cs
++ = _MASKED_BIT_ENABLE(
640 GEN6_PSMI_SLEEP_MSG_DISABLE
);
646 *cs
++ = MI_SET_CONTEXT
;
647 *cs
++ = i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
;
649 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
650 * WaMiSetContext_Hang:snb,ivb,vlv
654 if (INTEL_GEN(dev_priv
) >= 7) {
656 struct intel_engine_cs
*signaller
;
657 i915_reg_t last_reg
= {}; /* keep gcc quiet */
659 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
660 for_each_engine(signaller
, dev_priv
, id
) {
661 if (signaller
== engine
)
664 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
665 *cs
++ = i915_mmio_reg_offset(last_reg
);
666 *cs
++ = _MASKED_BIT_DISABLE(
667 GEN6_PSMI_SLEEP_MSG_DISABLE
);
670 /* Insert a delay before the next switch! */
671 *cs
++ = MI_STORE_REGISTER_MEM
| MI_SRM_LRM_GLOBAL_GTT
;
672 *cs
++ = i915_mmio_reg_offset(last_reg
);
673 *cs
++ = i915_ggtt_offset(engine
->scratch
);
676 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
679 intel_ring_advance(req
, cs
);
684 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
686 u32
*cs
, *remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
692 cs
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
697 * Note: We do not worry about the concurrent register cacheline hang
698 * here because no other code should access these registers other than
699 * at initialization time.
701 *cs
++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4);
702 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
703 *cs
++ = i915_mmio_reg_offset(GEN7_L3LOG(slice
, i
));
704 *cs
++ = remap_info
[i
];
707 intel_ring_advance(req
, cs
);
712 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
713 struct intel_engine_cs
*engine
,
714 struct i915_gem_context
*to
)
719 if (!to
->engine
[RCS
].initialised
)
722 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
725 return to
== engine
->legacy_active_context
;
729 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
, struct intel_engine_cs
*engine
)
731 struct i915_gem_context
*from
= engine
->legacy_active_context
;
736 /* Always load the ppgtt on first use */
740 /* Same context without new entries, skip */
741 if ((!from
->ppgtt
|| from
->ppgtt
== ppgtt
) &&
742 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
745 if (engine
->id
!= RCS
)
748 if (INTEL_GEN(engine
->i915
) < 8)
755 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
756 struct i915_gem_context
*to
,
762 if (!IS_GEN8(to
->i915
))
765 if (hw_flags
& MI_RESTORE_INHIBIT
)
771 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
773 struct i915_gem_context
*to
= req
->ctx
;
774 struct intel_engine_cs
*engine
= req
->engine
;
775 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
776 struct i915_gem_context
*from
= engine
->legacy_active_context
;
780 GEM_BUG_ON(engine
->id
!= RCS
);
782 if (skip_rcs_switch(ppgtt
, engine
, to
))
785 if (needs_pd_load_pre(ppgtt
, engine
)) {
786 /* Older GENs and non render rings still want the load first,
787 * "PP_DCLV followed by PP_DIR_BASE register through Load
788 * Register Immediate commands in Ring Buffer before submitting
790 trace_switch_mm(engine
, to
);
791 ret
= ppgtt
->switch_mm(ppgtt
, req
);
796 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
797 /* NB: If we inhibit the restore, the context is not allowed to
798 * die because future work may end up depending on valid address
799 * space. This means we must enforce that a page table load
800 * occur when this occurs. */
801 hw_flags
= MI_RESTORE_INHIBIT
;
802 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
803 hw_flags
= MI_FORCE_RESTORE
;
807 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
808 ret
= mi_set_context(req
, hw_flags
);
812 engine
->legacy_active_context
= to
;
815 /* GEN8 does *not* require an explicit reload if the PDPs have been
816 * setup, and we do not wish to move them.
818 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
819 trace_switch_mm(engine
, to
);
820 ret
= ppgtt
->switch_mm(ppgtt
, req
);
821 /* The hardware context switch is emitted, but we haven't
822 * actually changed the state - so it's probably safe to bail
823 * here. Still, let the user know something dangerous has
831 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
833 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
834 if (!(to
->remap_slice
& (1<<i
)))
837 ret
= remap_l3(req
, i
);
841 to
->remap_slice
&= ~(1<<i
);
844 if (!to
->engine
[RCS
].initialised
) {
845 if (engine
->init_context
) {
846 ret
= engine
->init_context(req
);
850 to
->engine
[RCS
].initialised
= true;
857 * i915_switch_context() - perform a GPU context switch.
858 * @req: request for which we'll execute the context switch
860 * The context life cycle is simple. The context refcount is incremented and
861 * decremented by 1 and create and destroy. If the context is in use by the GPU,
862 * it will have a refcount > 1. This allows us to destroy the context abstract
863 * object while letting the normal object tracking destroy the backing BO.
865 * This function should not be used in execlists mode. Instead the context is
866 * switched by writing to the ELSP and requests keep a reference to their
869 int i915_switch_context(struct drm_i915_gem_request
*req
)
871 struct intel_engine_cs
*engine
= req
->engine
;
873 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
874 if (i915_modparams
.enable_execlists
)
877 if (!req
->ctx
->engine
[engine
->id
].state
) {
878 struct i915_gem_context
*to
= req
->ctx
;
879 struct i915_hw_ppgtt
*ppgtt
=
880 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
882 if (needs_pd_load_pre(ppgtt
, engine
)) {
885 trace_switch_mm(engine
, to
);
886 ret
= ppgtt
->switch_mm(ppgtt
, req
);
890 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
893 engine
->legacy_active_context
= to
;
897 return do_rcs_switch(req
);
900 static bool engine_has_kernel_context(struct intel_engine_cs
*engine
)
902 struct i915_gem_timeline
*timeline
;
904 list_for_each_entry(timeline
, &engine
->i915
->gt
.timelines
, link
) {
905 struct intel_timeline
*tl
;
907 if (timeline
== &engine
->i915
->gt
.global_timeline
)
910 tl
= &timeline
->engine
[engine
->id
];
911 if (i915_gem_active_peek(&tl
->last_request
,
912 &engine
->i915
->drm
.struct_mutex
))
916 return (!engine
->last_retired_context
||
917 i915_gem_context_is_kernel(engine
->last_retired_context
));
920 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
922 struct intel_engine_cs
*engine
;
923 struct i915_gem_timeline
*timeline
;
924 enum intel_engine_id id
;
926 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
928 i915_gem_retire_requests(dev_priv
);
930 for_each_engine(engine
, dev_priv
, id
) {
931 struct drm_i915_gem_request
*req
;
934 if (engine_has_kernel_context(engine
))
937 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
941 /* Queue this switch after all other activity */
942 list_for_each_entry(timeline
, &dev_priv
->gt
.timelines
, link
) {
943 struct drm_i915_gem_request
*prev
;
944 struct intel_timeline
*tl
;
946 tl
= &timeline
->engine
[engine
->id
];
947 prev
= i915_gem_active_raw(&tl
->last_request
,
948 &dev_priv
->drm
.struct_mutex
);
950 i915_sw_fence_await_sw_fence_gfp(&req
->submit
,
955 ret
= i915_switch_context(req
);
956 i915_add_request(req
);
964 static bool client_is_banned(struct drm_i915_file_private
*file_priv
)
966 return atomic_read(&file_priv
->context_bans
) > I915_MAX_CLIENT_CONTEXT_BANS
;
969 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
970 struct drm_file
*file
)
972 struct drm_i915_private
*dev_priv
= to_i915(dev
);
973 struct drm_i915_gem_context_create
*args
= data
;
974 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
975 struct i915_gem_context
*ctx
;
978 if (!dev_priv
->engine
[RCS
]->context_size
)
984 if (client_is_banned(file_priv
)) {
985 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
987 pid_nr(get_task_pid(current
, PIDTYPE_PID
)));
992 ret
= i915_mutex_lock_interruptible(dev
);
996 ctx
= i915_gem_create_context(dev_priv
, file_priv
);
997 mutex_unlock(&dev
->struct_mutex
);
1001 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
1003 args
->ctx_id
= ctx
->user_handle
;
1004 DRM_DEBUG("HW context %d created\n", args
->ctx_id
);
1009 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1010 struct drm_file
*file
)
1012 struct drm_i915_gem_context_destroy
*args
= data
;
1013 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1014 struct i915_gem_context
*ctx
;
1020 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
1023 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1027 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1031 __destroy_hw_context(ctx
, file_priv
);
1032 mutex_unlock(&dev
->struct_mutex
);
1035 i915_gem_context_put(ctx
);
1039 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1040 struct drm_file
*file
)
1042 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1043 struct drm_i915_gem_context_param
*args
= data
;
1044 struct i915_gem_context
*ctx
;
1047 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1052 switch (args
->param
) {
1053 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1056 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1057 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1059 case I915_CONTEXT_PARAM_GTT_SIZE
:
1061 args
->value
= ctx
->ppgtt
->base
.total
;
1062 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1063 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1065 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1067 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1068 args
->value
= i915_gem_context_no_error_capture(ctx
);
1070 case I915_CONTEXT_PARAM_BANNABLE
:
1071 args
->value
= i915_gem_context_is_bannable(ctx
);
1073 case I915_CONTEXT_PARAM_PRIORITY
:
1074 args
->value
= ctx
->priority
;
1081 i915_gem_context_put(ctx
);
1085 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1086 struct drm_file
*file
)
1088 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1089 struct drm_i915_gem_context_param
*args
= data
;
1090 struct i915_gem_context
*ctx
;
1093 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1097 ret
= i915_mutex_lock_interruptible(dev
);
1101 switch (args
->param
) {
1102 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1105 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1109 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1110 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1113 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1116 else if (args
->value
)
1117 i915_gem_context_set_no_error_capture(ctx
);
1119 i915_gem_context_clear_no_error_capture(ctx
);
1121 case I915_CONTEXT_PARAM_BANNABLE
:
1124 else if (!capable(CAP_SYS_ADMIN
) && !args
->value
)
1126 else if (args
->value
)
1127 i915_gem_context_set_bannable(ctx
);
1129 i915_gem_context_clear_bannable(ctx
);
1132 case I915_CONTEXT_PARAM_PRIORITY
:
1134 int priority
= args
->value
;
1138 else if (!to_i915(dev
)->engine
[RCS
]->schedule
)
1140 else if (priority
> I915_CONTEXT_MAX_USER_PRIORITY
||
1141 priority
< I915_CONTEXT_MIN_USER_PRIORITY
)
1143 else if (priority
> I915_CONTEXT_DEFAULT_PRIORITY
&&
1144 !capable(CAP_SYS_NICE
))
1147 ctx
->priority
= priority
;
1155 mutex_unlock(&dev
->struct_mutex
);
1158 i915_gem_context_put(ctx
);
1162 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1163 void *data
, struct drm_file
*file
)
1165 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1166 struct drm_i915_reset_stats
*args
= data
;
1167 struct i915_gem_context
*ctx
;
1170 if (args
->flags
|| args
->pad
)
1175 ctx
= __i915_gem_context_lookup_rcu(file
->driver_priv
, args
->ctx_id
);
1180 * We opt for unserialised reads here. This may result in tearing
1181 * in the extremely unlikely event of a GPU hang on this context
1182 * as we are querying them. If we need that extra layer of protection,
1183 * we should wrap the hangstats with a seqlock.
1186 if (capable(CAP_SYS_ADMIN
))
1187 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1189 args
->reset_count
= 0;
1191 args
->batch_active
= atomic_read(&ctx
->guilty_count
);
1192 args
->batch_pending
= atomic_read(&ctx
->active_count
);
1200 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1201 #include "selftests/mock_context.c"
1202 #include "selftests/i915_gem_context.c"