2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 static void lut_close(struct i915_gem_context
*ctx
)
98 struct i915_lut_handle
*lut
, *ln
;
99 struct radix_tree_iter iter
;
102 list_for_each_entry_safe(lut
, ln
, &ctx
->handles_list
, ctx_link
) {
103 list_del(&lut
->obj_link
);
104 kmem_cache_free(ctx
->i915
->luts
, lut
);
108 radix_tree_for_each_slot(slot
, &ctx
->handles_vma
, &iter
, 0) {
109 struct i915_vma
*vma
= rcu_dereference_raw(*slot
);
110 struct drm_i915_gem_object
*obj
= vma
->obj
;
112 radix_tree_iter_delete(&ctx
->handles_vma
, &iter
, slot
);
114 if (!i915_vma_is_ggtt(vma
))
117 __i915_gem_object_release_unless_active(obj
);
122 static void i915_gem_context_free(struct i915_gem_context
*ctx
)
126 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
127 GEM_BUG_ON(!i915_gem_context_is_closed(ctx
));
129 i915_ppgtt_put(ctx
->ppgtt
);
131 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
132 struct intel_context
*ce
= &ctx
->engine
[i
];
137 WARN_ON(ce
->pin_count
);
139 intel_ring_free(ce
->ring
);
141 __i915_gem_object_release_unless_active(ce
->state
->obj
);
147 list_del(&ctx
->link
);
149 ida_simple_remove(&ctx
->i915
->contexts
.hw_ida
, ctx
->hw_id
);
153 static void contexts_free(struct drm_i915_private
*i915
)
155 struct llist_node
*freed
= llist_del_all(&i915
->contexts
.free_list
);
156 struct i915_gem_context
*ctx
, *cn
;
158 lockdep_assert_held(&i915
->drm
.struct_mutex
);
160 llist_for_each_entry_safe(ctx
, cn
, freed
, free_link
)
161 i915_gem_context_free(ctx
);
164 static void contexts_free_first(struct drm_i915_private
*i915
)
166 struct i915_gem_context
*ctx
;
167 struct llist_node
*freed
;
169 lockdep_assert_held(&i915
->drm
.struct_mutex
);
171 freed
= llist_del_first(&i915
->contexts
.free_list
);
175 ctx
= container_of(freed
, typeof(*ctx
), free_link
);
176 i915_gem_context_free(ctx
);
179 static void contexts_free_worker(struct work_struct
*work
)
181 struct drm_i915_private
*i915
=
182 container_of(work
, typeof(*i915
), contexts
.free_work
);
184 mutex_lock(&i915
->drm
.struct_mutex
);
186 mutex_unlock(&i915
->drm
.struct_mutex
);
189 void i915_gem_context_release(struct kref
*ref
)
191 struct i915_gem_context
*ctx
= container_of(ref
, typeof(*ctx
), ref
);
192 struct drm_i915_private
*i915
= ctx
->i915
;
194 trace_i915_context_free(ctx
);
195 if (llist_add(&ctx
->free_link
, &i915
->contexts
.free_list
))
196 queue_work(i915
->wq
, &i915
->contexts
.free_work
);
199 static void context_close(struct i915_gem_context
*ctx
)
201 i915_gem_context_set_closed(ctx
);
205 i915_ppgtt_close(&ctx
->ppgtt
->base
);
207 ctx
->file_priv
= ERR_PTR(-EBADF
);
208 i915_gem_context_put(ctx
);
211 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
215 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
216 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
218 /* Contexts are only released when no longer active.
219 * Flush any pending retires to hopefully release some
220 * stale contexts and try again.
222 i915_gem_retire_requests(dev_priv
);
223 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
224 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
233 static u32
default_desc_template(const struct drm_i915_private
*i915
,
234 const struct i915_hw_ppgtt
*ppgtt
)
239 desc
= GEN8_CTX_VALID
| GEN8_CTX_PRIVILEGE
;
241 address_mode
= INTEL_LEGACY_32B_CONTEXT
;
242 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
))
243 address_mode
= INTEL_LEGACY_64B_CONTEXT
;
244 desc
|= address_mode
<< GEN8_CTX_ADDRESSING_MODE_SHIFT
;
247 desc
|= GEN8_CTX_L3LLC_COHERENT
;
249 /* TODO: WaDisableLiteRestore when we start using semaphore
250 * signalling between Command Streamers
251 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
257 static struct i915_gem_context
*
258 __create_hw_context(struct drm_i915_private
*dev_priv
,
259 struct drm_i915_file_private
*file_priv
)
261 struct i915_gem_context
*ctx
;
264 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
266 return ERR_PTR(-ENOMEM
);
268 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
274 kref_init(&ctx
->ref
);
275 list_add_tail(&ctx
->link
, &dev_priv
->contexts
.list
);
276 ctx
->i915
= dev_priv
;
277 ctx
->priority
= I915_PRIORITY_NORMAL
;
279 INIT_RADIX_TREE(&ctx
->handles_vma
, GFP_KERNEL
);
280 INIT_LIST_HEAD(&ctx
->handles_list
);
282 /* Default context will never have a file_priv */
283 ret
= DEFAULT_CONTEXT_HANDLE
;
285 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
286 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
290 ctx
->user_handle
= ret
;
292 ctx
->file_priv
= file_priv
;
294 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
295 ctx
->name
= kasprintf(GFP_KERNEL
, "%s[%d]/%x",
305 /* NB: Mark all slices as needing a remap so that when the context first
306 * loads it will restore whatever remap state already exists. If there
307 * is no remap info, it will be a NOP. */
308 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
310 i915_gem_context_set_bannable(ctx
);
311 ctx
->ring_size
= 4 * PAGE_SIZE
;
313 default_desc_template(dev_priv
, dev_priv
->mm
.aliasing_ppgtt
);
315 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
316 * present or not in use we still need a small bias as ring wraparound
317 * at offset 0 sometimes hangs. No idea why.
319 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
)
320 ctx
->ggtt_offset_bias
= GUC_WOPCM_TOP
;
322 ctx
->ggtt_offset_bias
= I915_GTT_PAGE_SIZE
;
328 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
334 static void __destroy_hw_context(struct i915_gem_context
*ctx
,
335 struct drm_i915_file_private
*file_priv
)
337 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
342 * The default context needs to exist per ring that uses contexts. It stores the
343 * context state of the GPU for applications that don't utilize HW contexts, as
344 * well as an idle case.
346 static struct i915_gem_context
*
347 i915_gem_create_context(struct drm_i915_private
*dev_priv
,
348 struct drm_i915_file_private
*file_priv
)
350 struct i915_gem_context
*ctx
;
352 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
354 /* Reap the most stale context */
355 contexts_free_first(dev_priv
);
357 ctx
= __create_hw_context(dev_priv
, file_priv
);
361 if (USES_FULL_PPGTT(dev_priv
)) {
362 struct i915_hw_ppgtt
*ppgtt
;
364 ppgtt
= i915_ppgtt_create(dev_priv
, file_priv
, ctx
->name
);
366 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
368 __destroy_hw_context(ctx
, file_priv
);
369 return ERR_CAST(ppgtt
);
373 ctx
->desc_template
= default_desc_template(dev_priv
, ppgtt
);
376 trace_i915_context_create(ctx
);
382 * i915_gem_context_create_gvt - create a GVT GEM context
385 * This function is used to create a GVT specific GEM context.
388 * pointer to i915_gem_context on success, error pointer if failed
391 struct i915_gem_context
*
392 i915_gem_context_create_gvt(struct drm_device
*dev
)
394 struct i915_gem_context
*ctx
;
397 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
398 return ERR_PTR(-ENODEV
);
400 ret
= i915_mutex_lock_interruptible(dev
);
404 ctx
= __create_hw_context(to_i915(dev
), NULL
);
408 ctx
->file_priv
= ERR_PTR(-EBADF
);
409 i915_gem_context_set_closed(ctx
); /* not user accessible */
410 i915_gem_context_clear_bannable(ctx
);
411 i915_gem_context_set_force_single_submission(ctx
);
412 if (!i915
.enable_guc_submission
)
413 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
415 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
417 mutex_unlock(&dev
->struct_mutex
);
421 int i915_gem_contexts_init(struct drm_i915_private
*dev_priv
)
423 struct i915_gem_context
*ctx
;
425 /* Init should only be called once per module load. Eventually the
426 * restriction on the context_disabled check can be loosened. */
427 if (WARN_ON(dev_priv
->kernel_context
))
430 INIT_LIST_HEAD(&dev_priv
->contexts
.list
);
431 INIT_WORK(&dev_priv
->contexts
.free_work
, contexts_free_worker
);
432 init_llist_head(&dev_priv
->contexts
.free_list
);
434 if (intel_vgpu_active(dev_priv
) &&
435 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
436 if (!i915
.enable_execlists
) {
437 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
442 /* Using the simple ida interface, the max is limited by sizeof(int) */
443 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
444 ida_init(&dev_priv
->contexts
.hw_ida
);
446 ctx
= i915_gem_create_context(dev_priv
, NULL
);
448 DRM_ERROR("Failed to create default global context (error %ld)\n",
453 /* For easy recognisablity, we want the kernel context to be 0 and then
454 * all user contexts will have non-zero hw_id.
456 GEM_BUG_ON(ctx
->hw_id
);
458 i915_gem_context_clear_bannable(ctx
);
459 ctx
->priority
= I915_PRIORITY_MIN
; /* lowest priority; idle task */
460 dev_priv
->kernel_context
= ctx
;
462 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
464 DRM_DEBUG_DRIVER("%s context support initialized\n",
465 dev_priv
->engine
[RCS
]->context_size
? "logical" :
470 void i915_gem_contexts_lost(struct drm_i915_private
*dev_priv
)
472 struct intel_engine_cs
*engine
;
473 enum intel_engine_id id
;
475 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
477 for_each_engine(engine
, dev_priv
, id
) {
478 engine
->legacy_active_context
= NULL
;
480 if (!engine
->last_retired_context
)
483 engine
->context_unpin(engine
, engine
->last_retired_context
);
484 engine
->last_retired_context
= NULL
;
487 /* Force the GPU state to be restored on enabling */
488 if (!i915
.enable_execlists
) {
489 struct i915_gem_context
*ctx
;
491 list_for_each_entry(ctx
, &dev_priv
->contexts
.list
, link
) {
492 if (!i915_gem_context_is_default(ctx
))
495 for_each_engine(engine
, dev_priv
, id
)
496 ctx
->engine
[engine
->id
].initialised
= false;
498 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
501 for_each_engine(engine
, dev_priv
, id
) {
502 struct intel_context
*kce
=
503 &dev_priv
->kernel_context
->engine
[engine
->id
];
505 kce
->initialised
= true;
510 void i915_gem_contexts_fini(struct drm_i915_private
*i915
)
512 struct i915_gem_context
*ctx
;
514 lockdep_assert_held(&i915
->drm
.struct_mutex
);
516 /* Keep the context so that we can free it immediately ourselves */
517 ctx
= i915_gem_context_get(fetch_and_zero(&i915
->kernel_context
));
518 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
520 i915_gem_context_free(ctx
);
522 /* Must free all deferred contexts (via flush_workqueue) first */
523 ida_destroy(&i915
->contexts
.hw_ida
);
526 static int context_idr_cleanup(int id
, void *p
, void *data
)
528 struct i915_gem_context
*ctx
= p
;
534 int i915_gem_context_open(struct drm_i915_private
*i915
,
535 struct drm_file
*file
)
537 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
538 struct i915_gem_context
*ctx
;
540 idr_init(&file_priv
->context_idr
);
542 mutex_lock(&i915
->drm
.struct_mutex
);
543 ctx
= i915_gem_create_context(i915
, file_priv
);
544 mutex_unlock(&i915
->drm
.struct_mutex
);
546 idr_destroy(&file_priv
->context_idr
);
550 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
555 void i915_gem_context_close(struct drm_file
*file
)
557 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
559 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
561 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
562 idr_destroy(&file_priv
->context_idr
);
566 mi_set_context(struct drm_i915_gem_request
*req
, u32 flags
)
568 struct drm_i915_private
*dev_priv
= req
->i915
;
569 struct intel_engine_cs
*engine
= req
->engine
;
570 enum intel_engine_id id
;
571 const int num_rings
=
572 /* Use an extended w/a on gen7 if signalling from other rings */
573 (i915
.semaphores
&& INTEL_GEN(dev_priv
) == 7) ?
574 INTEL_INFO(dev_priv
)->num_rings
- 1 :
579 flags
|= MI_MM_SPACE_GTT
;
580 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
581 /* These flags are for resource streamer on HSW+ */
582 flags
|= HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
;
584 flags
|= MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
;
587 if (INTEL_GEN(dev_priv
) >= 7)
588 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
590 cs
= intel_ring_begin(req
, len
);
594 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
595 if (INTEL_GEN(dev_priv
) >= 7) {
596 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
598 struct intel_engine_cs
*signaller
;
600 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
601 for_each_engine(signaller
, dev_priv
, id
) {
602 if (signaller
== engine
)
605 *cs
++ = i915_mmio_reg_offset(
606 RING_PSMI_CTL(signaller
->mmio_base
));
607 *cs
++ = _MASKED_BIT_ENABLE(
608 GEN6_PSMI_SLEEP_MSG_DISABLE
);
614 *cs
++ = MI_SET_CONTEXT
;
615 *cs
++ = i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
;
617 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
618 * WaMiSetContext_Hang:snb,ivb,vlv
622 if (INTEL_GEN(dev_priv
) >= 7) {
624 struct intel_engine_cs
*signaller
;
625 i915_reg_t last_reg
= {}; /* keep gcc quiet */
627 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
628 for_each_engine(signaller
, dev_priv
, id
) {
629 if (signaller
== engine
)
632 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
633 *cs
++ = i915_mmio_reg_offset(last_reg
);
634 *cs
++ = _MASKED_BIT_DISABLE(
635 GEN6_PSMI_SLEEP_MSG_DISABLE
);
638 /* Insert a delay before the next switch! */
639 *cs
++ = MI_STORE_REGISTER_MEM
| MI_SRM_LRM_GLOBAL_GTT
;
640 *cs
++ = i915_mmio_reg_offset(last_reg
);
641 *cs
++ = i915_ggtt_offset(engine
->scratch
);
644 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
647 intel_ring_advance(req
, cs
);
652 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
654 u32
*cs
, *remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
660 cs
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
665 * Note: We do not worry about the concurrent register cacheline hang
666 * here because no other code should access these registers other than
667 * at initialization time.
669 *cs
++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4);
670 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
671 *cs
++ = i915_mmio_reg_offset(GEN7_L3LOG(slice
, i
));
672 *cs
++ = remap_info
[i
];
675 intel_ring_advance(req
, cs
);
680 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
681 struct intel_engine_cs
*engine
,
682 struct i915_gem_context
*to
)
687 if (!to
->engine
[RCS
].initialised
)
690 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
693 return to
== engine
->legacy_active_context
;
697 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
, struct intel_engine_cs
*engine
)
699 struct i915_gem_context
*from
= engine
->legacy_active_context
;
704 /* Always load the ppgtt on first use */
708 /* Same context without new entries, skip */
709 if ((!from
->ppgtt
|| from
->ppgtt
== ppgtt
) &&
710 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
713 if (engine
->id
!= RCS
)
716 if (INTEL_GEN(engine
->i915
) < 8)
723 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
724 struct i915_gem_context
*to
,
730 if (!IS_GEN8(to
->i915
))
733 if (hw_flags
& MI_RESTORE_INHIBIT
)
739 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
741 struct i915_gem_context
*to
= req
->ctx
;
742 struct intel_engine_cs
*engine
= req
->engine
;
743 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
744 struct i915_gem_context
*from
= engine
->legacy_active_context
;
748 GEM_BUG_ON(engine
->id
!= RCS
);
750 if (skip_rcs_switch(ppgtt
, engine
, to
))
753 if (needs_pd_load_pre(ppgtt
, engine
)) {
754 /* Older GENs and non render rings still want the load first,
755 * "PP_DCLV followed by PP_DIR_BASE register through Load
756 * Register Immediate commands in Ring Buffer before submitting
758 trace_switch_mm(engine
, to
);
759 ret
= ppgtt
->switch_mm(ppgtt
, req
);
764 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
765 /* NB: If we inhibit the restore, the context is not allowed to
766 * die because future work may end up depending on valid address
767 * space. This means we must enforce that a page table load
768 * occur when this occurs. */
769 hw_flags
= MI_RESTORE_INHIBIT
;
770 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
771 hw_flags
= MI_FORCE_RESTORE
;
775 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
776 ret
= mi_set_context(req
, hw_flags
);
780 engine
->legacy_active_context
= to
;
783 /* GEN8 does *not* require an explicit reload if the PDPs have been
784 * setup, and we do not wish to move them.
786 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
787 trace_switch_mm(engine
, to
);
788 ret
= ppgtt
->switch_mm(ppgtt
, req
);
789 /* The hardware context switch is emitted, but we haven't
790 * actually changed the state - so it's probably safe to bail
791 * here. Still, let the user know something dangerous has
799 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
801 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
802 if (!(to
->remap_slice
& (1<<i
)))
805 ret
= remap_l3(req
, i
);
809 to
->remap_slice
&= ~(1<<i
);
812 if (!to
->engine
[RCS
].initialised
) {
813 if (engine
->init_context
) {
814 ret
= engine
->init_context(req
);
818 to
->engine
[RCS
].initialised
= true;
825 * i915_switch_context() - perform a GPU context switch.
826 * @req: request for which we'll execute the context switch
828 * The context life cycle is simple. The context refcount is incremented and
829 * decremented by 1 and create and destroy. If the context is in use by the GPU,
830 * it will have a refcount > 1. This allows us to destroy the context abstract
831 * object while letting the normal object tracking destroy the backing BO.
833 * This function should not be used in execlists mode. Instead the context is
834 * switched by writing to the ELSP and requests keep a reference to their
837 int i915_switch_context(struct drm_i915_gem_request
*req
)
839 struct intel_engine_cs
*engine
= req
->engine
;
841 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
842 if (i915
.enable_execlists
)
845 if (!req
->ctx
->engine
[engine
->id
].state
) {
846 struct i915_gem_context
*to
= req
->ctx
;
847 struct i915_hw_ppgtt
*ppgtt
=
848 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
850 if (needs_pd_load_pre(ppgtt
, engine
)) {
853 trace_switch_mm(engine
, to
);
854 ret
= ppgtt
->switch_mm(ppgtt
, req
);
858 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
861 engine
->legacy_active_context
= to
;
865 return do_rcs_switch(req
);
868 static bool engine_has_kernel_context(struct intel_engine_cs
*engine
)
870 struct i915_gem_timeline
*timeline
;
872 list_for_each_entry(timeline
, &engine
->i915
->gt
.timelines
, link
) {
873 struct intel_timeline
*tl
;
875 if (timeline
== &engine
->i915
->gt
.global_timeline
)
878 tl
= &timeline
->engine
[engine
->id
];
879 if (i915_gem_active_peek(&tl
->last_request
,
880 &engine
->i915
->drm
.struct_mutex
))
884 return (!engine
->last_retired_context
||
885 i915_gem_context_is_kernel(engine
->last_retired_context
));
888 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
890 struct intel_engine_cs
*engine
;
891 struct i915_gem_timeline
*timeline
;
892 enum intel_engine_id id
;
894 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
896 i915_gem_retire_requests(dev_priv
);
898 for_each_engine(engine
, dev_priv
, id
) {
899 struct drm_i915_gem_request
*req
;
902 if (engine_has_kernel_context(engine
))
905 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
909 /* Queue this switch after all other activity */
910 list_for_each_entry(timeline
, &dev_priv
->gt
.timelines
, link
) {
911 struct drm_i915_gem_request
*prev
;
912 struct intel_timeline
*tl
;
914 tl
= &timeline
->engine
[engine
->id
];
915 prev
= i915_gem_active_raw(&tl
->last_request
,
916 &dev_priv
->drm
.struct_mutex
);
918 i915_sw_fence_await_sw_fence_gfp(&req
->submit
,
923 ret
= i915_switch_context(req
);
924 i915_add_request(req
);
932 static bool client_is_banned(struct drm_i915_file_private
*file_priv
)
934 return atomic_read(&file_priv
->context_bans
) > I915_MAX_CLIENT_CONTEXT_BANS
;
937 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
938 struct drm_file
*file
)
940 struct drm_i915_private
*dev_priv
= to_i915(dev
);
941 struct drm_i915_gem_context_create
*args
= data
;
942 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
943 struct i915_gem_context
*ctx
;
946 if (!dev_priv
->engine
[RCS
]->context_size
)
952 if (client_is_banned(file_priv
)) {
953 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
955 pid_nr(get_task_pid(current
, PIDTYPE_PID
)));
960 ret
= i915_mutex_lock_interruptible(dev
);
964 ctx
= i915_gem_create_context(dev_priv
, file_priv
);
965 mutex_unlock(&dev
->struct_mutex
);
969 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
971 args
->ctx_id
= ctx
->user_handle
;
972 DRM_DEBUG("HW context %d created\n", args
->ctx_id
);
977 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
978 struct drm_file
*file
)
980 struct drm_i915_gem_context_destroy
*args
= data
;
981 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
982 struct i915_gem_context
*ctx
;
988 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
991 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
995 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
999 __destroy_hw_context(ctx
, file_priv
);
1000 mutex_unlock(&dev
->struct_mutex
);
1003 i915_gem_context_put(ctx
);
1007 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1008 struct drm_file
*file
)
1010 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1011 struct drm_i915_gem_context_param
*args
= data
;
1012 struct i915_gem_context
*ctx
;
1015 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1020 switch (args
->param
) {
1021 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1024 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1025 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1027 case I915_CONTEXT_PARAM_GTT_SIZE
:
1029 args
->value
= ctx
->ppgtt
->base
.total
;
1030 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1031 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1033 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1035 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1036 args
->value
= i915_gem_context_no_error_capture(ctx
);
1038 case I915_CONTEXT_PARAM_BANNABLE
:
1039 args
->value
= i915_gem_context_is_bannable(ctx
);
1046 i915_gem_context_put(ctx
);
1050 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1051 struct drm_file
*file
)
1053 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1054 struct drm_i915_gem_context_param
*args
= data
;
1055 struct i915_gem_context
*ctx
;
1058 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1062 ret
= i915_mutex_lock_interruptible(dev
);
1066 switch (args
->param
) {
1067 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1070 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1074 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1075 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1078 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1081 else if (args
->value
)
1082 i915_gem_context_set_no_error_capture(ctx
);
1084 i915_gem_context_clear_no_error_capture(ctx
);
1086 case I915_CONTEXT_PARAM_BANNABLE
:
1089 else if (!capable(CAP_SYS_ADMIN
) && !args
->value
)
1091 else if (args
->value
)
1092 i915_gem_context_set_bannable(ctx
);
1094 i915_gem_context_clear_bannable(ctx
);
1100 mutex_unlock(&dev
->struct_mutex
);
1103 i915_gem_context_put(ctx
);
1107 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1108 void *data
, struct drm_file
*file
)
1110 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1111 struct drm_i915_reset_stats
*args
= data
;
1112 struct i915_gem_context
*ctx
;
1115 if (args
->flags
|| args
->pad
)
1120 ctx
= __i915_gem_context_lookup_rcu(file
->driver_priv
, args
->ctx_id
);
1125 * We opt for unserialised reads here. This may result in tearing
1126 * in the extremely unlikely event of a GPU hang on this context
1127 * as we are querying them. If we need that extra layer of protection,
1128 * we should wrap the hangstats with a seqlock.
1131 if (capable(CAP_SYS_ADMIN
))
1132 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1134 args
->reset_count
= 0;
1136 args
->batch_active
= atomic_read(&ctx
->guilty_count
);
1137 args
->batch_pending
= atomic_read(&ctx
->active_count
);
1145 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1146 #include "selftests/mock_context.c"
1147 #include "selftests/i915_gem_context.c"