2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 void i915_gem_context_free(struct kref
*ctx_ref
)
139 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
142 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
143 trace_i915_context_free(ctx
);
144 GEM_BUG_ON(!i915_gem_context_is_closed(ctx
));
146 i915_ppgtt_put(ctx
->ppgtt
);
148 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
149 struct intel_context
*ce
= &ctx
->engine
[i
];
154 WARN_ON(ce
->pin_count
);
156 intel_ring_free(ce
->ring
);
158 __i915_gem_object_release_unless_active(ce
->state
->obj
);
163 list_del(&ctx
->link
);
165 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
169 static struct drm_i915_gem_object
*
170 alloc_context_obj(struct drm_i915_private
*dev_priv
, u64 size
)
172 struct drm_i915_gem_object
*obj
;
175 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
177 obj
= i915_gem_object_create(dev_priv
, size
);
182 * Try to make the context utilize L3 as well as LLC.
184 * On VLV we don't have L3 controls in the PTEs so we
185 * shouldn't touch the cache level, especially as that
186 * would make the object snooped which might have a
187 * negative performance impact.
189 * Snooping is required on non-llc platforms in execlist
190 * mode, but since all GGTT accesses use PAT entry 0 we
191 * get snooping anyway regardless of cache_level.
193 * This is only applicable for Ivy Bridge devices since
194 * later platforms don't have L3 control bits in the PTE.
196 if (IS_IVYBRIDGE(dev_priv
)) {
197 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
198 /* Failure shouldn't ever happen this early */
200 i915_gem_object_put(obj
);
208 static void context_close(struct i915_gem_context
*ctx
)
210 i915_gem_context_set_closed(ctx
);
212 i915_ppgtt_close(&ctx
->ppgtt
->base
);
213 ctx
->file_priv
= ERR_PTR(-EBADF
);
214 i915_gem_context_put(ctx
);
217 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
221 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
222 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
224 /* Contexts are only released when no longer active.
225 * Flush any pending retires to hopefully release some
226 * stale contexts and try again.
228 i915_gem_retire_requests(dev_priv
);
229 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
230 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
239 static struct i915_gem_context
*
240 __create_hw_context(struct drm_i915_private
*dev_priv
,
241 struct drm_i915_file_private
*file_priv
)
243 struct i915_gem_context
*ctx
;
246 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
248 return ERR_PTR(-ENOMEM
);
250 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
256 kref_init(&ctx
->ref
);
257 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
258 ctx
->i915
= dev_priv
;
260 ctx
->ggtt_alignment
= get_context_alignment(dev_priv
);
262 if (dev_priv
->hw_context_size
) {
263 struct drm_i915_gem_object
*obj
;
264 struct i915_vma
*vma
;
266 obj
= alloc_context_obj(dev_priv
, dev_priv
->hw_context_size
);
272 vma
= i915_vma_instance(obj
, &dev_priv
->ggtt
.base
, NULL
);
274 i915_gem_object_put(obj
);
279 ctx
->engine
[RCS
].state
= vma
;
282 /* Default context will never have a file_priv */
283 ret
= DEFAULT_CONTEXT_HANDLE
;
285 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
286 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
290 ctx
->user_handle
= ret
;
292 ctx
->file_priv
= file_priv
;
294 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
295 ctx
->name
= kasprintf(GFP_KERNEL
, "%s[%d]/%x",
305 /* NB: Mark all slices as needing a remap so that when the context first
306 * loads it will restore whatever remap state already exists. If there
307 * is no remap info, it will be a NOP. */
308 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
310 i915_gem_context_set_bannable(ctx
);
311 ctx
->ring_size
= 4 * PAGE_SIZE
;
312 ctx
->desc_template
= GEN8_CTX_ADDRESSING_MODE(dev_priv
) <<
313 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
315 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
316 * present or not in use we still need a small bias as ring wraparound
317 * at offset 0 sometimes hangs. No idea why.
319 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
)
320 ctx
->ggtt_offset_bias
= GUC_WOPCM_TOP
;
322 ctx
->ggtt_offset_bias
= I915_GTT_PAGE_SIZE
;
328 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
335 * The default context needs to exist per ring that uses contexts. It stores the
336 * context state of the GPU for applications that don't utilize HW contexts, as
337 * well as an idle case.
339 static struct i915_gem_context
*
340 i915_gem_create_context(struct drm_i915_private
*dev_priv
,
341 struct drm_i915_file_private
*file_priv
)
343 struct i915_gem_context
*ctx
;
345 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
347 ctx
= __create_hw_context(dev_priv
, file_priv
);
351 if (USES_FULL_PPGTT(dev_priv
)) {
352 struct i915_hw_ppgtt
*ppgtt
;
354 ppgtt
= i915_ppgtt_create(dev_priv
, file_priv
, ctx
->name
);
356 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
358 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
360 return ERR_CAST(ppgtt
);
366 trace_i915_context_create(ctx
);
372 * i915_gem_context_create_gvt - create a GVT GEM context
375 * This function is used to create a GVT specific GEM context.
378 * pointer to i915_gem_context on success, error pointer if failed
381 struct i915_gem_context
*
382 i915_gem_context_create_gvt(struct drm_device
*dev
)
384 struct i915_gem_context
*ctx
;
387 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
388 return ERR_PTR(-ENODEV
);
390 ret
= i915_mutex_lock_interruptible(dev
);
394 ctx
= __create_hw_context(to_i915(dev
), NULL
);
398 ctx
->file_priv
= ERR_PTR(-EBADF
);
399 i915_gem_context_set_closed(ctx
); /* not user accessible */
400 i915_gem_context_clear_bannable(ctx
);
401 i915_gem_context_set_force_single_submission(ctx
);
402 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
404 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
406 mutex_unlock(&dev
->struct_mutex
);
410 int i915_gem_context_init(struct drm_i915_private
*dev_priv
)
412 struct i915_gem_context
*ctx
;
414 /* Init should only be called once per module load. Eventually the
415 * restriction on the context_disabled check can be loosened. */
416 if (WARN_ON(dev_priv
->kernel_context
))
419 if (intel_vgpu_active(dev_priv
) &&
420 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
421 if (!i915
.enable_execlists
) {
422 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
427 /* Using the simple ida interface, the max is limited by sizeof(int) */
428 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
429 ida_init(&dev_priv
->context_hw_ida
);
431 if (i915
.enable_execlists
) {
432 /* NB: intentionally left blank. We will allocate our own
433 * backing objects as we need them, thank you very much */
434 dev_priv
->hw_context_size
= 0;
435 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
436 dev_priv
->hw_context_size
=
437 round_up(get_context_size(dev_priv
),
439 if (dev_priv
->hw_context_size
> (1<<20)) {
440 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
441 dev_priv
->hw_context_size
);
442 dev_priv
->hw_context_size
= 0;
446 ctx
= i915_gem_create_context(dev_priv
, NULL
);
448 DRM_ERROR("Failed to create default global context (error %ld)\n",
453 i915_gem_context_clear_bannable(ctx
);
454 ctx
->priority
= I915_PRIORITY_MIN
; /* lowest priority; idle task */
455 dev_priv
->kernel_context
= ctx
;
457 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
459 DRM_DEBUG_DRIVER("%s context support initialized\n",
460 i915
.enable_execlists
? "LR" :
461 dev_priv
->hw_context_size
? "HW" : "fake");
465 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
467 struct intel_engine_cs
*engine
;
468 enum intel_engine_id id
;
470 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
472 for_each_engine(engine
, dev_priv
, id
) {
473 engine
->legacy_active_context
= NULL
;
475 if (!engine
->last_retired_context
)
478 engine
->context_unpin(engine
, engine
->last_retired_context
);
479 engine
->last_retired_context
= NULL
;
482 /* Force the GPU state to be restored on enabling */
483 if (!i915
.enable_execlists
) {
484 struct i915_gem_context
*ctx
;
486 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
487 if (!i915_gem_context_is_default(ctx
))
490 for_each_engine(engine
, dev_priv
, id
)
491 ctx
->engine
[engine
->id
].initialised
= false;
493 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
496 for_each_engine(engine
, dev_priv
, id
) {
497 struct intel_context
*kce
=
498 &dev_priv
->kernel_context
->engine
[engine
->id
];
500 kce
->initialised
= true;
505 void i915_gem_context_fini(struct drm_i915_private
*dev_priv
)
507 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
509 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
511 GEM_BUG_ON(!i915_gem_context_is_kernel(dctx
));
514 dev_priv
->kernel_context
= NULL
;
516 ida_destroy(&dev_priv
->context_hw_ida
);
519 static int context_idr_cleanup(int id
, void *p
, void *data
)
521 struct i915_gem_context
*ctx
= p
;
527 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
529 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
530 struct i915_gem_context
*ctx
;
532 idr_init(&file_priv
->context_idr
);
534 mutex_lock(&dev
->struct_mutex
);
535 ctx
= i915_gem_create_context(to_i915(dev
), file_priv
);
536 mutex_unlock(&dev
->struct_mutex
);
538 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
541 idr_destroy(&file_priv
->context_idr
);
548 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
550 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
552 lockdep_assert_held(&dev
->struct_mutex
);
554 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
555 idr_destroy(&file_priv
->context_idr
);
559 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
561 struct drm_i915_private
*dev_priv
= req
->i915
;
562 struct intel_ring
*ring
= req
->ring
;
563 struct intel_engine_cs
*engine
= req
->engine
;
564 enum intel_engine_id id
;
565 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
566 const int num_rings
=
567 /* Use an extended w/a on ivb+ if signalling from other rings */
569 INTEL_INFO(dev_priv
)->num_rings
- 1 :
573 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
574 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
575 * explicitly, so we rely on the value at ring init, stored in
576 * itlb_before_ctx_switch.
578 if (IS_GEN6(dev_priv
)) {
579 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
);
584 /* These flags are for resource streamer on HSW+ */
585 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
586 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
587 else if (INTEL_GEN(dev_priv
) < 8)
588 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
592 if (INTEL_GEN(dev_priv
) >= 7)
593 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
595 ret
= intel_ring_begin(req
, len
);
599 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
600 if (INTEL_GEN(dev_priv
) >= 7) {
601 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
603 struct intel_engine_cs
*signaller
;
605 intel_ring_emit(ring
,
606 MI_LOAD_REGISTER_IMM(num_rings
));
607 for_each_engine(signaller
, dev_priv
, id
) {
608 if (signaller
== engine
)
611 intel_ring_emit_reg(ring
,
612 RING_PSMI_CTL(signaller
->mmio_base
));
613 intel_ring_emit(ring
,
614 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
619 intel_ring_emit(ring
, MI_NOOP
);
620 intel_ring_emit(ring
, MI_SET_CONTEXT
);
621 intel_ring_emit(ring
,
622 i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
);
624 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
625 * WaMiSetContext_Hang:snb,ivb,vlv
627 intel_ring_emit(ring
, MI_NOOP
);
629 if (INTEL_GEN(dev_priv
) >= 7) {
631 struct intel_engine_cs
*signaller
;
632 i915_reg_t last_reg
= {}; /* keep gcc quiet */
634 intel_ring_emit(ring
,
635 MI_LOAD_REGISTER_IMM(num_rings
));
636 for_each_engine(signaller
, dev_priv
, id
) {
637 if (signaller
== engine
)
640 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
641 intel_ring_emit_reg(ring
, last_reg
);
642 intel_ring_emit(ring
,
643 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
646 /* Insert a delay before the next switch! */
647 intel_ring_emit(ring
,
648 MI_STORE_REGISTER_MEM
|
649 MI_SRM_LRM_GLOBAL_GTT
);
650 intel_ring_emit_reg(ring
, last_reg
);
651 intel_ring_emit(ring
,
652 i915_ggtt_offset(engine
->scratch
));
653 intel_ring_emit(ring
, MI_NOOP
);
655 intel_ring_emit(ring
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
658 intel_ring_advance(ring
);
663 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
665 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
666 struct intel_ring
*ring
= req
->ring
;
672 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
677 * Note: We do not worry about the concurrent register cacheline hang
678 * here because no other code should access these registers other than
679 * at initialization time.
681 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
682 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
683 intel_ring_emit_reg(ring
, GEN7_L3LOG(slice
, i
));
684 intel_ring_emit(ring
, remap_info
[i
]);
686 intel_ring_emit(ring
, MI_NOOP
);
687 intel_ring_advance(ring
);
692 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
693 struct intel_engine_cs
*engine
,
694 struct i915_gem_context
*to
)
699 if (!to
->engine
[RCS
].initialised
)
702 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
705 return to
== engine
->legacy_active_context
;
709 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
710 struct intel_engine_cs
*engine
,
711 struct i915_gem_context
*to
)
716 /* Always load the ppgtt on first use */
717 if (!engine
->legacy_active_context
)
720 /* Same context without new entries, skip */
721 if (engine
->legacy_active_context
== to
&&
722 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
725 if (engine
->id
!= RCS
)
728 if (INTEL_GEN(engine
->i915
) < 8)
735 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
736 struct i915_gem_context
*to
,
742 if (!IS_GEN8(to
->i915
))
745 if (hw_flags
& MI_RESTORE_INHIBIT
)
751 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
753 struct i915_gem_context
*to
= req
->ctx
;
754 struct intel_engine_cs
*engine
= req
->engine
;
755 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
756 struct i915_gem_context
*from
= engine
->legacy_active_context
;
760 GEM_BUG_ON(engine
->id
!= RCS
);
762 if (skip_rcs_switch(ppgtt
, engine
, to
))
765 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
766 /* Older GENs and non render rings still want the load first,
767 * "PP_DCLV followed by PP_DIR_BASE register through Load
768 * Register Immediate commands in Ring Buffer before submitting
770 trace_switch_mm(engine
, to
);
771 ret
= ppgtt
->switch_mm(ppgtt
, req
);
776 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
777 /* NB: If we inhibit the restore, the context is not allowed to
778 * die because future work may end up depending on valid address
779 * space. This means we must enforce that a page table load
780 * occur when this occurs. */
781 hw_flags
= MI_RESTORE_INHIBIT
;
782 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
783 hw_flags
= MI_FORCE_RESTORE
;
787 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
788 ret
= mi_set_context(req
, hw_flags
);
792 engine
->legacy_active_context
= to
;
795 /* GEN8 does *not* require an explicit reload if the PDPs have been
796 * setup, and we do not wish to move them.
798 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
799 trace_switch_mm(engine
, to
);
800 ret
= ppgtt
->switch_mm(ppgtt
, req
);
801 /* The hardware context switch is emitted, but we haven't
802 * actually changed the state - so it's probably safe to bail
803 * here. Still, let the user know something dangerous has
811 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
813 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
814 if (!(to
->remap_slice
& (1<<i
)))
817 ret
= remap_l3(req
, i
);
821 to
->remap_slice
&= ~(1<<i
);
824 if (!to
->engine
[RCS
].initialised
) {
825 if (engine
->init_context
) {
826 ret
= engine
->init_context(req
);
830 to
->engine
[RCS
].initialised
= true;
837 * i915_switch_context() - perform a GPU context switch.
838 * @req: request for which we'll execute the context switch
840 * The context life cycle is simple. The context refcount is incremented and
841 * decremented by 1 and create and destroy. If the context is in use by the GPU,
842 * it will have a refcount > 1. This allows us to destroy the context abstract
843 * object while letting the normal object tracking destroy the backing BO.
845 * This function should not be used in execlists mode. Instead the context is
846 * switched by writing to the ELSP and requests keep a reference to their
849 int i915_switch_context(struct drm_i915_gem_request
*req
)
851 struct intel_engine_cs
*engine
= req
->engine
;
853 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
854 if (i915
.enable_execlists
)
857 if (!req
->ctx
->engine
[engine
->id
].state
) {
858 struct i915_gem_context
*to
= req
->ctx
;
859 struct i915_hw_ppgtt
*ppgtt
=
860 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
862 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
865 trace_switch_mm(engine
, to
);
866 ret
= ppgtt
->switch_mm(ppgtt
, req
);
870 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
876 return do_rcs_switch(req
);
879 static bool engine_has_kernel_context(struct intel_engine_cs
*engine
)
881 struct i915_gem_timeline
*timeline
;
883 list_for_each_entry(timeline
, &engine
->i915
->gt
.timelines
, link
) {
884 struct intel_timeline
*tl
;
886 if (timeline
== &engine
->i915
->gt
.global_timeline
)
889 tl
= &timeline
->engine
[engine
->id
];
890 if (i915_gem_active_peek(&tl
->last_request
,
891 &engine
->i915
->drm
.struct_mutex
))
895 return (!engine
->last_retired_context
||
896 i915_gem_context_is_kernel(engine
->last_retired_context
));
899 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
901 struct intel_engine_cs
*engine
;
902 struct i915_gem_timeline
*timeline
;
903 enum intel_engine_id id
;
905 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
907 i915_gem_retire_requests(dev_priv
);
909 for_each_engine(engine
, dev_priv
, id
) {
910 struct drm_i915_gem_request
*req
;
913 if (engine_has_kernel_context(engine
))
916 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
920 /* Queue this switch after all other activity */
921 list_for_each_entry(timeline
, &dev_priv
->gt
.timelines
, link
) {
922 struct drm_i915_gem_request
*prev
;
923 struct intel_timeline
*tl
;
925 tl
= &timeline
->engine
[engine
->id
];
926 prev
= i915_gem_active_raw(&tl
->last_request
,
927 &dev_priv
->drm
.struct_mutex
);
929 i915_sw_fence_await_sw_fence_gfp(&req
->submit
,
934 ret
= i915_switch_context(req
);
935 i915_add_request_no_flush(req
);
943 static bool contexts_enabled(struct drm_device
*dev
)
945 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
948 static bool client_is_banned(struct drm_i915_file_private
*file_priv
)
950 return file_priv
->context_bans
> I915_MAX_CLIENT_CONTEXT_BANS
;
953 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
954 struct drm_file
*file
)
956 struct drm_i915_gem_context_create
*args
= data
;
957 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
958 struct i915_gem_context
*ctx
;
961 if (!contexts_enabled(dev
))
967 if (client_is_banned(file_priv
)) {
968 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
970 pid_nr(get_task_pid(current
, PIDTYPE_PID
)));
975 ret
= i915_mutex_lock_interruptible(dev
);
979 ctx
= i915_gem_create_context(to_i915(dev
), file_priv
);
980 mutex_unlock(&dev
->struct_mutex
);
984 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
986 args
->ctx_id
= ctx
->user_handle
;
987 DRM_DEBUG("HW context %d created\n", args
->ctx_id
);
992 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
993 struct drm_file
*file
)
995 struct drm_i915_gem_context_destroy
*args
= data
;
996 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
997 struct i915_gem_context
*ctx
;
1003 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
1006 ret
= i915_mutex_lock_interruptible(dev
);
1010 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1012 mutex_unlock(&dev
->struct_mutex
);
1013 return PTR_ERR(ctx
);
1016 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
1018 mutex_unlock(&dev
->struct_mutex
);
1020 DRM_DEBUG("HW context %d destroyed\n", args
->ctx_id
);
1024 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1025 struct drm_file
*file
)
1027 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1028 struct drm_i915_gem_context_param
*args
= data
;
1029 struct i915_gem_context
*ctx
;
1032 ret
= i915_mutex_lock_interruptible(dev
);
1036 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1038 mutex_unlock(&dev
->struct_mutex
);
1039 return PTR_ERR(ctx
);
1043 switch (args
->param
) {
1044 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1047 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1048 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1050 case I915_CONTEXT_PARAM_GTT_SIZE
:
1052 args
->value
= ctx
->ppgtt
->base
.total
;
1053 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1054 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1056 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1058 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1059 args
->value
= i915_gem_context_no_error_capture(ctx
);
1061 case I915_CONTEXT_PARAM_BANNABLE
:
1062 args
->value
= i915_gem_context_is_bannable(ctx
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1074 struct drm_file
*file
)
1076 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1077 struct drm_i915_gem_context_param
*args
= data
;
1078 struct i915_gem_context
*ctx
;
1081 ret
= i915_mutex_lock_interruptible(dev
);
1085 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1087 mutex_unlock(&dev
->struct_mutex
);
1088 return PTR_ERR(ctx
);
1091 switch (args
->param
) {
1092 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1095 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1099 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1100 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1103 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1106 else if (args
->value
)
1107 i915_gem_context_set_no_error_capture(ctx
);
1109 i915_gem_context_clear_no_error_capture(ctx
);
1111 case I915_CONTEXT_PARAM_BANNABLE
:
1114 else if (!capable(CAP_SYS_ADMIN
) && !args
->value
)
1116 else if (args
->value
)
1117 i915_gem_context_set_bannable(ctx
);
1119 i915_gem_context_clear_bannable(ctx
);
1125 mutex_unlock(&dev
->struct_mutex
);
1130 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1131 void *data
, struct drm_file
*file
)
1133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1134 struct drm_i915_reset_stats
*args
= data
;
1135 struct i915_gem_context
*ctx
;
1138 if (args
->flags
|| args
->pad
)
1141 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1144 ret
= i915_mutex_lock_interruptible(dev
);
1148 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1150 mutex_unlock(&dev
->struct_mutex
);
1151 return PTR_ERR(ctx
);
1154 if (capable(CAP_SYS_ADMIN
))
1155 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1157 args
->reset_count
= 0;
1159 args
->batch_active
= ctx
->guilty_count
;
1160 args
->batch_pending
= ctx
->active_count
;
1162 mutex_unlock(&dev
->struct_mutex
);