2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 static void i915_gem_context_clean(struct i915_gem_context
*ctx
)
139 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
140 struct i915_vma
*vma
, *next
;
145 list_for_each_entry_safe(vma
, next
, &ppgtt
->base
.inactive_list
,
147 if (WARN_ON(__i915_vma_unbind_no_wait(vma
)))
152 void i915_gem_context_free(struct kref
*ctx_ref
)
154 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
157 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
158 trace_i915_context_free(ctx
);
161 * This context is going away and we need to remove all VMAs still
162 * around. This is to handle imported shared objects for which
163 * destructor did not run when their handles were closed.
165 i915_gem_context_clean(ctx
);
167 i915_ppgtt_put(ctx
->ppgtt
);
169 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
170 struct intel_context
*ce
= &ctx
->engine
[i
];
175 WARN_ON(ce
->pin_count
);
177 intel_ringbuffer_free(ce
->ringbuf
);
179 drm_gem_object_unreference(&ce
->state
->base
);
182 list_del(&ctx
->link
);
184 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
188 struct drm_i915_gem_object
*
189 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
191 struct drm_i915_gem_object
*obj
;
194 lockdep_assert_held(&dev
->struct_mutex
);
196 obj
= i915_gem_object_create(dev
, size
);
201 * Try to make the context utilize L3 as well as LLC.
203 * On VLV we don't have L3 controls in the PTEs so we
204 * shouldn't touch the cache level, especially as that
205 * would make the object snooped which might have a
206 * negative performance impact.
208 * Snooping is required on non-llc platforms in execlist
209 * mode, but since all GGTT accesses use PAT entry 0 we
210 * get snooping anyway regardless of cache_level.
212 * This is only applicable for Ivy Bridge devices since
213 * later platforms don't have L3 control bits in the PTE.
215 if (IS_IVYBRIDGE(dev
)) {
216 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
217 /* Failure shouldn't ever happen this early */
219 drm_gem_object_unreference(&obj
->base
);
227 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
231 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
232 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
234 /* Contexts are only released when no longer active.
235 * Flush any pending retires to hopefully release some
236 * stale contexts and try again.
238 i915_gem_retire_requests(dev_priv
);
239 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
240 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
249 static struct i915_gem_context
*
250 __create_hw_context(struct drm_device
*dev
,
251 struct drm_i915_file_private
*file_priv
)
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
254 struct i915_gem_context
*ctx
;
257 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
259 return ERR_PTR(-ENOMEM
);
261 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
267 kref_init(&ctx
->ref
);
268 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
269 ctx
->i915
= dev_priv
;
271 if (dev_priv
->hw_context_size
) {
272 struct drm_i915_gem_object
*obj
=
273 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
278 ctx
->engine
[RCS
].state
= obj
;
281 /* Default context will never have a file_priv */
282 if (file_priv
!= NULL
) {
283 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
284 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
288 ret
= DEFAULT_CONTEXT_HANDLE
;
290 ctx
->file_priv
= file_priv
;
291 ctx
->user_handle
= ret
;
292 /* NB: Mark all slices as needing a remap so that when the context first
293 * loads it will restore whatever remap state already exists. If there
294 * is no remap info, it will be a NOP. */
295 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
297 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
302 i915_gem_context_unreference(ctx
);
307 * The default context needs to exist per ring that uses contexts. It stores the
308 * context state of the GPU for applications that don't utilize HW contexts, as
309 * well as an idle case.
311 static struct i915_gem_context
*
312 i915_gem_create_context(struct drm_device
*dev
,
313 struct drm_i915_file_private
*file_priv
)
315 struct i915_gem_context
*ctx
;
317 lockdep_assert_held(&dev
->struct_mutex
);
319 ctx
= __create_hw_context(dev
, file_priv
);
323 if (USES_FULL_PPGTT(dev
)) {
324 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
327 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
329 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
330 i915_gem_context_unreference(ctx
);
331 return ERR_CAST(ppgtt
);
337 trace_i915_context_create(ctx
);
342 static void i915_gem_context_unpin(struct i915_gem_context
*ctx
,
343 struct intel_engine_cs
*engine
)
345 if (i915
.enable_execlists
) {
346 intel_lr_context_unpin(ctx
, engine
);
348 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
351 i915_gem_object_ggtt_unpin(ce
->state
);
353 i915_gem_context_unreference(ctx
);
357 void i915_gem_context_reset(struct drm_device
*dev
)
359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
361 lockdep_assert_held(&dev
->struct_mutex
);
363 if (i915
.enable_execlists
) {
364 struct i915_gem_context
*ctx
;
366 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
367 intel_lr_context_reset(dev_priv
, ctx
);
370 i915_gem_context_lost(dev_priv
);
373 int i915_gem_context_init(struct drm_device
*dev
)
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
376 struct i915_gem_context
*ctx
;
378 /* Init should only be called once per module load. Eventually the
379 * restriction on the context_disabled check can be loosened. */
380 if (WARN_ON(dev_priv
->kernel_context
))
383 if (intel_vgpu_active(dev_priv
) &&
384 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
385 if (!i915
.enable_execlists
) {
386 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
391 /* Using the simple ida interface, the max is limited by sizeof(int) */
392 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
393 ida_init(&dev_priv
->context_hw_ida
);
395 if (i915
.enable_execlists
) {
396 /* NB: intentionally left blank. We will allocate our own
397 * backing objects as we need them, thank you very much */
398 dev_priv
->hw_context_size
= 0;
399 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
400 dev_priv
->hw_context_size
=
401 round_up(get_context_size(dev_priv
), 4096);
402 if (dev_priv
->hw_context_size
> (1<<20)) {
403 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
404 dev_priv
->hw_context_size
);
405 dev_priv
->hw_context_size
= 0;
409 ctx
= i915_gem_create_context(dev
, NULL
);
411 DRM_ERROR("Failed to create default global context (error %ld)\n",
416 if (!i915
.enable_execlists
&& ctx
->engine
[RCS
].state
) {
419 /* We may need to do things with the shrinker which
420 * require us to immediately switch back to the default
421 * context. This can cause a problem as pinning the
422 * default context also requires GTT space which may not
423 * be available. To avoid this we always pin the default
426 ret
= i915_gem_obj_ggtt_pin(ctx
->engine
[RCS
].state
,
427 get_context_alignment(dev_priv
), 0);
429 DRM_ERROR("Failed to pinned default global context (error %d)\n",
431 i915_gem_context_unreference(ctx
);
436 dev_priv
->kernel_context
= ctx
;
438 DRM_DEBUG_DRIVER("%s context support initialized\n",
439 i915
.enable_execlists
? "LR" :
440 dev_priv
->hw_context_size
? "HW" : "fake");
444 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
446 struct intel_engine_cs
*engine
;
448 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
450 for_each_engine(engine
, dev_priv
) {
451 if (engine
->last_context
) {
452 i915_gem_context_unpin(engine
->last_context
, engine
);
453 engine
->last_context
= NULL
;
456 /* Force the GPU state to be reinitialised on enabling */
457 dev_priv
->kernel_context
->engine
[engine
->id
].initialised
=
458 engine
->init_context
== NULL
;
461 /* Force the GPU state to be reinitialised on enabling */
462 dev_priv
->kernel_context
->remap_slice
= ALL_L3_SLICES(dev_priv
);
465 void i915_gem_context_fini(struct drm_device
*dev
)
467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
468 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
470 lockdep_assert_held(&dev
->struct_mutex
);
472 if (!i915
.enable_execlists
&& dctx
->engine
[RCS
].state
)
473 i915_gem_object_ggtt_unpin(dctx
->engine
[RCS
].state
);
475 i915_gem_context_unreference(dctx
);
476 dev_priv
->kernel_context
= NULL
;
478 ida_destroy(&dev_priv
->context_hw_ida
);
481 static int context_idr_cleanup(int id
, void *p
, void *data
)
483 struct i915_gem_context
*ctx
= p
;
485 ctx
->file_priv
= ERR_PTR(-EBADF
);
486 i915_gem_context_unreference(ctx
);
490 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
492 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
493 struct i915_gem_context
*ctx
;
495 idr_init(&file_priv
->context_idr
);
497 mutex_lock(&dev
->struct_mutex
);
498 ctx
= i915_gem_create_context(dev
, file_priv
);
499 mutex_unlock(&dev
->struct_mutex
);
502 idr_destroy(&file_priv
->context_idr
);
509 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
511 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
513 lockdep_assert_held(&dev
->struct_mutex
);
515 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
516 idr_destroy(&file_priv
->context_idr
);
520 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
522 struct drm_i915_private
*dev_priv
= req
->i915
;
523 struct intel_engine_cs
*engine
= req
->engine
;
524 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
525 const int num_rings
=
526 /* Use an extended w/a on ivb+ if signalling from other rings */
527 i915_semaphore_is_enabled(dev_priv
) ?
528 hweight32(INTEL_INFO(dev_priv
)->ring_mask
) - 1 :
532 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
533 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
534 * explicitly, so we rely on the value at ring init, stored in
535 * itlb_before_ctx_switch.
537 if (IS_GEN6(dev_priv
)) {
538 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, 0);
543 /* These flags are for resource streamer on HSW+ */
544 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
545 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
546 else if (INTEL_GEN(dev_priv
) < 8)
547 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
551 if (INTEL_GEN(dev_priv
) >= 7)
552 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
554 ret
= intel_ring_begin(req
, len
);
558 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
559 if (INTEL_GEN(dev_priv
) >= 7) {
560 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
562 struct intel_engine_cs
*signaller
;
564 intel_ring_emit(engine
,
565 MI_LOAD_REGISTER_IMM(num_rings
));
566 for_each_engine(signaller
, dev_priv
) {
567 if (signaller
== engine
)
570 intel_ring_emit_reg(engine
,
571 RING_PSMI_CTL(signaller
->mmio_base
));
572 intel_ring_emit(engine
,
573 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
578 intel_ring_emit(engine
, MI_NOOP
);
579 intel_ring_emit(engine
, MI_SET_CONTEXT
);
580 intel_ring_emit(engine
,
581 i915_gem_obj_ggtt_offset(req
->ctx
->engine
[RCS
].state
) |
584 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
585 * WaMiSetContext_Hang:snb,ivb,vlv
587 intel_ring_emit(engine
, MI_NOOP
);
589 if (INTEL_GEN(dev_priv
) >= 7) {
591 struct intel_engine_cs
*signaller
;
592 i915_reg_t last_reg
= {}; /* keep gcc quiet */
594 intel_ring_emit(engine
,
595 MI_LOAD_REGISTER_IMM(num_rings
));
596 for_each_engine(signaller
, dev_priv
) {
597 if (signaller
== engine
)
600 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
601 intel_ring_emit_reg(engine
, last_reg
);
602 intel_ring_emit(engine
,
603 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
606 /* Insert a delay before the next switch! */
607 intel_ring_emit(engine
,
608 MI_STORE_REGISTER_MEM
|
609 MI_SRM_LRM_GLOBAL_GTT
);
610 intel_ring_emit_reg(engine
, last_reg
);
611 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
);
612 intel_ring_emit(engine
, MI_NOOP
);
614 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
617 intel_ring_advance(engine
);
622 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
624 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
625 struct intel_engine_cs
*engine
= req
->engine
;
631 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
636 * Note: We do not worry about the concurrent register cacheline hang
637 * here because no other code should access these registers other than
638 * at initialization time.
640 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
641 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
642 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
643 intel_ring_emit(engine
, remap_info
[i
]);
645 intel_ring_emit(engine
, MI_NOOP
);
646 intel_ring_advance(engine
);
651 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
652 struct intel_engine_cs
*engine
,
653 struct i915_gem_context
*to
)
658 if (!to
->engine
[RCS
].initialised
)
661 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
664 return to
== engine
->last_context
;
668 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
669 struct intel_engine_cs
*engine
,
670 struct i915_gem_context
*to
)
675 /* Always load the ppgtt on first use */
676 if (!engine
->last_context
)
679 /* Same context without new entries, skip */
680 if (engine
->last_context
== to
&&
681 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
684 if (engine
->id
!= RCS
)
687 if (INTEL_GEN(engine
->i915
) < 8)
694 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
695 struct i915_gem_context
*to
,
701 if (!IS_GEN8(to
->i915
))
704 if (hw_flags
& MI_RESTORE_INHIBIT
)
710 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
712 struct i915_gem_context
*to
= req
->ctx
;
713 struct intel_engine_cs
*engine
= req
->engine
;
714 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
715 struct i915_gem_context
*from
;
719 if (skip_rcs_switch(ppgtt
, engine
, to
))
722 /* Trying to pin first makes error handling easier. */
723 ret
= i915_gem_obj_ggtt_pin(to
->engine
[RCS
].state
,
724 get_context_alignment(engine
->i915
),
730 * Pin can switch back to the default context if we end up calling into
731 * evict_everything - as a last ditch gtt defrag effort that also
732 * switches to the default context. Hence we need to reload from here.
734 * XXX: Doing so is painfully broken!
736 from
= engine
->last_context
;
739 * Clear this page out of any CPU caches for coherent swap-in/out. Note
740 * that thanks to write = false in this call and us not setting any gpu
741 * write domains when putting a context object onto the active list
742 * (when switching away from it), this won't block.
744 * XXX: We need a real interface to do this instead of trickery.
746 ret
= i915_gem_object_set_to_gtt_domain(to
->engine
[RCS
].state
, false);
750 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
751 /* Older GENs and non render rings still want the load first,
752 * "PP_DCLV followed by PP_DIR_BASE register through Load
753 * Register Immediate commands in Ring Buffer before submitting
755 trace_switch_mm(engine
, to
);
756 ret
= ppgtt
->switch_mm(ppgtt
, req
);
761 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
762 /* NB: If we inhibit the restore, the context is not allowed to
763 * die because future work may end up depending on valid address
764 * space. This means we must enforce that a page table load
765 * occur when this occurs. */
766 hw_flags
= MI_RESTORE_INHIBIT
;
767 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
768 hw_flags
= MI_FORCE_RESTORE
;
772 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
773 ret
= mi_set_context(req
, hw_flags
);
778 /* The backing object for the context is done after switching to the
779 * *next* context. Therefore we cannot retire the previous context until
780 * the next context has already started running. In fact, the below code
781 * is a bit suboptimal because the retiring can occur simply after the
782 * MI_SET_CONTEXT instead of when the next seqno has completed.
785 from
->engine
[RCS
].state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
786 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->engine
[RCS
].state
), req
);
787 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
788 * whole damn pipeline, we don't need to explicitly mark the
789 * object dirty. The only exception is that the context must be
790 * correct in case the object gets swapped out. Ideally we'd be
791 * able to defer doing this until we know the object would be
792 * swapped, but there is no way to do that yet.
794 from
->engine
[RCS
].state
->dirty
= 1;
796 /* obj is kept alive until the next request by its active ref */
797 i915_gem_object_ggtt_unpin(from
->engine
[RCS
].state
);
798 i915_gem_context_unreference(from
);
800 i915_gem_context_reference(to
);
801 engine
->last_context
= to
;
803 /* GEN8 does *not* require an explicit reload if the PDPs have been
804 * setup, and we do not wish to move them.
806 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
807 trace_switch_mm(engine
, to
);
808 ret
= ppgtt
->switch_mm(ppgtt
, req
);
809 /* The hardware context switch is emitted, but we haven't
810 * actually changed the state - so it's probably safe to bail
811 * here. Still, let the user know something dangerous has
819 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
821 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
822 if (!(to
->remap_slice
& (1<<i
)))
825 ret
= remap_l3(req
, i
);
829 to
->remap_slice
&= ~(1<<i
);
832 if (!to
->engine
[RCS
].initialised
) {
833 if (engine
->init_context
) {
834 ret
= engine
->init_context(req
);
838 to
->engine
[RCS
].initialised
= true;
844 i915_gem_object_ggtt_unpin(to
->engine
[RCS
].state
);
849 * i915_switch_context() - perform a GPU context switch.
850 * @req: request for which we'll execute the context switch
852 * The context life cycle is simple. The context refcount is incremented and
853 * decremented by 1 and create and destroy. If the context is in use by the GPU,
854 * it will have a refcount > 1. This allows us to destroy the context abstract
855 * object while letting the normal object tracking destroy the backing BO.
857 * This function should not be used in execlists mode. Instead the context is
858 * switched by writing to the ELSP and requests keep a reference to their
861 int i915_switch_context(struct drm_i915_gem_request
*req
)
863 struct intel_engine_cs
*engine
= req
->engine
;
865 WARN_ON(i915
.enable_execlists
);
866 lockdep_assert_held(&req
->i915
->dev
->struct_mutex
);
868 if (!req
->ctx
->engine
[engine
->id
].state
) {
869 struct i915_gem_context
*to
= req
->ctx
;
870 struct i915_hw_ppgtt
*ppgtt
=
871 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
873 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
876 trace_switch_mm(engine
, to
);
877 ret
= ppgtt
->switch_mm(ppgtt
, req
);
881 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
884 if (to
!= engine
->last_context
) {
885 i915_gem_context_reference(to
);
886 if (engine
->last_context
)
887 i915_gem_context_unreference(engine
->last_context
);
888 engine
->last_context
= to
;
894 return do_rcs_switch(req
);
897 static bool contexts_enabled(struct drm_device
*dev
)
899 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
902 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
903 struct drm_file
*file
)
905 struct drm_i915_gem_context_create
*args
= data
;
906 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
907 struct i915_gem_context
*ctx
;
910 if (!contexts_enabled(dev
))
916 ret
= i915_mutex_lock_interruptible(dev
);
920 ctx
= i915_gem_create_context(dev
, file_priv
);
921 mutex_unlock(&dev
->struct_mutex
);
925 args
->ctx_id
= ctx
->user_handle
;
926 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
931 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
932 struct drm_file
*file
)
934 struct drm_i915_gem_context_destroy
*args
= data
;
935 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
936 struct i915_gem_context
*ctx
;
942 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
945 ret
= i915_mutex_lock_interruptible(dev
);
949 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
951 mutex_unlock(&dev
->struct_mutex
);
955 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
956 i915_gem_context_unreference(ctx
);
957 mutex_unlock(&dev
->struct_mutex
);
959 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
963 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
964 struct drm_file
*file
)
966 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
967 struct drm_i915_gem_context_param
*args
= data
;
968 struct i915_gem_context
*ctx
;
971 ret
= i915_mutex_lock_interruptible(dev
);
975 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
977 mutex_unlock(&dev
->struct_mutex
);
982 switch (args
->param
) {
983 case I915_CONTEXT_PARAM_BAN_PERIOD
:
984 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
986 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
987 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
989 case I915_CONTEXT_PARAM_GTT_SIZE
:
991 args
->value
= ctx
->ppgtt
->base
.total
;
992 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
993 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
995 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1001 mutex_unlock(&dev
->struct_mutex
);
1006 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1007 struct drm_file
*file
)
1009 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1010 struct drm_i915_gem_context_param
*args
= data
;
1011 struct i915_gem_context
*ctx
;
1014 ret
= i915_mutex_lock_interruptible(dev
);
1018 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1020 mutex_unlock(&dev
->struct_mutex
);
1021 return PTR_ERR(ctx
);
1024 switch (args
->param
) {
1025 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1028 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
1029 !capable(CAP_SYS_ADMIN
))
1032 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
1034 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1038 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1039 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1046 mutex_unlock(&dev
->struct_mutex
);
1051 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1052 void *data
, struct drm_file
*file
)
1054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1055 struct drm_i915_reset_stats
*args
= data
;
1056 struct i915_ctx_hang_stats
*hs
;
1057 struct i915_gem_context
*ctx
;
1060 if (args
->flags
|| args
->pad
)
1063 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1072 mutex_unlock(&dev
->struct_mutex
);
1073 return PTR_ERR(ctx
);
1075 hs
= &ctx
->hang_stats
;
1077 if (capable(CAP_SYS_ADMIN
))
1078 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1080 args
->reset_count
= 0;
1082 args
->batch_active
= hs
->batch_active
;
1083 args
->batch_pending
= hs
->batch_pending
;
1085 mutex_unlock(&dev
->struct_mutex
);