2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 static void lut_close(struct i915_gem_context
*ctx
)
98 struct i915_lut_handle
*lut
, *ln
;
99 struct radix_tree_iter iter
;
102 list_for_each_entry_safe(lut
, ln
, &ctx
->handles_list
, ctx_link
) {
103 list_del(&lut
->obj_link
);
104 kmem_cache_free(ctx
->i915
->luts
, lut
);
107 radix_tree_for_each_slot(slot
, &ctx
->handles_vma
, &iter
, 0) {
108 struct i915_vma
*vma
= rcu_dereference_raw(*slot
);
109 struct drm_i915_gem_object
*obj
= vma
->obj
;
111 radix_tree_iter_delete(&ctx
->handles_vma
, &iter
, slot
);
113 if (!i915_vma_is_ggtt(vma
))
116 __i915_gem_object_release_unless_active(obj
);
120 static void i915_gem_context_free(struct i915_gem_context
*ctx
)
124 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
125 GEM_BUG_ON(!i915_gem_context_is_closed(ctx
));
127 i915_ppgtt_put(ctx
->ppgtt
);
129 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
130 struct intel_context
*ce
= &ctx
->engine
[i
];
135 WARN_ON(ce
->pin_count
);
137 intel_ring_free(ce
->ring
);
139 __i915_gem_object_release_unless_active(ce
->state
->obj
);
145 list_del(&ctx
->link
);
147 ida_simple_remove(&ctx
->i915
->contexts
.hw_ida
, ctx
->hw_id
);
151 static void contexts_free(struct drm_i915_private
*i915
)
153 struct llist_node
*freed
= llist_del_all(&i915
->contexts
.free_list
);
154 struct i915_gem_context
*ctx
, *cn
;
156 lockdep_assert_held(&i915
->drm
.struct_mutex
);
158 llist_for_each_entry_safe(ctx
, cn
, freed
, free_link
)
159 i915_gem_context_free(ctx
);
162 static void contexts_free_first(struct drm_i915_private
*i915
)
164 struct i915_gem_context
*ctx
;
165 struct llist_node
*freed
;
167 lockdep_assert_held(&i915
->drm
.struct_mutex
);
169 freed
= llist_del_first(&i915
->contexts
.free_list
);
173 ctx
= container_of(freed
, typeof(*ctx
), free_link
);
174 i915_gem_context_free(ctx
);
177 static void contexts_free_worker(struct work_struct
*work
)
179 struct drm_i915_private
*i915
=
180 container_of(work
, typeof(*i915
), contexts
.free_work
);
182 mutex_lock(&i915
->drm
.struct_mutex
);
184 mutex_unlock(&i915
->drm
.struct_mutex
);
187 void i915_gem_context_release(struct kref
*ref
)
189 struct i915_gem_context
*ctx
= container_of(ref
, typeof(*ctx
), ref
);
190 struct drm_i915_private
*i915
= ctx
->i915
;
192 trace_i915_context_free(ctx
);
193 if (llist_add(&ctx
->free_link
, &i915
->contexts
.free_list
))
194 queue_work(i915
->wq
, &i915
->contexts
.free_work
);
197 static void context_close(struct i915_gem_context
*ctx
)
199 i915_gem_context_set_closed(ctx
);
203 i915_ppgtt_close(&ctx
->ppgtt
->base
);
205 ctx
->file_priv
= ERR_PTR(-EBADF
);
206 i915_gem_context_put(ctx
);
209 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
213 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
214 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
216 /* Contexts are only released when no longer active.
217 * Flush any pending retires to hopefully release some
218 * stale contexts and try again.
220 i915_gem_retire_requests(dev_priv
);
221 ret
= ida_simple_get(&dev_priv
->contexts
.hw_ida
,
222 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
231 static u32
default_desc_template(const struct drm_i915_private
*i915
,
232 const struct i915_hw_ppgtt
*ppgtt
)
237 desc
= GEN8_CTX_VALID
| GEN8_CTX_PRIVILEGE
;
239 address_mode
= INTEL_LEGACY_32B_CONTEXT
;
240 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
))
241 address_mode
= INTEL_LEGACY_64B_CONTEXT
;
242 desc
|= address_mode
<< GEN8_CTX_ADDRESSING_MODE_SHIFT
;
245 desc
|= GEN8_CTX_L3LLC_COHERENT
;
247 /* TODO: WaDisableLiteRestore when we start using semaphore
248 * signalling between Command Streamers
249 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
255 static struct i915_gem_context
*
256 __create_hw_context(struct drm_i915_private
*dev_priv
,
257 struct drm_i915_file_private
*file_priv
)
259 struct i915_gem_context
*ctx
;
262 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
264 return ERR_PTR(-ENOMEM
);
266 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
272 kref_init(&ctx
->ref
);
273 list_add_tail(&ctx
->link
, &dev_priv
->contexts
.list
);
274 ctx
->i915
= dev_priv
;
275 ctx
->priority
= I915_PRIORITY_NORMAL
;
277 INIT_RADIX_TREE(&ctx
->handles_vma
, GFP_KERNEL
);
278 INIT_LIST_HEAD(&ctx
->handles_list
);
280 /* Default context will never have a file_priv */
281 ret
= DEFAULT_CONTEXT_HANDLE
;
283 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
284 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
288 ctx
->user_handle
= ret
;
290 ctx
->file_priv
= file_priv
;
292 ctx
->pid
= get_task_pid(current
, PIDTYPE_PID
);
293 ctx
->name
= kasprintf(GFP_KERNEL
, "%s[%d]/%x",
303 /* NB: Mark all slices as needing a remap so that when the context first
304 * loads it will restore whatever remap state already exists. If there
305 * is no remap info, it will be a NOP. */
306 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
308 i915_gem_context_set_bannable(ctx
);
309 ctx
->ring_size
= 4 * PAGE_SIZE
;
311 default_desc_template(dev_priv
, dev_priv
->mm
.aliasing_ppgtt
);
313 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
314 * present or not in use we still need a small bias as ring wraparound
315 * at offset 0 sometimes hangs. No idea why.
317 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
)
318 ctx
->ggtt_offset_bias
= GUC_WOPCM_TOP
;
320 ctx
->ggtt_offset_bias
= I915_GTT_PAGE_SIZE
;
326 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
332 static void __destroy_hw_context(struct i915_gem_context
*ctx
,
333 struct drm_i915_file_private
*file_priv
)
335 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
340 * The default context needs to exist per ring that uses contexts. It stores the
341 * context state of the GPU for applications that don't utilize HW contexts, as
342 * well as an idle case.
344 static struct i915_gem_context
*
345 i915_gem_create_context(struct drm_i915_private
*dev_priv
,
346 struct drm_i915_file_private
*file_priv
)
348 struct i915_gem_context
*ctx
;
350 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
352 /* Reap the most stale context */
353 contexts_free_first(dev_priv
);
355 ctx
= __create_hw_context(dev_priv
, file_priv
);
359 if (USES_FULL_PPGTT(dev_priv
)) {
360 struct i915_hw_ppgtt
*ppgtt
;
362 ppgtt
= i915_ppgtt_create(dev_priv
, file_priv
, ctx
->name
);
364 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
366 __destroy_hw_context(ctx
, file_priv
);
367 return ERR_CAST(ppgtt
);
371 ctx
->desc_template
= default_desc_template(dev_priv
, ppgtt
);
374 trace_i915_context_create(ctx
);
380 * i915_gem_context_create_gvt - create a GVT GEM context
383 * This function is used to create a GVT specific GEM context.
386 * pointer to i915_gem_context on success, error pointer if failed
389 struct i915_gem_context
*
390 i915_gem_context_create_gvt(struct drm_device
*dev
)
392 struct i915_gem_context
*ctx
;
395 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
396 return ERR_PTR(-ENODEV
);
398 ret
= i915_mutex_lock_interruptible(dev
);
402 ctx
= __create_hw_context(to_i915(dev
), NULL
);
406 ctx
->file_priv
= ERR_PTR(-EBADF
);
407 i915_gem_context_set_closed(ctx
); /* not user accessible */
408 i915_gem_context_clear_bannable(ctx
);
409 i915_gem_context_set_force_single_submission(ctx
);
410 if (!i915
.enable_guc_submission
)
411 ctx
->ring_size
= 512 * PAGE_SIZE
; /* Max ring buffer size */
413 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
415 mutex_unlock(&dev
->struct_mutex
);
419 int i915_gem_contexts_init(struct drm_i915_private
*dev_priv
)
421 struct i915_gem_context
*ctx
;
423 /* Init should only be called once per module load. Eventually the
424 * restriction on the context_disabled check can be loosened. */
425 if (WARN_ON(dev_priv
->kernel_context
))
428 INIT_LIST_HEAD(&dev_priv
->contexts
.list
);
429 INIT_WORK(&dev_priv
->contexts
.free_work
, contexts_free_worker
);
430 init_llist_head(&dev_priv
->contexts
.free_list
);
432 if (intel_vgpu_active(dev_priv
) &&
433 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
434 if (!i915
.enable_execlists
) {
435 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
440 /* Using the simple ida interface, the max is limited by sizeof(int) */
441 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
442 ida_init(&dev_priv
->contexts
.hw_ida
);
444 ctx
= i915_gem_create_context(dev_priv
, NULL
);
446 DRM_ERROR("Failed to create default global context (error %ld)\n",
451 /* For easy recognisablity, we want the kernel context to be 0 and then
452 * all user contexts will have non-zero hw_id.
454 GEM_BUG_ON(ctx
->hw_id
);
456 i915_gem_context_clear_bannable(ctx
);
457 ctx
->priority
= I915_PRIORITY_MIN
; /* lowest priority; idle task */
458 dev_priv
->kernel_context
= ctx
;
460 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
462 DRM_DEBUG_DRIVER("%s context support initialized\n",
463 dev_priv
->engine
[RCS
]->context_size
? "logical" :
468 void i915_gem_contexts_lost(struct drm_i915_private
*dev_priv
)
470 struct intel_engine_cs
*engine
;
471 enum intel_engine_id id
;
473 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
475 for_each_engine(engine
, dev_priv
, id
) {
476 engine
->legacy_active_context
= NULL
;
478 if (!engine
->last_retired_context
)
481 engine
->context_unpin(engine
, engine
->last_retired_context
);
482 engine
->last_retired_context
= NULL
;
485 /* Force the GPU state to be restored on enabling */
486 if (!i915
.enable_execlists
) {
487 struct i915_gem_context
*ctx
;
489 list_for_each_entry(ctx
, &dev_priv
->contexts
.list
, link
) {
490 if (!i915_gem_context_is_default(ctx
))
493 for_each_engine(engine
, dev_priv
, id
)
494 ctx
->engine
[engine
->id
].initialised
= false;
496 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
499 for_each_engine(engine
, dev_priv
, id
) {
500 struct intel_context
*kce
=
501 &dev_priv
->kernel_context
->engine
[engine
->id
];
503 kce
->initialised
= true;
508 void i915_gem_contexts_fini(struct drm_i915_private
*i915
)
510 struct i915_gem_context
*ctx
;
512 lockdep_assert_held(&i915
->drm
.struct_mutex
);
514 /* Keep the context so that we can free it immediately ourselves */
515 ctx
= i915_gem_context_get(fetch_and_zero(&i915
->kernel_context
));
516 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx
));
518 i915_gem_context_free(ctx
);
520 /* Must free all deferred contexts (via flush_workqueue) first */
521 ida_destroy(&i915
->contexts
.hw_ida
);
524 static int context_idr_cleanup(int id
, void *p
, void *data
)
526 struct i915_gem_context
*ctx
= p
;
532 int i915_gem_context_open(struct drm_i915_private
*i915
,
533 struct drm_file
*file
)
535 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
536 struct i915_gem_context
*ctx
;
538 idr_init(&file_priv
->context_idr
);
540 mutex_lock(&i915
->drm
.struct_mutex
);
541 ctx
= i915_gem_create_context(i915
, file_priv
);
542 mutex_unlock(&i915
->drm
.struct_mutex
);
544 idr_destroy(&file_priv
->context_idr
);
548 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
553 void i915_gem_context_close(struct drm_file
*file
)
555 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
557 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
559 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
560 idr_destroy(&file_priv
->context_idr
);
564 mi_set_context(struct drm_i915_gem_request
*req
, u32 flags
)
566 struct drm_i915_private
*dev_priv
= req
->i915
;
567 struct intel_engine_cs
*engine
= req
->engine
;
568 enum intel_engine_id id
;
569 const int num_rings
=
570 /* Use an extended w/a on gen7 if signalling from other rings */
571 (i915
.semaphores
&& INTEL_GEN(dev_priv
) == 7) ?
572 INTEL_INFO(dev_priv
)->num_rings
- 1 :
577 flags
|= MI_MM_SPACE_GTT
;
578 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
579 /* These flags are for resource streamer on HSW+ */
580 flags
|= HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
;
582 flags
|= MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
;
585 if (INTEL_GEN(dev_priv
) >= 7)
586 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
588 cs
= intel_ring_begin(req
, len
);
592 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
593 if (INTEL_GEN(dev_priv
) >= 7) {
594 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
596 struct intel_engine_cs
*signaller
;
598 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
599 for_each_engine(signaller
, dev_priv
, id
) {
600 if (signaller
== engine
)
603 *cs
++ = i915_mmio_reg_offset(
604 RING_PSMI_CTL(signaller
->mmio_base
));
605 *cs
++ = _MASKED_BIT_ENABLE(
606 GEN6_PSMI_SLEEP_MSG_DISABLE
);
612 *cs
++ = MI_SET_CONTEXT
;
613 *cs
++ = i915_ggtt_offset(req
->ctx
->engine
[RCS
].state
) | flags
;
615 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
616 * WaMiSetContext_Hang:snb,ivb,vlv
620 if (INTEL_GEN(dev_priv
) >= 7) {
622 struct intel_engine_cs
*signaller
;
623 i915_reg_t last_reg
= {}; /* keep gcc quiet */
625 *cs
++ = MI_LOAD_REGISTER_IMM(num_rings
);
626 for_each_engine(signaller
, dev_priv
, id
) {
627 if (signaller
== engine
)
630 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
631 *cs
++ = i915_mmio_reg_offset(last_reg
);
632 *cs
++ = _MASKED_BIT_DISABLE(
633 GEN6_PSMI_SLEEP_MSG_DISABLE
);
636 /* Insert a delay before the next switch! */
637 *cs
++ = MI_STORE_REGISTER_MEM
| MI_SRM_LRM_GLOBAL_GTT
;
638 *cs
++ = i915_mmio_reg_offset(last_reg
);
639 *cs
++ = i915_ggtt_offset(engine
->scratch
);
642 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
645 intel_ring_advance(req
, cs
);
650 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
652 u32
*cs
, *remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
658 cs
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
663 * Note: We do not worry about the concurrent register cacheline hang
664 * here because no other code should access these registers other than
665 * at initialization time.
667 *cs
++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4);
668 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
669 *cs
++ = i915_mmio_reg_offset(GEN7_L3LOG(slice
, i
));
670 *cs
++ = remap_info
[i
];
673 intel_ring_advance(req
, cs
);
678 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
679 struct intel_engine_cs
*engine
,
680 struct i915_gem_context
*to
)
685 if (!to
->engine
[RCS
].initialised
)
688 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
691 return to
== engine
->legacy_active_context
;
695 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
, struct intel_engine_cs
*engine
)
697 struct i915_gem_context
*from
= engine
->legacy_active_context
;
702 /* Always load the ppgtt on first use */
706 /* Same context without new entries, skip */
707 if ((!from
->ppgtt
|| from
->ppgtt
== ppgtt
) &&
708 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
711 if (engine
->id
!= RCS
)
714 if (INTEL_GEN(engine
->i915
) < 8)
721 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
722 struct i915_gem_context
*to
,
728 if (!IS_GEN8(to
->i915
))
731 if (hw_flags
& MI_RESTORE_INHIBIT
)
737 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
739 struct i915_gem_context
*to
= req
->ctx
;
740 struct intel_engine_cs
*engine
= req
->engine
;
741 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
742 struct i915_gem_context
*from
= engine
->legacy_active_context
;
746 GEM_BUG_ON(engine
->id
!= RCS
);
748 if (skip_rcs_switch(ppgtt
, engine
, to
))
751 if (needs_pd_load_pre(ppgtt
, engine
)) {
752 /* Older GENs and non render rings still want the load first,
753 * "PP_DCLV followed by PP_DIR_BASE register through Load
754 * Register Immediate commands in Ring Buffer before submitting
756 trace_switch_mm(engine
, to
);
757 ret
= ppgtt
->switch_mm(ppgtt
, req
);
762 if (!to
->engine
[RCS
].initialised
|| i915_gem_context_is_default(to
))
763 /* NB: If we inhibit the restore, the context is not allowed to
764 * die because future work may end up depending on valid address
765 * space. This means we must enforce that a page table load
766 * occur when this occurs. */
767 hw_flags
= MI_RESTORE_INHIBIT
;
768 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
769 hw_flags
= MI_FORCE_RESTORE
;
773 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
774 ret
= mi_set_context(req
, hw_flags
);
778 engine
->legacy_active_context
= to
;
781 /* GEN8 does *not* require an explicit reload if the PDPs have been
782 * setup, and we do not wish to move them.
784 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
785 trace_switch_mm(engine
, to
);
786 ret
= ppgtt
->switch_mm(ppgtt
, req
);
787 /* The hardware context switch is emitted, but we haven't
788 * actually changed the state - so it's probably safe to bail
789 * here. Still, let the user know something dangerous has
797 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
799 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
800 if (!(to
->remap_slice
& (1<<i
)))
803 ret
= remap_l3(req
, i
);
807 to
->remap_slice
&= ~(1<<i
);
810 if (!to
->engine
[RCS
].initialised
) {
811 if (engine
->init_context
) {
812 ret
= engine
->init_context(req
);
816 to
->engine
[RCS
].initialised
= true;
823 * i915_switch_context() - perform a GPU context switch.
824 * @req: request for which we'll execute the context switch
826 * The context life cycle is simple. The context refcount is incremented and
827 * decremented by 1 and create and destroy. If the context is in use by the GPU,
828 * it will have a refcount > 1. This allows us to destroy the context abstract
829 * object while letting the normal object tracking destroy the backing BO.
831 * This function should not be used in execlists mode. Instead the context is
832 * switched by writing to the ELSP and requests keep a reference to their
835 int i915_switch_context(struct drm_i915_gem_request
*req
)
837 struct intel_engine_cs
*engine
= req
->engine
;
839 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
840 if (i915
.enable_execlists
)
843 if (!req
->ctx
->engine
[engine
->id
].state
) {
844 struct i915_gem_context
*to
= req
->ctx
;
845 struct i915_hw_ppgtt
*ppgtt
=
846 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
848 if (needs_pd_load_pre(ppgtt
, engine
)) {
851 trace_switch_mm(engine
, to
);
852 ret
= ppgtt
->switch_mm(ppgtt
, req
);
856 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
859 engine
->legacy_active_context
= to
;
863 return do_rcs_switch(req
);
866 static bool engine_has_kernel_context(struct intel_engine_cs
*engine
)
868 struct i915_gem_timeline
*timeline
;
870 list_for_each_entry(timeline
, &engine
->i915
->gt
.timelines
, link
) {
871 struct intel_timeline
*tl
;
873 if (timeline
== &engine
->i915
->gt
.global_timeline
)
876 tl
= &timeline
->engine
[engine
->id
];
877 if (i915_gem_active_peek(&tl
->last_request
,
878 &engine
->i915
->drm
.struct_mutex
))
882 return (!engine
->last_retired_context
||
883 i915_gem_context_is_kernel(engine
->last_retired_context
));
886 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
)
888 struct intel_engine_cs
*engine
;
889 struct i915_gem_timeline
*timeline
;
890 enum intel_engine_id id
;
892 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
894 i915_gem_retire_requests(dev_priv
);
896 for_each_engine(engine
, dev_priv
, id
) {
897 struct drm_i915_gem_request
*req
;
900 if (engine_has_kernel_context(engine
))
903 req
= i915_gem_request_alloc(engine
, dev_priv
->kernel_context
);
907 /* Queue this switch after all other activity */
908 list_for_each_entry(timeline
, &dev_priv
->gt
.timelines
, link
) {
909 struct drm_i915_gem_request
*prev
;
910 struct intel_timeline
*tl
;
912 tl
= &timeline
->engine
[engine
->id
];
913 prev
= i915_gem_active_raw(&tl
->last_request
,
914 &dev_priv
->drm
.struct_mutex
);
916 i915_sw_fence_await_sw_fence_gfp(&req
->submit
,
921 ret
= i915_switch_context(req
);
922 i915_add_request(req
);
930 static bool client_is_banned(struct drm_i915_file_private
*file_priv
)
932 return atomic_read(&file_priv
->context_bans
) > I915_MAX_CLIENT_CONTEXT_BANS
;
935 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
936 struct drm_file
*file
)
938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
939 struct drm_i915_gem_context_create
*args
= data
;
940 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
941 struct i915_gem_context
*ctx
;
944 if (!dev_priv
->engine
[RCS
]->context_size
)
950 if (client_is_banned(file_priv
)) {
951 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
953 pid_nr(get_task_pid(current
, PIDTYPE_PID
)));
958 ret
= i915_mutex_lock_interruptible(dev
);
962 ctx
= i915_gem_create_context(dev_priv
, file_priv
);
963 mutex_unlock(&dev
->struct_mutex
);
967 GEM_BUG_ON(i915_gem_context_is_kernel(ctx
));
969 args
->ctx_id
= ctx
->user_handle
;
970 DRM_DEBUG("HW context %d created\n", args
->ctx_id
);
975 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
976 struct drm_file
*file
)
978 struct drm_i915_gem_context_destroy
*args
= data
;
979 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
980 struct i915_gem_context
*ctx
;
986 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
989 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
993 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
997 __destroy_hw_context(ctx
, file_priv
);
998 mutex_unlock(&dev
->struct_mutex
);
1001 i915_gem_context_put(ctx
);
1005 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
1006 struct drm_file
*file
)
1008 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1009 struct drm_i915_gem_context_param
*args
= data
;
1010 struct i915_gem_context
*ctx
;
1013 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1018 switch (args
->param
) {
1019 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1022 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1023 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
1025 case I915_CONTEXT_PARAM_GTT_SIZE
:
1027 args
->value
= ctx
->ppgtt
->base
.total
;
1028 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
1029 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
1031 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
1033 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1034 args
->value
= i915_gem_context_no_error_capture(ctx
);
1036 case I915_CONTEXT_PARAM_BANNABLE
:
1037 args
->value
= i915_gem_context_is_bannable(ctx
);
1044 i915_gem_context_put(ctx
);
1048 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
1049 struct drm_file
*file
)
1051 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1052 struct drm_i915_gem_context_param
*args
= data
;
1053 struct i915_gem_context
*ctx
;
1056 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1060 ret
= i915_mutex_lock_interruptible(dev
);
1064 switch (args
->param
) {
1065 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1068 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1072 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1073 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1076 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
:
1079 else if (args
->value
)
1080 i915_gem_context_set_no_error_capture(ctx
);
1082 i915_gem_context_clear_no_error_capture(ctx
);
1084 case I915_CONTEXT_PARAM_BANNABLE
:
1087 else if (!capable(CAP_SYS_ADMIN
) && !args
->value
)
1089 else if (args
->value
)
1090 i915_gem_context_set_bannable(ctx
);
1092 i915_gem_context_clear_bannable(ctx
);
1098 mutex_unlock(&dev
->struct_mutex
);
1101 i915_gem_context_put(ctx
);
1105 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1106 void *data
, struct drm_file
*file
)
1108 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1109 struct drm_i915_reset_stats
*args
= data
;
1110 struct i915_gem_context
*ctx
;
1113 if (args
->flags
|| args
->pad
)
1118 ctx
= __i915_gem_context_lookup_rcu(file
->driver_priv
, args
->ctx_id
);
1123 * We opt for unserialised reads here. This may result in tearing
1124 * in the extremely unlikely event of a GPU hang on this context
1125 * as we are querying them. If we need that extra layer of protection,
1126 * we should wrap the hangstats with a seqlock.
1129 if (capable(CAP_SYS_ADMIN
))
1130 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1132 args
->reset_count
= 0;
1134 args
->batch_active
= atomic_read(&ctx
->guilty_count
);
1135 args
->batch_pending
= atomic_read(&ctx
->active_count
);
1143 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1144 #include "selftests/mock_context.c"
1145 #include "selftests/i915_gem_context.c"