2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private
*dev_priv
)
104 if (IS_GEN6(dev_priv
))
105 return GEN6_CONTEXT_ALIGN
;
107 return GEN7_CONTEXT_ALIGN
;
110 static int get_context_size(struct drm_i915_private
*dev_priv
)
115 switch (INTEL_GEN(dev_priv
)) {
117 reg
= I915_READ(CXT_SIZE
);
118 ret
= GEN6_CXT_TOTAL_SIZE(reg
) * 64;
121 reg
= I915_READ(GEN7_CXT_SIZE
);
122 if (IS_HASWELL(dev_priv
))
123 ret
= HSW_CXT_TOTAL_SIZE
;
125 ret
= GEN7_CXT_TOTAL_SIZE(reg
) * 64;
128 ret
= GEN8_CXT_TOTAL_SIZE
;
137 static void i915_gem_context_clean(struct i915_gem_context
*ctx
)
139 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
140 struct i915_vma
*vma
, *next
;
145 list_for_each_entry_safe(vma
, next
, &ppgtt
->base
.inactive_list
,
147 if (WARN_ON(__i915_vma_unbind_no_wait(vma
)))
152 void i915_gem_context_free(struct kref
*ctx_ref
)
154 struct i915_gem_context
*ctx
= container_of(ctx_ref
, typeof(*ctx
), ref
);
156 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
157 trace_i915_context_free(ctx
);
159 if (i915
.enable_execlists
)
160 intel_lr_context_free(ctx
);
163 * This context is going away and we need to remove all VMAs still
164 * around. This is to handle imported shared objects for which
165 * destructor did not run when their handles were closed.
167 i915_gem_context_clean(ctx
);
169 i915_ppgtt_put(ctx
->ppgtt
);
171 if (ctx
->legacy_hw_ctx
.rcs_state
)
172 drm_gem_object_unreference(&ctx
->legacy_hw_ctx
.rcs_state
->base
);
173 list_del(&ctx
->link
);
175 ida_simple_remove(&ctx
->i915
->context_hw_ida
, ctx
->hw_id
);
179 struct drm_i915_gem_object
*
180 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
)
182 struct drm_i915_gem_object
*obj
;
185 lockdep_assert_held(&dev
->struct_mutex
);
187 obj
= i915_gem_object_create(dev
, size
);
192 * Try to make the context utilize L3 as well as LLC.
194 * On VLV we don't have L3 controls in the PTEs so we
195 * shouldn't touch the cache level, especially as that
196 * would make the object snooped which might have a
197 * negative performance impact.
199 * Snooping is required on non-llc platforms in execlist
200 * mode, but since all GGTT accesses use PAT entry 0 we
201 * get snooping anyway regardless of cache_level.
203 * This is only applicable for Ivy Bridge devices since
204 * later platforms don't have L3 control bits in the PTE.
206 if (IS_IVYBRIDGE(dev
)) {
207 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_L3_LLC
);
208 /* Failure shouldn't ever happen this early */
210 drm_gem_object_unreference(&obj
->base
);
218 static int assign_hw_id(struct drm_i915_private
*dev_priv
, unsigned *out
)
222 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
223 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
225 /* Contexts are only released when no longer active.
226 * Flush any pending retires to hopefully release some
227 * stale contexts and try again.
229 i915_gem_retire_requests(dev_priv
);
230 ret
= ida_simple_get(&dev_priv
->context_hw_ida
,
231 0, MAX_CONTEXT_HW_ID
, GFP_KERNEL
);
240 static struct i915_gem_context
*
241 __create_hw_context(struct drm_device
*dev
,
242 struct drm_i915_file_private
*file_priv
)
244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
245 struct i915_gem_context
*ctx
;
248 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
250 return ERR_PTR(-ENOMEM
);
252 ret
= assign_hw_id(dev_priv
, &ctx
->hw_id
);
258 kref_init(&ctx
->ref
);
259 list_add_tail(&ctx
->link
, &dev_priv
->context_list
);
260 ctx
->i915
= dev_priv
;
262 if (dev_priv
->hw_context_size
) {
263 struct drm_i915_gem_object
*obj
=
264 i915_gem_alloc_context_obj(dev
, dev_priv
->hw_context_size
);
269 ctx
->legacy_hw_ctx
.rcs_state
= obj
;
272 /* Default context will never have a file_priv */
273 if (file_priv
!= NULL
) {
274 ret
= idr_alloc(&file_priv
->context_idr
, ctx
,
275 DEFAULT_CONTEXT_HANDLE
, 0, GFP_KERNEL
);
279 ret
= DEFAULT_CONTEXT_HANDLE
;
281 ctx
->file_priv
= file_priv
;
282 ctx
->user_handle
= ret
;
283 /* NB: Mark all slices as needing a remap so that when the context first
284 * loads it will restore whatever remap state already exists. If there
285 * is no remap info, it will be a NOP. */
286 ctx
->remap_slice
= ALL_L3_SLICES(dev_priv
);
288 ctx
->hang_stats
.ban_period_seconds
= DRM_I915_CTX_BAN_PERIOD
;
293 i915_gem_context_unreference(ctx
);
298 * The default context needs to exist per ring that uses contexts. It stores the
299 * context state of the GPU for applications that don't utilize HW contexts, as
300 * well as an idle case.
302 static struct i915_gem_context
*
303 i915_gem_create_context(struct drm_device
*dev
,
304 struct drm_i915_file_private
*file_priv
)
306 struct i915_gem_context
*ctx
;
308 lockdep_assert_held(&dev
->struct_mutex
);
310 ctx
= __create_hw_context(dev
, file_priv
);
314 if (USES_FULL_PPGTT(dev
)) {
315 struct i915_hw_ppgtt
*ppgtt
= i915_ppgtt_create(dev
, file_priv
);
318 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
320 idr_remove(&file_priv
->context_idr
, ctx
->user_handle
);
321 i915_gem_context_unreference(ctx
);
322 return ERR_CAST(ppgtt
);
328 trace_i915_context_create(ctx
);
333 static void i915_gem_context_unpin(struct i915_gem_context
*ctx
,
334 struct intel_engine_cs
*engine
)
336 if (i915
.enable_execlists
) {
337 intel_lr_context_unpin(ctx
, engine
);
339 if (engine
->id
== RCS
&& ctx
->legacy_hw_ctx
.rcs_state
)
340 i915_gem_object_ggtt_unpin(ctx
->legacy_hw_ctx
.rcs_state
);
341 i915_gem_context_unreference(ctx
);
345 void i915_gem_context_reset(struct drm_device
*dev
)
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
349 lockdep_assert_held(&dev
->struct_mutex
);
351 if (i915
.enable_execlists
) {
352 struct i915_gem_context
*ctx
;
354 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
355 intel_lr_context_reset(dev_priv
, ctx
);
358 i915_gem_context_lost(dev_priv
);
361 int i915_gem_context_init(struct drm_device
*dev
)
363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 struct i915_gem_context
*ctx
;
366 /* Init should only be called once per module load. Eventually the
367 * restriction on the context_disabled check can be loosened. */
368 if (WARN_ON(dev_priv
->kernel_context
))
371 if (intel_vgpu_active(dev_priv
) &&
372 HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
373 if (!i915
.enable_execlists
) {
374 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
379 /* Using the simple ida interface, the max is limited by sizeof(int) */
380 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> INT_MAX
);
381 ida_init(&dev_priv
->context_hw_ida
);
383 if (i915
.enable_execlists
) {
384 /* NB: intentionally left blank. We will allocate our own
385 * backing objects as we need them, thank you very much */
386 dev_priv
->hw_context_size
= 0;
387 } else if (HAS_HW_CONTEXTS(dev_priv
)) {
388 dev_priv
->hw_context_size
=
389 round_up(get_context_size(dev_priv
), 4096);
390 if (dev_priv
->hw_context_size
> (1<<20)) {
391 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
392 dev_priv
->hw_context_size
);
393 dev_priv
->hw_context_size
= 0;
397 ctx
= i915_gem_create_context(dev
, NULL
);
399 DRM_ERROR("Failed to create default global context (error %ld)\n",
404 if (ctx
->legacy_hw_ctx
.rcs_state
) {
407 /* We may need to do things with the shrinker which
408 * require us to immediately switch back to the default
409 * context. This can cause a problem as pinning the
410 * default context also requires GTT space which may not
411 * be available. To avoid this we always pin the default
414 ret
= i915_gem_obj_ggtt_pin(ctx
->legacy_hw_ctx
.rcs_state
,
415 get_context_alignment(dev_priv
), 0);
417 DRM_ERROR("Failed to pinned default global context (error %d)\n",
419 i915_gem_context_unreference(ctx
);
424 dev_priv
->kernel_context
= ctx
;
426 DRM_DEBUG_DRIVER("%s context support initialized\n",
427 i915
.enable_execlists
? "LR" :
428 dev_priv
->hw_context_size
? "HW" : "fake");
432 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
)
434 struct intel_engine_cs
*engine
;
436 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
438 for_each_engine(engine
, dev_priv
) {
439 if (engine
->last_context
== NULL
)
442 i915_gem_context_unpin(engine
->last_context
, engine
);
443 engine
->last_context
= NULL
;
446 /* Force the GPU state to be reinitialised on enabling */
447 dev_priv
->kernel_context
->legacy_hw_ctx
.initialized
= false;
448 dev_priv
->kernel_context
->remap_slice
= ALL_L3_SLICES(dev_priv
);
451 void i915_gem_context_fini(struct drm_device
*dev
)
453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
454 struct i915_gem_context
*dctx
= dev_priv
->kernel_context
;
456 lockdep_assert_held(&dev
->struct_mutex
);
458 if (dctx
->legacy_hw_ctx
.rcs_state
)
459 i915_gem_object_ggtt_unpin(dctx
->legacy_hw_ctx
.rcs_state
);
461 i915_gem_context_unreference(dctx
);
462 dev_priv
->kernel_context
= NULL
;
464 ida_destroy(&dev_priv
->context_hw_ida
);
467 static int context_idr_cleanup(int id
, void *p
, void *data
)
469 struct i915_gem_context
*ctx
= p
;
471 i915_gem_context_unreference(ctx
);
475 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
)
477 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
478 struct i915_gem_context
*ctx
;
480 idr_init(&file_priv
->context_idr
);
482 mutex_lock(&dev
->struct_mutex
);
483 ctx
= i915_gem_create_context(dev
, file_priv
);
484 mutex_unlock(&dev
->struct_mutex
);
487 idr_destroy(&file_priv
->context_idr
);
494 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
)
496 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
498 lockdep_assert_held(&dev
->struct_mutex
);
500 idr_for_each(&file_priv
->context_idr
, context_idr_cleanup
, NULL
);
501 idr_destroy(&file_priv
->context_idr
);
505 mi_set_context(struct drm_i915_gem_request
*req
, u32 hw_flags
)
507 struct drm_i915_private
*dev_priv
= req
->i915
;
508 struct intel_engine_cs
*engine
= req
->engine
;
509 u32 flags
= hw_flags
| MI_MM_SPACE_GTT
;
510 const int num_rings
=
511 /* Use an extended w/a on ivb+ if signalling from other rings */
512 i915_semaphore_is_enabled(dev_priv
) ?
513 hweight32(INTEL_INFO(dev_priv
)->ring_mask
) - 1 :
517 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
518 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
519 * explicitly, so we rely on the value at ring init, stored in
520 * itlb_before_ctx_switch.
522 if (IS_GEN6(dev_priv
)) {
523 ret
= engine
->flush(req
, I915_GEM_GPU_DOMAINS
, 0);
528 /* These flags are for resource streamer on HSW+ */
529 if (IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8)
530 flags
|= (HSW_MI_RS_SAVE_STATE_EN
| HSW_MI_RS_RESTORE_STATE_EN
);
531 else if (INTEL_GEN(dev_priv
) < 8)
532 flags
|= (MI_SAVE_EXT_STATE_EN
| MI_RESTORE_EXT_STATE_EN
);
536 if (INTEL_GEN(dev_priv
) >= 7)
537 len
+= 2 + (num_rings
? 4*num_rings
+ 6 : 0);
539 ret
= intel_ring_begin(req
, len
);
543 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
544 if (INTEL_GEN(dev_priv
) >= 7) {
545 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
547 struct intel_engine_cs
*signaller
;
549 intel_ring_emit(engine
,
550 MI_LOAD_REGISTER_IMM(num_rings
));
551 for_each_engine(signaller
, dev_priv
) {
552 if (signaller
== engine
)
555 intel_ring_emit_reg(engine
,
556 RING_PSMI_CTL(signaller
->mmio_base
));
557 intel_ring_emit(engine
,
558 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
563 intel_ring_emit(engine
, MI_NOOP
);
564 intel_ring_emit(engine
, MI_SET_CONTEXT
);
565 intel_ring_emit(engine
,
566 i915_gem_obj_ggtt_offset(req
->ctx
->legacy_hw_ctx
.rcs_state
) |
569 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
570 * WaMiSetContext_Hang:snb,ivb,vlv
572 intel_ring_emit(engine
, MI_NOOP
);
574 if (INTEL_GEN(dev_priv
) >= 7) {
576 struct intel_engine_cs
*signaller
;
577 i915_reg_t last_reg
= {}; /* keep gcc quiet */
579 intel_ring_emit(engine
,
580 MI_LOAD_REGISTER_IMM(num_rings
));
581 for_each_engine(signaller
, dev_priv
) {
582 if (signaller
== engine
)
585 last_reg
= RING_PSMI_CTL(signaller
->mmio_base
);
586 intel_ring_emit_reg(engine
, last_reg
);
587 intel_ring_emit(engine
,
588 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE
));
591 /* Insert a delay before the next switch! */
592 intel_ring_emit(engine
,
593 MI_STORE_REGISTER_MEM
|
594 MI_SRM_LRM_GLOBAL_GTT
);
595 intel_ring_emit_reg(engine
, last_reg
);
596 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
);
597 intel_ring_emit(engine
, MI_NOOP
);
599 intel_ring_emit(engine
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
602 intel_ring_advance(engine
);
607 static int remap_l3(struct drm_i915_gem_request
*req
, int slice
)
609 u32
*remap_info
= req
->i915
->l3_parity
.remap_info
[slice
];
610 struct intel_engine_cs
*engine
= req
->engine
;
616 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/4 * 2 + 2);
621 * Note: We do not worry about the concurrent register cacheline hang
622 * here because no other code should access these registers other than
623 * at initialization time.
625 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE
/4));
626 for (i
= 0; i
< GEN7_L3LOG_SIZE
/4; i
++) {
627 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
628 intel_ring_emit(engine
, remap_info
[i
]);
630 intel_ring_emit(engine
, MI_NOOP
);
631 intel_ring_advance(engine
);
636 static inline bool skip_rcs_switch(struct i915_hw_ppgtt
*ppgtt
,
637 struct intel_engine_cs
*engine
,
638 struct i915_gem_context
*to
)
643 if (!to
->legacy_hw_ctx
.initialized
)
646 if (ppgtt
&& (intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
649 return to
== engine
->last_context
;
653 needs_pd_load_pre(struct i915_hw_ppgtt
*ppgtt
,
654 struct intel_engine_cs
*engine
,
655 struct i915_gem_context
*to
)
660 /* Always load the ppgtt on first use */
661 if (!engine
->last_context
)
664 /* Same context without new entries, skip */
665 if (engine
->last_context
== to
&&
666 !(intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
))
669 if (engine
->id
!= RCS
)
672 if (INTEL_GEN(engine
->i915
) < 8)
679 needs_pd_load_post(struct i915_hw_ppgtt
*ppgtt
,
680 struct i915_gem_context
*to
,
686 if (!IS_GEN8(to
->i915
))
689 if (hw_flags
& MI_RESTORE_INHIBIT
)
695 static int do_rcs_switch(struct drm_i915_gem_request
*req
)
697 struct i915_gem_context
*to
= req
->ctx
;
698 struct intel_engine_cs
*engine
= req
->engine
;
699 struct i915_hw_ppgtt
*ppgtt
= to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
700 struct i915_gem_context
*from
;
704 if (skip_rcs_switch(ppgtt
, engine
, to
))
707 /* Trying to pin first makes error handling easier. */
708 ret
= i915_gem_obj_ggtt_pin(to
->legacy_hw_ctx
.rcs_state
,
709 get_context_alignment(engine
->i915
),
715 * Pin can switch back to the default context if we end up calling into
716 * evict_everything - as a last ditch gtt defrag effort that also
717 * switches to the default context. Hence we need to reload from here.
719 * XXX: Doing so is painfully broken!
721 from
= engine
->last_context
;
724 * Clear this page out of any CPU caches for coherent swap-in/out. Note
725 * that thanks to write = false in this call and us not setting any gpu
726 * write domains when putting a context object onto the active list
727 * (when switching away from it), this won't block.
729 * XXX: We need a real interface to do this instead of trickery.
731 ret
= i915_gem_object_set_to_gtt_domain(to
->legacy_hw_ctx
.rcs_state
, false);
735 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
736 /* Older GENs and non render rings still want the load first,
737 * "PP_DCLV followed by PP_DIR_BASE register through Load
738 * Register Immediate commands in Ring Buffer before submitting
740 trace_switch_mm(engine
, to
);
741 ret
= ppgtt
->switch_mm(ppgtt
, req
);
746 if (!to
->legacy_hw_ctx
.initialized
|| i915_gem_context_is_default(to
))
747 /* NB: If we inhibit the restore, the context is not allowed to
748 * die because future work may end up depending on valid address
749 * space. This means we must enforce that a page table load
750 * occur when this occurs. */
751 hw_flags
= MI_RESTORE_INHIBIT
;
752 else if (ppgtt
&& intel_engine_flag(engine
) & ppgtt
->pd_dirty_rings
)
753 hw_flags
= MI_FORCE_RESTORE
;
757 if (to
!= from
|| (hw_flags
& MI_FORCE_RESTORE
)) {
758 ret
= mi_set_context(req
, hw_flags
);
763 /* The backing object for the context is done after switching to the
764 * *next* context. Therefore we cannot retire the previous context until
765 * the next context has already started running. In fact, the below code
766 * is a bit suboptimal because the retiring can occur simply after the
767 * MI_SET_CONTEXT instead of when the next seqno has completed.
770 from
->legacy_hw_ctx
.rcs_state
->base
.read_domains
= I915_GEM_DOMAIN_INSTRUCTION
;
771 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from
->legacy_hw_ctx
.rcs_state
), req
);
772 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
773 * whole damn pipeline, we don't need to explicitly mark the
774 * object dirty. The only exception is that the context must be
775 * correct in case the object gets swapped out. Ideally we'd be
776 * able to defer doing this until we know the object would be
777 * swapped, but there is no way to do that yet.
779 from
->legacy_hw_ctx
.rcs_state
->dirty
= 1;
781 /* obj is kept alive until the next request by its active ref */
782 i915_gem_object_ggtt_unpin(from
->legacy_hw_ctx
.rcs_state
);
783 i915_gem_context_unreference(from
);
785 i915_gem_context_reference(to
);
786 engine
->last_context
= to
;
788 /* GEN8 does *not* require an explicit reload if the PDPs have been
789 * setup, and we do not wish to move them.
791 if (needs_pd_load_post(ppgtt
, to
, hw_flags
)) {
792 trace_switch_mm(engine
, to
);
793 ret
= ppgtt
->switch_mm(ppgtt
, req
);
794 /* The hardware context switch is emitted, but we haven't
795 * actually changed the state - so it's probably safe to bail
796 * here. Still, let the user know something dangerous has
804 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
806 for (i
= 0; i
< MAX_L3_SLICES
; i
++) {
807 if (!(to
->remap_slice
& (1<<i
)))
810 ret
= remap_l3(req
, i
);
814 to
->remap_slice
&= ~(1<<i
);
817 if (!to
->legacy_hw_ctx
.initialized
) {
818 if (engine
->init_context
) {
819 ret
= engine
->init_context(req
);
823 to
->legacy_hw_ctx
.initialized
= true;
829 i915_gem_object_ggtt_unpin(to
->legacy_hw_ctx
.rcs_state
);
834 * i915_switch_context() - perform a GPU context switch.
835 * @req: request for which we'll execute the context switch
837 * The context life cycle is simple. The context refcount is incremented and
838 * decremented by 1 and create and destroy. If the context is in use by the GPU,
839 * it will have a refcount > 1. This allows us to destroy the context abstract
840 * object while letting the normal object tracking destroy the backing BO.
842 * This function should not be used in execlists mode. Instead the context is
843 * switched by writing to the ELSP and requests keep a reference to their
846 int i915_switch_context(struct drm_i915_gem_request
*req
)
848 struct intel_engine_cs
*engine
= req
->engine
;
850 WARN_ON(i915
.enable_execlists
);
851 lockdep_assert_held(&req
->i915
->dev
->struct_mutex
);
853 if (engine
->id
!= RCS
||
854 req
->ctx
->legacy_hw_ctx
.rcs_state
== NULL
) {
855 struct i915_gem_context
*to
= req
->ctx
;
856 struct i915_hw_ppgtt
*ppgtt
=
857 to
->ppgtt
?: req
->i915
->mm
.aliasing_ppgtt
;
859 if (needs_pd_load_pre(ppgtt
, engine
, to
)) {
862 trace_switch_mm(engine
, to
);
863 ret
= ppgtt
->switch_mm(ppgtt
, req
);
867 ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(engine
);
870 if (to
!= engine
->last_context
) {
871 i915_gem_context_reference(to
);
872 if (engine
->last_context
)
873 i915_gem_context_unreference(engine
->last_context
);
874 engine
->last_context
= to
;
880 return do_rcs_switch(req
);
883 static bool contexts_enabled(struct drm_device
*dev
)
885 return i915
.enable_execlists
|| to_i915(dev
)->hw_context_size
;
888 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
889 struct drm_file
*file
)
891 struct drm_i915_gem_context_create
*args
= data
;
892 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
893 struct i915_gem_context
*ctx
;
896 if (!contexts_enabled(dev
))
902 ret
= i915_mutex_lock_interruptible(dev
);
906 ctx
= i915_gem_create_context(dev
, file_priv
);
907 mutex_unlock(&dev
->struct_mutex
);
911 args
->ctx_id
= ctx
->user_handle
;
912 DRM_DEBUG_DRIVER("HW context %d created\n", args
->ctx_id
);
917 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
918 struct drm_file
*file
)
920 struct drm_i915_gem_context_destroy
*args
= data
;
921 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
922 struct i915_gem_context
*ctx
;
928 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
)
931 ret
= i915_mutex_lock_interruptible(dev
);
935 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
937 mutex_unlock(&dev
->struct_mutex
);
941 idr_remove(&ctx
->file_priv
->context_idr
, ctx
->user_handle
);
942 i915_gem_context_unreference(ctx
);
943 mutex_unlock(&dev
->struct_mutex
);
945 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args
->ctx_id
);
949 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
950 struct drm_file
*file
)
952 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
953 struct drm_i915_gem_context_param
*args
= data
;
954 struct i915_gem_context
*ctx
;
957 ret
= i915_mutex_lock_interruptible(dev
);
961 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
963 mutex_unlock(&dev
->struct_mutex
);
968 switch (args
->param
) {
969 case I915_CONTEXT_PARAM_BAN_PERIOD
:
970 args
->value
= ctx
->hang_stats
.ban_period_seconds
;
972 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
973 args
->value
= ctx
->flags
& CONTEXT_NO_ZEROMAP
;
975 case I915_CONTEXT_PARAM_GTT_SIZE
:
977 args
->value
= ctx
->ppgtt
->base
.total
;
978 else if (to_i915(dev
)->mm
.aliasing_ppgtt
)
979 args
->value
= to_i915(dev
)->mm
.aliasing_ppgtt
->base
.total
;
981 args
->value
= to_i915(dev
)->ggtt
.base
.total
;
987 mutex_unlock(&dev
->struct_mutex
);
992 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
993 struct drm_file
*file
)
995 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
996 struct drm_i915_gem_context_param
*args
= data
;
997 struct i915_gem_context
*ctx
;
1000 ret
= i915_mutex_lock_interruptible(dev
);
1004 ctx
= i915_gem_context_lookup(file_priv
, args
->ctx_id
);
1006 mutex_unlock(&dev
->struct_mutex
);
1007 return PTR_ERR(ctx
);
1010 switch (args
->param
) {
1011 case I915_CONTEXT_PARAM_BAN_PERIOD
:
1014 else if (args
->value
< ctx
->hang_stats
.ban_period_seconds
&&
1015 !capable(CAP_SYS_ADMIN
))
1018 ctx
->hang_stats
.ban_period_seconds
= args
->value
;
1020 case I915_CONTEXT_PARAM_NO_ZEROMAP
:
1024 ctx
->flags
&= ~CONTEXT_NO_ZEROMAP
;
1025 ctx
->flags
|= args
->value
? CONTEXT_NO_ZEROMAP
: 0;
1032 mutex_unlock(&dev
->struct_mutex
);
1037 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
,
1038 void *data
, struct drm_file
*file
)
1040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 struct drm_i915_reset_stats
*args
= data
;
1042 struct i915_ctx_hang_stats
*hs
;
1043 struct i915_gem_context
*ctx
;
1046 if (args
->flags
|| args
->pad
)
1049 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1052 ret
= i915_mutex_lock_interruptible(dev
);
1056 ctx
= i915_gem_context_lookup(file
->driver_priv
, args
->ctx_id
);
1058 mutex_unlock(&dev
->struct_mutex
);
1059 return PTR_ERR(ctx
);
1061 hs
= &ctx
->hang_stats
;
1063 if (capable(CAP_SYS_ADMIN
))
1064 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1066 args
->reset_count
= 0;
1068 args
->batch_active
= hs
->batch_active
;
1069 args
->batch_pending
= hs
->batch_pending
;
1071 mutex_unlock(&dev
->struct_mutex
);