2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/i915_drm.h>
38 #include "i915_gem_clflush.h"
39 #include "i915_trace.h"
40 #include "intel_drv.h"
41 #include "intel_frontbuffer.h"
47 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
50 #define __EXEC_OBJECT_HAS_REF BIT(31)
51 #define __EXEC_OBJECT_HAS_PIN BIT(30)
52 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
53 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
54 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
55 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
56 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
58 #define __EXEC_HAS_RELOC BIT(31)
59 #define __EXEC_VALIDATED BIT(30)
60 #define UPDATE PIN_OFFSET_FIXED
62 #define BATCH_OFFSET_BIAS (256*1024)
64 #define __I915_EXEC_ILLEGAL_FLAGS \
65 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
68 * DOC: User command execution
70 * Userspace submits commands to be executed on the GPU as an instruction
71 * stream within a GEM object we call a batchbuffer. This instructions may
72 * refer to other GEM objects containing auxiliary state such as kernels,
73 * samplers, render targets and even secondary batchbuffers. Userspace does
74 * not know where in the GPU memory these objects reside and so before the
75 * batchbuffer is passed to the GPU for execution, those addresses in the
76 * batchbuffer and auxiliary objects are updated. This is known as relocation,
77 * or patching. To try and avoid having to relocate each object on the next
78 * execution, userspace is told the location of those objects in this pass,
79 * but this remains just a hint as the kernel may choose a new location for
80 * any object in the future.
82 * Processing an execbuf ioctl is conceptually split up into a few phases.
84 * 1. Validation - Ensure all the pointers, handles and flags are valid.
85 * 2. Reservation - Assign GPU address space for every object
86 * 3. Relocation - Update any addresses to point to the final locations
87 * 4. Serialisation - Order the request with respect to its dependencies
88 * 5. Construction - Construct a request to execute the batchbuffer
89 * 6. Submission (at some point in the future execution)
91 * Reserving resources for the execbuf is the most complicated phase. We
92 * neither want to have to migrate the object in the address space, nor do
93 * we want to have to update any relocations pointing to this object. Ideally,
94 * we want to leave the object where it is and for all the existing relocations
95 * to match. If the object is given a new address, or if userspace thinks the
96 * object is elsewhere, we have to parse all the relocation entries and update
97 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
98 * all the target addresses in all of its objects match the value in the
99 * relocation entries and that they all match the presumed offsets given by the
100 * list of execbuffer objects. Using this knowledge, we know that if we haven't
101 * moved any buffers, all the relocation entries are valid and we can skip
102 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
103 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
105 * The addresses written in the objects must match the corresponding
106 * reloc.presumed_offset which in turn must match the corresponding
109 * Any render targets written to in the batch must be flagged with
112 * To avoid stalling, execobject.offset should match the current
113 * address of that object within the active context.
115 * The reservation is done is multiple phases. First we try and keep any
116 * object already bound in its current location - so as long as meets the
117 * constraints imposed by the new execbuffer. Any object left unbound after the
118 * first pass is then fitted into any available idle space. If an object does
119 * not fit, all objects are removed from the reservation and the process rerun
120 * after sorting the objects into a priority order (more difficult to fit
121 * objects are tried first). Failing that, the entire VM is cleared and we try
122 * to fit the execbuf once last time before concluding that it simply will not
125 * A small complication to all of this is that we allow userspace not only to
126 * specify an alignment and a size for the object in the address space, but
127 * we also allow userspace to specify the exact offset. This objects are
128 * simpler to place (the location is known a priori) all we have to do is make
129 * sure the space is available.
131 * Once all the objects are in place, patching up the buried pointers to point
132 * to the final locations is a fairly simple job of walking over the relocation
133 * entry arrays, looking up the right address and rewriting the value into
134 * the object. Simple! ... The relocation entries are stored in user memory
135 * and so to access them we have to copy them into a local buffer. That copy
136 * has to avoid taking any pagefaults as they may lead back to a GEM object
137 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
138 * the relocation into multiple passes. First we try to do everything within an
139 * atomic context (avoid the pagefaults) which requires that we never wait. If
140 * we detect that we may wait, or if we need to fault, then we have to fallback
141 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
142 * bells yet?) Dropping the mutex means that we lose all the state we have
143 * built up so far for the execbuf and we must reset any global data. However,
144 * we do leave the objects pinned in their final locations - which is a
145 * potential issue for concurrent execbufs. Once we have left the mutex, we can
146 * allocate and copy all the relocation entries into a large array at our
147 * leisure, reacquire the mutex, reclaim all the objects and other state and
148 * then proceed to update any incorrect addresses with the objects.
150 * As we process the relocation entries, we maintain a record of whether the
151 * object is being written to. Using NORELOC, we expect userspace to provide
152 * this information instead. We also check whether we can skip the relocation
153 * by comparing the expected value inside the relocation entry with the target's
154 * final address. If they differ, we have to map the current object and rewrite
155 * the 4 or 8 byte pointer within.
157 * Serialising an execbuf is quite simple according to the rules of the GEM
158 * ABI. Execution within each context is ordered by the order of submission.
159 * Writes to any GEM object are in order of submission and are exclusive. Reads
160 * from a GEM object are unordered with respect to other reads, but ordered by
161 * writes. A write submitted after a read cannot occur before the read, and
162 * similarly any read submitted after a write cannot occur before the write.
163 * Writes are ordered between engines such that only one write occurs at any
164 * time (completing any reads beforehand) - using semaphores where available
165 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
166 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
167 * reads before starting, and any read (either using set-domain or pread) must
168 * flush all GPU writes before starting. (Note we only employ a barrier before,
169 * we currently rely on userspace not concurrently starting a new execution
170 * whilst reading or writing to an object. This may be an advantage or not
171 * depending on how much you trust userspace not to shoot themselves in the
172 * foot.) Serialisation may just result in the request being inserted into
173 * a DAG awaiting its turn, but most simple is to wait on the CPU until
174 * all dependencies are resolved.
176 * After all of that, is just a matter of closing the request and handing it to
177 * the hardware (well, leaving it in a queue to be executed). However, we also
178 * offer the ability for batchbuffers to be run with elevated privileges so
179 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
180 * Before any batch is given extra privileges we first must check that it
181 * contains no nefarious instructions, we check that each instruction is from
182 * our whitelist and all registers are also from an allowed list. We first
183 * copy the user's batchbuffer to a shadow (so that the user doesn't have
184 * access to it, either by the CPU or GPU as we scan it) and then parse each
185 * instruction. If everything is ok, we set a flag telling the hardware to run
186 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
189 struct i915_execbuffer
{
190 struct drm_i915_private
*i915
; /** i915 backpointer */
191 struct drm_file
*file
; /** per-file lookup tables and limits */
192 struct drm_i915_gem_execbuffer2
*args
; /** ioctl parameters */
193 struct drm_i915_gem_exec_object2
*exec
; /** ioctl execobj[] */
195 struct intel_engine_cs
*engine
; /** engine to queue the request to */
196 struct i915_gem_context
*ctx
; /** context for building the request */
197 struct i915_address_space
*vm
; /** GTT and vma for the request */
199 struct drm_i915_gem_request
*request
; /** our request to build */
200 struct i915_vma
*batch
; /** identity of the batch obj/vma */
202 /** actual size of execobj[] as we may extend it for the cmdparser */
203 unsigned int buffer_count
;
205 /** list of vma not yet bound during reservation phase */
206 struct list_head unbound
;
208 /** list of vma that have execobj.relocation_count */
209 struct list_head relocs
;
212 * Track the most recently used object for relocations, as we
213 * frequently have to perform multiple relocations within the same
217 struct drm_mm_node node
; /** temporary GTT binding */
218 unsigned long vaddr
; /** Current kmap address */
219 unsigned long page
; /** Currently mapped page index */
220 unsigned int gen
; /** Cached value of INTEL_GEN */
221 bool use_64bit_reloc
: 1;
224 bool needs_unfenced
: 1;
226 struct drm_i915_gem_request
*rq
;
228 unsigned int rq_size
;
231 u64 invalid_flags
; /** Set of execobj.flags that are invalid */
232 u32 context_flags
; /** Set of execobj.flags to insert from the ctx */
234 u32 batch_start_offset
; /** Location within object of batch */
235 u32 batch_len
; /** Length of batch within object */
236 u32 batch_flags
; /** Flags composed for emit_bb_start() */
239 * Indicate either the size of the hastable used to resolve
240 * relocation handles, or if negative that we are using a direct
241 * index into the execobj[].
244 struct hlist_head
*buckets
; /** ht for relocation handles */
248 * As an alternative to creating a hashtable of handle-to-vma for a batch,
249 * we used the last available reserved field in the execobject[] and stash
250 * a link from the execobj to its vma.
252 #define __exec_to_vma(ee) (ee)->rsvd2
253 #define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee))
256 * Used to convert any address to canonical form.
257 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
258 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
259 * addresses to be in a canonical form:
260 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
261 * canonical form [63:48] == [47]."
263 #define GEN8_HIGH_ADDRESS_BIT 47
264 static inline u64
gen8_canonical_addr(u64 address
)
266 return sign_extend64(address
, GEN8_HIGH_ADDRESS_BIT
);
269 static inline u64
gen8_noncanonical_addr(u64 address
)
271 return address
& GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT
, 0);
274 static int eb_create(struct i915_execbuffer
*eb
)
276 if (!(eb
->args
->flags
& I915_EXEC_HANDLE_LUT
)) {
277 unsigned int size
= 1 + ilog2(eb
->buffer_count
);
280 * Without a 1:1 association between relocation handles and
281 * the execobject[] index, we instead create a hashtable.
282 * We size it dynamically based on available memory, starting
283 * first with 1:1 assocative hash and scaling back until
284 * the allocation succeeds.
286 * Later on we use a positive lut_size to indicate we are
287 * using this hashtable, and a negative value to indicate a
293 /* While we can still reduce the allocation size, don't
294 * raise a warning and allow the allocation to fail.
295 * On the last pass though, we want to try as hard
296 * as possible to perform the allocation and warn
299 flags
= GFP_TEMPORARY
;
301 flags
|= __GFP_NORETRY
| __GFP_NOWARN
;
303 eb
->buckets
= kzalloc(sizeof(struct hlist_head
) << size
,
314 eb
->lut_size
= -eb
->buffer_count
;
321 eb_vma_misplaced(const struct drm_i915_gem_exec_object2
*entry
,
322 const struct i915_vma
*vma
)
324 if (!(entry
->flags
& __EXEC_OBJECT_HAS_PIN
))
327 if (vma
->node
.size
< entry
->pad_to_size
)
330 if (entry
->alignment
&& !IS_ALIGNED(vma
->node
.start
, entry
->alignment
))
333 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
334 vma
->node
.start
!= entry
->offset
)
337 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
338 vma
->node
.start
< BATCH_OFFSET_BIAS
)
341 if (!(entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) &&
342 (vma
->node
.start
+ vma
->node
.size
- 1) >> 32)
349 eb_pin_vma(struct i915_execbuffer
*eb
,
350 struct drm_i915_gem_exec_object2
*entry
,
351 struct i915_vma
*vma
)
356 flags
= vma
->node
.start
;
358 flags
= entry
->offset
& PIN_OFFSET_MASK
;
360 flags
|= PIN_USER
| PIN_NOEVICT
| PIN_OFFSET_FIXED
;
361 if (unlikely(entry
->flags
& EXEC_OBJECT_NEEDS_GTT
))
364 if (unlikely(i915_vma_pin(vma
, 0, 0, flags
)))
367 if (unlikely(entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
)) {
368 if (unlikely(i915_vma_get_fence(vma
))) {
373 if (i915_vma_pin_fence(vma
))
374 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
377 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
381 __eb_unreserve_vma(struct i915_vma
*vma
,
382 const struct drm_i915_gem_exec_object2
*entry
)
384 GEM_BUG_ON(!(entry
->flags
& __EXEC_OBJECT_HAS_PIN
));
386 if (unlikely(entry
->flags
& __EXEC_OBJECT_HAS_FENCE
))
387 i915_vma_unpin_fence(vma
);
389 __i915_vma_unpin(vma
);
393 eb_unreserve_vma(struct i915_vma
*vma
,
394 struct drm_i915_gem_exec_object2
*entry
)
396 if (!(entry
->flags
& __EXEC_OBJECT_HAS_PIN
))
399 __eb_unreserve_vma(vma
, entry
);
400 entry
->flags
&= ~__EXEC_OBJECT_RESERVED
;
404 eb_validate_vma(struct i915_execbuffer
*eb
,
405 struct drm_i915_gem_exec_object2
*entry
,
406 struct i915_vma
*vma
)
408 if (unlikely(entry
->flags
& eb
->invalid_flags
))
411 if (unlikely(entry
->alignment
&& !is_power_of_2(entry
->alignment
)))
415 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
416 * any non-page-aligned or non-canonical addresses.
418 if (unlikely(entry
->flags
& EXEC_OBJECT_PINNED
&&
419 entry
->offset
!= gen8_canonical_addr(entry
->offset
& PAGE_MASK
)))
422 /* pad_to_size was once a reserved field, so sanitize it */
423 if (entry
->flags
& EXEC_OBJECT_PAD_TO_SIZE
) {
424 if (unlikely(offset_in_page(entry
->pad_to_size
)))
427 entry
->pad_to_size
= 0;
430 if (unlikely(vma
->exec_entry
)) {
431 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
432 entry
->handle
, (int)(entry
- eb
->exec
));
437 * From drm_mm perspective address space is continuous,
438 * so from this point we're always using non-canonical
441 entry
->offset
= gen8_noncanonical_addr(entry
->offset
);
447 eb_add_vma(struct i915_execbuffer
*eb
,
448 struct drm_i915_gem_exec_object2
*entry
,
449 struct i915_vma
*vma
)
453 GEM_BUG_ON(i915_vma_is_closed(vma
));
455 if (!(eb
->args
->flags
& __EXEC_VALIDATED
)) {
456 err
= eb_validate_vma(eb
, entry
, vma
);
461 if (eb
->lut_size
> 0) {
462 vma
->exec_handle
= entry
->handle
;
463 hlist_add_head(&vma
->exec_node
,
464 &eb
->buckets
[hash_32(entry
->handle
,
468 if (entry
->relocation_count
)
469 list_add_tail(&vma
->reloc_link
, &eb
->relocs
);
471 if (!eb
->reloc_cache
.has_fence
) {
472 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
474 if ((entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
||
475 eb
->reloc_cache
.needs_unfenced
) &&
476 i915_gem_object_is_tiled(vma
->obj
))
477 entry
->flags
|= EXEC_OBJECT_NEEDS_GTT
| __EXEC_OBJECT_NEEDS_MAP
;
480 if (!(entry
->flags
& EXEC_OBJECT_PINNED
))
481 entry
->flags
|= eb
->context_flags
;
484 * Stash a pointer from the vma to execobj, so we can query its flags,
485 * size, alignment etc as provided by the user. Also we stash a pointer
486 * to the vma inside the execobj so that we can use a direct lookup
487 * to find the right target VMA when doing relocations.
489 vma
->exec_entry
= entry
;
490 __exec_to_vma(entry
) = (uintptr_t)vma
;
493 eb_pin_vma(eb
, entry
, vma
);
494 if (eb_vma_misplaced(entry
, vma
)) {
495 eb_unreserve_vma(vma
, entry
);
497 list_add_tail(&vma
->exec_link
, &eb
->unbound
);
498 if (drm_mm_node_allocated(&vma
->node
))
499 err
= i915_vma_unbind(vma
);
501 if (entry
->offset
!= vma
->node
.start
) {
502 entry
->offset
= vma
->node
.start
| UPDATE
;
503 eb
->args
->flags
|= __EXEC_HAS_RELOC
;
509 static inline int use_cpu_reloc(const struct reloc_cache
*cache
,
510 const struct drm_i915_gem_object
*obj
)
512 if (!i915_gem_object_has_struct_page(obj
))
515 if (DBG_FORCE_RELOC
== FORCE_CPU_RELOC
)
518 if (DBG_FORCE_RELOC
== FORCE_GTT_RELOC
)
521 return (cache
->has_llc
||
523 obj
->cache_level
!= I915_CACHE_NONE
);
526 static int eb_reserve_vma(const struct i915_execbuffer
*eb
,
527 struct i915_vma
*vma
)
529 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
533 flags
= PIN_USER
| PIN_NONBLOCK
;
534 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
538 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
539 * limit address to the first 4GBs for unflagged objects.
541 if (!(entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
))
542 flags
|= PIN_ZONE_4G
;
544 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
545 flags
|= PIN_MAPPABLE
;
547 if (entry
->flags
& EXEC_OBJECT_PINNED
) {
548 flags
|= entry
->offset
| PIN_OFFSET_FIXED
;
549 flags
&= ~PIN_NONBLOCK
; /* force overlapping PINNED checks */
550 } else if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
) {
551 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
554 err
= i915_vma_pin(vma
, entry
->pad_to_size
, entry
->alignment
, flags
);
558 if (entry
->offset
!= vma
->node
.start
) {
559 entry
->offset
= vma
->node
.start
| UPDATE
;
560 eb
->args
->flags
|= __EXEC_HAS_RELOC
;
563 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
564 GEM_BUG_ON(eb_vma_misplaced(entry
, vma
));
566 if (unlikely(entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
)) {
567 err
= i915_vma_get_fence(vma
);
573 if (i915_vma_pin_fence(vma
))
574 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
580 static int eb_reserve(struct i915_execbuffer
*eb
)
582 const unsigned int count
= eb
->buffer_count
;
583 struct list_head last
;
584 struct i915_vma
*vma
;
585 unsigned int i
, pass
;
589 * Attempt to pin all of the buffers into the GTT.
590 * This is done in 3 phases:
592 * 1a. Unbind all objects that do not match the GTT constraints for
593 * the execbuffer (fenceable, mappable, alignment etc).
594 * 1b. Increment pin count for already bound objects.
595 * 2. Bind new objects.
596 * 3. Decrement pin count.
598 * This avoid unnecessary unbinding of later objects in order to make
599 * room for the earlier objects *unless* we need to defragment.
605 list_for_each_entry(vma
, &eb
->unbound
, exec_link
) {
606 err
= eb_reserve_vma(eb
, vma
);
613 /* Resort *all* the objects into priority order */
614 INIT_LIST_HEAD(&eb
->unbound
);
615 INIT_LIST_HEAD(&last
);
616 for (i
= 0; i
< count
; i
++) {
617 struct drm_i915_gem_exec_object2
*entry
= &eb
->exec
[i
];
619 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
620 entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
623 vma
= exec_to_vma(entry
);
624 eb_unreserve_vma(vma
, entry
);
626 if (entry
->flags
& EXEC_OBJECT_PINNED
)
627 list_add(&vma
->exec_link
, &eb
->unbound
);
628 else if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
629 list_add_tail(&vma
->exec_link
, &eb
->unbound
);
631 list_add_tail(&vma
->exec_link
, &last
);
633 list_splice_tail(&last
, &eb
->unbound
);
640 /* Too fragmented, unbind everything and retry */
641 err
= i915_gem_evict_vm(eb
->vm
);
652 static inline struct hlist_head
*
653 ht_head(const struct i915_gem_context_vma_lut
*lut
, u32 handle
)
655 return &lut
->ht
[hash_32(handle
, lut
->ht_bits
)];
659 ht_needs_resize(const struct i915_gem_context_vma_lut
*lut
)
661 return (4*lut
->ht_count
> 3*lut
->ht_size
||
662 4*lut
->ht_count
+ 1 < lut
->ht_size
);
665 static unsigned int eb_batch_index(const struct i915_execbuffer
*eb
)
667 if (eb
->args
->flags
& I915_EXEC_BATCH_FIRST
)
670 return eb
->buffer_count
- 1;
673 static int eb_select_context(struct i915_execbuffer
*eb
)
675 struct i915_gem_context
*ctx
;
677 ctx
= i915_gem_context_lookup(eb
->file
->driver_priv
, eb
->args
->rsvd1
);
678 if (unlikely(IS_ERR(ctx
)))
681 if (unlikely(i915_gem_context_is_banned(ctx
))) {
682 DRM_DEBUG("Context %u tried to submit while banned\n",
687 eb
->ctx
= i915_gem_context_get(ctx
);
688 eb
->vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &eb
->i915
->ggtt
.base
;
690 eb
->context_flags
= 0;
691 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
692 eb
->context_flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
697 static int eb_lookup_vmas(struct i915_execbuffer
*eb
)
699 #define INTERMEDIATE BIT(0)
700 const unsigned int count
= eb
->buffer_count
;
701 struct i915_gem_context_vma_lut
*lut
= &eb
->ctx
->vma_lut
;
702 struct i915_vma
*vma
;
708 INIT_LIST_HEAD(&eb
->relocs
);
709 INIT_LIST_HEAD(&eb
->unbound
);
711 if (unlikely(lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
))
712 flush_work(&lut
->resize
);
713 GEM_BUG_ON(lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
);
715 for (i
= 0; i
< count
; i
++) {
716 __exec_to_vma(&eb
->exec
[i
]) = 0;
718 hlist_for_each_entry(vma
,
719 ht_head(lut
, eb
->exec
[i
].handle
),
721 if (vma
->ctx_handle
!= eb
->exec
[i
].handle
)
724 err
= eb_add_vma(eb
, &eb
->exec
[i
], vma
);
739 spin_lock(&eb
->file
->table_lock
);
741 * Grab a reference to the object and release the lock so we can lookup
742 * or create the VMA without using GFP_ATOMIC
744 idr
= &eb
->file
->object_idr
;
745 for (i
= slow_pass
; i
< count
; i
++) {
746 struct drm_i915_gem_object
*obj
;
748 if (__exec_to_vma(&eb
->exec
[i
]))
751 obj
= to_intel_bo(idr_find(idr
, eb
->exec
[i
].handle
));
752 if (unlikely(!obj
)) {
753 spin_unlock(&eb
->file
->table_lock
);
754 DRM_DEBUG("Invalid object handle %d at index %d\n",
755 eb
->exec
[i
].handle
, i
);
760 __exec_to_vma(&eb
->exec
[i
]) = INTERMEDIATE
| (uintptr_t)obj
;
762 spin_unlock(&eb
->file
->table_lock
);
764 for (i
= slow_pass
; i
< count
; i
++) {
765 struct drm_i915_gem_object
*obj
;
767 if (!(__exec_to_vma(&eb
->exec
[i
]) & INTERMEDIATE
))
771 * NOTE: We can leak any vmas created here when something fails
772 * later on. But that's no issue since vma_unbind can deal with
773 * vmas which are not actually bound. And since only
774 * lookup_or_create exists as an interface to get at the vma
775 * from the (obj, vm) we don't run the risk of creating
776 * duplicated vmas for the same vm.
778 obj
= u64_to_ptr(typeof(*obj
),
779 __exec_to_vma(&eb
->exec
[i
]) & ~INTERMEDIATE
);
780 vma
= i915_vma_instance(obj
, eb
->vm
, NULL
);
781 if (unlikely(IS_ERR(vma
))) {
782 DRM_DEBUG("Failed to lookup VMA\n");
787 /* First come, first served */
790 vma
->ctx_handle
= eb
->exec
[i
].handle
;
791 hlist_add_head(&vma
->ctx_node
,
792 ht_head(lut
, eb
->exec
[i
].handle
));
794 lut
->ht_size
|= I915_CTX_RESIZE_IN_PROGRESS
;
795 if (i915_vma_is_ggtt(vma
)) {
796 GEM_BUG_ON(obj
->vma_hashed
);
797 obj
->vma_hashed
= vma
;
803 err
= eb_add_vma(eb
, &eb
->exec
[i
], vma
);
807 /* Only after we validated the user didn't use our bits */
808 if (vma
->ctx
!= eb
->ctx
) {
810 eb
->exec
[i
].flags
|= __EXEC_OBJECT_HAS_REF
;
814 if (lut
->ht_size
& I915_CTX_RESIZE_IN_PROGRESS
) {
815 if (ht_needs_resize(lut
))
816 queue_work(system_highpri_wq
, &lut
->resize
);
818 lut
->ht_size
&= ~I915_CTX_RESIZE_IN_PROGRESS
;
822 /* take note of the batch buffer before we might reorder the lists */
823 i
= eb_batch_index(eb
);
824 eb
->batch
= exec_to_vma(&eb
->exec
[i
]);
827 * SNA is doing fancy tricks with compressing batch buffers, which leads
828 * to negative relocation deltas. Usually that works out ok since the
829 * relocate address is still positive, except when the batch is placed
830 * very low in the GTT. Ensure this doesn't happen.
832 * Note that actual hangs have only been observed on gen7, but for
833 * paranoia do it everywhere.
835 if (!(eb
->exec
[i
].flags
& EXEC_OBJECT_PINNED
))
836 eb
->exec
[i
].flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
837 if (eb
->reloc_cache
.has_fence
)
838 eb
->exec
[i
].flags
|= EXEC_OBJECT_NEEDS_FENCE
;
840 eb
->args
->flags
|= __EXEC_VALIDATED
;
841 return eb_reserve(eb
);
844 for (i
= slow_pass
; i
< count
; i
++) {
845 if (__exec_to_vma(&eb
->exec
[i
]) & INTERMEDIATE
)
846 __exec_to_vma(&eb
->exec
[i
]) = 0;
848 lut
->ht_size
&= ~I915_CTX_RESIZE_IN_PROGRESS
;
853 static struct i915_vma
*
854 eb_get_vma(const struct i915_execbuffer
*eb
, unsigned long handle
)
856 if (eb
->lut_size
< 0) {
857 if (handle
>= -eb
->lut_size
)
859 return exec_to_vma(&eb
->exec
[handle
]);
861 struct hlist_head
*head
;
862 struct i915_vma
*vma
;
864 head
= &eb
->buckets
[hash_32(handle
, eb
->lut_size
)];
865 hlist_for_each_entry(vma
, head
, exec_node
) {
866 if (vma
->exec_handle
== handle
)
873 static void eb_release_vmas(const struct i915_execbuffer
*eb
)
875 const unsigned int count
= eb
->buffer_count
;
878 for (i
= 0; i
< count
; i
++) {
879 struct drm_i915_gem_exec_object2
*entry
= &eb
->exec
[i
];
880 struct i915_vma
*vma
= exec_to_vma(entry
);
885 GEM_BUG_ON(vma
->exec_entry
!= entry
);
886 vma
->exec_entry
= NULL
;
887 __exec_to_vma(entry
) = 0;
889 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
890 __eb_unreserve_vma(vma
, entry
);
892 if (entry
->flags
& __EXEC_OBJECT_HAS_REF
)
896 ~(__EXEC_OBJECT_RESERVED
| __EXEC_OBJECT_HAS_REF
);
900 static void eb_reset_vmas(const struct i915_execbuffer
*eb
)
903 if (eb
->lut_size
> 0)
904 memset(eb
->buckets
, 0,
905 sizeof(struct hlist_head
) << eb
->lut_size
);
908 static void eb_destroy(const struct i915_execbuffer
*eb
)
910 GEM_BUG_ON(eb
->reloc_cache
.rq
);
912 if (eb
->lut_size
> 0)
917 relocation_target(const struct drm_i915_gem_relocation_entry
*reloc
,
918 const struct i915_vma
*target
)
920 return gen8_canonical_addr((int)reloc
->delta
+ target
->node
.start
);
923 static void reloc_cache_init(struct reloc_cache
*cache
,
924 struct drm_i915_private
*i915
)
928 /* Must be a variable in the struct to allow GCC to unroll. */
929 cache
->gen
= INTEL_GEN(i915
);
930 cache
->has_llc
= HAS_LLC(i915
);
931 cache
->use_64bit_reloc
= HAS_64BIT_RELOC(i915
);
932 cache
->has_fence
= cache
->gen
< 4;
933 cache
->needs_unfenced
= INTEL_INFO(i915
)->unfenced_needs_alignment
;
934 cache
->node
.allocated
= false;
939 static inline void *unmask_page(unsigned long p
)
941 return (void *)(uintptr_t)(p
& PAGE_MASK
);
944 static inline unsigned int unmask_flags(unsigned long p
)
946 return p
& ~PAGE_MASK
;
949 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
951 static inline struct i915_ggtt
*cache_to_ggtt(struct reloc_cache
*cache
)
953 struct drm_i915_private
*i915
=
954 container_of(cache
, struct i915_execbuffer
, reloc_cache
)->i915
;
958 static void reloc_gpu_flush(struct reloc_cache
*cache
)
960 GEM_BUG_ON(cache
->rq_size
>= cache
->rq
->batch
->obj
->base
.size
/ sizeof(u32
));
961 cache
->rq_cmd
[cache
->rq_size
] = MI_BATCH_BUFFER_END
;
962 i915_gem_object_unpin_map(cache
->rq
->batch
->obj
);
963 i915_gem_chipset_flush(cache
->rq
->i915
);
965 __i915_add_request(cache
->rq
, true);
969 static void reloc_cache_reset(struct reloc_cache
*cache
)
974 reloc_gpu_flush(cache
);
979 vaddr
= unmask_page(cache
->vaddr
);
980 if (cache
->vaddr
& KMAP
) {
981 if (cache
->vaddr
& CLFLUSH_AFTER
)
984 kunmap_atomic(vaddr
);
985 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object
*)cache
->node
.mm
);
988 io_mapping_unmap_atomic((void __iomem
*)vaddr
);
989 if (cache
->node
.allocated
) {
990 struct i915_ggtt
*ggtt
= cache_to_ggtt(cache
);
992 ggtt
->base
.clear_range(&ggtt
->base
,
995 drm_mm_remove_node(&cache
->node
);
997 i915_vma_unpin((struct i915_vma
*)cache
->node
.mm
);
1005 static void *reloc_kmap(struct drm_i915_gem_object
*obj
,
1006 struct reloc_cache
*cache
,
1012 kunmap_atomic(unmask_page(cache
->vaddr
));
1014 unsigned int flushes
;
1017 err
= i915_gem_obj_prepare_shmem_write(obj
, &flushes
);
1019 return ERR_PTR(err
);
1021 BUILD_BUG_ON(KMAP
& CLFLUSH_FLAGS
);
1022 BUILD_BUG_ON((KMAP
| CLFLUSH_FLAGS
) & PAGE_MASK
);
1024 cache
->vaddr
= flushes
| KMAP
;
1025 cache
->node
.mm
= (void *)obj
;
1030 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
, page
));
1031 cache
->vaddr
= unmask_flags(cache
->vaddr
) | (unsigned long)vaddr
;
1037 static void *reloc_iomap(struct drm_i915_gem_object
*obj
,
1038 struct reloc_cache
*cache
,
1041 struct i915_ggtt
*ggtt
= cache_to_ggtt(cache
);
1042 unsigned long offset
;
1046 io_mapping_unmap_atomic((void __force __iomem
*) unmask_page(cache
->vaddr
));
1048 struct i915_vma
*vma
;
1051 if (use_cpu_reloc(cache
, obj
))
1054 err
= i915_gem_object_set_to_gtt_domain(obj
, true);
1056 return ERR_PTR(err
);
1058 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1059 PIN_MAPPABLE
| PIN_NONBLOCK
);
1061 memset(&cache
->node
, 0, sizeof(cache
->node
));
1062 err
= drm_mm_insert_node_in_range
1063 (&ggtt
->base
.mm
, &cache
->node
,
1064 PAGE_SIZE
, 0, I915_COLOR_UNEVICTABLE
,
1065 0, ggtt
->mappable_end
,
1067 if (err
) /* no inactive aperture space, use cpu reloc */
1070 err
= i915_vma_put_fence(vma
);
1072 i915_vma_unpin(vma
);
1073 return ERR_PTR(err
);
1076 cache
->node
.start
= vma
->node
.start
;
1077 cache
->node
.mm
= (void *)vma
;
1081 offset
= cache
->node
.start
;
1082 if (cache
->node
.allocated
) {
1084 ggtt
->base
.insert_page(&ggtt
->base
,
1085 i915_gem_object_get_dma_address(obj
, page
),
1086 offset
, I915_CACHE_NONE
, 0);
1088 offset
+= page
<< PAGE_SHIFT
;
1091 vaddr
= (void __force
*)io_mapping_map_atomic_wc(&ggtt
->mappable
,
1094 cache
->vaddr
= (unsigned long)vaddr
;
1099 static void *reloc_vaddr(struct drm_i915_gem_object
*obj
,
1100 struct reloc_cache
*cache
,
1105 if (cache
->page
== page
) {
1106 vaddr
= unmask_page(cache
->vaddr
);
1109 if ((cache
->vaddr
& KMAP
) == 0)
1110 vaddr
= reloc_iomap(obj
, cache
, page
);
1112 vaddr
= reloc_kmap(obj
, cache
, page
);
1118 static void clflush_write32(u32
*addr
, u32 value
, unsigned int flushes
)
1120 if (unlikely(flushes
& (CLFLUSH_BEFORE
| CLFLUSH_AFTER
))) {
1121 if (flushes
& CLFLUSH_BEFORE
) {
1129 * Writes to the same cacheline are serialised by the CPU
1130 * (including clflush). On the write path, we only require
1131 * that it hits memory in an orderly fashion and place
1132 * mb barriers at the start and end of the relocation phase
1133 * to ensure ordering of clflush wrt to the system.
1135 if (flushes
& CLFLUSH_AFTER
)
1141 static int __reloc_gpu_alloc(struct i915_execbuffer
*eb
,
1142 struct i915_vma
*vma
,
1145 struct reloc_cache
*cache
= &eb
->reloc_cache
;
1146 struct drm_i915_gem_object
*obj
;
1147 struct drm_i915_gem_request
*rq
;
1148 struct i915_vma
*batch
;
1152 GEM_BUG_ON(vma
->obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
);
1154 obj
= i915_gem_batch_pool_get(&eb
->engine
->batch_pool
, PAGE_SIZE
);
1156 return PTR_ERR(obj
);
1158 cmd
= i915_gem_object_pin_map(obj
,
1159 cache
->has_llc
? I915_MAP_WB
: I915_MAP_WC
);
1160 i915_gem_object_unpin_pages(obj
);
1162 return PTR_ERR(cmd
);
1164 err
= i915_gem_object_set_to_wc_domain(obj
, false);
1168 batch
= i915_vma_instance(obj
, vma
->vm
, NULL
);
1169 if (IS_ERR(batch
)) {
1170 err
= PTR_ERR(batch
);
1174 err
= i915_vma_pin(batch
, 0, 0, PIN_USER
| PIN_NONBLOCK
);
1178 rq
= i915_gem_request_alloc(eb
->engine
, eb
->ctx
);
1184 err
= i915_gem_request_await_object(rq
, vma
->obj
, true);
1188 err
= eb
->engine
->emit_flush(rq
, EMIT_INVALIDATE
);
1192 err
= i915_switch_context(rq
);
1196 err
= eb
->engine
->emit_bb_start(rq
,
1197 batch
->node
.start
, PAGE_SIZE
,
1198 cache
->gen
> 5 ? 0 : I915_DISPATCH_SECURE
);
1202 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch
->resv
, true));
1203 i915_vma_move_to_active(batch
, rq
, 0);
1204 reservation_object_lock(batch
->resv
, NULL
);
1205 reservation_object_add_excl_fence(batch
->resv
, &rq
->fence
);
1206 reservation_object_unlock(batch
->resv
);
1207 i915_vma_unpin(batch
);
1209 i915_vma_move_to_active(vma
, rq
, EXEC_OBJECT_WRITE
);
1210 reservation_object_lock(vma
->resv
, NULL
);
1211 reservation_object_add_excl_fence(vma
->resv
, &rq
->fence
);
1212 reservation_object_unlock(vma
->resv
);
1217 cache
->rq_cmd
= cmd
;
1220 /* Return with batch mapping (cmd) still pinned */
1224 i915_add_request(rq
);
1226 i915_vma_unpin(batch
);
1228 i915_gem_object_unpin_map(obj
);
1232 static u32
*reloc_gpu(struct i915_execbuffer
*eb
,
1233 struct i915_vma
*vma
,
1236 struct reloc_cache
*cache
= &eb
->reloc_cache
;
1239 if (cache
->rq_size
> PAGE_SIZE
/sizeof(u32
) - (len
+ 1))
1240 reloc_gpu_flush(cache
);
1242 if (unlikely(!cache
->rq
)) {
1245 err
= __reloc_gpu_alloc(eb
, vma
, len
);
1247 return ERR_PTR(err
);
1250 cmd
= cache
->rq_cmd
+ cache
->rq_size
;
1251 cache
->rq_size
+= len
;
1257 relocate_entry(struct i915_vma
*vma
,
1258 const struct drm_i915_gem_relocation_entry
*reloc
,
1259 struct i915_execbuffer
*eb
,
1260 const struct i915_vma
*target
)
1262 u64 offset
= reloc
->offset
;
1263 u64 target_offset
= relocation_target(reloc
, target
);
1264 bool wide
= eb
->reloc_cache
.use_64bit_reloc
;
1267 if (!eb
->reloc_cache
.vaddr
&&
1268 (DBG_FORCE_RELOC
== FORCE_GPU_RELOC
||
1269 !reservation_object_test_signaled_rcu(vma
->resv
, true))) {
1270 const unsigned int gen
= eb
->reloc_cache
.gen
;
1276 len
= offset
& 7 ? 8 : 5;
1281 else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */
1284 batch
= reloc_gpu(eb
, vma
, len
);
1288 addr
= gen8_canonical_addr(vma
->node
.start
+ offset
);
1291 *batch
++ = MI_STORE_DWORD_IMM_GEN4
;
1292 *batch
++ = lower_32_bits(addr
);
1293 *batch
++ = upper_32_bits(addr
);
1294 *batch
++ = lower_32_bits(target_offset
);
1296 addr
= gen8_canonical_addr(addr
+ 4);
1298 *batch
++ = MI_STORE_DWORD_IMM_GEN4
;
1299 *batch
++ = lower_32_bits(addr
);
1300 *batch
++ = upper_32_bits(addr
);
1301 *batch
++ = upper_32_bits(target_offset
);
1303 *batch
++ = (MI_STORE_DWORD_IMM_GEN4
| (1 << 21)) + 1;
1304 *batch
++ = lower_32_bits(addr
);
1305 *batch
++ = upper_32_bits(addr
);
1306 *batch
++ = lower_32_bits(target_offset
);
1307 *batch
++ = upper_32_bits(target_offset
);
1309 } else if (gen
>= 6) {
1310 *batch
++ = MI_STORE_DWORD_IMM_GEN4
;
1313 *batch
++ = target_offset
;
1314 } else if (gen
>= 4) {
1315 *batch
++ = MI_STORE_DWORD_IMM_GEN4
| MI_USE_GGTT
;
1318 *batch
++ = target_offset
;
1320 *batch
++ = MI_STORE_DWORD_IMM
| MI_MEM_VIRTUAL
;
1322 *batch
++ = target_offset
;
1329 vaddr
= reloc_vaddr(vma
->obj
, &eb
->reloc_cache
, offset
>> PAGE_SHIFT
);
1331 return PTR_ERR(vaddr
);
1333 clflush_write32(vaddr
+ offset_in_page(offset
),
1334 lower_32_bits(target_offset
),
1335 eb
->reloc_cache
.vaddr
);
1338 offset
+= sizeof(u32
);
1339 target_offset
>>= 32;
1345 return target
->node
.start
| UPDATE
;
1349 eb_relocate_entry(struct i915_execbuffer
*eb
,
1350 struct i915_vma
*vma
,
1351 const struct drm_i915_gem_relocation_entry
*reloc
)
1353 struct i915_vma
*target
;
1356 /* we've already hold a reference to all valid objects */
1357 target
= eb_get_vma(eb
, reloc
->target_handle
);
1358 if (unlikely(!target
))
1361 /* Validate that the target is in a valid r/w GPU domain */
1362 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
1363 DRM_DEBUG("reloc with multiple write domains: "
1364 "target %d offset %d "
1365 "read %08x write %08x",
1366 reloc
->target_handle
,
1367 (int) reloc
->offset
,
1368 reloc
->read_domains
,
1369 reloc
->write_domain
);
1372 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
1373 & ~I915_GEM_GPU_DOMAINS
)) {
1374 DRM_DEBUG("reloc with read/write non-GPU domains: "
1375 "target %d offset %d "
1376 "read %08x write %08x",
1377 reloc
->target_handle
,
1378 (int) reloc
->offset
,
1379 reloc
->read_domains
,
1380 reloc
->write_domain
);
1384 if (reloc
->write_domain
) {
1385 target
->exec_entry
->flags
|= EXEC_OBJECT_WRITE
;
1388 * Sandybridge PPGTT errata: We need a global gtt mapping
1389 * for MI and pipe_control writes because the gpu doesn't
1390 * properly redirect them through the ppgtt for non_secure
1393 if (reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
1394 IS_GEN6(eb
->i915
)) {
1395 err
= i915_vma_bind(target
, target
->obj
->cache_level
,
1398 "Unexpected failure to bind target VMA!"))
1404 * If the relocation already has the right value in it, no
1405 * more work needs to be done.
1407 if (!DBG_FORCE_RELOC
&&
1408 gen8_canonical_addr(target
->node
.start
) == reloc
->presumed_offset
)
1411 /* Check that the relocation address is valid... */
1412 if (unlikely(reloc
->offset
>
1413 vma
->size
- (eb
->reloc_cache
.use_64bit_reloc
? 8 : 4))) {
1414 DRM_DEBUG("Relocation beyond object bounds: "
1415 "target %d offset %d size %d.\n",
1416 reloc
->target_handle
,
1421 if (unlikely(reloc
->offset
& 3)) {
1422 DRM_DEBUG("Relocation not 4-byte aligned: "
1423 "target %d offset %d.\n",
1424 reloc
->target_handle
,
1425 (int)reloc
->offset
);
1430 * If we write into the object, we need to force the synchronisation
1431 * barrier, either with an asynchronous clflush or if we executed the
1432 * patching using the GPU (though that should be serialised by the
1433 * timeline). To be completely sure, and since we are required to
1434 * do relocations we are already stalling, disable the user's opt
1435 * of our synchronisation.
1437 vma
->exec_entry
->flags
&= ~EXEC_OBJECT_ASYNC
;
1439 /* and update the user's relocation entry */
1440 return relocate_entry(vma
, reloc
, eb
, target
);
1443 static int eb_relocate_vma(struct i915_execbuffer
*eb
, struct i915_vma
*vma
)
1445 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1446 struct drm_i915_gem_relocation_entry stack
[N_RELOC(512)];
1447 struct drm_i915_gem_relocation_entry __user
*urelocs
;
1448 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
1449 unsigned int remain
;
1451 urelocs
= u64_to_user_ptr(entry
->relocs_ptr
);
1452 remain
= entry
->relocation_count
;
1453 if (unlikely(remain
> N_RELOC(ULONG_MAX
)))
1457 * We must check that the entire relocation array is safe
1458 * to read. However, if the array is not writable the user loses
1459 * the updated relocation values.
1461 if (unlikely(!access_ok(VERIFY_READ
, urelocs
, remain
*sizeof(urelocs
))))
1465 struct drm_i915_gem_relocation_entry
*r
= stack
;
1466 unsigned int count
=
1467 min_t(unsigned int, remain
, ARRAY_SIZE(stack
));
1468 unsigned int copied
;
1471 * This is the fast path and we cannot handle a pagefault
1472 * whilst holding the struct mutex lest the user pass in the
1473 * relocations contained within a mmaped bo. For in such a case
1474 * we, the page fault handler would call i915_gem_fault() and
1475 * we would try to acquire the struct mutex again. Obviously
1476 * this is bad and so lockdep complains vehemently.
1478 pagefault_disable();
1479 copied
= __copy_from_user_inatomic(r
, urelocs
, count
* sizeof(r
[0]));
1481 if (unlikely(copied
)) {
1488 u64 offset
= eb_relocate_entry(eb
, vma
, r
);
1490 if (likely(offset
== 0)) {
1491 } else if ((s64
)offset
< 0) {
1492 remain
= (int)offset
;
1496 * Note that reporting an error now
1497 * leaves everything in an inconsistent
1498 * state as we have *already* changed
1499 * the relocation value inside the
1500 * object. As we have not changed the
1501 * reloc.presumed_offset or will not
1502 * change the execobject.offset, on the
1503 * call we may not rewrite the value
1504 * inside the object, leaving it
1505 * dangling and causing a GPU hang. Unless
1506 * userspace dynamically rebuilds the
1507 * relocations on each execbuf rather than
1508 * presume a static tree.
1510 * We did previously check if the relocations
1511 * were writable (access_ok), an error now
1512 * would be a strange race with mprotect,
1513 * having already demonstrated that we
1514 * can read from this userspace address.
1516 offset
= gen8_canonical_addr(offset
& ~UPDATE
);
1518 &urelocs
[r
-stack
].presumed_offset
);
1520 } while (r
++, --count
);
1521 urelocs
+= ARRAY_SIZE(stack
);
1524 reloc_cache_reset(&eb
->reloc_cache
);
1529 eb_relocate_vma_slow(struct i915_execbuffer
*eb
, struct i915_vma
*vma
)
1531 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
1532 struct drm_i915_gem_relocation_entry
*relocs
=
1533 u64_to_ptr(typeof(*relocs
), entry
->relocs_ptr
);
1537 for (i
= 0; i
< entry
->relocation_count
; i
++) {
1538 u64 offset
= eb_relocate_entry(eb
, vma
, &relocs
[i
]);
1540 if ((s64
)offset
< 0) {
1547 reloc_cache_reset(&eb
->reloc_cache
);
1551 static int check_relocations(const struct drm_i915_gem_exec_object2
*entry
)
1553 const char __user
*addr
, *end
;
1555 char __maybe_unused c
;
1557 size
= entry
->relocation_count
;
1561 if (size
> N_RELOC(ULONG_MAX
))
1564 addr
= u64_to_user_ptr(entry
->relocs_ptr
);
1565 size
*= sizeof(struct drm_i915_gem_relocation_entry
);
1566 if (!access_ok(VERIFY_READ
, addr
, size
))
1570 for (; addr
< end
; addr
+= PAGE_SIZE
) {
1571 int err
= __get_user(c
, addr
);
1575 return __get_user(c
, end
- 1);
1578 static int eb_copy_relocations(const struct i915_execbuffer
*eb
)
1580 const unsigned int count
= eb
->buffer_count
;
1584 for (i
= 0; i
< count
; i
++) {
1585 const unsigned int nreloc
= eb
->exec
[i
].relocation_count
;
1586 struct drm_i915_gem_relocation_entry __user
*urelocs
;
1587 struct drm_i915_gem_relocation_entry
*relocs
;
1589 unsigned long copied
;
1594 err
= check_relocations(&eb
->exec
[i
]);
1598 urelocs
= u64_to_user_ptr(eb
->exec
[i
].relocs_ptr
);
1599 size
= nreloc
* sizeof(*relocs
);
1601 relocs
= kvmalloc_array(size
, 1, GFP_TEMPORARY
);
1608 /* copy_from_user is limited to < 4GiB */
1612 min_t(u64
, BIT_ULL(31), size
- copied
);
1614 if (__copy_from_user((char *)relocs
+ copied
,
1615 (char *)urelocs
+ copied
,
1623 } while (copied
< size
);
1626 * As we do not update the known relocation offsets after
1627 * relocating (due to the complexities in lock handling),
1628 * we need to mark them as invalid now so that we force the
1629 * relocation processing next time. Just in case the target
1630 * object is evicted and then rebound into its old
1631 * presumed_offset before the next execbuffer - if that
1632 * happened we would make the mistake of assuming that the
1633 * relocations were valid.
1635 user_access_begin();
1636 for (copied
= 0; copied
< nreloc
; copied
++)
1638 &urelocs
[copied
].presumed_offset
,
1643 eb
->exec
[i
].relocs_ptr
= (uintptr_t)relocs
;
1650 struct drm_i915_gem_relocation_entry
*relocs
=
1651 u64_to_ptr(typeof(*relocs
), eb
->exec
[i
].relocs_ptr
);
1652 if (eb
->exec
[i
].relocation_count
)
1658 static int eb_prefault_relocations(const struct i915_execbuffer
*eb
)
1660 const unsigned int count
= eb
->buffer_count
;
1663 if (unlikely(i915
.prefault_disable
))
1666 for (i
= 0; i
< count
; i
++) {
1669 err
= check_relocations(&eb
->exec
[i
]);
1677 static noinline
int eb_relocate_slow(struct i915_execbuffer
*eb
)
1679 struct drm_device
*dev
= &eb
->i915
->drm
;
1680 bool have_copy
= false;
1681 struct i915_vma
*vma
;
1685 if (signal_pending(current
)) {
1690 /* We may process another execbuffer during the unlock... */
1692 mutex_unlock(&dev
->struct_mutex
);
1695 * We take 3 passes through the slowpatch.
1697 * 1 - we try to just prefault all the user relocation entries and
1698 * then attempt to reuse the atomic pagefault disabled fast path again.
1700 * 2 - we copy the user entries to a local buffer here outside of the
1701 * local and allow ourselves to wait upon any rendering before
1704 * 3 - we already have a local copy of the relocation entries, but
1705 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1708 err
= eb_prefault_relocations(eb
);
1709 } else if (!have_copy
) {
1710 err
= eb_copy_relocations(eb
);
1711 have_copy
= err
== 0;
1717 mutex_lock(&dev
->struct_mutex
);
1721 /* A frequent cause for EAGAIN are currently unavailable client pages */
1722 flush_workqueue(eb
->i915
->mm
.userptr_wq
);
1724 err
= i915_mutex_lock_interruptible(dev
);
1726 mutex_lock(&dev
->struct_mutex
);
1730 /* reacquire the objects */
1731 err
= eb_lookup_vmas(eb
);
1735 list_for_each_entry(vma
, &eb
->relocs
, reloc_link
) {
1737 pagefault_disable();
1738 err
= eb_relocate_vma(eb
, vma
);
1743 err
= eb_relocate_vma_slow(eb
, vma
);
1750 * Leave the user relocations as are, this is the painfully slow path,
1751 * and we want to avoid the complication of dropping the lock whilst
1752 * having buffers reserved in the aperture and so causing spurious
1753 * ENOSPC for random operations.
1762 const unsigned int count
= eb
->buffer_count
;
1765 for (i
= 0; i
< count
; i
++) {
1766 const struct drm_i915_gem_exec_object2
*entry
=
1768 struct drm_i915_gem_relocation_entry
*relocs
;
1770 if (!entry
->relocation_count
)
1773 relocs
= u64_to_ptr(typeof(*relocs
), entry
->relocs_ptr
);
1778 return err
?: have_copy
;
1781 static int eb_relocate(struct i915_execbuffer
*eb
)
1783 if (eb_lookup_vmas(eb
))
1786 /* The objects are in their final locations, apply the relocations. */
1787 if (eb
->args
->flags
& __EXEC_HAS_RELOC
) {
1788 struct i915_vma
*vma
;
1790 list_for_each_entry(vma
, &eb
->relocs
, reloc_link
) {
1791 if (eb_relocate_vma(eb
, vma
))
1799 return eb_relocate_slow(eb
);
1802 static void eb_export_fence(struct i915_vma
*vma
,
1803 struct drm_i915_gem_request
*req
,
1806 struct reservation_object
*resv
= vma
->resv
;
1809 * Ignore errors from failing to allocate the new fence, we can't
1810 * handle an error right now. Worst case should be missed
1811 * synchronisation leading to rendering corruption.
1813 reservation_object_lock(resv
, NULL
);
1814 if (flags
& EXEC_OBJECT_WRITE
)
1815 reservation_object_add_excl_fence(resv
, &req
->fence
);
1816 else if (reservation_object_reserve_shared(resv
) == 0)
1817 reservation_object_add_shared_fence(resv
, &req
->fence
);
1818 reservation_object_unlock(resv
);
1821 static int eb_move_to_gpu(struct i915_execbuffer
*eb
)
1823 const unsigned int count
= eb
->buffer_count
;
1827 for (i
= 0; i
< count
; i
++) {
1828 const struct drm_i915_gem_exec_object2
*entry
= &eb
->exec
[i
];
1829 struct i915_vma
*vma
= exec_to_vma(entry
);
1830 struct drm_i915_gem_object
*obj
= vma
->obj
;
1832 if (entry
->flags
& EXEC_OBJECT_CAPTURE
) {
1833 struct i915_gem_capture_list
*capture
;
1835 capture
= kmalloc(sizeof(*capture
), GFP_KERNEL
);
1836 if (unlikely(!capture
))
1839 capture
->next
= eb
->request
->capture_list
;
1841 eb
->request
->capture_list
= capture
;
1844 if (entry
->flags
& EXEC_OBJECT_ASYNC
)
1847 if (unlikely(obj
->cache_dirty
&& !obj
->cache_coherent
))
1848 i915_gem_clflush_object(obj
, 0);
1850 err
= i915_gem_request_await_object
1851 (eb
->request
, obj
, entry
->flags
& EXEC_OBJECT_WRITE
);
1856 i915_vma_move_to_active(vma
, eb
->request
, entry
->flags
);
1857 __eb_unreserve_vma(vma
, entry
);
1858 vma
->exec_entry
= NULL
;
1861 for (i
= 0; i
< count
; i
++) {
1862 const struct drm_i915_gem_exec_object2
*entry
= &eb
->exec
[i
];
1863 struct i915_vma
*vma
= exec_to_vma(entry
);
1865 eb_export_fence(vma
, eb
->request
, entry
->flags
);
1866 if (unlikely(entry
->flags
& __EXEC_OBJECT_HAS_REF
))
1871 /* Unconditionally flush any chipset caches (for streaming writes). */
1872 i915_gem_chipset_flush(eb
->i915
);
1874 /* Unconditionally invalidate GPU caches and TLBs. */
1875 return eb
->engine
->emit_flush(eb
->request
, EMIT_INVALIDATE
);
1878 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
1880 if (exec
->flags
& __I915_EXEC_ILLEGAL_FLAGS
)
1883 /* Kernel clipping was a DRI1 misfeature */
1884 if (exec
->num_cliprects
|| exec
->cliprects_ptr
)
1887 if (exec
->DR4
== 0xffffffff) {
1888 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1891 if (exec
->DR1
|| exec
->DR4
)
1894 if ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7)
1900 void i915_vma_move_to_active(struct i915_vma
*vma
,
1901 struct drm_i915_gem_request
*req
,
1904 struct drm_i915_gem_object
*obj
= vma
->obj
;
1905 const unsigned int idx
= req
->engine
->id
;
1907 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
1908 GEM_BUG_ON(!drm_mm_node_allocated(&vma
->node
));
1911 * Add a reference if we're newly entering the active list.
1912 * The order in which we add operations to the retirement queue is
1913 * vital here: mark_active adds to the start of the callback list,
1914 * such that subsequent callbacks are called first. Therefore we
1915 * add the active reference first and queue for it to be dropped
1918 if (!i915_vma_is_active(vma
))
1919 obj
->active_count
++;
1920 i915_vma_set_active(vma
, idx
);
1921 i915_gem_active_set(&vma
->last_read
[idx
], req
);
1922 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
1924 obj
->base
.write_domain
= 0;
1925 if (flags
& EXEC_OBJECT_WRITE
) {
1926 obj
->base
.write_domain
= I915_GEM_DOMAIN_RENDER
;
1928 if (intel_fb_obj_invalidate(obj
, ORIGIN_CS
))
1929 i915_gem_active_set(&obj
->frontbuffer_write
, req
);
1931 obj
->base
.read_domains
= 0;
1933 obj
->base
.read_domains
|= I915_GEM_GPU_DOMAINS
;
1935 if (flags
& EXEC_OBJECT_NEEDS_FENCE
)
1936 i915_gem_active_set(&vma
->last_fence
, req
);
1939 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request
*req
)
1944 if (!IS_GEN7(req
->i915
) || req
->engine
->id
!= RCS
) {
1945 DRM_DEBUG("sol reset is gen7/rcs only\n");
1949 cs
= intel_ring_begin(req
, 4 * 2 + 2);
1953 *cs
++ = MI_LOAD_REGISTER_IMM(4);
1954 for (i
= 0; i
< 4; i
++) {
1955 *cs
++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i
));
1959 intel_ring_advance(req
, cs
);
1964 static struct i915_vma
*eb_parse(struct i915_execbuffer
*eb
, bool is_master
)
1966 struct drm_i915_gem_object
*shadow_batch_obj
;
1967 struct i915_vma
*vma
;
1970 shadow_batch_obj
= i915_gem_batch_pool_get(&eb
->engine
->batch_pool
,
1971 PAGE_ALIGN(eb
->batch_len
));
1972 if (IS_ERR(shadow_batch_obj
))
1973 return ERR_CAST(shadow_batch_obj
);
1975 err
= intel_engine_cmd_parser(eb
->engine
,
1978 eb
->batch_start_offset
,
1982 if (err
== -EACCES
) /* unhandled chained batch */
1989 vma
= i915_gem_object_ggtt_pin(shadow_batch_obj
, NULL
, 0, 0, 0);
1994 memset(&eb
->exec
[eb
->buffer_count
++],
1995 0, sizeof(*vma
->exec_entry
));
1996 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
| __EXEC_OBJECT_HAS_REF
;
1997 __exec_to_vma(vma
->exec_entry
) = (uintptr_t)i915_vma_get(vma
);
2000 i915_gem_object_unpin_pages(shadow_batch_obj
);
2005 add_to_client(struct drm_i915_gem_request
*req
, struct drm_file
*file
)
2007 req
->file_priv
= file
->driver_priv
;
2008 list_add_tail(&req
->client_link
, &req
->file_priv
->mm
.request_list
);
2011 static int eb_submit(struct i915_execbuffer
*eb
)
2015 err
= eb_move_to_gpu(eb
);
2019 err
= i915_switch_context(eb
->request
);
2023 if (eb
->args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
2024 err
= i915_reset_gen7_sol_offsets(eb
->request
);
2029 err
= eb
->engine
->emit_bb_start(eb
->request
,
2030 eb
->batch
->node
.start
+
2031 eb
->batch_start_offset
,
2041 * Find one BSD ring to dispatch the corresponding BSD command.
2042 * The engine index is returned.
2045 gen8_dispatch_bsd_engine(struct drm_i915_private
*dev_priv
,
2046 struct drm_file
*file
)
2048 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2050 /* Check whether the file_priv has already selected one ring. */
2051 if ((int)file_priv
->bsd_engine
< 0)
2052 file_priv
->bsd_engine
= atomic_fetch_xor(1,
2053 &dev_priv
->mm
.bsd_engine_dispatch_index
);
2055 return file_priv
->bsd_engine
;
2058 #define I915_USER_RINGS (4)
2060 static const enum intel_engine_id user_ring_map
[I915_USER_RINGS
+ 1] = {
2061 [I915_EXEC_DEFAULT
] = RCS
,
2062 [I915_EXEC_RENDER
] = RCS
,
2063 [I915_EXEC_BLT
] = BCS
,
2064 [I915_EXEC_BSD
] = VCS
,
2065 [I915_EXEC_VEBOX
] = VECS
2068 static struct intel_engine_cs
*
2069 eb_select_engine(struct drm_i915_private
*dev_priv
,
2070 struct drm_file
*file
,
2071 struct drm_i915_gem_execbuffer2
*args
)
2073 unsigned int user_ring_id
= args
->flags
& I915_EXEC_RING_MASK
;
2074 struct intel_engine_cs
*engine
;
2076 if (user_ring_id
> I915_USER_RINGS
) {
2077 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id
);
2081 if ((user_ring_id
!= I915_EXEC_BSD
) &&
2082 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
2083 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2084 "bsd dispatch flags: %d\n", (int)(args
->flags
));
2088 if (user_ring_id
== I915_EXEC_BSD
&& HAS_BSD2(dev_priv
)) {
2089 unsigned int bsd_idx
= args
->flags
& I915_EXEC_BSD_MASK
;
2091 if (bsd_idx
== I915_EXEC_BSD_DEFAULT
) {
2092 bsd_idx
= gen8_dispatch_bsd_engine(dev_priv
, file
);
2093 } else if (bsd_idx
>= I915_EXEC_BSD_RING1
&&
2094 bsd_idx
<= I915_EXEC_BSD_RING2
) {
2095 bsd_idx
>>= I915_EXEC_BSD_SHIFT
;
2098 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2103 engine
= dev_priv
->engine
[_VCS(bsd_idx
)];
2105 engine
= dev_priv
->engine
[user_ring_map
[user_ring_id
]];
2109 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id
);
2117 i915_gem_do_execbuffer(struct drm_device
*dev
,
2118 struct drm_file
*file
,
2119 struct drm_i915_gem_execbuffer2
*args
,
2120 struct drm_i915_gem_exec_object2
*exec
)
2122 struct i915_execbuffer eb
;
2123 struct dma_fence
*in_fence
= NULL
;
2124 struct sync_file
*out_fence
= NULL
;
2125 int out_fence_fd
= -1;
2128 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS
&
2129 ~__EXEC_OBJECT_UNKNOWN_FLAGS
);
2131 eb
.i915
= to_i915(dev
);
2134 if (DBG_FORCE_RELOC
|| !(args
->flags
& I915_EXEC_NO_RELOC
))
2135 args
->flags
|= __EXEC_HAS_RELOC
;
2138 eb
.invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
2139 if (USES_FULL_PPGTT(eb
.i915
))
2140 eb
.invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
2141 reloc_cache_init(&eb
.reloc_cache
, eb
.i915
);
2143 eb
.buffer_count
= args
->buffer_count
;
2144 eb
.batch_start_offset
= args
->batch_start_offset
;
2145 eb
.batch_len
= args
->batch_len
;
2148 if (args
->flags
& I915_EXEC_SECURE
) {
2149 if (!drm_is_current_master(file
) || !capable(CAP_SYS_ADMIN
))
2152 eb
.batch_flags
|= I915_DISPATCH_SECURE
;
2154 if (args
->flags
& I915_EXEC_IS_PINNED
)
2155 eb
.batch_flags
|= I915_DISPATCH_PINNED
;
2157 eb
.engine
= eb_select_engine(eb
.i915
, file
, args
);
2161 if (args
->flags
& I915_EXEC_RESOURCE_STREAMER
) {
2162 if (!HAS_RESOURCE_STREAMER(eb
.i915
)) {
2163 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2166 if (eb
.engine
->id
!= RCS
) {
2167 DRM_DEBUG("RS is not available on %s\n",
2172 eb
.batch_flags
|= I915_DISPATCH_RS
;
2175 if (args
->flags
& I915_EXEC_FENCE_IN
) {
2176 in_fence
= sync_file_get_fence(lower_32_bits(args
->rsvd2
));
2181 if (args
->flags
& I915_EXEC_FENCE_OUT
) {
2182 out_fence_fd
= get_unused_fd_flags(O_CLOEXEC
);
2183 if (out_fence_fd
< 0) {
2189 err
= eb_create(&eb
);
2193 GEM_BUG_ON(!eb
.lut_size
);
2196 * Take a local wakeref for preparing to dispatch the execbuf as
2197 * we expect to access the hardware fairly frequently in the
2198 * process. Upon first dispatch, we acquire another prolonged
2199 * wakeref that we hold until the GPU has been idle for at least
2202 intel_runtime_pm_get(eb
.i915
);
2203 err
= i915_mutex_lock_interruptible(dev
);
2207 err
= eb_select_context(&eb
);
2211 err
= eb_relocate(&eb
);
2214 * If the user expects the execobject.offset and
2215 * reloc.presumed_offset to be an exact match,
2216 * as for using NO_RELOC, then we cannot update
2217 * the execobject.offset until we have completed
2220 args
->flags
&= ~__EXEC_HAS_RELOC
;
2224 if (unlikely(eb
.batch
->exec_entry
->flags
& EXEC_OBJECT_WRITE
)) {
2225 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2229 if (eb
.batch_start_offset
> eb
.batch
->size
||
2230 eb
.batch_len
> eb
.batch
->size
- eb
.batch_start_offset
) {
2231 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2236 if (eb
.engine
->needs_cmd_parser
&& eb
.batch_len
) {
2237 struct i915_vma
*vma
;
2239 vma
= eb_parse(&eb
, drm_is_current_master(file
));
2247 * Batch parsed and accepted:
2249 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2250 * bit from MI_BATCH_BUFFER_START commands issued in
2251 * the dispatch_execbuffer implementations. We
2252 * specifically don't want that set on batches the
2253 * command parser has accepted.
2255 eb
.batch_flags
|= I915_DISPATCH_SECURE
;
2256 eb
.batch_start_offset
= 0;
2261 if (eb
.batch_len
== 0)
2262 eb
.batch_len
= eb
.batch
->size
- eb
.batch_start_offset
;
2265 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2266 * batch" bit. Hence we need to pin secure batches into the global gtt.
2267 * hsw should have this fixed, but bdw mucks it up again. */
2268 if (eb
.batch_flags
& I915_DISPATCH_SECURE
) {
2269 struct i915_vma
*vma
;
2272 * So on first glance it looks freaky that we pin the batch here
2273 * outside of the reservation loop. But:
2274 * - The batch is already pinned into the relevant ppgtt, so we
2275 * already have the backing storage fully allocated.
2276 * - No other BO uses the global gtt (well contexts, but meh),
2277 * so we don't really have issues with multiple objects not
2278 * fitting due to fragmentation.
2279 * So this is actually safe.
2281 vma
= i915_gem_object_ggtt_pin(eb
.batch
->obj
, NULL
, 0, 0, 0);
2290 /* All GPU relocation batches must be submitted prior to the user rq */
2291 GEM_BUG_ON(eb
.reloc_cache
.rq
);
2293 /* Allocate a request for this batch buffer nice and early. */
2294 eb
.request
= i915_gem_request_alloc(eb
.engine
, eb
.ctx
);
2295 if (IS_ERR(eb
.request
)) {
2296 err
= PTR_ERR(eb
.request
);
2297 goto err_batch_unpin
;
2301 err
= i915_gem_request_await_dma_fence(eb
.request
, in_fence
);
2306 if (out_fence_fd
!= -1) {
2307 out_fence
= sync_file_create(&eb
.request
->fence
);
2315 * Whilst this request exists, batch_obj will be on the
2316 * active_list, and so will hold the active reference. Only when this
2317 * request is retired will the the batch_obj be moved onto the
2318 * inactive_list and lose its active reference. Hence we do not need
2319 * to explicitly hold another reference here.
2321 eb
.request
->batch
= eb
.batch
;
2323 trace_i915_gem_request_queue(eb
.request
, eb
.batch_flags
);
2324 err
= eb_submit(&eb
);
2326 __i915_add_request(eb
.request
, err
== 0);
2327 add_to_client(eb
.request
, file
);
2331 fd_install(out_fence_fd
, out_fence
->file
);
2332 args
->rsvd2
&= GENMASK_ULL(0, 31); /* keep in-fence */
2333 args
->rsvd2
|= (u64
)out_fence_fd
<< 32;
2336 fput(out_fence
->file
);
2341 if (eb
.batch_flags
& I915_DISPATCH_SECURE
)
2342 i915_vma_unpin(eb
.batch
);
2345 eb_release_vmas(&eb
);
2346 i915_gem_context_put(eb
.ctx
);
2348 mutex_unlock(&dev
->struct_mutex
);
2350 intel_runtime_pm_put(eb
.i915
);
2353 if (out_fence_fd
!= -1)
2354 put_unused_fd(out_fence_fd
);
2356 dma_fence_put(in_fence
);
2361 * Legacy execbuffer just creates an exec2 list from the original exec object
2362 * list array and passes it to the real function.
2365 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2366 struct drm_file
*file
)
2368 const size_t sz
= sizeof(struct drm_i915_gem_exec_object2
);
2369 struct drm_i915_gem_execbuffer
*args
= data
;
2370 struct drm_i915_gem_execbuffer2 exec2
;
2371 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
2372 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
2376 if (args
->buffer_count
< 1 || args
->buffer_count
> SIZE_MAX
/ sz
- 1) {
2377 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
2381 exec2
.buffers_ptr
= args
->buffers_ptr
;
2382 exec2
.buffer_count
= args
->buffer_count
;
2383 exec2
.batch_start_offset
= args
->batch_start_offset
;
2384 exec2
.batch_len
= args
->batch_len
;
2385 exec2
.DR1
= args
->DR1
;
2386 exec2
.DR4
= args
->DR4
;
2387 exec2
.num_cliprects
= args
->num_cliprects
;
2388 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
2389 exec2
.flags
= I915_EXEC_RENDER
;
2390 i915_execbuffer2_set_context_id(exec2
, 0);
2392 if (!i915_gem_check_execbuffer(&exec2
))
2395 /* Copy in the exec list from userland */
2396 exec_list
= kvmalloc_array(args
->buffer_count
, sizeof(*exec_list
),
2397 __GFP_NOWARN
| GFP_TEMPORARY
);
2398 exec2_list
= kvmalloc_array(args
->buffer_count
+ 1, sz
,
2399 __GFP_NOWARN
| GFP_TEMPORARY
);
2400 if (exec_list
== NULL
|| exec2_list
== NULL
) {
2401 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2402 args
->buffer_count
);
2407 err
= copy_from_user(exec_list
,
2408 u64_to_user_ptr(args
->buffers_ptr
),
2409 sizeof(*exec_list
) * args
->buffer_count
);
2411 DRM_DEBUG("copy %d exec entries failed %d\n",
2412 args
->buffer_count
, err
);
2418 for (i
= 0; i
< args
->buffer_count
; i
++) {
2419 exec2_list
[i
].handle
= exec_list
[i
].handle
;
2420 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
2421 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
2422 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
2423 exec2_list
[i
].offset
= exec_list
[i
].offset
;
2424 if (INTEL_GEN(to_i915(dev
)) < 4)
2425 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
2427 exec2_list
[i
].flags
= 0;
2430 err
= i915_gem_do_execbuffer(dev
, file
, &exec2
, exec2_list
);
2431 if (exec2
.flags
& __EXEC_HAS_RELOC
) {
2432 struct drm_i915_gem_exec_object __user
*user_exec_list
=
2433 u64_to_user_ptr(args
->buffers_ptr
);
2435 /* Copy the new buffer offsets back to the user's exec list. */
2436 for (i
= 0; i
< args
->buffer_count
; i
++) {
2437 if (!(exec2_list
[i
].offset
& UPDATE
))
2440 exec2_list
[i
].offset
=
2441 gen8_canonical_addr(exec2_list
[i
].offset
& PIN_OFFSET_MASK
);
2442 exec2_list
[i
].offset
&= PIN_OFFSET_MASK
;
2443 if (__copy_to_user(&user_exec_list
[i
].offset
,
2444 &exec2_list
[i
].offset
,
2445 sizeof(user_exec_list
[i
].offset
)))
2456 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2457 struct drm_file
*file
)
2459 const size_t sz
= sizeof(struct drm_i915_gem_exec_object2
);
2460 struct drm_i915_gem_execbuffer2
*args
= data
;
2461 struct drm_i915_gem_exec_object2
*exec2_list
;
2464 if (args
->buffer_count
< 1 || args
->buffer_count
> SIZE_MAX
/ sz
- 1) {
2465 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
2469 if (!i915_gem_check_execbuffer(args
))
2472 /* Allocate an extra slot for use by the command parser */
2473 exec2_list
= kvmalloc_array(args
->buffer_count
+ 1, sz
,
2474 __GFP_NOWARN
| GFP_TEMPORARY
);
2475 if (exec2_list
== NULL
) {
2476 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2477 args
->buffer_count
);
2480 if (copy_from_user(exec2_list
,
2481 u64_to_user_ptr(args
->buffers_ptr
),
2482 sizeof(*exec2_list
) * args
->buffer_count
)) {
2483 DRM_DEBUG("copy %d exec entries failed\n", args
->buffer_count
);
2488 err
= i915_gem_do_execbuffer(dev
, file
, args
, exec2_list
);
2491 * Now that we have begun execution of the batchbuffer, we ignore
2492 * any new error after this point. Also given that we have already
2493 * updated the associated relocations, we try to write out the current
2494 * object locations irrespective of any error.
2496 if (args
->flags
& __EXEC_HAS_RELOC
) {
2497 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
2498 u64_to_user_ptr(args
->buffers_ptr
);
2501 /* Copy the new buffer offsets back to the user's exec list. */
2502 user_access_begin();
2503 for (i
= 0; i
< args
->buffer_count
; i
++) {
2504 if (!(exec2_list
[i
].offset
& UPDATE
))
2507 exec2_list
[i
].offset
=
2508 gen8_canonical_addr(exec2_list
[i
].offset
& PIN_OFFSET_MASK
);
2509 unsafe_put_user(exec2_list
[i
].offset
,
2510 &user_exec_list
[i
].offset
,
2517 args
->flags
&= ~__I915_EXEC_UNKNOWN_FLAGS
;