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Merge branch 'x86/boot' into x86/mm, to avoid conflict
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/uaccess.h>
32
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40
41 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
42
43 #define __EXEC_OBJECT_HAS_PIN (1<<31)
44 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
45 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
46 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
47 #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
48
49 #define BATCH_OFFSET_BIAS (256*1024)
50
51 struct i915_execbuffer_params {
52 struct drm_device *dev;
53 struct drm_file *file;
54 struct i915_vma *batch;
55 u32 dispatch_flags;
56 u32 args_batch_start_offset;
57 struct intel_engine_cs *engine;
58 struct i915_gem_context *ctx;
59 struct drm_i915_gem_request *request;
60 };
61
62 struct eb_vmas {
63 struct drm_i915_private *i915;
64 struct list_head vmas;
65 int and;
66 union {
67 struct i915_vma *lut[0];
68 struct hlist_head buckets[0];
69 };
70 };
71
72 static struct eb_vmas *
73 eb_create(struct drm_i915_private *i915,
74 struct drm_i915_gem_execbuffer2 *args)
75 {
76 struct eb_vmas *eb = NULL;
77
78 if (args->flags & I915_EXEC_HANDLE_LUT) {
79 unsigned size = args->buffer_count;
80 size *= sizeof(struct i915_vma *);
81 size += sizeof(struct eb_vmas);
82 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
83 }
84
85 if (eb == NULL) {
86 unsigned size = args->buffer_count;
87 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
88 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
89 while (count > 2*size)
90 count >>= 1;
91 eb = kzalloc(count*sizeof(struct hlist_head) +
92 sizeof(struct eb_vmas),
93 GFP_TEMPORARY);
94 if (eb == NULL)
95 return eb;
96
97 eb->and = count - 1;
98 } else
99 eb->and = -args->buffer_count;
100
101 eb->i915 = i915;
102 INIT_LIST_HEAD(&eb->vmas);
103 return eb;
104 }
105
106 static void
107 eb_reset(struct eb_vmas *eb)
108 {
109 if (eb->and >= 0)
110 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
111 }
112
113 static struct i915_vma *
114 eb_get_batch(struct eb_vmas *eb)
115 {
116 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
117
118 /*
119 * SNA is doing fancy tricks with compressing batch buffers, which leads
120 * to negative relocation deltas. Usually that works out ok since the
121 * relocate address is still positive, except when the batch is placed
122 * very low in the GTT. Ensure this doesn't happen.
123 *
124 * Note that actual hangs have only been observed on gen7, but for
125 * paranoia do it everywhere.
126 */
127 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
128 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
129
130 return vma;
131 }
132
133 static int
134 eb_lookup_vmas(struct eb_vmas *eb,
135 struct drm_i915_gem_exec_object2 *exec,
136 const struct drm_i915_gem_execbuffer2 *args,
137 struct i915_address_space *vm,
138 struct drm_file *file)
139 {
140 struct drm_i915_gem_object *obj;
141 struct list_head objects;
142 int i, ret;
143
144 INIT_LIST_HEAD(&objects);
145 spin_lock(&file->table_lock);
146 /* Grab a reference to the object and release the lock so we can lookup
147 * or create the VMA without using GFP_ATOMIC */
148 for (i = 0; i < args->buffer_count; i++) {
149 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
150 if (obj == NULL) {
151 spin_unlock(&file->table_lock);
152 DRM_DEBUG("Invalid object handle %d at index %d\n",
153 exec[i].handle, i);
154 ret = -ENOENT;
155 goto err;
156 }
157
158 if (!list_empty(&obj->obj_exec_link)) {
159 spin_unlock(&file->table_lock);
160 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
161 obj, exec[i].handle, i);
162 ret = -EINVAL;
163 goto err;
164 }
165
166 i915_gem_object_get(obj);
167 list_add_tail(&obj->obj_exec_link, &objects);
168 }
169 spin_unlock(&file->table_lock);
170
171 i = 0;
172 while (!list_empty(&objects)) {
173 struct i915_vma *vma;
174
175 obj = list_first_entry(&objects,
176 struct drm_i915_gem_object,
177 obj_exec_link);
178
179 /*
180 * NOTE: We can leak any vmas created here when something fails
181 * later on. But that's no issue since vma_unbind can deal with
182 * vmas which are not actually bound. And since only
183 * lookup_or_create exists as an interface to get at the vma
184 * from the (obj, vm) we don't run the risk of creating
185 * duplicated vmas for the same vm.
186 */
187 vma = i915_vma_instance(obj, vm, NULL);
188 if (unlikely(IS_ERR(vma))) {
189 DRM_DEBUG("Failed to lookup VMA\n");
190 ret = PTR_ERR(vma);
191 goto err;
192 }
193
194 /* Transfer ownership from the objects list to the vmas list. */
195 list_add_tail(&vma->exec_list, &eb->vmas);
196 list_del_init(&obj->obj_exec_link);
197
198 vma->exec_entry = &exec[i];
199 if (eb->and < 0) {
200 eb->lut[i] = vma;
201 } else {
202 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
203 vma->exec_handle = handle;
204 hlist_add_head(&vma->exec_node,
205 &eb->buckets[handle & eb->and]);
206 }
207 ++i;
208 }
209
210 return 0;
211
212
213 err:
214 while (!list_empty(&objects)) {
215 obj = list_first_entry(&objects,
216 struct drm_i915_gem_object,
217 obj_exec_link);
218 list_del_init(&obj->obj_exec_link);
219 i915_gem_object_put(obj);
220 }
221 /*
222 * Objects already transfered to the vmas list will be unreferenced by
223 * eb_destroy.
224 */
225
226 return ret;
227 }
228
229 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
230 {
231 if (eb->and < 0) {
232 if (handle >= -eb->and)
233 return NULL;
234 return eb->lut[handle];
235 } else {
236 struct hlist_head *head;
237 struct i915_vma *vma;
238
239 head = &eb->buckets[handle & eb->and];
240 hlist_for_each_entry(vma, head, exec_node) {
241 if (vma->exec_handle == handle)
242 return vma;
243 }
244 return NULL;
245 }
246 }
247
248 static void
249 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
250 {
251 struct drm_i915_gem_exec_object2 *entry;
252
253 if (!drm_mm_node_allocated(&vma->node))
254 return;
255
256 entry = vma->exec_entry;
257
258 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
259 i915_vma_unpin_fence(vma);
260
261 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
262 __i915_vma_unpin(vma);
263
264 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
265 }
266
267 static void eb_destroy(struct eb_vmas *eb)
268 {
269 while (!list_empty(&eb->vmas)) {
270 struct i915_vma *vma;
271
272 vma = list_first_entry(&eb->vmas,
273 struct i915_vma,
274 exec_list);
275 list_del_init(&vma->exec_list);
276 i915_gem_execbuffer_unreserve_vma(vma);
277 vma->exec_entry = NULL;
278 i915_vma_put(vma);
279 }
280 kfree(eb);
281 }
282
283 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
284 {
285 if (!i915_gem_object_has_struct_page(obj))
286 return false;
287
288 if (DBG_USE_CPU_RELOC)
289 return DBG_USE_CPU_RELOC > 0;
290
291 return (HAS_LLC(to_i915(obj->base.dev)) ||
292 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
293 obj->cache_level != I915_CACHE_NONE);
294 }
295
296 /* Used to convert any address to canonical form.
297 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
298 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
299 * addresses to be in a canonical form:
300 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
301 * canonical form [63:48] == [47]."
302 */
303 #define GEN8_HIGH_ADDRESS_BIT 47
304 static inline uint64_t gen8_canonical_addr(uint64_t address)
305 {
306 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
307 }
308
309 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
310 {
311 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
312 }
313
314 static inline uint64_t
315 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
316 uint64_t target_offset)
317 {
318 return gen8_canonical_addr((int)reloc->delta + target_offset);
319 }
320
321 struct reloc_cache {
322 struct drm_i915_private *i915;
323 struct drm_mm_node node;
324 unsigned long vaddr;
325 unsigned int page;
326 bool use_64bit_reloc;
327 };
328
329 static void reloc_cache_init(struct reloc_cache *cache,
330 struct drm_i915_private *i915)
331 {
332 cache->page = -1;
333 cache->vaddr = 0;
334 cache->i915 = i915;
335 /* Must be a variable in the struct to allow GCC to unroll. */
336 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
337 cache->node.allocated = false;
338 }
339
340 static inline void *unmask_page(unsigned long p)
341 {
342 return (void *)(uintptr_t)(p & PAGE_MASK);
343 }
344
345 static inline unsigned int unmask_flags(unsigned long p)
346 {
347 return p & ~PAGE_MASK;
348 }
349
350 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
351
352 static void reloc_cache_fini(struct reloc_cache *cache)
353 {
354 void *vaddr;
355
356 if (!cache->vaddr)
357 return;
358
359 vaddr = unmask_page(cache->vaddr);
360 if (cache->vaddr & KMAP) {
361 if (cache->vaddr & CLFLUSH_AFTER)
362 mb();
363
364 kunmap_atomic(vaddr);
365 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
366 } else {
367 wmb();
368 io_mapping_unmap_atomic((void __iomem *)vaddr);
369 if (cache->node.allocated) {
370 struct i915_ggtt *ggtt = &cache->i915->ggtt;
371
372 ggtt->base.clear_range(&ggtt->base,
373 cache->node.start,
374 cache->node.size);
375 drm_mm_remove_node(&cache->node);
376 } else {
377 i915_vma_unpin((struct i915_vma *)cache->node.mm);
378 }
379 }
380 }
381
382 static void *reloc_kmap(struct drm_i915_gem_object *obj,
383 struct reloc_cache *cache,
384 int page)
385 {
386 void *vaddr;
387
388 if (cache->vaddr) {
389 kunmap_atomic(unmask_page(cache->vaddr));
390 } else {
391 unsigned int flushes;
392 int ret;
393
394 ret = i915_gem_obj_prepare_shmem_write(obj, &flushes);
395 if (ret)
396 return ERR_PTR(ret);
397
398 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
399 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
400
401 cache->vaddr = flushes | KMAP;
402 cache->node.mm = (void *)obj;
403 if (flushes)
404 mb();
405 }
406
407 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
408 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
409 cache->page = page;
410
411 return vaddr;
412 }
413
414 static void *reloc_iomap(struct drm_i915_gem_object *obj,
415 struct reloc_cache *cache,
416 int page)
417 {
418 struct i915_ggtt *ggtt = &cache->i915->ggtt;
419 unsigned long offset;
420 void *vaddr;
421
422 if (cache->vaddr) {
423 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
424 } else {
425 struct i915_vma *vma;
426 int ret;
427
428 if (use_cpu_reloc(obj))
429 return NULL;
430
431 ret = i915_gem_object_set_to_gtt_domain(obj, true);
432 if (ret)
433 return ERR_PTR(ret);
434
435 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
436 PIN_MAPPABLE | PIN_NONBLOCK);
437 if (IS_ERR(vma)) {
438 memset(&cache->node, 0, sizeof(cache->node));
439 ret = drm_mm_insert_node_in_range
440 (&ggtt->base.mm, &cache->node,
441 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
442 0, ggtt->mappable_end,
443 DRM_MM_INSERT_LOW);
444 if (ret) /* no inactive aperture space, use cpu reloc */
445 return NULL;
446 } else {
447 ret = i915_vma_put_fence(vma);
448 if (ret) {
449 i915_vma_unpin(vma);
450 return ERR_PTR(ret);
451 }
452
453 cache->node.start = vma->node.start;
454 cache->node.mm = (void *)vma;
455 }
456 }
457
458 offset = cache->node.start;
459 if (cache->node.allocated) {
460 wmb();
461 ggtt->base.insert_page(&ggtt->base,
462 i915_gem_object_get_dma_address(obj, page),
463 offset, I915_CACHE_NONE, 0);
464 } else {
465 offset += page << PAGE_SHIFT;
466 }
467
468 vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
469 cache->page = page;
470 cache->vaddr = (unsigned long)vaddr;
471
472 return vaddr;
473 }
474
475 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
476 struct reloc_cache *cache,
477 int page)
478 {
479 void *vaddr;
480
481 if (cache->page == page) {
482 vaddr = unmask_page(cache->vaddr);
483 } else {
484 vaddr = NULL;
485 if ((cache->vaddr & KMAP) == 0)
486 vaddr = reloc_iomap(obj, cache, page);
487 if (!vaddr)
488 vaddr = reloc_kmap(obj, cache, page);
489 }
490
491 return vaddr;
492 }
493
494 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
495 {
496 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
497 if (flushes & CLFLUSH_BEFORE) {
498 clflushopt(addr);
499 mb();
500 }
501
502 *addr = value;
503
504 /* Writes to the same cacheline are serialised by the CPU
505 * (including clflush). On the write path, we only require
506 * that it hits memory in an orderly fashion and place
507 * mb barriers at the start and end of the relocation phase
508 * to ensure ordering of clflush wrt to the system.
509 */
510 if (flushes & CLFLUSH_AFTER)
511 clflushopt(addr);
512 } else
513 *addr = value;
514 }
515
516 static int
517 relocate_entry(struct drm_i915_gem_object *obj,
518 const struct drm_i915_gem_relocation_entry *reloc,
519 struct reloc_cache *cache,
520 u64 target_offset)
521 {
522 u64 offset = reloc->offset;
523 bool wide = cache->use_64bit_reloc;
524 void *vaddr;
525
526 target_offset = relocation_target(reloc, target_offset);
527 repeat:
528 vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT);
529 if (IS_ERR(vaddr))
530 return PTR_ERR(vaddr);
531
532 clflush_write32(vaddr + offset_in_page(offset),
533 lower_32_bits(target_offset),
534 cache->vaddr);
535
536 if (wide) {
537 offset += sizeof(u32);
538 target_offset >>= 32;
539 wide = false;
540 goto repeat;
541 }
542
543 return 0;
544 }
545
546 static int
547 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
548 struct eb_vmas *eb,
549 struct drm_i915_gem_relocation_entry *reloc,
550 struct reloc_cache *cache)
551 {
552 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
553 struct drm_gem_object *target_obj;
554 struct drm_i915_gem_object *target_i915_obj;
555 struct i915_vma *target_vma;
556 uint64_t target_offset;
557 int ret;
558
559 /* we've already hold a reference to all valid objects */
560 target_vma = eb_get_vma(eb, reloc->target_handle);
561 if (unlikely(target_vma == NULL))
562 return -ENOENT;
563 target_i915_obj = target_vma->obj;
564 target_obj = &target_vma->obj->base;
565
566 target_offset = gen8_canonical_addr(target_vma->node.start);
567
568 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
569 * pipe_control writes because the gpu doesn't properly redirect them
570 * through the ppgtt for non_secure batchbuffers. */
571 if (unlikely(IS_GEN6(dev_priv) &&
572 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
573 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
574 PIN_GLOBAL);
575 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
576 return ret;
577 }
578
579 /* Validate that the target is in a valid r/w GPU domain */
580 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
581 DRM_DEBUG("reloc with multiple write domains: "
582 "obj %p target %d offset %d "
583 "read %08x write %08x",
584 obj, reloc->target_handle,
585 (int) reloc->offset,
586 reloc->read_domains,
587 reloc->write_domain);
588 return -EINVAL;
589 }
590 if (unlikely((reloc->write_domain | reloc->read_domains)
591 & ~I915_GEM_GPU_DOMAINS)) {
592 DRM_DEBUG("reloc with read/write non-GPU domains: "
593 "obj %p target %d offset %d "
594 "read %08x write %08x",
595 obj, reloc->target_handle,
596 (int) reloc->offset,
597 reloc->read_domains,
598 reloc->write_domain);
599 return -EINVAL;
600 }
601
602 target_obj->pending_read_domains |= reloc->read_domains;
603 target_obj->pending_write_domain |= reloc->write_domain;
604
605 /* If the relocation already has the right value in it, no
606 * more work needs to be done.
607 */
608 if (target_offset == reloc->presumed_offset)
609 return 0;
610
611 /* Check that the relocation address is valid... */
612 if (unlikely(reloc->offset >
613 obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) {
614 DRM_DEBUG("Relocation beyond object bounds: "
615 "obj %p target %d offset %d size %d.\n",
616 obj, reloc->target_handle,
617 (int) reloc->offset,
618 (int) obj->base.size);
619 return -EINVAL;
620 }
621 if (unlikely(reloc->offset & 3)) {
622 DRM_DEBUG("Relocation not 4-byte aligned: "
623 "obj %p target %d offset %d.\n",
624 obj, reloc->target_handle,
625 (int) reloc->offset);
626 return -EINVAL;
627 }
628
629 ret = relocate_entry(obj, reloc, cache, target_offset);
630 if (ret)
631 return ret;
632
633 /* and update the user's relocation entry */
634 reloc->presumed_offset = target_offset;
635 return 0;
636 }
637
638 static int
639 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
640 struct eb_vmas *eb)
641 {
642 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
643 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
644 struct drm_i915_gem_relocation_entry __user *user_relocs;
645 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
646 struct reloc_cache cache;
647 int remain, ret = 0;
648
649 user_relocs = u64_to_user_ptr(entry->relocs_ptr);
650 reloc_cache_init(&cache, eb->i915);
651
652 remain = entry->relocation_count;
653 while (remain) {
654 struct drm_i915_gem_relocation_entry *r = stack_reloc;
655 unsigned long unwritten;
656 unsigned int count;
657
658 count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc));
659 remain -= count;
660
661 /* This is the fast path and we cannot handle a pagefault
662 * whilst holding the struct mutex lest the user pass in the
663 * relocations contained within a mmaped bo. For in such a case
664 * we, the page fault handler would call i915_gem_fault() and
665 * we would try to acquire the struct mutex again. Obviously
666 * this is bad and so lockdep complains vehemently.
667 */
668 pagefault_disable();
669 unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]));
670 pagefault_enable();
671 if (unlikely(unwritten)) {
672 ret = -EFAULT;
673 goto out;
674 }
675
676 do {
677 u64 offset = r->presumed_offset;
678
679 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache);
680 if (ret)
681 goto out;
682
683 if (r->presumed_offset != offset) {
684 pagefault_disable();
685 unwritten = __put_user(r->presumed_offset,
686 &user_relocs->presumed_offset);
687 pagefault_enable();
688 if (unlikely(unwritten)) {
689 /* Note that reporting an error now
690 * leaves everything in an inconsistent
691 * state as we have *already* changed
692 * the relocation value inside the
693 * object. As we have not changed the
694 * reloc.presumed_offset or will not
695 * change the execobject.offset, on the
696 * call we may not rewrite the value
697 * inside the object, leaving it
698 * dangling and causing a GPU hang.
699 */
700 ret = -EFAULT;
701 goto out;
702 }
703 }
704
705 user_relocs++;
706 r++;
707 } while (--count);
708 }
709
710 out:
711 reloc_cache_fini(&cache);
712 return ret;
713 #undef N_RELOC
714 }
715
716 static int
717 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
718 struct eb_vmas *eb,
719 struct drm_i915_gem_relocation_entry *relocs)
720 {
721 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
722 struct reloc_cache cache;
723 int i, ret = 0;
724
725 reloc_cache_init(&cache, eb->i915);
726 for (i = 0; i < entry->relocation_count; i++) {
727 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache);
728 if (ret)
729 break;
730 }
731 reloc_cache_fini(&cache);
732
733 return ret;
734 }
735
736 static int
737 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
738 {
739 struct i915_vma *vma;
740 int ret = 0;
741
742 list_for_each_entry(vma, &eb->vmas, exec_list) {
743 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
744 if (ret)
745 break;
746 }
747
748 return ret;
749 }
750
751 static bool only_mappable_for_reloc(unsigned int flags)
752 {
753 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
754 __EXEC_OBJECT_NEEDS_MAP;
755 }
756
757 static int
758 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
759 struct intel_engine_cs *engine,
760 bool *need_reloc)
761 {
762 struct drm_i915_gem_object *obj = vma->obj;
763 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
764 uint64_t flags;
765 int ret;
766
767 flags = PIN_USER;
768 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
769 flags |= PIN_GLOBAL;
770
771 if (!drm_mm_node_allocated(&vma->node)) {
772 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
773 * limit address to the first 4GBs for unflagged objects.
774 */
775 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
776 flags |= PIN_ZONE_4G;
777 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
778 flags |= PIN_GLOBAL | PIN_MAPPABLE;
779 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
780 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
781 if (entry->flags & EXEC_OBJECT_PINNED)
782 flags |= entry->offset | PIN_OFFSET_FIXED;
783 if ((flags & PIN_MAPPABLE) == 0)
784 flags |= PIN_HIGH;
785 }
786
787 ret = i915_vma_pin(vma,
788 entry->pad_to_size,
789 entry->alignment,
790 flags);
791 if ((ret == -ENOSPC || ret == -E2BIG) &&
792 only_mappable_for_reloc(entry->flags))
793 ret = i915_vma_pin(vma,
794 entry->pad_to_size,
795 entry->alignment,
796 flags & ~PIN_MAPPABLE);
797 if (ret)
798 return ret;
799
800 entry->flags |= __EXEC_OBJECT_HAS_PIN;
801
802 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
803 ret = i915_vma_get_fence(vma);
804 if (ret)
805 return ret;
806
807 if (i915_vma_pin_fence(vma))
808 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
809 }
810
811 if (entry->offset != vma->node.start) {
812 entry->offset = vma->node.start;
813 *need_reloc = true;
814 }
815
816 if (entry->flags & EXEC_OBJECT_WRITE) {
817 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
818 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
819 }
820
821 return 0;
822 }
823
824 static bool
825 need_reloc_mappable(struct i915_vma *vma)
826 {
827 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
828
829 if (entry->relocation_count == 0)
830 return false;
831
832 if (!i915_vma_is_ggtt(vma))
833 return false;
834
835 /* See also use_cpu_reloc() */
836 if (HAS_LLC(to_i915(vma->obj->base.dev)))
837 return false;
838
839 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
840 return false;
841
842 return true;
843 }
844
845 static bool
846 eb_vma_misplaced(struct i915_vma *vma)
847 {
848 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
849
850 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
851 !i915_vma_is_ggtt(vma));
852
853 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
854 return true;
855
856 if (vma->node.size < entry->pad_to_size)
857 return true;
858
859 if (entry->flags & EXEC_OBJECT_PINNED &&
860 vma->node.start != entry->offset)
861 return true;
862
863 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
864 vma->node.start < BATCH_OFFSET_BIAS)
865 return true;
866
867 /* avoid costly ping-pong once a batch bo ended up non-mappable */
868 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
869 !i915_vma_is_map_and_fenceable(vma))
870 return !only_mappable_for_reloc(entry->flags);
871
872 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
873 (vma->node.start + vma->node.size - 1) >> 32)
874 return true;
875
876 return false;
877 }
878
879 static int
880 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
881 struct list_head *vmas,
882 struct i915_gem_context *ctx,
883 bool *need_relocs)
884 {
885 struct drm_i915_gem_object *obj;
886 struct i915_vma *vma;
887 struct i915_address_space *vm;
888 struct list_head ordered_vmas;
889 struct list_head pinned_vmas;
890 bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
891 int retry;
892
893 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
894
895 INIT_LIST_HEAD(&ordered_vmas);
896 INIT_LIST_HEAD(&pinned_vmas);
897 while (!list_empty(vmas)) {
898 struct drm_i915_gem_exec_object2 *entry;
899 bool need_fence, need_mappable;
900
901 vma = list_first_entry(vmas, struct i915_vma, exec_list);
902 obj = vma->obj;
903 entry = vma->exec_entry;
904
905 if (ctx->flags & CONTEXT_NO_ZEROMAP)
906 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
907
908 if (!has_fenced_gpu_access)
909 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
910 need_fence =
911 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
912 i915_gem_object_is_tiled(obj);
913 need_mappable = need_fence || need_reloc_mappable(vma);
914
915 if (entry->flags & EXEC_OBJECT_PINNED)
916 list_move_tail(&vma->exec_list, &pinned_vmas);
917 else if (need_mappable) {
918 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
919 list_move(&vma->exec_list, &ordered_vmas);
920 } else
921 list_move_tail(&vma->exec_list, &ordered_vmas);
922
923 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
924 obj->base.pending_write_domain = 0;
925 }
926 list_splice(&ordered_vmas, vmas);
927 list_splice(&pinned_vmas, vmas);
928
929 /* Attempt to pin all of the buffers into the GTT.
930 * This is done in 3 phases:
931 *
932 * 1a. Unbind all objects that do not match the GTT constraints for
933 * the execbuffer (fenceable, mappable, alignment etc).
934 * 1b. Increment pin count for already bound objects.
935 * 2. Bind new objects.
936 * 3. Decrement pin count.
937 *
938 * This avoid unnecessary unbinding of later objects in order to make
939 * room for the earlier objects *unless* we need to defragment.
940 */
941 retry = 0;
942 do {
943 int ret = 0;
944
945 /* Unbind any ill-fitting objects or pin. */
946 list_for_each_entry(vma, vmas, exec_list) {
947 if (!drm_mm_node_allocated(&vma->node))
948 continue;
949
950 if (eb_vma_misplaced(vma))
951 ret = i915_vma_unbind(vma);
952 else
953 ret = i915_gem_execbuffer_reserve_vma(vma,
954 engine,
955 need_relocs);
956 if (ret)
957 goto err;
958 }
959
960 /* Bind fresh objects */
961 list_for_each_entry(vma, vmas, exec_list) {
962 if (drm_mm_node_allocated(&vma->node))
963 continue;
964
965 ret = i915_gem_execbuffer_reserve_vma(vma, engine,
966 need_relocs);
967 if (ret)
968 goto err;
969 }
970
971 err:
972 if (ret != -ENOSPC || retry++)
973 return ret;
974
975 /* Decrement pin count for bound objects */
976 list_for_each_entry(vma, vmas, exec_list)
977 i915_gem_execbuffer_unreserve_vma(vma);
978
979 ret = i915_gem_evict_vm(vm, true);
980 if (ret)
981 return ret;
982 } while (1);
983 }
984
985 static int
986 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
987 struct drm_i915_gem_execbuffer2 *args,
988 struct drm_file *file,
989 struct intel_engine_cs *engine,
990 struct eb_vmas *eb,
991 struct drm_i915_gem_exec_object2 *exec,
992 struct i915_gem_context *ctx)
993 {
994 struct drm_i915_gem_relocation_entry *reloc;
995 struct i915_address_space *vm;
996 struct i915_vma *vma;
997 bool need_relocs;
998 int *reloc_offset;
999 int i, total, ret;
1000 unsigned count = args->buffer_count;
1001
1002 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
1003
1004 /* We may process another execbuffer during the unlock... */
1005 while (!list_empty(&eb->vmas)) {
1006 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
1007 list_del_init(&vma->exec_list);
1008 i915_gem_execbuffer_unreserve_vma(vma);
1009 i915_vma_put(vma);
1010 }
1011
1012 mutex_unlock(&dev->struct_mutex);
1013
1014 total = 0;
1015 for (i = 0; i < count; i++)
1016 total += exec[i].relocation_count;
1017
1018 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
1019 reloc = drm_malloc_ab(total, sizeof(*reloc));
1020 if (reloc == NULL || reloc_offset == NULL) {
1021 drm_free_large(reloc);
1022 drm_free_large(reloc_offset);
1023 mutex_lock(&dev->struct_mutex);
1024 return -ENOMEM;
1025 }
1026
1027 total = 0;
1028 for (i = 0; i < count; i++) {
1029 struct drm_i915_gem_relocation_entry __user *user_relocs;
1030 u64 invalid_offset = (u64)-1;
1031 int j;
1032
1033 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
1034
1035 if (copy_from_user(reloc+total, user_relocs,
1036 exec[i].relocation_count * sizeof(*reloc))) {
1037 ret = -EFAULT;
1038 mutex_lock(&dev->struct_mutex);
1039 goto err;
1040 }
1041
1042 /* As we do not update the known relocation offsets after
1043 * relocating (due to the complexities in lock handling),
1044 * we need to mark them as invalid now so that we force the
1045 * relocation processing next time. Just in case the target
1046 * object is evicted and then rebound into its old
1047 * presumed_offset before the next execbuffer - if that
1048 * happened we would make the mistake of assuming that the
1049 * relocations were valid.
1050 */
1051 for (j = 0; j < exec[i].relocation_count; j++) {
1052 if (__copy_to_user(&user_relocs[j].presumed_offset,
1053 &invalid_offset,
1054 sizeof(invalid_offset))) {
1055 ret = -EFAULT;
1056 mutex_lock(&dev->struct_mutex);
1057 goto err;
1058 }
1059 }
1060
1061 reloc_offset[i] = total;
1062 total += exec[i].relocation_count;
1063 }
1064
1065 ret = i915_mutex_lock_interruptible(dev);
1066 if (ret) {
1067 mutex_lock(&dev->struct_mutex);
1068 goto err;
1069 }
1070
1071 /* reacquire the objects */
1072 eb_reset(eb);
1073 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1074 if (ret)
1075 goto err;
1076
1077 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1078 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1079 &need_relocs);
1080 if (ret)
1081 goto err;
1082
1083 list_for_each_entry(vma, &eb->vmas, exec_list) {
1084 int offset = vma->exec_entry - exec;
1085 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
1086 reloc + reloc_offset[offset]);
1087 if (ret)
1088 goto err;
1089 }
1090
1091 /* Leave the user relocations as are, this is the painfully slow path,
1092 * and we want to avoid the complication of dropping the lock whilst
1093 * having buffers reserved in the aperture and so causing spurious
1094 * ENOSPC for random operations.
1095 */
1096
1097 err:
1098 drm_free_large(reloc);
1099 drm_free_large(reloc_offset);
1100 return ret;
1101 }
1102
1103 static int
1104 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
1105 struct list_head *vmas)
1106 {
1107 struct i915_vma *vma;
1108 int ret;
1109
1110 list_for_each_entry(vma, vmas, exec_list) {
1111 struct drm_i915_gem_object *obj = vma->obj;
1112
1113 ret = i915_gem_request_await_object
1114 (req, obj, obj->base.pending_write_domain);
1115 if (ret)
1116 return ret;
1117
1118 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1119 i915_gem_clflush_object(obj, false);
1120 }
1121
1122 /* Unconditionally flush any chipset caches (for streaming writes). */
1123 i915_gem_chipset_flush(req->engine->i915);
1124
1125 /* Unconditionally invalidate GPU caches and TLBs. */
1126 return req->engine->emit_flush(req, EMIT_INVALIDATE);
1127 }
1128
1129 static bool
1130 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1131 {
1132 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1133 return false;
1134
1135 /* Kernel clipping was a DRI1 misfeature */
1136 if (exec->num_cliprects || exec->cliprects_ptr)
1137 return false;
1138
1139 if (exec->DR4 == 0xffffffff) {
1140 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1141 exec->DR4 = 0;
1142 }
1143 if (exec->DR1 || exec->DR4)
1144 return false;
1145
1146 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1147 return false;
1148
1149 return true;
1150 }
1151
1152 static int
1153 validate_exec_list(struct drm_device *dev,
1154 struct drm_i915_gem_exec_object2 *exec,
1155 int count)
1156 {
1157 unsigned relocs_total = 0;
1158 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1159 unsigned invalid_flags;
1160 int i;
1161
1162 /* INTERNAL flags must not overlap with external ones */
1163 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1164
1165 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1166 if (USES_FULL_PPGTT(dev))
1167 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1168
1169 for (i = 0; i < count; i++) {
1170 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1171 int length; /* limited by fault_in_pages_readable() */
1172
1173 if (exec[i].flags & invalid_flags)
1174 return -EINVAL;
1175
1176 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1177 * any non-page-aligned or non-canonical addresses.
1178 */
1179 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1180 if (exec[i].offset !=
1181 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1182 return -EINVAL;
1183 }
1184
1185 /* From drm_mm perspective address space is continuous,
1186 * so from this point we're always using non-canonical
1187 * form internally.
1188 */
1189 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1190
1191 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1192 return -EINVAL;
1193
1194 /* pad_to_size was once a reserved field, so sanitize it */
1195 if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) {
1196 if (offset_in_page(exec[i].pad_to_size))
1197 return -EINVAL;
1198 } else {
1199 exec[i].pad_to_size = 0;
1200 }
1201
1202 /* First check for malicious input causing overflow in
1203 * the worst case where we need to allocate the entire
1204 * relocation tree as a single array.
1205 */
1206 if (exec[i].relocation_count > relocs_max - relocs_total)
1207 return -EINVAL;
1208 relocs_total += exec[i].relocation_count;
1209
1210 length = exec[i].relocation_count *
1211 sizeof(struct drm_i915_gem_relocation_entry);
1212 /*
1213 * We must check that the entire relocation array is safe
1214 * to read, but since we may need to update the presumed
1215 * offsets during execution, check for full write access.
1216 */
1217 if (!access_ok(VERIFY_WRITE, ptr, length))
1218 return -EFAULT;
1219
1220 if (likely(!i915.prefault_disable)) {
1221 if (fault_in_pages_readable(ptr, length))
1222 return -EFAULT;
1223 }
1224 }
1225
1226 return 0;
1227 }
1228
1229 static struct i915_gem_context *
1230 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1231 struct intel_engine_cs *engine, const u32 ctx_id)
1232 {
1233 struct i915_gem_context *ctx;
1234
1235 ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1236 if (IS_ERR(ctx))
1237 return ctx;
1238
1239 if (i915_gem_context_is_banned(ctx)) {
1240 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1241 return ERR_PTR(-EIO);
1242 }
1243
1244 return ctx;
1245 }
1246
1247 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
1248 {
1249 return !(obj->cache_level == I915_CACHE_NONE ||
1250 obj->cache_level == I915_CACHE_WT);
1251 }
1252
1253 void i915_vma_move_to_active(struct i915_vma *vma,
1254 struct drm_i915_gem_request *req,
1255 unsigned int flags)
1256 {
1257 struct drm_i915_gem_object *obj = vma->obj;
1258 const unsigned int idx = req->engine->id;
1259
1260 lockdep_assert_held(&req->i915->drm.struct_mutex);
1261 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1262
1263 /* Add a reference if we're newly entering the active list.
1264 * The order in which we add operations to the retirement queue is
1265 * vital here: mark_active adds to the start of the callback list,
1266 * such that subsequent callbacks are called first. Therefore we
1267 * add the active reference first and queue for it to be dropped
1268 * *last*.
1269 */
1270 if (!i915_vma_is_active(vma))
1271 obj->active_count++;
1272 i915_vma_set_active(vma, idx);
1273 i915_gem_active_set(&vma->last_read[idx], req);
1274 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1275
1276 if (flags & EXEC_OBJECT_WRITE) {
1277 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1278 i915_gem_active_set(&obj->frontbuffer_write, req);
1279
1280 /* update for the implicit flush after a batch */
1281 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1282 if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
1283 obj->cache_dirty = true;
1284 }
1285
1286 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1287 i915_gem_active_set(&vma->last_fence, req);
1288 }
1289
1290 static void eb_export_fence(struct drm_i915_gem_object *obj,
1291 struct drm_i915_gem_request *req,
1292 unsigned int flags)
1293 {
1294 struct reservation_object *resv = obj->resv;
1295
1296 /* Ignore errors from failing to allocate the new fence, we can't
1297 * handle an error right now. Worst case should be missed
1298 * synchronisation leading to rendering corruption.
1299 */
1300 ww_mutex_lock(&resv->lock, NULL);
1301 if (flags & EXEC_OBJECT_WRITE)
1302 reservation_object_add_excl_fence(resv, &req->fence);
1303 else if (reservation_object_reserve_shared(resv) == 0)
1304 reservation_object_add_shared_fence(resv, &req->fence);
1305 ww_mutex_unlock(&resv->lock);
1306 }
1307
1308 static void
1309 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1310 struct drm_i915_gem_request *req)
1311 {
1312 struct i915_vma *vma;
1313
1314 list_for_each_entry(vma, vmas, exec_list) {
1315 struct drm_i915_gem_object *obj = vma->obj;
1316 u32 old_read = obj->base.read_domains;
1317 u32 old_write = obj->base.write_domain;
1318
1319 obj->base.write_domain = obj->base.pending_write_domain;
1320 if (obj->base.write_domain)
1321 vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
1322 else
1323 obj->base.pending_read_domains |= obj->base.read_domains;
1324 obj->base.read_domains = obj->base.pending_read_domains;
1325
1326 i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
1327 eb_export_fence(obj, req, vma->exec_entry->flags);
1328 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1329 }
1330 }
1331
1332 static int
1333 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1334 {
1335 struct intel_ring *ring = req->ring;
1336 int ret, i;
1337
1338 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1339 DRM_DEBUG("sol reset is gen7/rcs only\n");
1340 return -EINVAL;
1341 }
1342
1343 ret = intel_ring_begin(req, 4 * 3);
1344 if (ret)
1345 return ret;
1346
1347 for (i = 0; i < 4; i++) {
1348 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1349 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1350 intel_ring_emit(ring, 0);
1351 }
1352
1353 intel_ring_advance(ring);
1354
1355 return 0;
1356 }
1357
1358 static struct i915_vma *
1359 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1360 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1361 struct drm_i915_gem_object *batch_obj,
1362 struct eb_vmas *eb,
1363 u32 batch_start_offset,
1364 u32 batch_len,
1365 bool is_master)
1366 {
1367 struct drm_i915_gem_object *shadow_batch_obj;
1368 struct i915_vma *vma;
1369 int ret;
1370
1371 shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1372 PAGE_ALIGN(batch_len));
1373 if (IS_ERR(shadow_batch_obj))
1374 return ERR_CAST(shadow_batch_obj);
1375
1376 ret = intel_engine_cmd_parser(engine,
1377 batch_obj,
1378 shadow_batch_obj,
1379 batch_start_offset,
1380 batch_len,
1381 is_master);
1382 if (ret) {
1383 if (ret == -EACCES) /* unhandled chained batch */
1384 vma = NULL;
1385 else
1386 vma = ERR_PTR(ret);
1387 goto out;
1388 }
1389
1390 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1391 if (IS_ERR(vma))
1392 goto out;
1393
1394 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1395
1396 vma->exec_entry = shadow_exec_entry;
1397 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1398 i915_gem_object_get(shadow_batch_obj);
1399 list_add_tail(&vma->exec_list, &eb->vmas);
1400
1401 out:
1402 i915_gem_object_unpin_pages(shadow_batch_obj);
1403 return vma;
1404 }
1405
1406 static int
1407 execbuf_submit(struct i915_execbuffer_params *params,
1408 struct drm_i915_gem_execbuffer2 *args,
1409 struct list_head *vmas)
1410 {
1411 u64 exec_start, exec_len;
1412 int ret;
1413
1414 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1415 if (ret)
1416 return ret;
1417
1418 ret = i915_switch_context(params->request);
1419 if (ret)
1420 return ret;
1421
1422 if (args->flags & I915_EXEC_CONSTANTS_MASK) {
1423 DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n");
1424 return -EINVAL;
1425 }
1426
1427 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1428 ret = i915_reset_gen7_sol_offsets(params->request);
1429 if (ret)
1430 return ret;
1431 }
1432
1433 exec_len = args->batch_len;
1434 exec_start = params->batch->node.start +
1435 params->args_batch_start_offset;
1436
1437 if (exec_len == 0)
1438 exec_len = params->batch->size - params->args_batch_start_offset;
1439
1440 ret = params->engine->emit_bb_start(params->request,
1441 exec_start, exec_len,
1442 params->dispatch_flags);
1443 if (ret)
1444 return ret;
1445
1446 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1447
1448 i915_gem_execbuffer_move_to_active(vmas, params->request);
1449
1450 return 0;
1451 }
1452
1453 /**
1454 * Find one BSD ring to dispatch the corresponding BSD command.
1455 * The engine index is returned.
1456 */
1457 static unsigned int
1458 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1459 struct drm_file *file)
1460 {
1461 struct drm_i915_file_private *file_priv = file->driver_priv;
1462
1463 /* Check whether the file_priv has already selected one ring. */
1464 if ((int)file_priv->bsd_engine < 0)
1465 file_priv->bsd_engine = atomic_fetch_xor(1,
1466 &dev_priv->mm.bsd_engine_dispatch_index);
1467
1468 return file_priv->bsd_engine;
1469 }
1470
1471 #define I915_USER_RINGS (4)
1472
1473 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1474 [I915_EXEC_DEFAULT] = RCS,
1475 [I915_EXEC_RENDER] = RCS,
1476 [I915_EXEC_BLT] = BCS,
1477 [I915_EXEC_BSD] = VCS,
1478 [I915_EXEC_VEBOX] = VECS
1479 };
1480
1481 static struct intel_engine_cs *
1482 eb_select_engine(struct drm_i915_private *dev_priv,
1483 struct drm_file *file,
1484 struct drm_i915_gem_execbuffer2 *args)
1485 {
1486 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1487 struct intel_engine_cs *engine;
1488
1489 if (user_ring_id > I915_USER_RINGS) {
1490 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1491 return NULL;
1492 }
1493
1494 if ((user_ring_id != I915_EXEC_BSD) &&
1495 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1496 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1497 "bsd dispatch flags: %d\n", (int)(args->flags));
1498 return NULL;
1499 }
1500
1501 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1502 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1503
1504 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1505 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1506 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1507 bsd_idx <= I915_EXEC_BSD_RING2) {
1508 bsd_idx >>= I915_EXEC_BSD_SHIFT;
1509 bsd_idx--;
1510 } else {
1511 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1512 bsd_idx);
1513 return NULL;
1514 }
1515
1516 engine = dev_priv->engine[_VCS(bsd_idx)];
1517 } else {
1518 engine = dev_priv->engine[user_ring_map[user_ring_id]];
1519 }
1520
1521 if (!engine) {
1522 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1523 return NULL;
1524 }
1525
1526 return engine;
1527 }
1528
1529 static int
1530 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1531 struct drm_file *file,
1532 struct drm_i915_gem_execbuffer2 *args,
1533 struct drm_i915_gem_exec_object2 *exec)
1534 {
1535 struct drm_i915_private *dev_priv = to_i915(dev);
1536 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1537 struct eb_vmas *eb;
1538 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1539 struct intel_engine_cs *engine;
1540 struct i915_gem_context *ctx;
1541 struct i915_address_space *vm;
1542 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1543 struct i915_execbuffer_params *params = &params_master;
1544 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1545 u32 dispatch_flags;
1546 int ret;
1547 bool need_relocs;
1548
1549 if (!i915_gem_check_execbuffer(args))
1550 return -EINVAL;
1551
1552 ret = validate_exec_list(dev, exec, args->buffer_count);
1553 if (ret)
1554 return ret;
1555
1556 dispatch_flags = 0;
1557 if (args->flags & I915_EXEC_SECURE) {
1558 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1559 return -EPERM;
1560
1561 dispatch_flags |= I915_DISPATCH_SECURE;
1562 }
1563 if (args->flags & I915_EXEC_IS_PINNED)
1564 dispatch_flags |= I915_DISPATCH_PINNED;
1565
1566 engine = eb_select_engine(dev_priv, file, args);
1567 if (!engine)
1568 return -EINVAL;
1569
1570 if (args->buffer_count < 1) {
1571 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1572 return -EINVAL;
1573 }
1574
1575 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1576 if (!HAS_RESOURCE_STREAMER(dev_priv)) {
1577 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1578 return -EINVAL;
1579 }
1580 if (engine->id != RCS) {
1581 DRM_DEBUG("RS is not available on %s\n",
1582 engine->name);
1583 return -EINVAL;
1584 }
1585
1586 dispatch_flags |= I915_DISPATCH_RS;
1587 }
1588
1589 /* Take a local wakeref for preparing to dispatch the execbuf as
1590 * we expect to access the hardware fairly frequently in the
1591 * process. Upon first dispatch, we acquire another prolonged
1592 * wakeref that we hold until the GPU has been idle for at least
1593 * 100ms.
1594 */
1595 intel_runtime_pm_get(dev_priv);
1596
1597 ret = i915_mutex_lock_interruptible(dev);
1598 if (ret)
1599 goto pre_mutex_err;
1600
1601 ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1602 if (IS_ERR(ctx)) {
1603 mutex_unlock(&dev->struct_mutex);
1604 ret = PTR_ERR(ctx);
1605 goto pre_mutex_err;
1606 }
1607
1608 i915_gem_context_get(ctx);
1609
1610 if (ctx->ppgtt)
1611 vm = &ctx->ppgtt->base;
1612 else
1613 vm = &ggtt->base;
1614
1615 memset(&params_master, 0x00, sizeof(params_master));
1616
1617 eb = eb_create(dev_priv, args);
1618 if (eb == NULL) {
1619 i915_gem_context_put(ctx);
1620 mutex_unlock(&dev->struct_mutex);
1621 ret = -ENOMEM;
1622 goto pre_mutex_err;
1623 }
1624
1625 /* Look up object handles */
1626 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1627 if (ret)
1628 goto err;
1629
1630 /* take note of the batch buffer before we might reorder the lists */
1631 params->batch = eb_get_batch(eb);
1632
1633 /* Move the objects en-masse into the GTT, evicting if necessary. */
1634 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1635 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1636 &need_relocs);
1637 if (ret)
1638 goto err;
1639
1640 /* The objects are in their final locations, apply the relocations. */
1641 if (need_relocs)
1642 ret = i915_gem_execbuffer_relocate(eb);
1643 if (ret) {
1644 if (ret == -EFAULT) {
1645 ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1646 engine,
1647 eb, exec, ctx);
1648 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1649 }
1650 if (ret)
1651 goto err;
1652 }
1653
1654 /* Set the pending read domains for the batch buffer to COMMAND */
1655 if (params->batch->obj->base.pending_write_domain) {
1656 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1657 ret = -EINVAL;
1658 goto err;
1659 }
1660 if (args->batch_start_offset > params->batch->size ||
1661 args->batch_len > params->batch->size - args->batch_start_offset) {
1662 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1663 ret = -EINVAL;
1664 goto err;
1665 }
1666
1667 params->args_batch_start_offset = args->batch_start_offset;
1668 if (engine->needs_cmd_parser && args->batch_len) {
1669 struct i915_vma *vma;
1670
1671 vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry,
1672 params->batch->obj,
1673 eb,
1674 args->batch_start_offset,
1675 args->batch_len,
1676 drm_is_current_master(file));
1677 if (IS_ERR(vma)) {
1678 ret = PTR_ERR(vma);
1679 goto err;
1680 }
1681
1682 if (vma) {
1683 /*
1684 * Batch parsed and accepted:
1685 *
1686 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1687 * bit from MI_BATCH_BUFFER_START commands issued in
1688 * the dispatch_execbuffer implementations. We
1689 * specifically don't want that set on batches the
1690 * command parser has accepted.
1691 */
1692 dispatch_flags |= I915_DISPATCH_SECURE;
1693 params->args_batch_start_offset = 0;
1694 params->batch = vma;
1695 }
1696 }
1697
1698 params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1699
1700 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1701 * batch" bit. Hence we need to pin secure batches into the global gtt.
1702 * hsw should have this fixed, but bdw mucks it up again. */
1703 if (dispatch_flags & I915_DISPATCH_SECURE) {
1704 struct drm_i915_gem_object *obj = params->batch->obj;
1705 struct i915_vma *vma;
1706
1707 /*
1708 * So on first glance it looks freaky that we pin the batch here
1709 * outside of the reservation loop. But:
1710 * - The batch is already pinned into the relevant ppgtt, so we
1711 * already have the backing storage fully allocated.
1712 * - No other BO uses the global gtt (well contexts, but meh),
1713 * so we don't really have issues with multiple objects not
1714 * fitting due to fragmentation.
1715 * So this is actually safe.
1716 */
1717 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
1718 if (IS_ERR(vma)) {
1719 ret = PTR_ERR(vma);
1720 goto err;
1721 }
1722
1723 params->batch = vma;
1724 }
1725
1726 /* Allocate a request for this batch buffer nice and early. */
1727 params->request = i915_gem_request_alloc(engine, ctx);
1728 if (IS_ERR(params->request)) {
1729 ret = PTR_ERR(params->request);
1730 goto err_batch_unpin;
1731 }
1732
1733 /* Whilst this request exists, batch_obj will be on the
1734 * active_list, and so will hold the active reference. Only when this
1735 * request is retired will the the batch_obj be moved onto the
1736 * inactive_list and lose its active reference. Hence we do not need
1737 * to explicitly hold another reference here.
1738 */
1739 params->request->batch = params->batch;
1740
1741 ret = i915_gem_request_add_to_client(params->request, file);
1742 if (ret)
1743 goto err_request;
1744
1745 /*
1746 * Save assorted stuff away to pass through to *_submission().
1747 * NB: This data should be 'persistent' and not local as it will
1748 * kept around beyond the duration of the IOCTL once the GPU
1749 * scheduler arrives.
1750 */
1751 params->dev = dev;
1752 params->file = file;
1753 params->engine = engine;
1754 params->dispatch_flags = dispatch_flags;
1755 params->ctx = ctx;
1756
1757 ret = execbuf_submit(params, args, &eb->vmas);
1758 err_request:
1759 __i915_add_request(params->request, ret == 0);
1760
1761 err_batch_unpin:
1762 /*
1763 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1764 * batch vma for correctness. For less ugly and less fragility this
1765 * needs to be adjusted to also track the ggtt batch vma properly as
1766 * active.
1767 */
1768 if (dispatch_flags & I915_DISPATCH_SECURE)
1769 i915_vma_unpin(params->batch);
1770 err:
1771 /* the request owns the ref now */
1772 i915_gem_context_put(ctx);
1773 eb_destroy(eb);
1774
1775 mutex_unlock(&dev->struct_mutex);
1776
1777 pre_mutex_err:
1778 /* intel_gpu_busy should also get a ref, so it will free when the device
1779 * is really idle. */
1780 intel_runtime_pm_put(dev_priv);
1781 return ret;
1782 }
1783
1784 /*
1785 * Legacy execbuffer just creates an exec2 list from the original exec object
1786 * list array and passes it to the real function.
1787 */
1788 int
1789 i915_gem_execbuffer(struct drm_device *dev, void *data,
1790 struct drm_file *file)
1791 {
1792 struct drm_i915_gem_execbuffer *args = data;
1793 struct drm_i915_gem_execbuffer2 exec2;
1794 struct drm_i915_gem_exec_object *exec_list = NULL;
1795 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1796 int ret, i;
1797
1798 if (args->buffer_count < 1) {
1799 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1800 return -EINVAL;
1801 }
1802
1803 /* Copy in the exec list from userland */
1804 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1805 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1806 if (exec_list == NULL || exec2_list == NULL) {
1807 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1808 args->buffer_count);
1809 drm_free_large(exec_list);
1810 drm_free_large(exec2_list);
1811 return -ENOMEM;
1812 }
1813 ret = copy_from_user(exec_list,
1814 u64_to_user_ptr(args->buffers_ptr),
1815 sizeof(*exec_list) * args->buffer_count);
1816 if (ret != 0) {
1817 DRM_DEBUG("copy %d exec entries failed %d\n",
1818 args->buffer_count, ret);
1819 drm_free_large(exec_list);
1820 drm_free_large(exec2_list);
1821 return -EFAULT;
1822 }
1823
1824 for (i = 0; i < args->buffer_count; i++) {
1825 exec2_list[i].handle = exec_list[i].handle;
1826 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1827 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1828 exec2_list[i].alignment = exec_list[i].alignment;
1829 exec2_list[i].offset = exec_list[i].offset;
1830 if (INTEL_GEN(to_i915(dev)) < 4)
1831 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1832 else
1833 exec2_list[i].flags = 0;
1834 }
1835
1836 exec2.buffers_ptr = args->buffers_ptr;
1837 exec2.buffer_count = args->buffer_count;
1838 exec2.batch_start_offset = args->batch_start_offset;
1839 exec2.batch_len = args->batch_len;
1840 exec2.DR1 = args->DR1;
1841 exec2.DR4 = args->DR4;
1842 exec2.num_cliprects = args->num_cliprects;
1843 exec2.cliprects_ptr = args->cliprects_ptr;
1844 exec2.flags = I915_EXEC_RENDER;
1845 i915_execbuffer2_set_context_id(exec2, 0);
1846
1847 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1848 if (!ret) {
1849 struct drm_i915_gem_exec_object __user *user_exec_list =
1850 u64_to_user_ptr(args->buffers_ptr);
1851
1852 /* Copy the new buffer offsets back to the user's exec list. */
1853 for (i = 0; i < args->buffer_count; i++) {
1854 exec2_list[i].offset =
1855 gen8_canonical_addr(exec2_list[i].offset);
1856 ret = __copy_to_user(&user_exec_list[i].offset,
1857 &exec2_list[i].offset,
1858 sizeof(user_exec_list[i].offset));
1859 if (ret) {
1860 ret = -EFAULT;
1861 DRM_DEBUG("failed to copy %d exec entries "
1862 "back to user (%d)\n",
1863 args->buffer_count, ret);
1864 break;
1865 }
1866 }
1867 }
1868
1869 drm_free_large(exec_list);
1870 drm_free_large(exec2_list);
1871 return ret;
1872 }
1873
1874 int
1875 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1876 struct drm_file *file)
1877 {
1878 struct drm_i915_gem_execbuffer2 *args = data;
1879 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1880 int ret;
1881
1882 if (args->buffer_count < 1 ||
1883 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1884 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1885 return -EINVAL;
1886 }
1887
1888 if (args->rsvd2 != 0) {
1889 DRM_DEBUG("dirty rvsd2 field\n");
1890 return -EINVAL;
1891 }
1892
1893 exec2_list = drm_malloc_gfp(args->buffer_count,
1894 sizeof(*exec2_list),
1895 GFP_TEMPORARY);
1896 if (exec2_list == NULL) {
1897 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1898 args->buffer_count);
1899 return -ENOMEM;
1900 }
1901 ret = copy_from_user(exec2_list,
1902 u64_to_user_ptr(args->buffers_ptr),
1903 sizeof(*exec2_list) * args->buffer_count);
1904 if (ret != 0) {
1905 DRM_DEBUG("copy %d exec entries failed %d\n",
1906 args->buffer_count, ret);
1907 drm_free_large(exec2_list);
1908 return -EFAULT;
1909 }
1910
1911 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1912 if (!ret) {
1913 /* Copy the new buffer offsets back to the user's exec list. */
1914 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1915 u64_to_user_ptr(args->buffers_ptr);
1916 int i;
1917
1918 for (i = 0; i < args->buffer_count; i++) {
1919 exec2_list[i].offset =
1920 gen8_canonical_addr(exec2_list[i].offset);
1921 ret = __copy_to_user(&user_exec_list[i].offset,
1922 &exec2_list[i].offset,
1923 sizeof(user_exec_list[i].offset));
1924 if (ret) {
1925 ret = -EFAULT;
1926 DRM_DEBUG("failed to copy %d exec entries "
1927 "back to user\n",
1928 args->buffer_count);
1929 break;
1930 }
1931 }
1932 }
1933
1934 drm_free_large(exec2_list);
1935 return ret;
1936 }
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