2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 struct change_domains
{
37 uint32_t invalidate_domains
;
38 uint32_t flush_domains
;
43 * Set the next domain for the specified object. This
44 * may not actually perform the necessary flushing/invaliding though,
45 * as that may want to be batched with other set_domain operations
47 * This is (we hope) the only really tricky part of gem. The goal
48 * is fairly simple -- track which caches hold bits of the object
49 * and make sure they remain coherent. A few concrete examples may
50 * help to explain how it works. For shorthand, we use the notation
51 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
52 * a pair of read and write domain masks.
54 * Case 1: the batch buffer
60 * 5. Unmapped from GTT
63 * Let's take these a step at a time
66 * Pages allocated from the kernel may still have
67 * cache contents, so we set them to (CPU, CPU) always.
68 * 2. Written by CPU (using pwrite)
69 * The pwrite function calls set_domain (CPU, CPU) and
70 * this function does nothing (as nothing changes)
72 * This function asserts that the object is not
73 * currently in any GPU-based read or write domains
75 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
76 * As write_domain is zero, this function adds in the
77 * current read domains (CPU+COMMAND, 0).
78 * flush_domains is set to CPU.
79 * invalidate_domains is set to COMMAND
80 * clflush is run to get data out of the CPU caches
81 * then i915_dev_set_domain calls i915_gem_flush to
82 * emit an MI_FLUSH and drm_agp_chipset_flush
83 * 5. Unmapped from GTT
84 * i915_gem_object_unbind calls set_domain (CPU, CPU)
85 * flush_domains and invalidate_domains end up both zero
86 * so no flushing/invalidating happens
90 * Case 2: The shared render buffer
94 * 3. Read/written by GPU
95 * 4. set_domain to (CPU,CPU)
96 * 5. Read/written by CPU
97 * 6. Read/written by GPU
100 * Same as last example, (CPU, CPU)
102 * Nothing changes (assertions find that it is not in the GPU)
103 * 3. Read/written by GPU
104 * execbuffer calls set_domain (RENDER, RENDER)
105 * flush_domains gets CPU
106 * invalidate_domains gets GPU
108 * MI_FLUSH and drm_agp_chipset_flush
109 * 4. set_domain (CPU, CPU)
110 * flush_domains gets GPU
111 * invalidate_domains gets CPU
112 * wait_rendering (obj) to make sure all drawing is complete.
113 * This will include an MI_FLUSH to get the data from GPU
115 * clflush (obj) to invalidate the CPU cache
116 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
117 * 5. Read/written by CPU
118 * cache lines are loaded and dirtied
119 * 6. Read written by GPU
120 * Same as last GPU access
122 * Case 3: The constant buffer
127 * 4. Updated (written) by CPU again
136 * flush_domains = CPU
137 * invalidate_domains = RENDER
140 * drm_agp_chipset_flush
141 * 4. Updated (written) by CPU again
143 * flush_domains = 0 (no previous write domain)
144 * invalidate_domains = 0 (no new read domains)
147 * flush_domains = CPU
148 * invalidate_domains = RENDER
151 * drm_agp_chipset_flush
154 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object
*obj
,
155 struct intel_ring_buffer
*ring
,
156 struct change_domains
*cd
)
158 uint32_t invalidate_domains
= 0, flush_domains
= 0;
161 * If the object isn't moving to a new write domain,
162 * let the object stay in multiple read domains
164 if (obj
->base
.pending_write_domain
== 0)
165 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
168 * Flush the current write domain if
169 * the new read domains don't match. Invalidate
170 * any read domains which differ from the old
173 if (obj
->base
.write_domain
&&
174 (((obj
->base
.write_domain
!= obj
->base
.pending_read_domains
||
175 obj
->ring
!= ring
)) ||
176 (obj
->fenced_gpu_access
&& !obj
->pending_fenced_gpu_access
))) {
177 flush_domains
|= obj
->base
.write_domain
;
178 invalidate_domains
|=
179 obj
->base
.pending_read_domains
& ~obj
->base
.write_domain
;
182 * Invalidate any read caches which may have
183 * stale data. That is, any new read domains.
185 invalidate_domains
|= obj
->base
.pending_read_domains
& ~obj
->base
.read_domains
;
186 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
187 i915_gem_clflush_object(obj
);
189 /* blow away mappings if mapped through GTT */
190 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
191 i915_gem_release_mmap(obj
);
193 /* The actual obj->write_domain will be updated with
194 * pending_write_domain after we emit the accumulated flush for all
195 * of our domain changes in execbuffers (which clears objects'
196 * write_domains). So if we have a current write domain that we
197 * aren't changing, set pending_write_domain to that.
199 if (flush_domains
== 0 && obj
->base
.pending_write_domain
== 0)
200 obj
->base
.pending_write_domain
= obj
->base
.write_domain
;
202 cd
->invalidate_domains
|= invalidate_domains
;
203 cd
->flush_domains
|= flush_domains
;
204 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
205 cd
->flush_rings
|= obj
->ring
->id
;
206 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
207 cd
->flush_rings
|= ring
->id
;
212 struct hlist_head buckets
[0];
215 static struct eb_objects
*
218 struct eb_objects
*eb
;
219 int count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
222 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
223 sizeof(struct eb_objects
),
233 eb_reset(struct eb_objects
*eb
)
235 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
239 eb_add_object(struct eb_objects
*eb
, struct drm_i915_gem_object
*obj
)
241 hlist_add_head(&obj
->exec_node
,
242 &eb
->buckets
[obj
->exec_handle
& eb
->and]);
245 static struct drm_i915_gem_object
*
246 eb_get_object(struct eb_objects
*eb
, unsigned long handle
)
248 struct hlist_head
*head
;
249 struct hlist_node
*node
;
250 struct drm_i915_gem_object
*obj
;
252 head
= &eb
->buckets
[handle
& eb
->and];
253 hlist_for_each(node
, head
) {
254 obj
= hlist_entry(node
, struct drm_i915_gem_object
, exec_node
);
255 if (obj
->exec_handle
== handle
)
263 eb_destroy(struct eb_objects
*eb
)
269 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
270 struct eb_objects
*eb
,
271 struct drm_i915_gem_relocation_entry
*reloc
)
273 struct drm_device
*dev
= obj
->base
.dev
;
274 struct drm_gem_object
*target_obj
;
275 uint32_t target_offset
;
278 /* we've already hold a reference to all valid objects */
279 target_obj
= &eb_get_object(eb
, reloc
->target_handle
)->base
;
280 if (unlikely(target_obj
== NULL
))
283 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
285 /* The target buffer should have appeared before us in the
286 * exec_object list, so it should have a GTT space bound by now.
288 if (unlikely(target_offset
== 0)) {
289 DRM_ERROR("No GTT space found for object %d\n",
290 reloc
->target_handle
);
294 /* Validate that the target is in a valid r/w GPU domain */
295 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
296 DRM_ERROR("reloc with multiple write domains: "
297 "obj %p target %d offset %d "
298 "read %08x write %08x",
299 obj
, reloc
->target_handle
,
302 reloc
->write_domain
);
305 if (unlikely((reloc
->write_domain
| reloc
->read_domains
) & I915_GEM_DOMAIN_CPU
)) {
306 DRM_ERROR("reloc with read/write CPU domains: "
307 "obj %p target %d offset %d "
308 "read %08x write %08x",
309 obj
, reloc
->target_handle
,
312 reloc
->write_domain
);
315 if (unlikely(reloc
->write_domain
&& target_obj
->pending_write_domain
&&
316 reloc
->write_domain
!= target_obj
->pending_write_domain
)) {
317 DRM_ERROR("Write domain conflict: "
318 "obj %p target %d offset %d "
319 "new %08x old %08x\n",
320 obj
, reloc
->target_handle
,
323 target_obj
->pending_write_domain
);
327 target_obj
->pending_read_domains
|= reloc
->read_domains
;
328 target_obj
->pending_write_domain
|= reloc
->write_domain
;
330 /* If the relocation already has the right value in it, no
331 * more work needs to be done.
333 if (target_offset
== reloc
->presumed_offset
)
336 /* Check that the relocation address is valid... */
337 if (unlikely(reloc
->offset
> obj
->base
.size
- 4)) {
338 DRM_ERROR("Relocation beyond object bounds: "
339 "obj %p target %d offset %d size %d.\n",
340 obj
, reloc
->target_handle
,
342 (int) obj
->base
.size
);
345 if (unlikely(reloc
->offset
& 3)) {
346 DRM_ERROR("Relocation not 4-byte aligned: "
347 "obj %p target %d offset %d.\n",
348 obj
, reloc
->target_handle
,
349 (int) reloc
->offset
);
353 /* and points to somewhere within the target object. */
354 if (unlikely(reloc
->delta
>= target_obj
->size
)) {
355 DRM_ERROR("Relocation beyond target object bounds: "
356 "obj %p target %d delta %d size %d.\n",
357 obj
, reloc
->target_handle
,
359 (int) target_obj
->size
);
363 reloc
->delta
+= target_offset
;
364 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
365 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
368 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
369 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
370 kunmap_atomic(vaddr
);
372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
373 uint32_t __iomem
*reloc_entry
;
374 void __iomem
*reloc_page
;
376 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
380 /* Map the page containing the relocation we're going to perform. */
381 reloc
->offset
+= obj
->gtt_offset
;
382 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
383 reloc
->offset
& PAGE_MASK
);
384 reloc_entry
= (uint32_t __iomem
*)
385 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
386 iowrite32(reloc
->delta
, reloc_entry
);
387 io_mapping_unmap_atomic(reloc_page
);
390 /* and update the user's relocation entry */
391 reloc
->presumed_offset
= target_offset
;
397 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
398 struct eb_objects
*eb
)
400 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
401 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
404 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
405 for (i
= 0; i
< entry
->relocation_count
; i
++) {
406 struct drm_i915_gem_relocation_entry reloc
;
408 if (__copy_from_user_inatomic(&reloc
,
413 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &reloc
);
417 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
418 &reloc
.presumed_offset
,
419 sizeof(reloc
.presumed_offset
)))
427 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
428 struct eb_objects
*eb
,
429 struct drm_i915_gem_relocation_entry
*relocs
)
431 const struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
434 for (i
= 0; i
< entry
->relocation_count
; i
++) {
435 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &relocs
[i
]);
444 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
445 struct eb_objects
*eb
,
446 struct list_head
*objects
)
448 struct drm_i915_gem_object
*obj
;
451 list_for_each_entry(obj
, objects
, exec_list
) {
452 ret
= i915_gem_execbuffer_relocate_object(obj
, eb
);
461 i915_gem_execbuffer_reserve(struct intel_ring_buffer
*ring
,
462 struct drm_file
*file
,
463 struct list_head
*objects
)
465 struct drm_i915_gem_object
*obj
;
467 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
468 struct list_head ordered_objects
;
470 INIT_LIST_HEAD(&ordered_objects
);
471 while (!list_empty(objects
)) {
472 struct drm_i915_gem_exec_object2
*entry
;
473 bool need_fence
, need_mappable
;
475 obj
= list_first_entry(objects
,
476 struct drm_i915_gem_object
,
478 entry
= obj
->exec_entry
;
481 has_fenced_gpu_access
&&
482 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
483 obj
->tiling_mode
!= I915_TILING_NONE
;
485 entry
->relocation_count
? true : need_fence
;
488 list_move(&obj
->exec_list
, &ordered_objects
);
490 list_move_tail(&obj
->exec_list
, &ordered_objects
);
492 obj
->base
.pending_read_domains
= 0;
493 obj
->base
.pending_write_domain
= 0;
495 list_splice(&ordered_objects
, objects
);
497 /* Attempt to pin all of the buffers into the GTT.
498 * This is done in 3 phases:
500 * 1a. Unbind all objects that do not match the GTT constraints for
501 * the execbuffer (fenceable, mappable, alignment etc).
502 * 1b. Increment pin count for already bound objects.
503 * 2. Bind new objects.
504 * 3. Decrement pin count.
506 * This avoid unnecessary unbinding of later objects in order to makr
507 * room for the earlier objects *unless* we need to defragment.
513 /* Unbind any ill-fitting objects or pin. */
514 list_for_each_entry(obj
, objects
, exec_list
) {
515 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
516 bool need_fence
, need_mappable
;
521 has_fenced_gpu_access
&&
522 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
523 obj
->tiling_mode
!= I915_TILING_NONE
;
525 entry
->relocation_count
? true : need_fence
;
527 if ((entry
->alignment
&& obj
->gtt_offset
& (entry
->alignment
- 1)) ||
528 (need_mappable
&& !obj
->map_and_fenceable
))
529 ret
= i915_gem_object_unbind(obj
);
531 ret
= i915_gem_object_pin(obj
,
540 /* Bind fresh objects */
541 list_for_each_entry(obj
, objects
, exec_list
) {
542 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
546 has_fenced_gpu_access
&&
547 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
548 obj
->tiling_mode
!= I915_TILING_NONE
;
550 if (!obj
->gtt_space
) {
552 entry
->relocation_count
? true : need_fence
;
554 ret
= i915_gem_object_pin(obj
,
561 if (has_fenced_gpu_access
) {
563 ret
= i915_gem_object_get_fence(obj
, ring
, 1);
566 } else if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
567 obj
->tiling_mode
== I915_TILING_NONE
) {
569 ret
= i915_gem_object_put_fence(obj
);
573 obj
->pending_fenced_gpu_access
= need_fence
;
576 entry
->offset
= obj
->gtt_offset
;
579 /* Decrement pin count for bound objects */
580 list_for_each_entry(obj
, objects
, exec_list
) {
582 i915_gem_object_unpin(obj
);
585 if (ret
!= -ENOSPC
|| retry
> 1)
588 /* First attempt, just clear anything that is purgeable.
589 * Second attempt, clear the entire GTT.
591 ret
= i915_gem_evict_everything(ring
->dev
, retry
== 0);
599 obj
= list_entry(obj
->exec_list
.prev
,
600 struct drm_i915_gem_object
,
602 while (objects
!= &obj
->exec_list
) {
604 i915_gem_object_unpin(obj
);
606 obj
= list_entry(obj
->exec_list
.prev
,
607 struct drm_i915_gem_object
,
615 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
616 struct drm_file
*file
,
617 struct intel_ring_buffer
*ring
,
618 struct list_head
*objects
,
619 struct eb_objects
*eb
,
620 struct drm_i915_gem_exec_object2
*exec
,
623 struct drm_i915_gem_relocation_entry
*reloc
;
624 struct drm_i915_gem_object
*obj
;
628 /* We may process another execbuffer during the unlock... */
629 while (!list_empty(objects
)) {
630 obj
= list_first_entry(objects
,
631 struct drm_i915_gem_object
,
633 list_del_init(&obj
->exec_list
);
634 drm_gem_object_unreference(&obj
->base
);
637 mutex_unlock(&dev
->struct_mutex
);
640 for (i
= 0; i
< count
; i
++)
641 total
+= exec
[i
].relocation_count
;
643 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
644 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
645 if (reloc
== NULL
|| reloc_offset
== NULL
) {
646 drm_free_large(reloc
);
647 drm_free_large(reloc_offset
);
648 mutex_lock(&dev
->struct_mutex
);
653 for (i
= 0; i
< count
; i
++) {
654 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
656 user_relocs
= (void __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
658 if (copy_from_user(reloc
+total
, user_relocs
,
659 exec
[i
].relocation_count
* sizeof(*reloc
))) {
661 mutex_lock(&dev
->struct_mutex
);
665 reloc_offset
[i
] = total
;
666 total
+= exec
[i
].relocation_count
;
669 ret
= i915_mutex_lock_interruptible(dev
);
671 mutex_lock(&dev
->struct_mutex
);
675 /* reacquire the objects */
677 for (i
= 0; i
< count
; i
++) {
678 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
681 DRM_ERROR("Invalid object handle %d at index %d\n",
687 list_add_tail(&obj
->exec_list
, objects
);
688 obj
->exec_handle
= exec
[i
].handle
;
689 obj
->exec_entry
= &exec
[i
];
690 eb_add_object(eb
, obj
);
693 ret
= i915_gem_execbuffer_reserve(ring
, file
, objects
);
697 list_for_each_entry(obj
, objects
, exec_list
) {
698 int offset
= obj
->exec_entry
- exec
;
699 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, eb
,
700 reloc
+ reloc_offset
[offset
]);
705 /* Leave the user relocations as are, this is the painfully slow path,
706 * and we want to avoid the complication of dropping the lock whilst
707 * having buffers reserved in the aperture and so causing spurious
708 * ENOSPC for random operations.
712 drm_free_large(reloc
);
713 drm_free_large(reloc_offset
);
718 i915_gem_execbuffer_flush(struct drm_device
*dev
,
719 uint32_t invalidate_domains
,
720 uint32_t flush_domains
,
721 uint32_t flush_rings
)
723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
726 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
727 intel_gtt_chipset_flush();
729 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
732 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
733 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
734 if (flush_rings
& (1 << i
)) {
735 ret
= i915_gem_flush_ring(&dev_priv
->ring
[i
],
747 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object
*obj
,
748 struct intel_ring_buffer
*to
)
750 struct intel_ring_buffer
*from
= obj
->ring
;
754 if (from
== NULL
|| to
== from
)
757 /* XXX gpu semaphores are currently causing hard hangs on SNB mobile */
758 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6 || IS_MOBILE(obj
->base
.dev
))
759 return i915_gem_object_wait_rendering(obj
, true);
761 idx
= intel_ring_sync_index(from
, to
);
763 seqno
= obj
->last_rendering_seqno
;
764 if (seqno
<= from
->sync_seqno
[idx
])
767 if (seqno
== from
->outstanding_lazy_request
) {
768 struct drm_i915_gem_request
*request
;
770 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
774 ret
= i915_add_request(from
, NULL
, request
);
780 seqno
= request
->seqno
;
783 from
->sync_seqno
[idx
] = seqno
;
784 return intel_ring_sync(to
, from
, seqno
- 1);
788 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer
*ring
,
789 struct list_head
*objects
)
791 struct drm_i915_gem_object
*obj
;
792 struct change_domains cd
;
795 cd
.invalidate_domains
= 0;
796 cd
.flush_domains
= 0;
798 list_for_each_entry(obj
, objects
, exec_list
)
799 i915_gem_object_set_to_gpu_domain(obj
, ring
, &cd
);
801 if (cd
.invalidate_domains
| cd
.flush_domains
) {
802 ret
= i915_gem_execbuffer_flush(ring
->dev
,
803 cd
.invalidate_domains
,
810 list_for_each_entry(obj
, objects
, exec_list
) {
811 ret
= i915_gem_execbuffer_sync_rings(obj
, ring
);
820 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
822 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
826 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
831 for (i
= 0; i
< count
; i
++) {
832 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
833 int length
; /* limited by fault_in_pages_readable() */
835 /* First check for malicious input causing overflow */
836 if (exec
[i
].relocation_count
>
837 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
840 length
= exec
[i
].relocation_count
*
841 sizeof(struct drm_i915_gem_relocation_entry
);
842 if (!access_ok(VERIFY_READ
, ptr
, length
))
845 /* we may also need to update the presumed offsets */
846 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
849 if (fault_in_pages_readable(ptr
, length
))
857 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer
*ring
,
858 struct list_head
*objects
)
860 struct drm_i915_gem_object
*obj
;
863 /* Check for any pending flips. As we only maintain a flip queue depth
864 * of 1, we can simply insert a WAIT for the next display flip prior
865 * to executing the batch and avoid stalling the CPU.
868 list_for_each_entry(obj
, objects
, exec_list
) {
869 if (obj
->base
.write_domain
)
870 flips
|= atomic_read(&obj
->pending_flip
);
873 int plane
, flip_mask
, ret
;
875 for (plane
= 0; flips
>> plane
; plane
++) {
876 if (((flips
>> plane
) & 1) == 0)
880 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
882 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
884 ret
= intel_ring_begin(ring
, 2);
888 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
889 intel_ring_emit(ring
, MI_NOOP
);
890 intel_ring_advance(ring
);
898 i915_gem_execbuffer_move_to_active(struct list_head
*objects
,
899 struct intel_ring_buffer
*ring
,
902 struct drm_i915_gem_object
*obj
;
904 list_for_each_entry(obj
, objects
, exec_list
) {
905 u32 old_read
= obj
->base
.read_domains
;
906 u32 old_write
= obj
->base
.write_domain
;
909 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
910 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
911 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
913 i915_gem_object_move_to_active(obj
, ring
, seqno
);
914 if (obj
->base
.write_domain
) {
916 obj
->pending_gpu_write
= true;
917 list_move_tail(&obj
->gpu_write_list
,
918 &ring
->gpu_write_list
);
919 intel_mark_busy(ring
->dev
, obj
);
922 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
927 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
928 struct drm_file
*file
,
929 struct intel_ring_buffer
*ring
)
931 struct drm_i915_gem_request
*request
;
935 * Ensure that the commands in the batch buffer are
936 * finished before the interrupt fires.
938 * The sampler always gets flushed on i965 (sigh).
940 invalidate
= I915_GEM_DOMAIN_COMMAND
;
941 if (INTEL_INFO(dev
)->gen
>= 4)
942 invalidate
|= I915_GEM_DOMAIN_SAMPLER
;
943 if (ring
->flush(ring
, invalidate
, 0)) {
944 i915_gem_next_request_seqno(ring
);
948 /* Add a breadcrumb for the completion of the batch buffer */
949 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
950 if (request
== NULL
|| i915_add_request(ring
, file
, request
)) {
951 i915_gem_next_request_seqno(ring
);
957 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
958 struct drm_file
*file
,
959 struct drm_i915_gem_execbuffer2
*args
,
960 struct drm_i915_gem_exec_object2
*exec
)
962 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
963 struct list_head objects
;
964 struct eb_objects
*eb
;
965 struct drm_i915_gem_object
*batch_obj
;
966 struct drm_clip_rect
*cliprects
= NULL
;
967 struct intel_ring_buffer
*ring
;
968 u32 exec_start
, exec_len
;
972 if (!i915_gem_check_execbuffer(args
)) {
973 DRM_ERROR("execbuf with invalid offset/length\n");
977 ret
= validate_exec_list(exec
, args
->buffer_count
);
981 switch (args
->flags
& I915_EXEC_RING_MASK
) {
982 case I915_EXEC_DEFAULT
:
983 case I915_EXEC_RENDER
:
984 ring
= &dev_priv
->ring
[RCS
];
988 DRM_ERROR("execbuf with invalid ring (BSD)\n");
991 ring
= &dev_priv
->ring
[VCS
];
995 DRM_ERROR("execbuf with invalid ring (BLT)\n");
998 ring
= &dev_priv
->ring
[BCS
];
1001 DRM_ERROR("execbuf with unknown ring: %d\n",
1002 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1006 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1008 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1009 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1010 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1011 if (ring
== &dev_priv
->ring
[RCS
] &&
1012 mode
!= dev_priv
->relative_constants_mode
) {
1013 if (INTEL_INFO(dev
)->gen
< 4)
1016 if (INTEL_INFO(dev
)->gen
> 5 &&
1017 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
)
1020 ret
= intel_ring_begin(ring
, 4);
1024 intel_ring_emit(ring
, MI_NOOP
);
1025 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1026 intel_ring_emit(ring
, INSTPM
);
1027 intel_ring_emit(ring
,
1028 I915_EXEC_CONSTANTS_MASK
<< 16 | mode
);
1029 intel_ring_advance(ring
);
1031 dev_priv
->relative_constants_mode
= mode
;
1035 DRM_ERROR("execbuf with unknown constants: %d\n", mode
);
1039 if (args
->buffer_count
< 1) {
1040 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1044 if (args
->num_cliprects
!= 0) {
1045 if (ring
!= &dev_priv
->ring
[RCS
]) {
1046 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1050 cliprects
= kmalloc(args
->num_cliprects
* sizeof(*cliprects
),
1052 if (cliprects
== NULL
) {
1057 if (copy_from_user(cliprects
,
1058 (struct drm_clip_rect __user
*)(uintptr_t)
1059 args
->cliprects_ptr
,
1060 sizeof(*cliprects
)*args
->num_cliprects
)) {
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 if (dev_priv
->mm
.suspended
) {
1071 mutex_unlock(&dev
->struct_mutex
);
1076 eb
= eb_create(args
->buffer_count
);
1078 mutex_unlock(&dev
->struct_mutex
);
1083 /* Look up object handles */
1084 INIT_LIST_HEAD(&objects
);
1085 for (i
= 0; i
< args
->buffer_count
; i
++) {
1086 struct drm_i915_gem_object
*obj
;
1088 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
1091 DRM_ERROR("Invalid object handle %d at index %d\n",
1093 /* prevent error path from reading uninitialized data */
1098 if (!list_empty(&obj
->exec_list
)) {
1099 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1100 obj
, exec
[i
].handle
, i
);
1105 list_add_tail(&obj
->exec_list
, &objects
);
1106 obj
->exec_handle
= exec
[i
].handle
;
1107 obj
->exec_entry
= &exec
[i
];
1108 eb_add_object(eb
, obj
);
1111 /* take note of the batch buffer before we might reorder the lists */
1112 batch_obj
= list_entry(objects
.prev
,
1113 struct drm_i915_gem_object
,
1116 /* Move the objects en-masse into the GTT, evicting if necessary. */
1117 ret
= i915_gem_execbuffer_reserve(ring
, file
, &objects
);
1121 /* The objects are in their final locations, apply the relocations. */
1122 ret
= i915_gem_execbuffer_relocate(dev
, eb
, &objects
);
1124 if (ret
== -EFAULT
) {
1125 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
, ring
,
1128 args
->buffer_count
);
1129 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1135 /* Set the pending read domains for the batch buffer to COMMAND */
1136 if (batch_obj
->base
.pending_write_domain
) {
1137 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1141 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1143 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &objects
);
1147 ret
= i915_gem_execbuffer_wait_for_flips(ring
, &objects
);
1151 seqno
= i915_gem_next_request_seqno(ring
);
1152 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++) {
1153 if (seqno
< ring
->sync_seqno
[i
]) {
1154 /* The GPU can not handle its semaphore value wrapping,
1155 * so every billion or so execbuffers, we need to stall
1156 * the GPU in order to reset the counters.
1158 ret
= i915_gpu_idle(dev
);
1162 BUG_ON(ring
->sync_seqno
[i
]);
1166 trace_i915_gem_ring_dispatch(ring
, seqno
);
1168 exec_start
= batch_obj
->gtt_offset
+ args
->batch_start_offset
;
1169 exec_len
= args
->batch_len
;
1171 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1172 ret
= i915_emit_box(dev
, &cliprects
[i
],
1173 args
->DR1
, args
->DR4
);
1177 ret
= ring
->dispatch_execbuffer(ring
,
1178 exec_start
, exec_len
);
1183 ret
= ring
->dispatch_execbuffer(ring
, exec_start
, exec_len
);
1188 i915_gem_execbuffer_move_to_active(&objects
, ring
, seqno
);
1189 i915_gem_execbuffer_retire_commands(dev
, file
, ring
);
1193 while (!list_empty(&objects
)) {
1194 struct drm_i915_gem_object
*obj
;
1196 obj
= list_first_entry(&objects
,
1197 struct drm_i915_gem_object
,
1199 list_del_init(&obj
->exec_list
);
1200 drm_gem_object_unreference(&obj
->base
);
1203 mutex_unlock(&dev
->struct_mutex
);
1211 * Legacy execbuffer just creates an exec2 list from the original exec object
1212 * list array and passes it to the real function.
1215 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1216 struct drm_file
*file
)
1218 struct drm_i915_gem_execbuffer
*args
= data
;
1219 struct drm_i915_gem_execbuffer2 exec2
;
1220 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1221 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1224 if (args
->buffer_count
< 1) {
1225 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1229 /* Copy in the exec list from userland */
1230 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1231 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1232 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1233 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1234 args
->buffer_count
);
1235 drm_free_large(exec_list
);
1236 drm_free_large(exec2_list
);
1239 ret
= copy_from_user(exec_list
,
1240 (struct drm_i915_relocation_entry __user
*)
1241 (uintptr_t) args
->buffers_ptr
,
1242 sizeof(*exec_list
) * args
->buffer_count
);
1244 DRM_ERROR("copy %d exec entries failed %d\n",
1245 args
->buffer_count
, ret
);
1246 drm_free_large(exec_list
);
1247 drm_free_large(exec2_list
);
1251 for (i
= 0; i
< args
->buffer_count
; i
++) {
1252 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1253 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1254 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1255 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1256 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1257 if (INTEL_INFO(dev
)->gen
< 4)
1258 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1260 exec2_list
[i
].flags
= 0;
1263 exec2
.buffers_ptr
= args
->buffers_ptr
;
1264 exec2
.buffer_count
= args
->buffer_count
;
1265 exec2
.batch_start_offset
= args
->batch_start_offset
;
1266 exec2
.batch_len
= args
->batch_len
;
1267 exec2
.DR1
= args
->DR1
;
1268 exec2
.DR4
= args
->DR4
;
1269 exec2
.num_cliprects
= args
->num_cliprects
;
1270 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1271 exec2
.flags
= I915_EXEC_RENDER
;
1273 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1275 /* Copy the new buffer offsets back to the user's exec list. */
1276 for (i
= 0; i
< args
->buffer_count
; i
++)
1277 exec_list
[i
].offset
= exec2_list
[i
].offset
;
1278 /* ... and back out to userspace */
1279 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1280 (uintptr_t) args
->buffers_ptr
,
1282 sizeof(*exec_list
) * args
->buffer_count
);
1285 DRM_ERROR("failed to copy %d exec entries "
1286 "back to user (%d)\n",
1287 args
->buffer_count
, ret
);
1291 drm_free_large(exec_list
);
1292 drm_free_large(exec2_list
);
1297 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1298 struct drm_file
*file
)
1300 struct drm_i915_gem_execbuffer2
*args
= data
;
1301 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1304 if (args
->buffer_count
< 1) {
1305 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
1309 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1310 if (exec2_list
== NULL
) {
1311 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1312 args
->buffer_count
);
1315 ret
= copy_from_user(exec2_list
,
1316 (struct drm_i915_relocation_entry __user
*)
1317 (uintptr_t) args
->buffers_ptr
,
1318 sizeof(*exec2_list
) * args
->buffer_count
);
1320 DRM_ERROR("copy %d exec entries failed %d\n",
1321 args
->buffer_count
, ret
);
1322 drm_free_large(exec2_list
);
1326 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1328 /* Copy the new buffer offsets back to the user's exec list. */
1329 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1330 (uintptr_t) args
->buffers_ptr
,
1332 sizeof(*exec2_list
) * args
->buffer_count
);
1335 DRM_ERROR("failed to copy %d exec entries "
1336 "back to user (%d)\n",
1337 args
->buffer_count
, ret
);
1341 drm_free_large(exec2_list
);