2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35 #include <linux/uaccess.h>
37 #define __EXEC_OBJECT_HAS_PIN (1<<31)
38 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41 #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
43 #define BATCH_OFFSET_BIAS (256*1024)
45 struct i915_execbuffer_params
{
46 struct drm_device
*dev
;
47 struct drm_file
*file
;
49 u32 args_batch_start_offset
;
50 u32 batch_obj_vm_offset
;
51 struct intel_engine_cs
*engine
;
52 struct drm_i915_gem_object
*batch_obj
;
53 struct i915_gem_context
*ctx
;
54 struct drm_i915_gem_request
*request
;
58 struct list_head vmas
;
61 struct i915_vma
*lut
[0];
62 struct hlist_head buckets
[0];
66 static struct eb_vmas
*
67 eb_create(struct drm_i915_gem_execbuffer2
*args
)
69 struct eb_vmas
*eb
= NULL
;
71 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
72 unsigned size
= args
->buffer_count
;
73 size
*= sizeof(struct i915_vma
*);
74 size
+= sizeof(struct eb_vmas
);
75 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
79 unsigned size
= args
->buffer_count
;
80 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
81 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
82 while (count
> 2*size
)
84 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
85 sizeof(struct eb_vmas
),
92 eb
->and = -args
->buffer_count
;
94 INIT_LIST_HEAD(&eb
->vmas
);
99 eb_reset(struct eb_vmas
*eb
)
102 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
106 eb_lookup_vmas(struct eb_vmas
*eb
,
107 struct drm_i915_gem_exec_object2
*exec
,
108 const struct drm_i915_gem_execbuffer2
*args
,
109 struct i915_address_space
*vm
,
110 struct drm_file
*file
)
112 struct drm_i915_gem_object
*obj
;
113 struct list_head objects
;
116 INIT_LIST_HEAD(&objects
);
117 spin_lock(&file
->table_lock
);
118 /* Grab a reference to the object and release the lock so we can lookup
119 * or create the VMA without using GFP_ATOMIC */
120 for (i
= 0; i
< args
->buffer_count
; i
++) {
121 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
123 spin_unlock(&file
->table_lock
);
124 DRM_DEBUG("Invalid object handle %d at index %d\n",
130 if (!list_empty(&obj
->obj_exec_link
)) {
131 spin_unlock(&file
->table_lock
);
132 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
133 obj
, exec
[i
].handle
, i
);
138 i915_gem_object_get(obj
);
139 list_add_tail(&obj
->obj_exec_link
, &objects
);
141 spin_unlock(&file
->table_lock
);
144 while (!list_empty(&objects
)) {
145 struct i915_vma
*vma
;
147 obj
= list_first_entry(&objects
,
148 struct drm_i915_gem_object
,
152 * NOTE: We can leak any vmas created here when something fails
153 * later on. But that's no issue since vma_unbind can deal with
154 * vmas which are not actually bound. And since only
155 * lookup_or_create exists as an interface to get at the vma
156 * from the (obj, vm) we don't run the risk of creating
157 * duplicated vmas for the same vm.
159 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
161 DRM_DEBUG("Failed to lookup VMA\n");
166 /* Transfer ownership from the objects list to the vmas list. */
167 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
168 list_del_init(&obj
->obj_exec_link
);
170 vma
->exec_entry
= &exec
[i
];
174 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
175 vma
->exec_handle
= handle
;
176 hlist_add_head(&vma
->exec_node
,
177 &eb
->buckets
[handle
& eb
->and]);
186 while (!list_empty(&objects
)) {
187 obj
= list_first_entry(&objects
,
188 struct drm_i915_gem_object
,
190 list_del_init(&obj
->obj_exec_link
);
191 i915_gem_object_put(obj
);
194 * Objects already transfered to the vmas list will be unreferenced by
201 static inline struct i915_vma
*
202 eb_get_batch_vma(struct eb_vmas
*eb
)
204 /* The batch is always the LAST item in the VMA list */
205 struct i915_vma
*vma
= list_last_entry(&eb
->vmas
, typeof(*vma
), exec_list
);
210 static struct drm_i915_gem_object
*
211 eb_get_batch(struct eb_vmas
*eb
)
213 struct i915_vma
*vma
= eb_get_batch_vma(eb
);
216 * SNA is doing fancy tricks with compressing batch buffers, which leads
217 * to negative relocation deltas. Usually that works out ok since the
218 * relocate address is still positive, except when the batch is placed
219 * very low in the GTT. Ensure this doesn't happen.
221 * Note that actual hangs have only been observed on gen7, but for
222 * paranoia do it everywhere.
224 if ((vma
->exec_entry
->flags
& EXEC_OBJECT_PINNED
) == 0)
225 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
230 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
233 if (handle
>= -eb
->and)
235 return eb
->lut
[handle
];
237 struct hlist_head
*head
;
238 struct i915_vma
*vma
;
240 head
= &eb
->buckets
[handle
& eb
->and];
241 hlist_for_each_entry(vma
, head
, exec_node
) {
242 if (vma
->exec_handle
== handle
)
250 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
252 struct drm_i915_gem_exec_object2
*entry
;
253 struct drm_i915_gem_object
*obj
= vma
->obj
;
255 if (!drm_mm_node_allocated(&vma
->node
))
258 entry
= vma
->exec_entry
;
260 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
261 i915_gem_object_unpin_fence(obj
);
263 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
266 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
269 static void eb_destroy(struct eb_vmas
*eb
)
271 while (!list_empty(&eb
->vmas
)) {
272 struct i915_vma
*vma
;
274 vma
= list_first_entry(&eb
->vmas
,
277 list_del_init(&vma
->exec_list
);
278 i915_gem_execbuffer_unreserve_vma(vma
);
279 i915_gem_object_put(vma
->obj
);
284 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
286 return (HAS_LLC(obj
->base
.dev
) ||
287 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
288 obj
->cache_level
!= I915_CACHE_NONE
);
291 /* Used to convert any address to canonical form.
292 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
293 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
294 * addresses to be in a canonical form:
295 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
296 * canonical form [63:48] == [47]."
298 #define GEN8_HIGH_ADDRESS_BIT 47
299 static inline uint64_t gen8_canonical_addr(uint64_t address
)
301 return sign_extend64(address
, GEN8_HIGH_ADDRESS_BIT
);
304 static inline uint64_t gen8_noncanonical_addr(uint64_t address
)
306 return address
& ((1ULL << (GEN8_HIGH_ADDRESS_BIT
+ 1)) - 1);
309 static inline uint64_t
310 relocation_target(struct drm_i915_gem_relocation_entry
*reloc
,
311 uint64_t target_offset
)
313 return gen8_canonical_addr((int)reloc
->delta
+ target_offset
);
317 relocate_entry_cpu(struct drm_i915_gem_object
*obj
,
318 struct drm_i915_gem_relocation_entry
*reloc
,
319 uint64_t target_offset
)
321 struct drm_device
*dev
= obj
->base
.dev
;
322 uint32_t page_offset
= offset_in_page(reloc
->offset
);
323 uint64_t delta
= relocation_target(reloc
, target_offset
);
327 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
331 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
332 reloc
->offset
>> PAGE_SHIFT
));
333 *(uint32_t *)(vaddr
+ page_offset
) = lower_32_bits(delta
);
335 if (INTEL_INFO(dev
)->gen
>= 8) {
336 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
338 if (page_offset
== 0) {
339 kunmap_atomic(vaddr
);
340 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
341 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
344 *(uint32_t *)(vaddr
+ page_offset
) = upper_32_bits(delta
);
347 kunmap_atomic(vaddr
);
353 relocate_entry_gtt(struct drm_i915_gem_object
*obj
,
354 struct drm_i915_gem_relocation_entry
*reloc
,
355 uint64_t target_offset
)
357 struct drm_device
*dev
= obj
->base
.dev
;
358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
359 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
360 uint64_t delta
= relocation_target(reloc
, target_offset
);
362 void __iomem
*reloc_page
;
365 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
369 ret
= i915_gem_object_put_fence(obj
);
373 /* Map the page containing the relocation we're going to perform. */
374 offset
= i915_gem_obj_ggtt_offset(obj
);
375 offset
+= reloc
->offset
;
376 reloc_page
= io_mapping_map_atomic_wc(ggtt
->mappable
,
378 iowrite32(lower_32_bits(delta
), reloc_page
+ offset_in_page(offset
));
380 if (INTEL_INFO(dev
)->gen
>= 8) {
381 offset
+= sizeof(uint32_t);
383 if (offset_in_page(offset
) == 0) {
384 io_mapping_unmap_atomic(reloc_page
);
386 io_mapping_map_atomic_wc(ggtt
->mappable
,
390 iowrite32(upper_32_bits(delta
),
391 reloc_page
+ offset_in_page(offset
));
394 io_mapping_unmap_atomic(reloc_page
);
400 clflush_write32(void *addr
, uint32_t value
)
402 /* This is not a fast path, so KISS. */
403 drm_clflush_virt_range(addr
, sizeof(uint32_t));
404 *(uint32_t *)addr
= value
;
405 drm_clflush_virt_range(addr
, sizeof(uint32_t));
409 relocate_entry_clflush(struct drm_i915_gem_object
*obj
,
410 struct drm_i915_gem_relocation_entry
*reloc
,
411 uint64_t target_offset
)
413 struct drm_device
*dev
= obj
->base
.dev
;
414 uint32_t page_offset
= offset_in_page(reloc
->offset
);
415 uint64_t delta
= relocation_target(reloc
, target_offset
);
419 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
423 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
424 reloc
->offset
>> PAGE_SHIFT
));
425 clflush_write32(vaddr
+ page_offset
, lower_32_bits(delta
));
427 if (INTEL_INFO(dev
)->gen
>= 8) {
428 page_offset
= offset_in_page(page_offset
+ sizeof(uint32_t));
430 if (page_offset
== 0) {
431 kunmap_atomic(vaddr
);
432 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
,
433 (reloc
->offset
+ sizeof(uint32_t)) >> PAGE_SHIFT
));
436 clflush_write32(vaddr
+ page_offset
, upper_32_bits(delta
));
439 kunmap_atomic(vaddr
);
444 static bool object_is_idle(struct drm_i915_gem_object
*obj
)
446 unsigned long active
= obj
->active
;
449 for_each_active(active
, idx
) {
450 if (!i915_gem_active_is_idle(&obj
->last_read
[idx
],
451 &obj
->base
.dev
->struct_mutex
))
459 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
461 struct drm_i915_gem_relocation_entry
*reloc
)
463 struct drm_device
*dev
= obj
->base
.dev
;
464 struct drm_gem_object
*target_obj
;
465 struct drm_i915_gem_object
*target_i915_obj
;
466 struct i915_vma
*target_vma
;
467 uint64_t target_offset
;
470 /* we've already hold a reference to all valid objects */
471 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
472 if (unlikely(target_vma
== NULL
))
474 target_i915_obj
= target_vma
->obj
;
475 target_obj
= &target_vma
->obj
->base
;
477 target_offset
= gen8_canonical_addr(target_vma
->node
.start
);
479 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
480 * pipe_control writes because the gpu doesn't properly redirect them
481 * through the ppgtt for non_secure batchbuffers. */
482 if (unlikely(IS_GEN6(dev
) &&
483 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
)) {
484 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
486 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
490 /* Validate that the target is in a valid r/w GPU domain */
491 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
492 DRM_DEBUG("reloc with multiple write domains: "
493 "obj %p target %d offset %d "
494 "read %08x write %08x",
495 obj
, reloc
->target_handle
,
498 reloc
->write_domain
);
501 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
502 & ~I915_GEM_GPU_DOMAINS
)) {
503 DRM_DEBUG("reloc with read/write non-GPU domains: "
504 "obj %p target %d offset %d "
505 "read %08x write %08x",
506 obj
, reloc
->target_handle
,
509 reloc
->write_domain
);
513 target_obj
->pending_read_domains
|= reloc
->read_domains
;
514 target_obj
->pending_write_domain
|= reloc
->write_domain
;
516 /* If the relocation already has the right value in it, no
517 * more work needs to be done.
519 if (target_offset
== reloc
->presumed_offset
)
522 /* Check that the relocation address is valid... */
523 if (unlikely(reloc
->offset
>
524 obj
->base
.size
- (INTEL_INFO(dev
)->gen
>= 8 ? 8 : 4))) {
525 DRM_DEBUG("Relocation beyond object bounds: "
526 "obj %p target %d offset %d size %d.\n",
527 obj
, reloc
->target_handle
,
529 (int) obj
->base
.size
);
532 if (unlikely(reloc
->offset
& 3)) {
533 DRM_DEBUG("Relocation not 4-byte aligned: "
534 "obj %p target %d offset %d.\n",
535 obj
, reloc
->target_handle
,
536 (int) reloc
->offset
);
540 /* We can't wait for rendering with pagefaults disabled */
541 if (pagefault_disabled() && !object_is_idle(obj
))
544 if (use_cpu_reloc(obj
))
545 ret
= relocate_entry_cpu(obj
, reloc
, target_offset
);
546 else if (obj
->map_and_fenceable
)
547 ret
= relocate_entry_gtt(obj
, reloc
, target_offset
);
548 else if (static_cpu_has(X86_FEATURE_CLFLUSH
))
549 ret
= relocate_entry_clflush(obj
, reloc
, target_offset
);
551 WARN_ONCE(1, "Impossible case in relocation handling\n");
558 /* and update the user's relocation entry */
559 reloc
->presumed_offset
= target_offset
;
565 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
568 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
569 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
570 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
571 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
574 user_relocs
= u64_to_user_ptr(entry
->relocs_ptr
);
576 remain
= entry
->relocation_count
;
578 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
580 if (count
> ARRAY_SIZE(stack_reloc
))
581 count
= ARRAY_SIZE(stack_reloc
);
584 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
588 u64 offset
= r
->presumed_offset
;
590 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
);
594 if (r
->presumed_offset
!= offset
&&
595 __put_user(r
->presumed_offset
, &user_relocs
->presumed_offset
)) {
609 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
611 struct drm_i915_gem_relocation_entry
*relocs
)
613 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
616 for (i
= 0; i
< entry
->relocation_count
; i
++) {
617 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
]);
626 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
628 struct i915_vma
*vma
;
631 /* This is the fast path and we cannot handle a pagefault whilst
632 * holding the struct mutex lest the user pass in the relocations
633 * contained within a mmaped bo. For in such a case we, the page
634 * fault handler would call i915_gem_fault() and we would try to
635 * acquire the struct mutex again. Obviously this is bad and so
636 * lockdep complains vehemently.
639 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
640 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
649 static bool only_mappable_for_reloc(unsigned int flags
)
651 return (flags
& (EXEC_OBJECT_NEEDS_FENCE
| __EXEC_OBJECT_NEEDS_MAP
)) ==
652 __EXEC_OBJECT_NEEDS_MAP
;
656 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
657 struct intel_engine_cs
*engine
,
660 struct drm_i915_gem_object
*obj
= vma
->obj
;
661 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
666 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
669 if (!drm_mm_node_allocated(&vma
->node
)) {
670 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
671 * limit address to the first 4GBs for unflagged objects.
673 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0)
674 flags
|= PIN_ZONE_4G
;
675 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
676 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
677 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
678 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
679 if (entry
->flags
& EXEC_OBJECT_PINNED
)
680 flags
|= entry
->offset
| PIN_OFFSET_FIXED
;
681 if ((flags
& PIN_MAPPABLE
) == 0)
685 ret
= i915_gem_object_pin(obj
, vma
->vm
, entry
->alignment
, flags
);
686 if ((ret
== -ENOSPC
|| ret
== -E2BIG
) &&
687 only_mappable_for_reloc(entry
->flags
))
688 ret
= i915_gem_object_pin(obj
, vma
->vm
,
690 flags
& ~PIN_MAPPABLE
);
694 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
696 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
697 ret
= i915_gem_object_get_fence(obj
);
701 if (i915_gem_object_pin_fence(obj
))
702 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
705 if (entry
->offset
!= vma
->node
.start
) {
706 entry
->offset
= vma
->node
.start
;
710 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
711 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
712 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
719 need_reloc_mappable(struct i915_vma
*vma
)
721 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
723 if (entry
->relocation_count
== 0)
729 /* See also use_cpu_reloc() */
730 if (HAS_LLC(vma
->obj
->base
.dev
))
733 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
740 eb_vma_misplaced(struct i915_vma
*vma
)
742 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
743 struct drm_i915_gem_object
*obj
= vma
->obj
;
745 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !vma
->is_ggtt
);
747 if (entry
->alignment
&&
748 vma
->node
.start
& (entry
->alignment
- 1))
751 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
752 vma
->node
.start
!= entry
->offset
)
755 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
756 vma
->node
.start
< BATCH_OFFSET_BIAS
)
759 /* avoid costly ping-pong once a batch bo ended up non-mappable */
760 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&& !obj
->map_and_fenceable
)
761 return !only_mappable_for_reloc(entry
->flags
);
763 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0 &&
764 (vma
->node
.start
+ vma
->node
.size
- 1) >> 32)
771 i915_gem_execbuffer_reserve(struct intel_engine_cs
*engine
,
772 struct list_head
*vmas
,
773 struct i915_gem_context
*ctx
,
776 struct drm_i915_gem_object
*obj
;
777 struct i915_vma
*vma
;
778 struct i915_address_space
*vm
;
779 struct list_head ordered_vmas
;
780 struct list_head pinned_vmas
;
781 bool has_fenced_gpu_access
= INTEL_GEN(engine
->i915
) < 4;
784 i915_gem_retire_requests_ring(engine
);
786 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
788 INIT_LIST_HEAD(&ordered_vmas
);
789 INIT_LIST_HEAD(&pinned_vmas
);
790 while (!list_empty(vmas
)) {
791 struct drm_i915_gem_exec_object2
*entry
;
792 bool need_fence
, need_mappable
;
794 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
796 entry
= vma
->exec_entry
;
798 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
799 entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
801 if (!has_fenced_gpu_access
)
802 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
804 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
805 obj
->tiling_mode
!= I915_TILING_NONE
;
806 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
808 if (entry
->flags
& EXEC_OBJECT_PINNED
)
809 list_move_tail(&vma
->exec_list
, &pinned_vmas
);
810 else if (need_mappable
) {
811 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
812 list_move(&vma
->exec_list
, &ordered_vmas
);
814 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
816 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
817 obj
->base
.pending_write_domain
= 0;
819 list_splice(&ordered_vmas
, vmas
);
820 list_splice(&pinned_vmas
, vmas
);
822 /* Attempt to pin all of the buffers into the GTT.
823 * This is done in 3 phases:
825 * 1a. Unbind all objects that do not match the GTT constraints for
826 * the execbuffer (fenceable, mappable, alignment etc).
827 * 1b. Increment pin count for already bound objects.
828 * 2. Bind new objects.
829 * 3. Decrement pin count.
831 * This avoid unnecessary unbinding of later objects in order to make
832 * room for the earlier objects *unless* we need to defragment.
838 /* Unbind any ill-fitting objects or pin. */
839 list_for_each_entry(vma
, vmas
, exec_list
) {
840 if (!drm_mm_node_allocated(&vma
->node
))
843 if (eb_vma_misplaced(vma
))
844 ret
= i915_vma_unbind(vma
);
846 ret
= i915_gem_execbuffer_reserve_vma(vma
,
853 /* Bind fresh objects */
854 list_for_each_entry(vma
, vmas
, exec_list
) {
855 if (drm_mm_node_allocated(&vma
->node
))
858 ret
= i915_gem_execbuffer_reserve_vma(vma
, engine
,
865 if (ret
!= -ENOSPC
|| retry
++)
868 /* Decrement pin count for bound objects */
869 list_for_each_entry(vma
, vmas
, exec_list
)
870 i915_gem_execbuffer_unreserve_vma(vma
);
872 ret
= i915_gem_evict_vm(vm
, true);
879 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
880 struct drm_i915_gem_execbuffer2
*args
,
881 struct drm_file
*file
,
882 struct intel_engine_cs
*engine
,
884 struct drm_i915_gem_exec_object2
*exec
,
885 struct i915_gem_context
*ctx
)
887 struct drm_i915_gem_relocation_entry
*reloc
;
888 struct i915_address_space
*vm
;
889 struct i915_vma
*vma
;
893 unsigned count
= args
->buffer_count
;
895 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
897 /* We may process another execbuffer during the unlock... */
898 while (!list_empty(&eb
->vmas
)) {
899 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
900 list_del_init(&vma
->exec_list
);
901 i915_gem_execbuffer_unreserve_vma(vma
);
902 i915_gem_object_put(vma
->obj
);
905 mutex_unlock(&dev
->struct_mutex
);
908 for (i
= 0; i
< count
; i
++)
909 total
+= exec
[i
].relocation_count
;
911 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
912 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
913 if (reloc
== NULL
|| reloc_offset
== NULL
) {
914 drm_free_large(reloc
);
915 drm_free_large(reloc_offset
);
916 mutex_lock(&dev
->struct_mutex
);
921 for (i
= 0; i
< count
; i
++) {
922 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
923 u64 invalid_offset
= (u64
)-1;
926 user_relocs
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
928 if (copy_from_user(reloc
+total
, user_relocs
,
929 exec
[i
].relocation_count
* sizeof(*reloc
))) {
931 mutex_lock(&dev
->struct_mutex
);
935 /* As we do not update the known relocation offsets after
936 * relocating (due to the complexities in lock handling),
937 * we need to mark them as invalid now so that we force the
938 * relocation processing next time. Just in case the target
939 * object is evicted and then rebound into its old
940 * presumed_offset before the next execbuffer - if that
941 * happened we would make the mistake of assuming that the
942 * relocations were valid.
944 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
945 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
947 sizeof(invalid_offset
))) {
949 mutex_lock(&dev
->struct_mutex
);
954 reloc_offset
[i
] = total
;
955 total
+= exec
[i
].relocation_count
;
958 ret
= i915_mutex_lock_interruptible(dev
);
960 mutex_lock(&dev
->struct_mutex
);
964 /* reacquire the objects */
966 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
970 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
971 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
976 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
977 int offset
= vma
->exec_entry
- exec
;
978 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
979 reloc
+ reloc_offset
[offset
]);
984 /* Leave the user relocations as are, this is the painfully slow path,
985 * and we want to avoid the complication of dropping the lock whilst
986 * having buffers reserved in the aperture and so causing spurious
987 * ENOSPC for random operations.
991 drm_free_large(reloc
);
992 drm_free_large(reloc_offset
);
997 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req
,
998 struct list_head
*vmas
)
1000 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
1001 struct i915_vma
*vma
;
1002 uint32_t flush_domains
= 0;
1003 bool flush_chipset
= false;
1006 list_for_each_entry(vma
, vmas
, exec_list
) {
1007 struct drm_i915_gem_object
*obj
= vma
->obj
;
1009 if (obj
->active
& other_rings
) {
1010 ret
= i915_gem_object_sync(obj
, req
);
1015 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
1016 flush_chipset
|= i915_gem_clflush_object(obj
, false);
1018 flush_domains
|= obj
->base
.write_domain
;
1022 i915_gem_chipset_flush(req
->engine
->i915
);
1024 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
1027 /* Unconditionally invalidate GPU caches and TLBs. */
1028 return req
->engine
->emit_flush(req
, EMIT_INVALIDATE
);
1032 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
1034 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
1037 /* Kernel clipping was a DRI1 misfeature */
1038 if (exec
->num_cliprects
|| exec
->cliprects_ptr
)
1041 if (exec
->DR4
== 0xffffffff) {
1042 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1045 if (exec
->DR1
|| exec
->DR4
)
1048 if ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7)
1055 validate_exec_list(struct drm_device
*dev
,
1056 struct drm_i915_gem_exec_object2
*exec
,
1059 unsigned relocs_total
= 0;
1060 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
1061 unsigned invalid_flags
;
1064 /* INTERNAL flags must not overlap with external ones */
1065 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS
& ~__EXEC_OBJECT_UNKNOWN_FLAGS
);
1067 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
1068 if (USES_FULL_PPGTT(dev
))
1069 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
1071 for (i
= 0; i
< count
; i
++) {
1072 char __user
*ptr
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
1073 int length
; /* limited by fault_in_pages_readable() */
1075 if (exec
[i
].flags
& invalid_flags
)
1078 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1079 * any non-page-aligned or non-canonical addresses.
1081 if (exec
[i
].flags
& EXEC_OBJECT_PINNED
) {
1082 if (exec
[i
].offset
!=
1083 gen8_canonical_addr(exec
[i
].offset
& PAGE_MASK
))
1086 /* From drm_mm perspective address space is continuous,
1087 * so from this point we're always using non-canonical
1090 exec
[i
].offset
= gen8_noncanonical_addr(exec
[i
].offset
);
1093 if (exec
[i
].alignment
&& !is_power_of_2(exec
[i
].alignment
))
1096 /* First check for malicious input causing overflow in
1097 * the worst case where we need to allocate the entire
1098 * relocation tree as a single array.
1100 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
1102 relocs_total
+= exec
[i
].relocation_count
;
1104 length
= exec
[i
].relocation_count
*
1105 sizeof(struct drm_i915_gem_relocation_entry
);
1107 * We must check that the entire relocation array is safe
1108 * to read, but since we may need to update the presumed
1109 * offsets during execution, check for full write access.
1111 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
1114 if (likely(!i915
.prefault_disable
)) {
1115 if (fault_in_multipages_readable(ptr
, length
))
1123 static struct i915_gem_context
*
1124 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
1125 struct intel_engine_cs
*engine
, const u32 ctx_id
)
1127 struct i915_gem_context
*ctx
= NULL
;
1128 struct i915_ctx_hang_stats
*hs
;
1130 if (engine
->id
!= RCS
&& ctx_id
!= DEFAULT_CONTEXT_HANDLE
)
1131 return ERR_PTR(-EINVAL
);
1133 ctx
= i915_gem_context_lookup(file
->driver_priv
, ctx_id
);
1137 hs
= &ctx
->hang_stats
;
1139 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
1140 return ERR_PTR(-EIO
);
1146 void i915_vma_move_to_active(struct i915_vma
*vma
,
1147 struct drm_i915_gem_request
*req
,
1150 struct drm_i915_gem_object
*obj
= vma
->obj
;
1151 const unsigned int idx
= req
->engine
->id
;
1153 GEM_BUG_ON(!drm_mm_node_allocated(&vma
->node
));
1155 obj
->dirty
= 1; /* be paranoid */
1157 /* Add a reference if we're newly entering the active list. */
1158 if (obj
->active
== 0)
1159 i915_gem_object_get(obj
);
1160 obj
->active
|= 1 << idx
;
1161 i915_gem_active_set(&obj
->last_read
[idx
], req
);
1163 if (flags
& EXEC_OBJECT_WRITE
) {
1164 i915_gem_active_set(&obj
->last_write
, req
);
1166 intel_fb_obj_invalidate(obj
, ORIGIN_CS
);
1168 /* update for the implicit flush after a batch */
1169 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1172 if (flags
& EXEC_OBJECT_NEEDS_FENCE
) {
1173 i915_gem_active_set(&obj
->last_fence
, req
);
1174 if (flags
& __EXEC_OBJECT_HAS_FENCE
) {
1175 struct drm_i915_private
*dev_priv
= req
->i915
;
1177 list_move_tail(&dev_priv
->fence_regs
[obj
->fence_reg
].lru_list
,
1178 &dev_priv
->mm
.fence_list
);
1182 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
1186 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
1187 struct drm_i915_gem_request
*req
)
1189 struct i915_vma
*vma
;
1191 list_for_each_entry(vma
, vmas
, exec_list
) {
1192 struct drm_i915_gem_object
*obj
= vma
->obj
;
1193 u32 old_read
= obj
->base
.read_domains
;
1194 u32 old_write
= obj
->base
.write_domain
;
1196 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
1197 if (obj
->base
.write_domain
)
1198 vma
->exec_entry
->flags
|= EXEC_OBJECT_WRITE
;
1200 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
1201 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
1203 i915_vma_move_to_active(vma
, req
, vma
->exec_entry
->flags
);
1204 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
1209 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
)
1211 /* Add a breadcrumb for the completion of the batch buffer */
1212 __i915_add_request(params
->request
, params
->batch_obj
, true);
1216 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request
*req
)
1218 struct intel_ring
*ring
= req
->ring
;
1221 if (!IS_GEN7(req
->i915
) || req
->engine
->id
!= RCS
) {
1222 DRM_DEBUG("sol reset is gen7/rcs only\n");
1226 ret
= intel_ring_begin(req
, 4 * 3);
1230 for (i
= 0; i
< 4; i
++) {
1231 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1232 intel_ring_emit_reg(ring
, GEN7_SO_WRITE_OFFSET(i
));
1233 intel_ring_emit(ring
, 0);
1236 intel_ring_advance(ring
);
1241 static struct drm_i915_gem_object
*
1242 i915_gem_execbuffer_parse(struct intel_engine_cs
*engine
,
1243 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1245 struct drm_i915_gem_object
*batch_obj
,
1246 u32 batch_start_offset
,
1250 struct drm_i915_gem_object
*shadow_batch_obj
;
1251 struct i915_vma
*vma
;
1254 shadow_batch_obj
= i915_gem_batch_pool_get(&engine
->batch_pool
,
1255 PAGE_ALIGN(batch_len
));
1256 if (IS_ERR(shadow_batch_obj
))
1257 return shadow_batch_obj
;
1259 ret
= intel_engine_cmd_parser(engine
,
1268 ret
= i915_gem_obj_ggtt_pin(shadow_batch_obj
, 0, 0);
1272 i915_gem_object_unpin_pages(shadow_batch_obj
);
1274 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1276 vma
= i915_gem_obj_to_ggtt(shadow_batch_obj
);
1277 vma
->exec_entry
= shadow_exec_entry
;
1278 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
;
1279 i915_gem_object_get(shadow_batch_obj
);
1280 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1282 shadow_batch_obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
1284 return shadow_batch_obj
;
1287 i915_gem_object_unpin_pages(shadow_batch_obj
);
1288 if (ret
== -EACCES
) /* unhandled chained batch */
1291 return ERR_PTR(ret
);
1295 execbuf_submit(struct i915_execbuffer_params
*params
,
1296 struct drm_i915_gem_execbuffer2
*args
,
1297 struct list_head
*vmas
)
1299 struct drm_i915_private
*dev_priv
= params
->request
->i915
;
1300 u64 exec_start
, exec_len
;
1305 ret
= i915_gem_execbuffer_move_to_gpu(params
->request
, vmas
);
1309 ret
= i915_switch_context(params
->request
);
1313 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1314 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1315 switch (instp_mode
) {
1316 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1317 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1318 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1319 if (instp_mode
!= 0 && params
->engine
->id
!= RCS
) {
1320 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1324 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1325 if (INTEL_INFO(dev_priv
)->gen
< 4) {
1326 DRM_DEBUG("no rel constants on pre-gen4\n");
1330 if (INTEL_INFO(dev_priv
)->gen
> 5 &&
1331 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1332 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1336 /* The HW changed the meaning on this bit on gen6 */
1337 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1338 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1342 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1346 if (params
->engine
->id
== RCS
&&
1347 instp_mode
!= dev_priv
->relative_constants_mode
) {
1348 struct intel_ring
*ring
= params
->request
->ring
;
1350 ret
= intel_ring_begin(params
->request
, 4);
1354 intel_ring_emit(ring
, MI_NOOP
);
1355 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1356 intel_ring_emit_reg(ring
, INSTPM
);
1357 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1358 intel_ring_advance(ring
);
1360 dev_priv
->relative_constants_mode
= instp_mode
;
1363 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1364 ret
= i915_reset_gen7_sol_offsets(params
->request
);
1369 exec_len
= args
->batch_len
;
1370 exec_start
= params
->batch_obj_vm_offset
+
1371 params
->args_batch_start_offset
;
1374 exec_len
= params
->batch_obj
->base
.size
;
1376 ret
= params
->engine
->emit_bb_start(params
->request
,
1377 exec_start
, exec_len
,
1378 params
->dispatch_flags
);
1382 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1384 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1390 * Find one BSD ring to dispatch the corresponding BSD command.
1391 * The engine index is returned.
1394 gen8_dispatch_bsd_engine(struct drm_i915_private
*dev_priv
,
1395 struct drm_file
*file
)
1397 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1399 /* Check whether the file_priv has already selected one ring. */
1400 if ((int)file_priv
->bsd_engine
< 0) {
1401 /* If not, use the ping-pong mechanism to select one. */
1402 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1403 file_priv
->bsd_engine
= dev_priv
->mm
.bsd_engine_dispatch_index
;
1404 dev_priv
->mm
.bsd_engine_dispatch_index
^= 1;
1405 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1408 return file_priv
->bsd_engine
;
1411 #define I915_USER_RINGS (4)
1413 static const enum intel_engine_id user_ring_map
[I915_USER_RINGS
+ 1] = {
1414 [I915_EXEC_DEFAULT
] = RCS
,
1415 [I915_EXEC_RENDER
] = RCS
,
1416 [I915_EXEC_BLT
] = BCS
,
1417 [I915_EXEC_BSD
] = VCS
,
1418 [I915_EXEC_VEBOX
] = VECS
1421 static struct intel_engine_cs
*
1422 eb_select_engine(struct drm_i915_private
*dev_priv
,
1423 struct drm_file
*file
,
1424 struct drm_i915_gem_execbuffer2
*args
)
1426 unsigned int user_ring_id
= args
->flags
& I915_EXEC_RING_MASK
;
1427 struct intel_engine_cs
*engine
;
1429 if (user_ring_id
> I915_USER_RINGS
) {
1430 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id
);
1434 if ((user_ring_id
!= I915_EXEC_BSD
) &&
1435 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1436 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1437 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1441 if (user_ring_id
== I915_EXEC_BSD
&& HAS_BSD2(dev_priv
)) {
1442 unsigned int bsd_idx
= args
->flags
& I915_EXEC_BSD_MASK
;
1444 if (bsd_idx
== I915_EXEC_BSD_DEFAULT
) {
1445 bsd_idx
= gen8_dispatch_bsd_engine(dev_priv
, file
);
1446 } else if (bsd_idx
>= I915_EXEC_BSD_RING1
&&
1447 bsd_idx
<= I915_EXEC_BSD_RING2
) {
1448 bsd_idx
>>= I915_EXEC_BSD_SHIFT
;
1451 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1456 engine
= &dev_priv
->engine
[_VCS(bsd_idx
)];
1458 engine
= &dev_priv
->engine
[user_ring_map
[user_ring_id
]];
1461 if (!intel_engine_initialized(engine
)) {
1462 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id
);
1470 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1471 struct drm_file
*file
,
1472 struct drm_i915_gem_execbuffer2
*args
,
1473 struct drm_i915_gem_exec_object2
*exec
)
1475 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1476 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1478 struct drm_i915_gem_object
*batch_obj
;
1479 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1480 struct intel_engine_cs
*engine
;
1481 struct i915_gem_context
*ctx
;
1482 struct i915_address_space
*vm
;
1483 struct i915_execbuffer_params params_master
; /* XXX: will be removed later */
1484 struct i915_execbuffer_params
*params
= ¶ms_master
;
1485 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1490 if (!i915_gem_check_execbuffer(args
))
1493 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1498 if (args
->flags
& I915_EXEC_SECURE
) {
1499 if (!drm_is_current_master(file
) || !capable(CAP_SYS_ADMIN
))
1502 dispatch_flags
|= I915_DISPATCH_SECURE
;
1504 if (args
->flags
& I915_EXEC_IS_PINNED
)
1505 dispatch_flags
|= I915_DISPATCH_PINNED
;
1507 engine
= eb_select_engine(dev_priv
, file
, args
);
1511 if (args
->buffer_count
< 1) {
1512 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1516 if (args
->flags
& I915_EXEC_RESOURCE_STREAMER
) {
1517 if (!HAS_RESOURCE_STREAMER(dev
)) {
1518 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1521 if (engine
->id
!= RCS
) {
1522 DRM_DEBUG("RS is not available on %s\n",
1527 dispatch_flags
|= I915_DISPATCH_RS
;
1530 /* Take a local wakeref for preparing to dispatch the execbuf as
1531 * we expect to access the hardware fairly frequently in the
1532 * process. Upon first dispatch, we acquire another prolonged
1533 * wakeref that we hold until the GPU has been idle for at least
1536 intel_runtime_pm_get(dev_priv
);
1538 ret
= i915_mutex_lock_interruptible(dev
);
1542 ctx
= i915_gem_validate_context(dev
, file
, engine
, ctx_id
);
1544 mutex_unlock(&dev
->struct_mutex
);
1549 i915_gem_context_get(ctx
);
1552 vm
= &ctx
->ppgtt
->base
;
1556 memset(¶ms_master
, 0x00, sizeof(params_master
));
1558 eb
= eb_create(args
);
1560 i915_gem_context_put(ctx
);
1561 mutex_unlock(&dev
->struct_mutex
);
1566 /* Look up object handles */
1567 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1571 /* take note of the batch buffer before we might reorder the lists */
1572 batch_obj
= eb_get_batch(eb
);
1574 /* Move the objects en-masse into the GTT, evicting if necessary. */
1575 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1576 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1581 /* The objects are in their final locations, apply the relocations. */
1583 ret
= i915_gem_execbuffer_relocate(eb
);
1585 if (ret
== -EFAULT
) {
1586 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
,
1589 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1595 /* Set the pending read domains for the batch buffer to COMMAND */
1596 if (batch_obj
->base
.pending_write_domain
) {
1597 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1602 params
->args_batch_start_offset
= args
->batch_start_offset
;
1603 if (intel_engine_needs_cmd_parser(engine
) && args
->batch_len
) {
1604 struct drm_i915_gem_object
*parsed_batch_obj
;
1606 parsed_batch_obj
= i915_gem_execbuffer_parse(engine
,
1610 args
->batch_start_offset
,
1612 drm_is_current_master(file
));
1613 if (IS_ERR(parsed_batch_obj
)) {
1614 ret
= PTR_ERR(parsed_batch_obj
);
1619 * parsed_batch_obj == batch_obj means batch not fully parsed:
1620 * Accept, but don't promote to secure.
1623 if (parsed_batch_obj
!= batch_obj
) {
1625 * Batch parsed and accepted:
1627 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1628 * bit from MI_BATCH_BUFFER_START commands issued in
1629 * the dispatch_execbuffer implementations. We
1630 * specifically don't want that set on batches the
1631 * command parser has accepted.
1633 dispatch_flags
|= I915_DISPATCH_SECURE
;
1634 params
->args_batch_start_offset
= 0;
1635 batch_obj
= parsed_batch_obj
;
1639 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1641 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1642 * batch" bit. Hence we need to pin secure batches into the global gtt.
1643 * hsw should have this fixed, but bdw mucks it up again. */
1644 if (dispatch_flags
& I915_DISPATCH_SECURE
) {
1646 * So on first glance it looks freaky that we pin the batch here
1647 * outside of the reservation loop. But:
1648 * - The batch is already pinned into the relevant ppgtt, so we
1649 * already have the backing storage fully allocated.
1650 * - No other BO uses the global gtt (well contexts, but meh),
1651 * so we don't really have issues with multiple objects not
1652 * fitting due to fragmentation.
1653 * So this is actually safe.
1655 ret
= i915_gem_obj_ggtt_pin(batch_obj
, 0, 0);
1659 params
->batch_obj_vm_offset
= i915_gem_obj_ggtt_offset(batch_obj
);
1661 params
->batch_obj_vm_offset
= i915_gem_obj_offset(batch_obj
, vm
);
1663 /* Allocate a request for this batch buffer nice and early. */
1664 params
->request
= i915_gem_request_alloc(engine
, ctx
);
1665 if (IS_ERR(params
->request
)) {
1666 ret
= PTR_ERR(params
->request
);
1667 goto err_batch_unpin
;
1670 ret
= i915_gem_request_add_to_client(params
->request
, file
);
1675 * Save assorted stuff away to pass through to *_submission().
1676 * NB: This data should be 'persistent' and not local as it will
1677 * kept around beyond the duration of the IOCTL once the GPU
1678 * scheduler arrives.
1681 params
->file
= file
;
1682 params
->engine
= engine
;
1683 params
->dispatch_flags
= dispatch_flags
;
1684 params
->batch_obj
= batch_obj
;
1687 ret
= execbuf_submit(params
, args
, &eb
->vmas
);
1689 i915_gem_execbuffer_retire_commands(params
);
1693 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1694 * batch vma for correctness. For less ugly and less fragility this
1695 * needs to be adjusted to also track the ggtt batch vma properly as
1698 if (dispatch_flags
& I915_DISPATCH_SECURE
)
1699 i915_gem_object_ggtt_unpin(batch_obj
);
1702 /* the request owns the ref now */
1703 i915_gem_context_put(ctx
);
1706 mutex_unlock(&dev
->struct_mutex
);
1709 /* intel_gpu_busy should also get a ref, so it will free when the device
1710 * is really idle. */
1711 intel_runtime_pm_put(dev_priv
);
1716 * Legacy execbuffer just creates an exec2 list from the original exec object
1717 * list array and passes it to the real function.
1720 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1721 struct drm_file
*file
)
1723 struct drm_i915_gem_execbuffer
*args
= data
;
1724 struct drm_i915_gem_execbuffer2 exec2
;
1725 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1726 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1729 if (args
->buffer_count
< 1) {
1730 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1734 /* Copy in the exec list from userland */
1735 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1736 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1737 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1738 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1739 args
->buffer_count
);
1740 drm_free_large(exec_list
);
1741 drm_free_large(exec2_list
);
1744 ret
= copy_from_user(exec_list
,
1745 u64_to_user_ptr(args
->buffers_ptr
),
1746 sizeof(*exec_list
) * args
->buffer_count
);
1748 DRM_DEBUG("copy %d exec entries failed %d\n",
1749 args
->buffer_count
, ret
);
1750 drm_free_large(exec_list
);
1751 drm_free_large(exec2_list
);
1755 for (i
= 0; i
< args
->buffer_count
; i
++) {
1756 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1757 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1758 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1759 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1760 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1761 if (INTEL_INFO(dev
)->gen
< 4)
1762 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1764 exec2_list
[i
].flags
= 0;
1767 exec2
.buffers_ptr
= args
->buffers_ptr
;
1768 exec2
.buffer_count
= args
->buffer_count
;
1769 exec2
.batch_start_offset
= args
->batch_start_offset
;
1770 exec2
.batch_len
= args
->batch_len
;
1771 exec2
.DR1
= args
->DR1
;
1772 exec2
.DR4
= args
->DR4
;
1773 exec2
.num_cliprects
= args
->num_cliprects
;
1774 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1775 exec2
.flags
= I915_EXEC_RENDER
;
1776 i915_execbuffer2_set_context_id(exec2
, 0);
1778 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1780 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1781 u64_to_user_ptr(args
->buffers_ptr
);
1783 /* Copy the new buffer offsets back to the user's exec list. */
1784 for (i
= 0; i
< args
->buffer_count
; i
++) {
1785 exec2_list
[i
].offset
=
1786 gen8_canonical_addr(exec2_list
[i
].offset
);
1787 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1788 &exec2_list
[i
].offset
,
1789 sizeof(user_exec_list
[i
].offset
));
1792 DRM_DEBUG("failed to copy %d exec entries "
1793 "back to user (%d)\n",
1794 args
->buffer_count
, ret
);
1800 drm_free_large(exec_list
);
1801 drm_free_large(exec2_list
);
1806 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1807 struct drm_file
*file
)
1809 struct drm_i915_gem_execbuffer2
*args
= data
;
1810 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1813 if (args
->buffer_count
< 1 ||
1814 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1815 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1819 if (args
->rsvd2
!= 0) {
1820 DRM_DEBUG("dirty rvsd2 field\n");
1824 exec2_list
= drm_malloc_gfp(args
->buffer_count
,
1825 sizeof(*exec2_list
),
1827 if (exec2_list
== NULL
) {
1828 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1829 args
->buffer_count
);
1832 ret
= copy_from_user(exec2_list
,
1833 u64_to_user_ptr(args
->buffers_ptr
),
1834 sizeof(*exec2_list
) * args
->buffer_count
);
1836 DRM_DEBUG("copy %d exec entries failed %d\n",
1837 args
->buffer_count
, ret
);
1838 drm_free_large(exec2_list
);
1842 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1844 /* Copy the new buffer offsets back to the user's exec list. */
1845 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1846 u64_to_user_ptr(args
->buffers_ptr
);
1849 for (i
= 0; i
< args
->buffer_count
; i
++) {
1850 exec2_list
[i
].offset
=
1851 gen8_canonical_addr(exec2_list
[i
].offset
);
1852 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1853 &exec2_list
[i
].offset
,
1854 sizeof(user_exec_list
[i
].offset
));
1857 DRM_DEBUG("failed to copy %d exec entries "
1859 args
->buffer_count
);
1865 drm_free_large(exec2_list
);