2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/dma_remapping.h>
37 struct change_domains
{
38 uint32_t invalidate_domains
;
39 uint32_t flush_domains
;
45 * Set the next domain for the specified object. This
46 * may not actually perform the necessary flushing/invaliding though,
47 * as that may want to be batched with other set_domain operations
49 * This is (we hope) the only really tricky part of gem. The goal
50 * is fairly simple -- track which caches hold bits of the object
51 * and make sure they remain coherent. A few concrete examples may
52 * help to explain how it works. For shorthand, we use the notation
53 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
54 * a pair of read and write domain masks.
56 * Case 1: the batch buffer
62 * 5. Unmapped from GTT
65 * Let's take these a step at a time
68 * Pages allocated from the kernel may still have
69 * cache contents, so we set them to (CPU, CPU) always.
70 * 2. Written by CPU (using pwrite)
71 * The pwrite function calls set_domain (CPU, CPU) and
72 * this function does nothing (as nothing changes)
74 * This function asserts that the object is not
75 * currently in any GPU-based read or write domains
77 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
78 * As write_domain is zero, this function adds in the
79 * current read domains (CPU+COMMAND, 0).
80 * flush_domains is set to CPU.
81 * invalidate_domains is set to COMMAND
82 * clflush is run to get data out of the CPU caches
83 * then i915_dev_set_domain calls i915_gem_flush to
84 * emit an MI_FLUSH and drm_agp_chipset_flush
85 * 5. Unmapped from GTT
86 * i915_gem_object_unbind calls set_domain (CPU, CPU)
87 * flush_domains and invalidate_domains end up both zero
88 * so no flushing/invalidating happens
92 * Case 2: The shared render buffer
96 * 3. Read/written by GPU
97 * 4. set_domain to (CPU,CPU)
98 * 5. Read/written by CPU
99 * 6. Read/written by GPU
102 * Same as last example, (CPU, CPU)
104 * Nothing changes (assertions find that it is not in the GPU)
105 * 3. Read/written by GPU
106 * execbuffer calls set_domain (RENDER, RENDER)
107 * flush_domains gets CPU
108 * invalidate_domains gets GPU
110 * MI_FLUSH and drm_agp_chipset_flush
111 * 4. set_domain (CPU, CPU)
112 * flush_domains gets GPU
113 * invalidate_domains gets CPU
114 * wait_rendering (obj) to make sure all drawing is complete.
115 * This will include an MI_FLUSH to get the data from GPU
117 * clflush (obj) to invalidate the CPU cache
118 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
119 * 5. Read/written by CPU
120 * cache lines are loaded and dirtied
121 * 6. Read written by GPU
122 * Same as last GPU access
124 * Case 3: The constant buffer
129 * 4. Updated (written) by CPU again
138 * flush_domains = CPU
139 * invalidate_domains = RENDER
142 * drm_agp_chipset_flush
143 * 4. Updated (written) by CPU again
145 * flush_domains = 0 (no previous write domain)
146 * invalidate_domains = 0 (no new read domains)
149 * flush_domains = CPU
150 * invalidate_domains = RENDER
153 * drm_agp_chipset_flush
156 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object
*obj
,
157 struct intel_ring_buffer
*ring
,
158 struct change_domains
*cd
)
160 uint32_t invalidate_domains
= 0, flush_domains
= 0;
163 * If the object isn't moving to a new write domain,
164 * let the object stay in multiple read domains
166 if (obj
->base
.pending_write_domain
== 0)
167 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
170 * Flush the current write domain if
171 * the new read domains don't match. Invalidate
172 * any read domains which differ from the old
175 if (obj
->base
.write_domain
&&
176 (((obj
->base
.write_domain
!= obj
->base
.pending_read_domains
||
177 obj
->ring
!= ring
)) ||
178 (obj
->fenced_gpu_access
&& !obj
->pending_fenced_gpu_access
))) {
179 flush_domains
|= obj
->base
.write_domain
;
180 invalidate_domains
|=
181 obj
->base
.pending_read_domains
& ~obj
->base
.write_domain
;
184 * Invalidate any read caches which may have
185 * stale data. That is, any new read domains.
187 invalidate_domains
|= obj
->base
.pending_read_domains
& ~obj
->base
.read_domains
;
188 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
189 i915_gem_clflush_object(obj
);
191 if (obj
->base
.pending_write_domain
)
192 cd
->flips
|= atomic_read(&obj
->pending_flip
);
194 /* The actual obj->write_domain will be updated with
195 * pending_write_domain after we emit the accumulated flush for all
196 * of our domain changes in execbuffers (which clears objects'
197 * write_domains). So if we have a current write domain that we
198 * aren't changing, set pending_write_domain to that.
200 if (flush_domains
== 0 && obj
->base
.pending_write_domain
== 0)
201 obj
->base
.pending_write_domain
= obj
->base
.write_domain
;
203 cd
->invalidate_domains
|= invalidate_domains
;
204 cd
->flush_domains
|= flush_domains
;
205 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
206 cd
->flush_rings
|= intel_ring_flag(obj
->ring
);
207 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
208 cd
->flush_rings
|= intel_ring_flag(ring
);
213 struct hlist_head buckets
[0];
216 static struct eb_objects
*
219 struct eb_objects
*eb
;
220 int count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
223 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
224 sizeof(struct eb_objects
),
234 eb_reset(struct eb_objects
*eb
)
236 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
240 eb_add_object(struct eb_objects
*eb
, struct drm_i915_gem_object
*obj
)
242 hlist_add_head(&obj
->exec_node
,
243 &eb
->buckets
[obj
->exec_handle
& eb
->and]);
246 static struct drm_i915_gem_object
*
247 eb_get_object(struct eb_objects
*eb
, unsigned long handle
)
249 struct hlist_head
*head
;
250 struct hlist_node
*node
;
251 struct drm_i915_gem_object
*obj
;
253 head
= &eb
->buckets
[handle
& eb
->and];
254 hlist_for_each(node
, head
) {
255 obj
= hlist_entry(node
, struct drm_i915_gem_object
, exec_node
);
256 if (obj
->exec_handle
== handle
)
264 eb_destroy(struct eb_objects
*eb
)
270 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
271 struct eb_objects
*eb
,
272 struct drm_i915_gem_relocation_entry
*reloc
)
274 struct drm_device
*dev
= obj
->base
.dev
;
275 struct drm_gem_object
*target_obj
;
276 uint32_t target_offset
;
279 /* we've already hold a reference to all valid objects */
280 target_obj
= &eb_get_object(eb
, reloc
->target_handle
)->base
;
281 if (unlikely(target_obj
== NULL
))
284 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
286 /* The target buffer should have appeared before us in the
287 * exec_object list, so it should have a GTT space bound by now.
289 if (unlikely(target_offset
== 0)) {
290 DRM_ERROR("No GTT space found for object %d\n",
291 reloc
->target_handle
);
295 /* Validate that the target is in a valid r/w GPU domain */
296 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
297 DRM_ERROR("reloc with multiple write domains: "
298 "obj %p target %d offset %d "
299 "read %08x write %08x",
300 obj
, reloc
->target_handle
,
303 reloc
->write_domain
);
306 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
307 & ~I915_GEM_GPU_DOMAINS
)) {
308 DRM_ERROR("reloc with read/write non-GPU domains: "
309 "obj %p target %d offset %d "
310 "read %08x write %08x",
311 obj
, reloc
->target_handle
,
314 reloc
->write_domain
);
317 if (unlikely(reloc
->write_domain
&& target_obj
->pending_write_domain
&&
318 reloc
->write_domain
!= target_obj
->pending_write_domain
)) {
319 DRM_ERROR("Write domain conflict: "
320 "obj %p target %d offset %d "
321 "new %08x old %08x\n",
322 obj
, reloc
->target_handle
,
325 target_obj
->pending_write_domain
);
329 target_obj
->pending_read_domains
|= reloc
->read_domains
;
330 target_obj
->pending_write_domain
|= reloc
->write_domain
;
332 /* If the relocation already has the right value in it, no
333 * more work needs to be done.
335 if (target_offset
== reloc
->presumed_offset
)
338 /* Check that the relocation address is valid... */
339 if (unlikely(reloc
->offset
> obj
->base
.size
- 4)) {
340 DRM_ERROR("Relocation beyond object bounds: "
341 "obj %p target %d offset %d size %d.\n",
342 obj
, reloc
->target_handle
,
344 (int) obj
->base
.size
);
347 if (unlikely(reloc
->offset
& 3)) {
348 DRM_ERROR("Relocation not 4-byte aligned: "
349 "obj %p target %d offset %d.\n",
350 obj
, reloc
->target_handle
,
351 (int) reloc
->offset
);
355 reloc
->delta
+= target_offset
;
356 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
357 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
360 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
361 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
362 kunmap_atomic(vaddr
);
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 uint32_t __iomem
*reloc_entry
;
366 void __iomem
*reloc_page
;
368 /* We can't wait for rendering with pagefaults disabled */
369 if (obj
->active
&& in_atomic())
372 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
376 /* Map the page containing the relocation we're going to perform. */
377 reloc
->offset
+= obj
->gtt_offset
;
378 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
379 reloc
->offset
& PAGE_MASK
);
380 reloc_entry
= (uint32_t __iomem
*)
381 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
382 iowrite32(reloc
->delta
, reloc_entry
);
383 io_mapping_unmap_atomic(reloc_page
);
386 /* and update the user's relocation entry */
387 reloc
->presumed_offset
= target_offset
;
393 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
394 struct eb_objects
*eb
)
396 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
397 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
400 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
401 for (i
= 0; i
< entry
->relocation_count
; i
++) {
402 struct drm_i915_gem_relocation_entry reloc
;
404 if (__copy_from_user_inatomic(&reloc
,
409 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &reloc
);
413 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
414 &reloc
.presumed_offset
,
415 sizeof(reloc
.presumed_offset
)))
423 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
424 struct eb_objects
*eb
,
425 struct drm_i915_gem_relocation_entry
*relocs
)
427 const struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
430 for (i
= 0; i
< entry
->relocation_count
; i
++) {
431 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &relocs
[i
]);
440 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
441 struct eb_objects
*eb
,
442 struct list_head
*objects
)
444 struct drm_i915_gem_object
*obj
;
447 /* This is the fast path and we cannot handle a pagefault whilst
448 * holding the struct mutex lest the user pass in the relocations
449 * contained within a mmaped bo. For in such a case we, the page
450 * fault handler would call i915_gem_fault() and we would try to
451 * acquire the struct mutex again. Obviously this is bad and so
452 * lockdep complains vehemently.
455 list_for_each_entry(obj
, objects
, exec_list
) {
456 ret
= i915_gem_execbuffer_relocate_object(obj
, eb
);
465 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
468 pin_and_fence_object(struct drm_i915_gem_object
*obj
,
469 struct intel_ring_buffer
*ring
)
471 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
472 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
473 bool need_fence
, need_mappable
;
477 has_fenced_gpu_access
&&
478 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
479 obj
->tiling_mode
!= I915_TILING_NONE
;
481 entry
->relocation_count
? true : need_fence
;
483 ret
= i915_gem_object_pin(obj
, entry
->alignment
, need_mappable
);
487 if (has_fenced_gpu_access
) {
488 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
489 if (obj
->tiling_mode
) {
490 ret
= i915_gem_object_get_fence(obj
, ring
);
494 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
495 i915_gem_object_pin_fence(obj
);
497 ret
= i915_gem_object_put_fence(obj
);
502 obj
->pending_fenced_gpu_access
= need_fence
;
505 entry
->offset
= obj
->gtt_offset
;
509 i915_gem_object_unpin(obj
);
514 i915_gem_execbuffer_reserve(struct intel_ring_buffer
*ring
,
515 struct drm_file
*file
,
516 struct list_head
*objects
)
518 struct drm_i915_gem_object
*obj
;
520 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
521 struct list_head ordered_objects
;
523 INIT_LIST_HEAD(&ordered_objects
);
524 while (!list_empty(objects
)) {
525 struct drm_i915_gem_exec_object2
*entry
;
526 bool need_fence
, need_mappable
;
528 obj
= list_first_entry(objects
,
529 struct drm_i915_gem_object
,
531 entry
= obj
->exec_entry
;
534 has_fenced_gpu_access
&&
535 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
536 obj
->tiling_mode
!= I915_TILING_NONE
;
538 entry
->relocation_count
? true : need_fence
;
541 list_move(&obj
->exec_list
, &ordered_objects
);
543 list_move_tail(&obj
->exec_list
, &ordered_objects
);
545 obj
->base
.pending_read_domains
= 0;
546 obj
->base
.pending_write_domain
= 0;
548 list_splice(&ordered_objects
, objects
);
550 /* Attempt to pin all of the buffers into the GTT.
551 * This is done in 3 phases:
553 * 1a. Unbind all objects that do not match the GTT constraints for
554 * the execbuffer (fenceable, mappable, alignment etc).
555 * 1b. Increment pin count for already bound objects.
556 * 2. Bind new objects.
557 * 3. Decrement pin count.
559 * This avoid unnecessary unbinding of later objects in order to makr
560 * room for the earlier objects *unless* we need to defragment.
566 /* Unbind any ill-fitting objects or pin. */
567 list_for_each_entry(obj
, objects
, exec_list
) {
568 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
569 bool need_fence
, need_mappable
;
575 has_fenced_gpu_access
&&
576 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
577 obj
->tiling_mode
!= I915_TILING_NONE
;
579 entry
->relocation_count
? true : need_fence
;
581 if ((entry
->alignment
&& obj
->gtt_offset
& (entry
->alignment
- 1)) ||
582 (need_mappable
&& !obj
->map_and_fenceable
))
583 ret
= i915_gem_object_unbind(obj
);
585 ret
= pin_and_fence_object(obj
, ring
);
590 /* Bind fresh objects */
591 list_for_each_entry(obj
, objects
, exec_list
) {
595 ret
= pin_and_fence_object(obj
, ring
);
599 /* This can potentially raise a harmless
600 * -EINVAL if we failed to bind in the above
601 * call. It cannot raise -EINTR since we know
602 * that the bo is freshly bound and so will
603 * not need to be flushed or waited upon.
605 ret_ignore
= i915_gem_object_unbind(obj
);
607 WARN_ON(obj
->gtt_space
);
612 /* Decrement pin count for bound objects */
613 list_for_each_entry(obj
, objects
, exec_list
) {
614 struct drm_i915_gem_exec_object2
*entry
;
619 entry
= obj
->exec_entry
;
620 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
621 i915_gem_object_unpin_fence(obj
);
622 entry
->flags
&= ~__EXEC_OBJECT_HAS_FENCE
;
625 i915_gem_object_unpin(obj
);
628 if (ret
!= -ENOSPC
|| retry
> 1)
631 /* First attempt, just clear anything that is purgeable.
632 * Second attempt, clear the entire GTT.
634 ret
= i915_gem_evict_everything(ring
->dev
, retry
== 0);
642 list_for_each_entry_continue_reverse(obj
, objects
, exec_list
) {
643 struct drm_i915_gem_exec_object2
*entry
;
648 entry
= obj
->exec_entry
;
649 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
650 i915_gem_object_unpin_fence(obj
);
651 entry
->flags
&= ~__EXEC_OBJECT_HAS_FENCE
;
654 i915_gem_object_unpin(obj
);
661 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
662 struct drm_file
*file
,
663 struct intel_ring_buffer
*ring
,
664 struct list_head
*objects
,
665 struct eb_objects
*eb
,
666 struct drm_i915_gem_exec_object2
*exec
,
669 struct drm_i915_gem_relocation_entry
*reloc
;
670 struct drm_i915_gem_object
*obj
;
674 /* We may process another execbuffer during the unlock... */
675 while (!list_empty(objects
)) {
676 obj
= list_first_entry(objects
,
677 struct drm_i915_gem_object
,
679 list_del_init(&obj
->exec_list
);
680 drm_gem_object_unreference(&obj
->base
);
683 mutex_unlock(&dev
->struct_mutex
);
686 for (i
= 0; i
< count
; i
++)
687 total
+= exec
[i
].relocation_count
;
689 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
690 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
691 if (reloc
== NULL
|| reloc_offset
== NULL
) {
692 drm_free_large(reloc
);
693 drm_free_large(reloc_offset
);
694 mutex_lock(&dev
->struct_mutex
);
699 for (i
= 0; i
< count
; i
++) {
700 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
702 user_relocs
= (void __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
704 if (copy_from_user(reloc
+total
, user_relocs
,
705 exec
[i
].relocation_count
* sizeof(*reloc
))) {
707 mutex_lock(&dev
->struct_mutex
);
711 reloc_offset
[i
] = total
;
712 total
+= exec
[i
].relocation_count
;
715 ret
= i915_mutex_lock_interruptible(dev
);
717 mutex_lock(&dev
->struct_mutex
);
721 /* reacquire the objects */
723 for (i
= 0; i
< count
; i
++) {
724 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
726 if (&obj
->base
== NULL
) {
727 DRM_ERROR("Invalid object handle %d at index %d\n",
733 list_add_tail(&obj
->exec_list
, objects
);
734 obj
->exec_handle
= exec
[i
].handle
;
735 obj
->exec_entry
= &exec
[i
];
736 eb_add_object(eb
, obj
);
739 ret
= i915_gem_execbuffer_reserve(ring
, file
, objects
);
743 list_for_each_entry(obj
, objects
, exec_list
) {
744 int offset
= obj
->exec_entry
- exec
;
745 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, eb
,
746 reloc
+ reloc_offset
[offset
]);
751 /* Leave the user relocations as are, this is the painfully slow path,
752 * and we want to avoid the complication of dropping the lock whilst
753 * having buffers reserved in the aperture and so causing spurious
754 * ENOSPC for random operations.
758 drm_free_large(reloc
);
759 drm_free_large(reloc_offset
);
764 i915_gem_execbuffer_flush(struct drm_device
*dev
,
765 uint32_t invalidate_domains
,
766 uint32_t flush_domains
,
767 uint32_t flush_rings
)
769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
772 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
773 intel_gtt_chipset_flush();
775 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
778 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
779 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
780 if (flush_rings
& (1 << i
)) {
781 ret
= i915_gem_flush_ring(&dev_priv
->ring
[i
],
793 intel_enable_semaphores(struct drm_device
*dev
)
795 if (INTEL_INFO(dev
)->gen
< 6)
798 if (i915_semaphores
>= 0)
799 return i915_semaphores
;
801 /* Disable semaphores on SNB */
802 if (INTEL_INFO(dev
)->gen
== 6)
809 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object
*obj
,
810 struct intel_ring_buffer
*to
)
812 struct intel_ring_buffer
*from
= obj
->ring
;
816 if (from
== NULL
|| to
== from
)
819 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
820 if (!intel_enable_semaphores(obj
->base
.dev
))
821 return i915_gem_object_wait_rendering(obj
);
823 idx
= intel_ring_sync_index(from
, to
);
825 seqno
= obj
->last_rendering_seqno
;
826 if (seqno
<= from
->sync_seqno
[idx
])
829 if (seqno
== from
->outstanding_lazy_request
) {
830 struct drm_i915_gem_request
*request
;
832 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
836 ret
= i915_add_request(from
, NULL
, request
);
842 seqno
= request
->seqno
;
845 from
->sync_seqno
[idx
] = seqno
;
847 return to
->sync_to(to
, from
, seqno
- 1);
851 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer
*ring
, u32 flips
)
853 u32 plane
, flip_mask
;
856 /* Check for any pending flips. As we only maintain a flip queue depth
857 * of 1, we can simply insert a WAIT for the next display flip prior
858 * to executing the batch and avoid stalling the CPU.
861 for (plane
= 0; flips
>> plane
; plane
++) {
862 if (((flips
>> plane
) & 1) == 0)
866 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
868 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
870 ret
= intel_ring_begin(ring
, 2);
874 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
875 intel_ring_emit(ring
, MI_NOOP
);
876 intel_ring_advance(ring
);
884 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer
*ring
,
885 struct list_head
*objects
)
887 struct drm_i915_gem_object
*obj
;
888 struct change_domains cd
;
891 memset(&cd
, 0, sizeof(cd
));
892 list_for_each_entry(obj
, objects
, exec_list
)
893 i915_gem_object_set_to_gpu_domain(obj
, ring
, &cd
);
895 if (cd
.invalidate_domains
| cd
.flush_domains
) {
896 ret
= i915_gem_execbuffer_flush(ring
->dev
,
897 cd
.invalidate_domains
,
905 ret
= i915_gem_execbuffer_wait_for_flips(ring
, cd
.flips
);
910 list_for_each_entry(obj
, objects
, exec_list
) {
911 ret
= i915_gem_execbuffer_sync_rings(obj
, ring
);
920 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
922 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
926 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
931 for (i
= 0; i
< count
; i
++) {
932 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
933 int length
; /* limited by fault_in_pages_readable() */
935 /* First check for malicious input causing overflow */
936 if (exec
[i
].relocation_count
>
937 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
940 length
= exec
[i
].relocation_count
*
941 sizeof(struct drm_i915_gem_relocation_entry
);
942 if (!access_ok(VERIFY_READ
, ptr
, length
))
945 /* we may also need to update the presumed offsets */
946 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
949 if (fault_in_pages_readable(ptr
, length
))
957 i915_gem_execbuffer_move_to_active(struct list_head
*objects
,
958 struct intel_ring_buffer
*ring
,
961 struct drm_i915_gem_object
*obj
;
963 list_for_each_entry(obj
, objects
, exec_list
) {
964 u32 old_read
= obj
->base
.read_domains
;
965 u32 old_write
= obj
->base
.write_domain
;
968 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
969 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
970 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
972 i915_gem_object_move_to_active(obj
, ring
, seqno
);
973 if (obj
->base
.write_domain
) {
975 obj
->pending_gpu_write
= true;
976 list_move_tail(&obj
->gpu_write_list
,
977 &ring
->gpu_write_list
);
978 intel_mark_busy(ring
->dev
, obj
);
981 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
986 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
987 struct drm_file
*file
,
988 struct intel_ring_buffer
*ring
)
990 struct drm_i915_gem_request
*request
;
994 * Ensure that the commands in the batch buffer are
995 * finished before the interrupt fires.
997 * The sampler always gets flushed on i965 (sigh).
999 invalidate
= I915_GEM_DOMAIN_COMMAND
;
1000 if (INTEL_INFO(dev
)->gen
>= 4)
1001 invalidate
|= I915_GEM_DOMAIN_SAMPLER
;
1002 if (ring
->flush(ring
, invalidate
, 0)) {
1003 i915_gem_next_request_seqno(ring
);
1007 /* Add a breadcrumb for the completion of the batch buffer */
1008 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1009 if (request
== NULL
|| i915_add_request(ring
, file
, request
)) {
1010 i915_gem_next_request_seqno(ring
);
1016 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
1017 struct intel_ring_buffer
*ring
)
1019 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1022 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
])
1025 ret
= intel_ring_begin(ring
, 4 * 3);
1029 for (i
= 0; i
< 4; i
++) {
1030 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1031 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1032 intel_ring_emit(ring
, 0);
1035 intel_ring_advance(ring
);
1041 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file
,
1043 struct drm_i915_gem_execbuffer2
*args
,
1044 struct drm_i915_gem_exec_object2
*exec
)
1046 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1047 struct list_head objects
;
1048 struct eb_objects
*eb
;
1049 struct drm_i915_gem_object
*batch_obj
;
1050 struct drm_clip_rect
*cliprects
= NULL
;
1051 struct intel_ring_buffer
*ring
;
1052 u32 exec_start
, exec_len
;
1057 if (!i915_gem_check_execbuffer(args
)) {
1058 DRM_ERROR("execbuf with invalid offset/length\n");
1062 ret
= validate_exec_list(exec
, args
->buffer_count
);
1066 switch (args
->flags
& I915_EXEC_RING_MASK
) {
1067 case I915_EXEC_DEFAULT
:
1068 case I915_EXEC_RENDER
:
1069 ring
= &dev_priv
->ring
[RCS
];
1072 if (!HAS_BSD(dev
)) {
1073 DRM_ERROR("execbuf with invalid ring (BSD)\n");
1076 ring
= &dev_priv
->ring
[VCS
];
1079 if (!HAS_BLT(dev
)) {
1080 DRM_ERROR("execbuf with invalid ring (BLT)\n");
1083 ring
= &dev_priv
->ring
[BCS
];
1086 DRM_ERROR("execbuf with unknown ring: %d\n",
1087 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1091 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1092 mask
= I915_EXEC_CONSTANTS_MASK
;
1094 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1095 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1096 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1097 if (ring
== &dev_priv
->ring
[RCS
] &&
1098 mode
!= dev_priv
->relative_constants_mode
) {
1099 if (INTEL_INFO(dev
)->gen
< 4)
1102 if (INTEL_INFO(dev
)->gen
> 5 &&
1103 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
)
1106 /* The HW changed the meaning on this bit on gen6 */
1107 if (INTEL_INFO(dev
)->gen
>= 6)
1108 mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1112 DRM_ERROR("execbuf with unknown constants: %d\n", mode
);
1116 if (args
->buffer_count
< 1) {
1117 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1121 if (args
->num_cliprects
!= 0) {
1122 if (ring
!= &dev_priv
->ring
[RCS
]) {
1123 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1127 cliprects
= kmalloc(args
->num_cliprects
* sizeof(*cliprects
),
1129 if (cliprects
== NULL
) {
1134 if (copy_from_user(cliprects
,
1135 (struct drm_clip_rect __user
*)(uintptr_t)
1136 args
->cliprects_ptr
,
1137 sizeof(*cliprects
)*args
->num_cliprects
)) {
1143 ret
= i915_mutex_lock_interruptible(dev
);
1147 if (dev_priv
->mm
.suspended
) {
1148 mutex_unlock(&dev
->struct_mutex
);
1153 eb
= eb_create(args
->buffer_count
);
1155 mutex_unlock(&dev
->struct_mutex
);
1160 /* Look up object handles */
1161 INIT_LIST_HEAD(&objects
);
1162 for (i
= 0; i
< args
->buffer_count
; i
++) {
1163 struct drm_i915_gem_object
*obj
;
1165 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
1167 if (&obj
->base
== NULL
) {
1168 DRM_ERROR("Invalid object handle %d at index %d\n",
1170 /* prevent error path from reading uninitialized data */
1175 if (!list_empty(&obj
->exec_list
)) {
1176 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1177 obj
, exec
[i
].handle
, i
);
1182 list_add_tail(&obj
->exec_list
, &objects
);
1183 obj
->exec_handle
= exec
[i
].handle
;
1184 obj
->exec_entry
= &exec
[i
];
1185 eb_add_object(eb
, obj
);
1188 /* take note of the batch buffer before we might reorder the lists */
1189 batch_obj
= list_entry(objects
.prev
,
1190 struct drm_i915_gem_object
,
1193 /* Move the objects en-masse into the GTT, evicting if necessary. */
1194 ret
= i915_gem_execbuffer_reserve(ring
, file
, &objects
);
1198 /* The objects are in their final locations, apply the relocations. */
1199 ret
= i915_gem_execbuffer_relocate(dev
, eb
, &objects
);
1201 if (ret
== -EFAULT
) {
1202 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
, ring
,
1205 args
->buffer_count
);
1206 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1212 /* Set the pending read domains for the batch buffer to COMMAND */
1213 if (batch_obj
->base
.pending_write_domain
) {
1214 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1218 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1220 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &objects
);
1224 seqno
= i915_gem_next_request_seqno(ring
);
1225 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++) {
1226 if (seqno
< ring
->sync_seqno
[i
]) {
1227 /* The GPU can not handle its semaphore value wrapping,
1228 * so every billion or so execbuffers, we need to stall
1229 * the GPU in order to reset the counters.
1231 ret
= i915_gpu_idle(dev
, true);
1235 BUG_ON(ring
->sync_seqno
[i
]);
1239 if (ring
== &dev_priv
->ring
[RCS
] &&
1240 mode
!= dev_priv
->relative_constants_mode
) {
1241 ret
= intel_ring_begin(ring
, 4);
1245 intel_ring_emit(ring
, MI_NOOP
);
1246 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1247 intel_ring_emit(ring
, INSTPM
);
1248 intel_ring_emit(ring
, mask
<< 16 | mode
);
1249 intel_ring_advance(ring
);
1251 dev_priv
->relative_constants_mode
= mode
;
1254 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1255 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1260 trace_i915_gem_ring_dispatch(ring
, seqno
);
1262 exec_start
= batch_obj
->gtt_offset
+ args
->batch_start_offset
;
1263 exec_len
= args
->batch_len
;
1265 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1266 ret
= i915_emit_box(dev
, &cliprects
[i
],
1267 args
->DR1
, args
->DR4
);
1271 ret
= ring
->dispatch_execbuffer(ring
,
1272 exec_start
, exec_len
);
1277 ret
= ring
->dispatch_execbuffer(ring
, exec_start
, exec_len
);
1282 i915_gem_execbuffer_move_to_active(&objects
, ring
, seqno
);
1283 i915_gem_execbuffer_retire_commands(dev
, file
, ring
);
1287 while (!list_empty(&objects
)) {
1288 struct drm_i915_gem_object
*obj
;
1290 obj
= list_first_entry(&objects
,
1291 struct drm_i915_gem_object
,
1293 list_del_init(&obj
->exec_list
);
1294 drm_gem_object_unreference(&obj
->base
);
1297 mutex_unlock(&dev
->struct_mutex
);
1305 * Legacy execbuffer just creates an exec2 list from the original exec object
1306 * list array and passes it to the real function.
1309 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1310 struct drm_file
*file
)
1312 struct drm_i915_gem_execbuffer
*args
= data
;
1313 struct drm_i915_gem_execbuffer2 exec2
;
1314 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1315 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1318 if (args
->buffer_count
< 1) {
1319 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1323 /* Copy in the exec list from userland */
1324 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1325 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1326 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1327 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1328 args
->buffer_count
);
1329 drm_free_large(exec_list
);
1330 drm_free_large(exec2_list
);
1333 ret
= copy_from_user(exec_list
,
1334 (struct drm_i915_relocation_entry __user
*)
1335 (uintptr_t) args
->buffers_ptr
,
1336 sizeof(*exec_list
) * args
->buffer_count
);
1338 DRM_ERROR("copy %d exec entries failed %d\n",
1339 args
->buffer_count
, ret
);
1340 drm_free_large(exec_list
);
1341 drm_free_large(exec2_list
);
1345 for (i
= 0; i
< args
->buffer_count
; i
++) {
1346 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1347 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1348 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1349 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1350 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1351 if (INTEL_INFO(dev
)->gen
< 4)
1352 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1354 exec2_list
[i
].flags
= 0;
1357 exec2
.buffers_ptr
= args
->buffers_ptr
;
1358 exec2
.buffer_count
= args
->buffer_count
;
1359 exec2
.batch_start_offset
= args
->batch_start_offset
;
1360 exec2
.batch_len
= args
->batch_len
;
1361 exec2
.DR1
= args
->DR1
;
1362 exec2
.DR4
= args
->DR4
;
1363 exec2
.num_cliprects
= args
->num_cliprects
;
1364 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1365 exec2
.flags
= I915_EXEC_RENDER
;
1367 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1369 /* Copy the new buffer offsets back to the user's exec list. */
1370 for (i
= 0; i
< args
->buffer_count
; i
++)
1371 exec_list
[i
].offset
= exec2_list
[i
].offset
;
1372 /* ... and back out to userspace */
1373 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1374 (uintptr_t) args
->buffers_ptr
,
1376 sizeof(*exec_list
) * args
->buffer_count
);
1379 DRM_ERROR("failed to copy %d exec entries "
1380 "back to user (%d)\n",
1381 args
->buffer_count
, ret
);
1385 drm_free_large(exec_list
);
1386 drm_free_large(exec2_list
);
1391 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1392 struct drm_file
*file
)
1394 struct drm_i915_gem_execbuffer2
*args
= data
;
1395 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1398 if (args
->buffer_count
< 1) {
1399 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
1403 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1404 GFP_KERNEL
| __GFP_NOWARN
| __GFP_NORETRY
);
1405 if (exec2_list
== NULL
)
1406 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1407 args
->buffer_count
);
1408 if (exec2_list
== NULL
) {
1409 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1410 args
->buffer_count
);
1413 ret
= copy_from_user(exec2_list
,
1414 (struct drm_i915_relocation_entry __user
*)
1415 (uintptr_t) args
->buffers_ptr
,
1416 sizeof(*exec2_list
) * args
->buffer_count
);
1418 DRM_ERROR("copy %d exec entries failed %d\n",
1419 args
->buffer_count
, ret
);
1420 drm_free_large(exec2_list
);
1424 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1426 /* Copy the new buffer offsets back to the user's exec list. */
1427 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1428 (uintptr_t) args
->buffers_ptr
,
1430 sizeof(*exec2_list
) * args
->buffer_count
);
1433 DRM_ERROR("failed to copy %d exec entries "
1434 "back to user (%d)\n",
1435 args
->buffer_count
, ret
);
1439 drm_free_large(exec2_list
);