2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/uaccess.h>
34 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
41 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
43 #define __EXEC_OBJECT_HAS_PIN (1<<31)
44 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
45 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
46 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
47 #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
49 #define BATCH_OFFSET_BIAS (256*1024)
51 struct i915_execbuffer_params
{
52 struct drm_device
*dev
;
53 struct drm_file
*file
;
54 struct i915_vma
*batch
;
56 u32 args_batch_start_offset
;
57 struct intel_engine_cs
*engine
;
58 struct i915_gem_context
*ctx
;
59 struct drm_i915_gem_request
*request
;
63 struct drm_i915_private
*i915
;
64 struct list_head vmas
;
67 struct i915_vma
*lut
[0];
68 struct hlist_head buckets
[0];
72 static struct eb_vmas
*
73 eb_create(struct drm_i915_private
*i915
,
74 struct drm_i915_gem_execbuffer2
*args
)
76 struct eb_vmas
*eb
= NULL
;
78 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
79 unsigned size
= args
->buffer_count
;
80 size
*= sizeof(struct i915_vma
*);
81 size
+= sizeof(struct eb_vmas
);
82 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
86 unsigned size
= args
->buffer_count
;
87 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
88 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
89 while (count
> 2*size
)
91 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
92 sizeof(struct eb_vmas
),
99 eb
->and = -args
->buffer_count
;
102 INIT_LIST_HEAD(&eb
->vmas
);
107 eb_reset(struct eb_vmas
*eb
)
110 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
113 static struct i915_vma
*
114 eb_get_batch(struct eb_vmas
*eb
)
116 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
119 * SNA is doing fancy tricks with compressing batch buffers, which leads
120 * to negative relocation deltas. Usually that works out ok since the
121 * relocate address is still positive, except when the batch is placed
122 * very low in the GTT. Ensure this doesn't happen.
124 * Note that actual hangs have only been observed on gen7, but for
125 * paranoia do it everywhere.
127 if ((vma
->exec_entry
->flags
& EXEC_OBJECT_PINNED
) == 0)
128 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
134 eb_lookup_vmas(struct eb_vmas
*eb
,
135 struct drm_i915_gem_exec_object2
*exec
,
136 const struct drm_i915_gem_execbuffer2
*args
,
137 struct i915_address_space
*vm
,
138 struct drm_file
*file
)
140 struct drm_i915_gem_object
*obj
;
141 struct list_head objects
;
144 INIT_LIST_HEAD(&objects
);
145 spin_lock(&file
->table_lock
);
146 /* Grab a reference to the object and release the lock so we can lookup
147 * or create the VMA without using GFP_ATOMIC */
148 for (i
= 0; i
< args
->buffer_count
; i
++) {
149 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
151 spin_unlock(&file
->table_lock
);
152 DRM_DEBUG("Invalid object handle %d at index %d\n",
158 if (!list_empty(&obj
->obj_exec_link
)) {
159 spin_unlock(&file
->table_lock
);
160 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
161 obj
, exec
[i
].handle
, i
);
166 i915_gem_object_get(obj
);
167 list_add_tail(&obj
->obj_exec_link
, &objects
);
169 spin_unlock(&file
->table_lock
);
172 while (!list_empty(&objects
)) {
173 struct i915_vma
*vma
;
175 obj
= list_first_entry(&objects
,
176 struct drm_i915_gem_object
,
180 * NOTE: We can leak any vmas created here when something fails
181 * later on. But that's no issue since vma_unbind can deal with
182 * vmas which are not actually bound. And since only
183 * lookup_or_create exists as an interface to get at the vma
184 * from the (obj, vm) we don't run the risk of creating
185 * duplicated vmas for the same vm.
187 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
, NULL
);
188 if (unlikely(IS_ERR(vma
))) {
189 DRM_DEBUG("Failed to lookup VMA\n");
194 /* Transfer ownership from the objects list to the vmas list. */
195 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
196 list_del_init(&obj
->obj_exec_link
);
198 vma
->exec_entry
= &exec
[i
];
202 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
203 vma
->exec_handle
= handle
;
204 hlist_add_head(&vma
->exec_node
,
205 &eb
->buckets
[handle
& eb
->and]);
214 while (!list_empty(&objects
)) {
215 obj
= list_first_entry(&objects
,
216 struct drm_i915_gem_object
,
218 list_del_init(&obj
->obj_exec_link
);
219 i915_gem_object_put(obj
);
222 * Objects already transfered to the vmas list will be unreferenced by
229 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
232 if (handle
>= -eb
->and)
234 return eb
->lut
[handle
];
236 struct hlist_head
*head
;
237 struct i915_vma
*vma
;
239 head
= &eb
->buckets
[handle
& eb
->and];
240 hlist_for_each_entry(vma
, head
, exec_node
) {
241 if (vma
->exec_handle
== handle
)
249 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
251 struct drm_i915_gem_exec_object2
*entry
;
253 if (!drm_mm_node_allocated(&vma
->node
))
256 entry
= vma
->exec_entry
;
258 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
259 i915_vma_unpin_fence(vma
);
261 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
262 __i915_vma_unpin(vma
);
264 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
267 static void eb_destroy(struct eb_vmas
*eb
)
269 while (!list_empty(&eb
->vmas
)) {
270 struct i915_vma
*vma
;
272 vma
= list_first_entry(&eb
->vmas
,
275 list_del_init(&vma
->exec_list
);
276 i915_gem_execbuffer_unreserve_vma(vma
);
282 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
284 if (!i915_gem_object_has_struct_page(obj
))
287 if (DBG_USE_CPU_RELOC
)
288 return DBG_USE_CPU_RELOC
> 0;
290 return (HAS_LLC(obj
->base
.dev
) ||
291 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
292 obj
->cache_level
!= I915_CACHE_NONE
);
295 /* Used to convert any address to canonical form.
296 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
297 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
298 * addresses to be in a canonical form:
299 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
300 * canonical form [63:48] == [47]."
302 #define GEN8_HIGH_ADDRESS_BIT 47
303 static inline uint64_t gen8_canonical_addr(uint64_t address
)
305 return sign_extend64(address
, GEN8_HIGH_ADDRESS_BIT
);
308 static inline uint64_t gen8_noncanonical_addr(uint64_t address
)
310 return address
& ((1ULL << (GEN8_HIGH_ADDRESS_BIT
+ 1)) - 1);
313 static inline uint64_t
314 relocation_target(const struct drm_i915_gem_relocation_entry
*reloc
,
315 uint64_t target_offset
)
317 return gen8_canonical_addr((int)reloc
->delta
+ target_offset
);
321 struct drm_i915_private
*i915
;
322 struct drm_mm_node node
;
325 bool use_64bit_reloc
;
328 static void reloc_cache_init(struct reloc_cache
*cache
,
329 struct drm_i915_private
*i915
)
334 /* Must be a variable in the struct to allow GCC to unroll. */
335 cache
->use_64bit_reloc
= HAS_64BIT_RELOC(i915
);
336 cache
->node
.allocated
= false;
339 static inline void *unmask_page(unsigned long p
)
341 return (void *)(uintptr_t)(p
& PAGE_MASK
);
344 static inline unsigned int unmask_flags(unsigned long p
)
346 return p
& ~PAGE_MASK
;
349 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
351 static void reloc_cache_fini(struct reloc_cache
*cache
)
358 vaddr
= unmask_page(cache
->vaddr
);
359 if (cache
->vaddr
& KMAP
) {
360 if (cache
->vaddr
& CLFLUSH_AFTER
)
363 kunmap_atomic(vaddr
);
364 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object
*)cache
->node
.mm
);
367 io_mapping_unmap_atomic((void __iomem
*)vaddr
);
368 if (cache
->node
.allocated
) {
369 struct i915_ggtt
*ggtt
= &cache
->i915
->ggtt
;
371 ggtt
->base
.clear_range(&ggtt
->base
,
374 drm_mm_remove_node(&cache
->node
);
376 i915_vma_unpin((struct i915_vma
*)cache
->node
.mm
);
381 static void *reloc_kmap(struct drm_i915_gem_object
*obj
,
382 struct reloc_cache
*cache
,
388 kunmap_atomic(unmask_page(cache
->vaddr
));
390 unsigned int flushes
;
393 ret
= i915_gem_obj_prepare_shmem_write(obj
, &flushes
);
397 BUILD_BUG_ON(KMAP
& CLFLUSH_FLAGS
);
398 BUILD_BUG_ON((KMAP
| CLFLUSH_FLAGS
) & PAGE_MASK
);
400 cache
->vaddr
= flushes
| KMAP
;
401 cache
->node
.mm
= (void *)obj
;
406 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
, page
));
407 cache
->vaddr
= unmask_flags(cache
->vaddr
) | (unsigned long)vaddr
;
413 static void *reloc_iomap(struct drm_i915_gem_object
*obj
,
414 struct reloc_cache
*cache
,
417 struct i915_ggtt
*ggtt
= &cache
->i915
->ggtt
;
418 unsigned long offset
;
422 io_mapping_unmap_atomic((void __force __iomem
*) unmask_page(cache
->vaddr
));
424 struct i915_vma
*vma
;
427 if (use_cpu_reloc(obj
))
430 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
434 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
435 PIN_MAPPABLE
| PIN_NONBLOCK
);
437 memset(&cache
->node
, 0, sizeof(cache
->node
));
438 ret
= drm_mm_insert_node_in_range_generic
439 (&ggtt
->base
.mm
, &cache
->node
,
441 0, ggtt
->mappable_end
,
442 DRM_MM_SEARCH_DEFAULT
,
443 DRM_MM_CREATE_DEFAULT
);
444 if (ret
) /* no inactive aperture space, use cpu reloc */
447 ret
= i915_vma_put_fence(vma
);
453 cache
->node
.start
= vma
->node
.start
;
454 cache
->node
.mm
= (void *)vma
;
458 offset
= cache
->node
.start
;
459 if (cache
->node
.allocated
) {
461 ggtt
->base
.insert_page(&ggtt
->base
,
462 i915_gem_object_get_dma_address(obj
, page
),
463 offset
, I915_CACHE_NONE
, 0);
465 offset
+= page
<< PAGE_SHIFT
;
468 vaddr
= (void __force
*) io_mapping_map_atomic_wc(&cache
->i915
->ggtt
.mappable
, offset
);
470 cache
->vaddr
= (unsigned long)vaddr
;
475 static void *reloc_vaddr(struct drm_i915_gem_object
*obj
,
476 struct reloc_cache
*cache
,
481 if (cache
->page
== page
) {
482 vaddr
= unmask_page(cache
->vaddr
);
485 if ((cache
->vaddr
& KMAP
) == 0)
486 vaddr
= reloc_iomap(obj
, cache
, page
);
488 vaddr
= reloc_kmap(obj
, cache
, page
);
494 static void clflush_write32(u32
*addr
, u32 value
, unsigned int flushes
)
496 if (unlikely(flushes
& (CLFLUSH_BEFORE
| CLFLUSH_AFTER
))) {
497 if (flushes
& CLFLUSH_BEFORE
) {
504 /* Writes to the same cacheline are serialised by the CPU
505 * (including clflush). On the write path, we only require
506 * that it hits memory in an orderly fashion and place
507 * mb barriers at the start and end of the relocation phase
508 * to ensure ordering of clflush wrt to the system.
510 if (flushes
& CLFLUSH_AFTER
)
517 relocate_entry(struct drm_i915_gem_object
*obj
,
518 const struct drm_i915_gem_relocation_entry
*reloc
,
519 struct reloc_cache
*cache
,
522 u64 offset
= reloc
->offset
;
523 bool wide
= cache
->use_64bit_reloc
;
526 target_offset
= relocation_target(reloc
, target_offset
);
528 vaddr
= reloc_vaddr(obj
, cache
, offset
>> PAGE_SHIFT
);
530 return PTR_ERR(vaddr
);
532 clflush_write32(vaddr
+ offset_in_page(offset
),
533 lower_32_bits(target_offset
),
537 offset
+= sizeof(u32
);
538 target_offset
>>= 32;
547 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
549 struct drm_i915_gem_relocation_entry
*reloc
,
550 struct reloc_cache
*cache
)
552 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
553 struct drm_gem_object
*target_obj
;
554 struct drm_i915_gem_object
*target_i915_obj
;
555 struct i915_vma
*target_vma
;
556 uint64_t target_offset
;
559 /* we've already hold a reference to all valid objects */
560 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
561 if (unlikely(target_vma
== NULL
))
563 target_i915_obj
= target_vma
->obj
;
564 target_obj
= &target_vma
->obj
->base
;
566 target_offset
= gen8_canonical_addr(target_vma
->node
.start
);
568 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
569 * pipe_control writes because the gpu doesn't properly redirect them
570 * through the ppgtt for non_secure batchbuffers. */
571 if (unlikely(IS_GEN6(dev_priv
) &&
572 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
)) {
573 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
575 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
579 /* Validate that the target is in a valid r/w GPU domain */
580 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
581 DRM_DEBUG("reloc with multiple write domains: "
582 "obj %p target %d offset %d "
583 "read %08x write %08x",
584 obj
, reloc
->target_handle
,
587 reloc
->write_domain
);
590 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
591 & ~I915_GEM_GPU_DOMAINS
)) {
592 DRM_DEBUG("reloc with read/write non-GPU domains: "
593 "obj %p target %d offset %d "
594 "read %08x write %08x",
595 obj
, reloc
->target_handle
,
598 reloc
->write_domain
);
602 target_obj
->pending_read_domains
|= reloc
->read_domains
;
603 target_obj
->pending_write_domain
|= reloc
->write_domain
;
605 /* If the relocation already has the right value in it, no
606 * more work needs to be done.
608 if (target_offset
== reloc
->presumed_offset
)
611 /* Check that the relocation address is valid... */
612 if (unlikely(reloc
->offset
>
613 obj
->base
.size
- (cache
->use_64bit_reloc
? 8 : 4))) {
614 DRM_DEBUG("Relocation beyond object bounds: "
615 "obj %p target %d offset %d size %d.\n",
616 obj
, reloc
->target_handle
,
618 (int) obj
->base
.size
);
621 if (unlikely(reloc
->offset
& 3)) {
622 DRM_DEBUG("Relocation not 4-byte aligned: "
623 "obj %p target %d offset %d.\n",
624 obj
, reloc
->target_handle
,
625 (int) reloc
->offset
);
629 ret
= relocate_entry(obj
, reloc
, cache
, target_offset
);
633 /* and update the user's relocation entry */
634 reloc
->presumed_offset
= target_offset
;
639 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
642 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
643 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
644 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
645 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
646 struct reloc_cache cache
;
649 user_relocs
= u64_to_user_ptr(entry
->relocs_ptr
);
650 reloc_cache_init(&cache
, eb
->i915
);
652 remain
= entry
->relocation_count
;
654 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
655 unsigned long unwritten
;
658 count
= min_t(unsigned int, remain
, ARRAY_SIZE(stack_reloc
));
661 /* This is the fast path and we cannot handle a pagefault
662 * whilst holding the struct mutex lest the user pass in the
663 * relocations contained within a mmaped bo. For in such a case
664 * we, the page fault handler would call i915_gem_fault() and
665 * we would try to acquire the struct mutex again. Obviously
666 * this is bad and so lockdep complains vehemently.
669 unwritten
= __copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0]));
671 if (unlikely(unwritten
)) {
677 u64 offset
= r
->presumed_offset
;
679 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
, &cache
);
683 if (r
->presumed_offset
!= offset
) {
685 unwritten
= __put_user(r
->presumed_offset
,
686 &user_relocs
->presumed_offset
);
688 if (unlikely(unwritten
)) {
689 /* Note that reporting an error now
690 * leaves everything in an inconsistent
691 * state as we have *already* changed
692 * the relocation value inside the
693 * object. As we have not changed the
694 * reloc.presumed_offset or will not
695 * change the execobject.offset, on the
696 * call we may not rewrite the value
697 * inside the object, leaving it
698 * dangling and causing a GPU hang.
711 reloc_cache_fini(&cache
);
717 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
719 struct drm_i915_gem_relocation_entry
*relocs
)
721 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
722 struct reloc_cache cache
;
725 reloc_cache_init(&cache
, eb
->i915
);
726 for (i
= 0; i
< entry
->relocation_count
; i
++) {
727 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
], &cache
);
731 reloc_cache_fini(&cache
);
737 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
739 struct i915_vma
*vma
;
742 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
743 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
751 static bool only_mappable_for_reloc(unsigned int flags
)
753 return (flags
& (EXEC_OBJECT_NEEDS_FENCE
| __EXEC_OBJECT_NEEDS_MAP
)) ==
754 __EXEC_OBJECT_NEEDS_MAP
;
758 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
759 struct intel_engine_cs
*engine
,
762 struct drm_i915_gem_object
*obj
= vma
->obj
;
763 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
768 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
771 if (!drm_mm_node_allocated(&vma
->node
)) {
772 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
773 * limit address to the first 4GBs for unflagged objects.
775 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0)
776 flags
|= PIN_ZONE_4G
;
777 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
778 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
779 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
780 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
781 if (entry
->flags
& EXEC_OBJECT_PINNED
)
782 flags
|= entry
->offset
| PIN_OFFSET_FIXED
;
783 if ((flags
& PIN_MAPPABLE
) == 0)
787 ret
= i915_vma_pin(vma
,
791 if ((ret
== -ENOSPC
|| ret
== -E2BIG
) &&
792 only_mappable_for_reloc(entry
->flags
))
793 ret
= i915_vma_pin(vma
,
796 flags
& ~PIN_MAPPABLE
);
800 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
802 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
803 ret
= i915_vma_get_fence(vma
);
807 if (i915_vma_pin_fence(vma
))
808 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
811 if (entry
->offset
!= vma
->node
.start
) {
812 entry
->offset
= vma
->node
.start
;
816 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
817 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
818 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
825 need_reloc_mappable(struct i915_vma
*vma
)
827 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
829 if (entry
->relocation_count
== 0)
832 if (!i915_vma_is_ggtt(vma
))
835 /* See also use_cpu_reloc() */
836 if (HAS_LLC(vma
->obj
->base
.dev
))
839 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
846 eb_vma_misplaced(struct i915_vma
*vma
)
848 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
850 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
851 !i915_vma_is_ggtt(vma
));
853 if (entry
->alignment
&&
854 vma
->node
.start
& (entry
->alignment
- 1))
857 if (vma
->node
.size
< entry
->pad_to_size
)
860 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
861 vma
->node
.start
!= entry
->offset
)
864 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
865 vma
->node
.start
< BATCH_OFFSET_BIAS
)
868 /* avoid costly ping-pong once a batch bo ended up non-mappable */
869 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
870 !i915_vma_is_map_and_fenceable(vma
))
871 return !only_mappable_for_reloc(entry
->flags
);
873 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0 &&
874 (vma
->node
.start
+ vma
->node
.size
- 1) >> 32)
881 i915_gem_execbuffer_reserve(struct intel_engine_cs
*engine
,
882 struct list_head
*vmas
,
883 struct i915_gem_context
*ctx
,
886 struct drm_i915_gem_object
*obj
;
887 struct i915_vma
*vma
;
888 struct i915_address_space
*vm
;
889 struct list_head ordered_vmas
;
890 struct list_head pinned_vmas
;
891 bool has_fenced_gpu_access
= INTEL_GEN(engine
->i915
) < 4;
894 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
896 INIT_LIST_HEAD(&ordered_vmas
);
897 INIT_LIST_HEAD(&pinned_vmas
);
898 while (!list_empty(vmas
)) {
899 struct drm_i915_gem_exec_object2
*entry
;
900 bool need_fence
, need_mappable
;
902 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
904 entry
= vma
->exec_entry
;
906 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
907 entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
909 if (!has_fenced_gpu_access
)
910 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
912 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
913 i915_gem_object_is_tiled(obj
);
914 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
916 if (entry
->flags
& EXEC_OBJECT_PINNED
)
917 list_move_tail(&vma
->exec_list
, &pinned_vmas
);
918 else if (need_mappable
) {
919 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
920 list_move(&vma
->exec_list
, &ordered_vmas
);
922 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
924 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
925 obj
->base
.pending_write_domain
= 0;
927 list_splice(&ordered_vmas
, vmas
);
928 list_splice(&pinned_vmas
, vmas
);
930 /* Attempt to pin all of the buffers into the GTT.
931 * This is done in 3 phases:
933 * 1a. Unbind all objects that do not match the GTT constraints for
934 * the execbuffer (fenceable, mappable, alignment etc).
935 * 1b. Increment pin count for already bound objects.
936 * 2. Bind new objects.
937 * 3. Decrement pin count.
939 * This avoid unnecessary unbinding of later objects in order to make
940 * room for the earlier objects *unless* we need to defragment.
946 /* Unbind any ill-fitting objects or pin. */
947 list_for_each_entry(vma
, vmas
, exec_list
) {
948 if (!drm_mm_node_allocated(&vma
->node
))
951 if (eb_vma_misplaced(vma
))
952 ret
= i915_vma_unbind(vma
);
954 ret
= i915_gem_execbuffer_reserve_vma(vma
,
961 /* Bind fresh objects */
962 list_for_each_entry(vma
, vmas
, exec_list
) {
963 if (drm_mm_node_allocated(&vma
->node
))
966 ret
= i915_gem_execbuffer_reserve_vma(vma
, engine
,
973 if (ret
!= -ENOSPC
|| retry
++)
976 /* Decrement pin count for bound objects */
977 list_for_each_entry(vma
, vmas
, exec_list
)
978 i915_gem_execbuffer_unreserve_vma(vma
);
980 ret
= i915_gem_evict_vm(vm
, true);
987 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
988 struct drm_i915_gem_execbuffer2
*args
,
989 struct drm_file
*file
,
990 struct intel_engine_cs
*engine
,
992 struct drm_i915_gem_exec_object2
*exec
,
993 struct i915_gem_context
*ctx
)
995 struct drm_i915_gem_relocation_entry
*reloc
;
996 struct i915_address_space
*vm
;
997 struct i915_vma
*vma
;
1001 unsigned count
= args
->buffer_count
;
1003 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
1005 /* We may process another execbuffer during the unlock... */
1006 while (!list_empty(&eb
->vmas
)) {
1007 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
1008 list_del_init(&vma
->exec_list
);
1009 i915_gem_execbuffer_unreserve_vma(vma
);
1013 mutex_unlock(&dev
->struct_mutex
);
1016 for (i
= 0; i
< count
; i
++)
1017 total
+= exec
[i
].relocation_count
;
1019 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
1020 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
1021 if (reloc
== NULL
|| reloc_offset
== NULL
) {
1022 drm_free_large(reloc
);
1023 drm_free_large(reloc_offset
);
1024 mutex_lock(&dev
->struct_mutex
);
1029 for (i
= 0; i
< count
; i
++) {
1030 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
1031 u64 invalid_offset
= (u64
)-1;
1034 user_relocs
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
1036 if (copy_from_user(reloc
+total
, user_relocs
,
1037 exec
[i
].relocation_count
* sizeof(*reloc
))) {
1039 mutex_lock(&dev
->struct_mutex
);
1043 /* As we do not update the known relocation offsets after
1044 * relocating (due to the complexities in lock handling),
1045 * we need to mark them as invalid now so that we force the
1046 * relocation processing next time. Just in case the target
1047 * object is evicted and then rebound into its old
1048 * presumed_offset before the next execbuffer - if that
1049 * happened we would make the mistake of assuming that the
1050 * relocations were valid.
1052 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
1053 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
1055 sizeof(invalid_offset
))) {
1057 mutex_lock(&dev
->struct_mutex
);
1062 reloc_offset
[i
] = total
;
1063 total
+= exec
[i
].relocation_count
;
1066 ret
= i915_mutex_lock_interruptible(dev
);
1068 mutex_lock(&dev
->struct_mutex
);
1072 /* reacquire the objects */
1074 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1078 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1079 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1084 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
1085 int offset
= vma
->exec_entry
- exec
;
1086 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
1087 reloc
+ reloc_offset
[offset
]);
1092 /* Leave the user relocations as are, this is the painfully slow path,
1093 * and we want to avoid the complication of dropping the lock whilst
1094 * having buffers reserved in the aperture and so causing spurious
1095 * ENOSPC for random operations.
1099 drm_free_large(reloc
);
1100 drm_free_large(reloc_offset
);
1105 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req
,
1106 struct list_head
*vmas
)
1108 struct i915_vma
*vma
;
1111 list_for_each_entry(vma
, vmas
, exec_list
) {
1112 struct drm_i915_gem_object
*obj
= vma
->obj
;
1114 ret
= i915_gem_request_await_object
1115 (req
, obj
, obj
->base
.pending_write_domain
);
1119 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
1120 i915_gem_clflush_object(obj
, false);
1123 /* Unconditionally flush any chipset caches (for streaming writes). */
1124 i915_gem_chipset_flush(req
->engine
->i915
);
1126 /* Unconditionally invalidate GPU caches and TLBs. */
1127 return req
->engine
->emit_flush(req
, EMIT_INVALIDATE
);
1131 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
1133 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
1136 /* Kernel clipping was a DRI1 misfeature */
1137 if (exec
->num_cliprects
|| exec
->cliprects_ptr
)
1140 if (exec
->DR4
== 0xffffffff) {
1141 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1144 if (exec
->DR1
|| exec
->DR4
)
1147 if ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7)
1154 validate_exec_list(struct drm_device
*dev
,
1155 struct drm_i915_gem_exec_object2
*exec
,
1158 unsigned relocs_total
= 0;
1159 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
1160 unsigned invalid_flags
;
1163 /* INTERNAL flags must not overlap with external ones */
1164 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS
& ~__EXEC_OBJECT_UNKNOWN_FLAGS
);
1166 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
1167 if (USES_FULL_PPGTT(dev
))
1168 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
1170 for (i
= 0; i
< count
; i
++) {
1171 char __user
*ptr
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
1172 int length
; /* limited by fault_in_pages_readable() */
1174 if (exec
[i
].flags
& invalid_flags
)
1177 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1178 * any non-page-aligned or non-canonical addresses.
1180 if (exec
[i
].flags
& EXEC_OBJECT_PINNED
) {
1181 if (exec
[i
].offset
!=
1182 gen8_canonical_addr(exec
[i
].offset
& PAGE_MASK
))
1185 /* From drm_mm perspective address space is continuous,
1186 * so from this point we're always using non-canonical
1189 exec
[i
].offset
= gen8_noncanonical_addr(exec
[i
].offset
);
1192 if (exec
[i
].alignment
&& !is_power_of_2(exec
[i
].alignment
))
1195 /* pad_to_size was once a reserved field, so sanitize it */
1196 if (exec
[i
].flags
& EXEC_OBJECT_PAD_TO_SIZE
) {
1197 if (offset_in_page(exec
[i
].pad_to_size
))
1200 exec
[i
].pad_to_size
= 0;
1203 /* First check for malicious input causing overflow in
1204 * the worst case where we need to allocate the entire
1205 * relocation tree as a single array.
1207 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
1209 relocs_total
+= exec
[i
].relocation_count
;
1211 length
= exec
[i
].relocation_count
*
1212 sizeof(struct drm_i915_gem_relocation_entry
);
1214 * We must check that the entire relocation array is safe
1215 * to read, but since we may need to update the presumed
1216 * offsets during execution, check for full write access.
1218 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
1221 if (likely(!i915
.prefault_disable
)) {
1222 if (fault_in_pages_readable(ptr
, length
))
1230 static struct i915_gem_context
*
1231 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
1232 struct intel_engine_cs
*engine
, const u32 ctx_id
)
1234 struct i915_gem_context
*ctx
;
1235 struct i915_ctx_hang_stats
*hs
;
1237 ctx
= i915_gem_context_lookup(file
->driver_priv
, ctx_id
);
1241 hs
= &ctx
->hang_stats
;
1243 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
1244 return ERR_PTR(-EIO
);
1250 static bool gpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
1252 return !(obj
->cache_level
== I915_CACHE_NONE
||
1253 obj
->cache_level
== I915_CACHE_WT
);
1256 void i915_vma_move_to_active(struct i915_vma
*vma
,
1257 struct drm_i915_gem_request
*req
,
1260 struct drm_i915_gem_object
*obj
= vma
->obj
;
1261 const unsigned int idx
= req
->engine
->id
;
1263 GEM_BUG_ON(!drm_mm_node_allocated(&vma
->node
));
1265 /* Add a reference if we're newly entering the active list.
1266 * The order in which we add operations to the retirement queue is
1267 * vital here: mark_active adds to the start of the callback list,
1268 * such that subsequent callbacks are called first. Therefore we
1269 * add the active reference first and queue for it to be dropped
1272 if (!i915_vma_is_active(vma
))
1273 obj
->active_count
++;
1274 i915_vma_set_active(vma
, idx
);
1275 i915_gem_active_set(&vma
->last_read
[idx
], req
);
1276 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
1278 if (flags
& EXEC_OBJECT_WRITE
) {
1279 i915_gem_active_set(&vma
->last_write
, req
);
1281 intel_fb_obj_invalidate(obj
, ORIGIN_CS
);
1283 /* update for the implicit flush after a batch */
1284 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1285 if (!obj
->cache_dirty
&& gpu_write_needs_clflush(obj
))
1286 obj
->cache_dirty
= true;
1289 if (flags
& EXEC_OBJECT_NEEDS_FENCE
)
1290 i915_gem_active_set(&vma
->last_fence
, req
);
1293 static void eb_export_fence(struct drm_i915_gem_object
*obj
,
1294 struct drm_i915_gem_request
*req
,
1297 struct reservation_object
*resv
= obj
->resv
;
1299 /* Ignore errors from failing to allocate the new fence, we can't
1300 * handle an error right now. Worst case should be missed
1301 * synchronisation leading to rendering corruption.
1303 ww_mutex_lock(&resv
->lock
, NULL
);
1304 if (flags
& EXEC_OBJECT_WRITE
)
1305 reservation_object_add_excl_fence(resv
, &req
->fence
);
1306 else if (reservation_object_reserve_shared(resv
) == 0)
1307 reservation_object_add_shared_fence(resv
, &req
->fence
);
1308 ww_mutex_unlock(&resv
->lock
);
1312 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
1313 struct drm_i915_gem_request
*req
)
1315 struct i915_vma
*vma
;
1317 list_for_each_entry(vma
, vmas
, exec_list
) {
1318 struct drm_i915_gem_object
*obj
= vma
->obj
;
1319 u32 old_read
= obj
->base
.read_domains
;
1320 u32 old_write
= obj
->base
.write_domain
;
1322 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
1323 if (obj
->base
.write_domain
)
1324 vma
->exec_entry
->flags
|= EXEC_OBJECT_WRITE
;
1326 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
1327 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
1329 i915_vma_move_to_active(vma
, req
, vma
->exec_entry
->flags
);
1330 eb_export_fence(obj
, req
, vma
->exec_entry
->flags
);
1331 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
1336 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request
*req
)
1338 struct intel_ring
*ring
= req
->ring
;
1341 if (!IS_GEN7(req
->i915
) || req
->engine
->id
!= RCS
) {
1342 DRM_DEBUG("sol reset is gen7/rcs only\n");
1346 ret
= intel_ring_begin(req
, 4 * 3);
1350 for (i
= 0; i
< 4; i
++) {
1351 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1352 intel_ring_emit_reg(ring
, GEN7_SO_WRITE_OFFSET(i
));
1353 intel_ring_emit(ring
, 0);
1356 intel_ring_advance(ring
);
1361 static struct i915_vma
*
1362 i915_gem_execbuffer_parse(struct intel_engine_cs
*engine
,
1363 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1364 struct drm_i915_gem_object
*batch_obj
,
1366 u32 batch_start_offset
,
1370 struct drm_i915_gem_object
*shadow_batch_obj
;
1371 struct i915_vma
*vma
;
1374 shadow_batch_obj
= i915_gem_batch_pool_get(&engine
->batch_pool
,
1375 PAGE_ALIGN(batch_len
));
1376 if (IS_ERR(shadow_batch_obj
))
1377 return ERR_CAST(shadow_batch_obj
);
1379 ret
= intel_engine_cmd_parser(engine
,
1386 if (ret
== -EACCES
) /* unhandled chained batch */
1393 vma
= i915_gem_object_ggtt_pin(shadow_batch_obj
, NULL
, 0, 0, 0);
1397 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1399 vma
->exec_entry
= shadow_exec_entry
;
1400 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
;
1401 i915_gem_object_get(shadow_batch_obj
);
1402 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1405 i915_gem_object_unpin_pages(shadow_batch_obj
);
1410 execbuf_submit(struct i915_execbuffer_params
*params
,
1411 struct drm_i915_gem_execbuffer2
*args
,
1412 struct list_head
*vmas
)
1414 struct drm_i915_private
*dev_priv
= params
->request
->i915
;
1415 u64 exec_start
, exec_len
;
1420 ret
= i915_gem_execbuffer_move_to_gpu(params
->request
, vmas
);
1424 ret
= i915_switch_context(params
->request
);
1428 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1429 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1430 switch (instp_mode
) {
1431 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1432 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1433 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1434 if (instp_mode
!= 0 && params
->engine
->id
!= RCS
) {
1435 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1439 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1440 if (INTEL_INFO(dev_priv
)->gen
< 4) {
1441 DRM_DEBUG("no rel constants on pre-gen4\n");
1445 if (INTEL_INFO(dev_priv
)->gen
> 5 &&
1446 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1447 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1451 /* The HW changed the meaning on this bit on gen6 */
1452 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1453 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1457 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1461 if (params
->engine
->id
== RCS
&&
1462 instp_mode
!= dev_priv
->relative_constants_mode
) {
1463 struct intel_ring
*ring
= params
->request
->ring
;
1465 ret
= intel_ring_begin(params
->request
, 4);
1469 intel_ring_emit(ring
, MI_NOOP
);
1470 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1471 intel_ring_emit_reg(ring
, INSTPM
);
1472 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1473 intel_ring_advance(ring
);
1475 dev_priv
->relative_constants_mode
= instp_mode
;
1478 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1479 ret
= i915_reset_gen7_sol_offsets(params
->request
);
1484 exec_len
= args
->batch_len
;
1485 exec_start
= params
->batch
->node
.start
+
1486 params
->args_batch_start_offset
;
1489 exec_len
= params
->batch
->size
- params
->args_batch_start_offset
;
1491 ret
= params
->engine
->emit_bb_start(params
->request
,
1492 exec_start
, exec_len
,
1493 params
->dispatch_flags
);
1497 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1499 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1505 * Find one BSD ring to dispatch the corresponding BSD command.
1506 * The engine index is returned.
1509 gen8_dispatch_bsd_engine(struct drm_i915_private
*dev_priv
,
1510 struct drm_file
*file
)
1512 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1514 /* Check whether the file_priv has already selected one ring. */
1515 if ((int)file_priv
->bsd_engine
< 0)
1516 file_priv
->bsd_engine
= atomic_fetch_xor(1,
1517 &dev_priv
->mm
.bsd_engine_dispatch_index
);
1519 return file_priv
->bsd_engine
;
1522 #define I915_USER_RINGS (4)
1524 static const enum intel_engine_id user_ring_map
[I915_USER_RINGS
+ 1] = {
1525 [I915_EXEC_DEFAULT
] = RCS
,
1526 [I915_EXEC_RENDER
] = RCS
,
1527 [I915_EXEC_BLT
] = BCS
,
1528 [I915_EXEC_BSD
] = VCS
,
1529 [I915_EXEC_VEBOX
] = VECS
1532 static struct intel_engine_cs
*
1533 eb_select_engine(struct drm_i915_private
*dev_priv
,
1534 struct drm_file
*file
,
1535 struct drm_i915_gem_execbuffer2
*args
)
1537 unsigned int user_ring_id
= args
->flags
& I915_EXEC_RING_MASK
;
1538 struct intel_engine_cs
*engine
;
1540 if (user_ring_id
> I915_USER_RINGS
) {
1541 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id
);
1545 if ((user_ring_id
!= I915_EXEC_BSD
) &&
1546 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1547 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1548 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1552 if (user_ring_id
== I915_EXEC_BSD
&& HAS_BSD2(dev_priv
)) {
1553 unsigned int bsd_idx
= args
->flags
& I915_EXEC_BSD_MASK
;
1555 if (bsd_idx
== I915_EXEC_BSD_DEFAULT
) {
1556 bsd_idx
= gen8_dispatch_bsd_engine(dev_priv
, file
);
1557 } else if (bsd_idx
>= I915_EXEC_BSD_RING1
&&
1558 bsd_idx
<= I915_EXEC_BSD_RING2
) {
1559 bsd_idx
>>= I915_EXEC_BSD_SHIFT
;
1562 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1567 engine
= dev_priv
->engine
[_VCS(bsd_idx
)];
1569 engine
= dev_priv
->engine
[user_ring_map
[user_ring_id
]];
1573 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id
);
1581 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1582 struct drm_file
*file
,
1583 struct drm_i915_gem_execbuffer2
*args
,
1584 struct drm_i915_gem_exec_object2
*exec
)
1586 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1587 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1589 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1590 struct intel_engine_cs
*engine
;
1591 struct i915_gem_context
*ctx
;
1592 struct i915_address_space
*vm
;
1593 struct i915_execbuffer_params params_master
; /* XXX: will be removed later */
1594 struct i915_execbuffer_params
*params
= ¶ms_master
;
1595 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1600 if (!i915_gem_check_execbuffer(args
))
1603 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1608 if (args
->flags
& I915_EXEC_SECURE
) {
1609 if (!drm_is_current_master(file
) || !capable(CAP_SYS_ADMIN
))
1612 dispatch_flags
|= I915_DISPATCH_SECURE
;
1614 if (args
->flags
& I915_EXEC_IS_PINNED
)
1615 dispatch_flags
|= I915_DISPATCH_PINNED
;
1617 engine
= eb_select_engine(dev_priv
, file
, args
);
1621 if (args
->buffer_count
< 1) {
1622 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1626 if (args
->flags
& I915_EXEC_RESOURCE_STREAMER
) {
1627 if (!HAS_RESOURCE_STREAMER(dev
)) {
1628 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1631 if (engine
->id
!= RCS
) {
1632 DRM_DEBUG("RS is not available on %s\n",
1637 dispatch_flags
|= I915_DISPATCH_RS
;
1640 /* Take a local wakeref for preparing to dispatch the execbuf as
1641 * we expect to access the hardware fairly frequently in the
1642 * process. Upon first dispatch, we acquire another prolonged
1643 * wakeref that we hold until the GPU has been idle for at least
1646 intel_runtime_pm_get(dev_priv
);
1648 ret
= i915_mutex_lock_interruptible(dev
);
1652 ctx
= i915_gem_validate_context(dev
, file
, engine
, ctx_id
);
1654 mutex_unlock(&dev
->struct_mutex
);
1659 i915_gem_context_get(ctx
);
1662 vm
= &ctx
->ppgtt
->base
;
1666 memset(¶ms_master
, 0x00, sizeof(params_master
));
1668 eb
= eb_create(dev_priv
, args
);
1670 i915_gem_context_put(ctx
);
1671 mutex_unlock(&dev
->struct_mutex
);
1676 /* Look up object handles */
1677 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1681 /* take note of the batch buffer before we might reorder the lists */
1682 params
->batch
= eb_get_batch(eb
);
1684 /* Move the objects en-masse into the GTT, evicting if necessary. */
1685 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1686 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1691 /* The objects are in their final locations, apply the relocations. */
1693 ret
= i915_gem_execbuffer_relocate(eb
);
1695 if (ret
== -EFAULT
) {
1696 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
,
1699 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1705 /* Set the pending read domains for the batch buffer to COMMAND */
1706 if (params
->batch
->obj
->base
.pending_write_domain
) {
1707 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1711 if (args
->batch_start_offset
> params
->batch
->size
||
1712 args
->batch_len
> params
->batch
->size
- args
->batch_start_offset
) {
1713 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1718 params
->args_batch_start_offset
= args
->batch_start_offset
;
1719 if (intel_engine_needs_cmd_parser(engine
) && args
->batch_len
) {
1720 struct i915_vma
*vma
;
1722 vma
= i915_gem_execbuffer_parse(engine
, &shadow_exec_entry
,
1725 args
->batch_start_offset
,
1727 drm_is_current_master(file
));
1735 * Batch parsed and accepted:
1737 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1738 * bit from MI_BATCH_BUFFER_START commands issued in
1739 * the dispatch_execbuffer implementations. We
1740 * specifically don't want that set on batches the
1741 * command parser has accepted.
1743 dispatch_flags
|= I915_DISPATCH_SECURE
;
1744 params
->args_batch_start_offset
= 0;
1745 params
->batch
= vma
;
1749 params
->batch
->obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1751 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1752 * batch" bit. Hence we need to pin secure batches into the global gtt.
1753 * hsw should have this fixed, but bdw mucks it up again. */
1754 if (dispatch_flags
& I915_DISPATCH_SECURE
) {
1755 struct drm_i915_gem_object
*obj
= params
->batch
->obj
;
1756 struct i915_vma
*vma
;
1759 * So on first glance it looks freaky that we pin the batch here
1760 * outside of the reservation loop. But:
1761 * - The batch is already pinned into the relevant ppgtt, so we
1762 * already have the backing storage fully allocated.
1763 * - No other BO uses the global gtt (well contexts, but meh),
1764 * so we don't really have issues with multiple objects not
1765 * fitting due to fragmentation.
1766 * So this is actually safe.
1768 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, 0);
1774 params
->batch
= vma
;
1777 /* Allocate a request for this batch buffer nice and early. */
1778 params
->request
= i915_gem_request_alloc(engine
, ctx
);
1779 if (IS_ERR(params
->request
)) {
1780 ret
= PTR_ERR(params
->request
);
1781 goto err_batch_unpin
;
1784 /* Whilst this request exists, batch_obj will be on the
1785 * active_list, and so will hold the active reference. Only when this
1786 * request is retired will the the batch_obj be moved onto the
1787 * inactive_list and lose its active reference. Hence we do not need
1788 * to explicitly hold another reference here.
1790 params
->request
->batch
= params
->batch
;
1792 ret
= i915_gem_request_add_to_client(params
->request
, file
);
1797 * Save assorted stuff away to pass through to *_submission().
1798 * NB: This data should be 'persistent' and not local as it will
1799 * kept around beyond the duration of the IOCTL once the GPU
1800 * scheduler arrives.
1803 params
->file
= file
;
1804 params
->engine
= engine
;
1805 params
->dispatch_flags
= dispatch_flags
;
1808 ret
= execbuf_submit(params
, args
, &eb
->vmas
);
1810 __i915_add_request(params
->request
, ret
== 0);
1814 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1815 * batch vma for correctness. For less ugly and less fragility this
1816 * needs to be adjusted to also track the ggtt batch vma properly as
1819 if (dispatch_flags
& I915_DISPATCH_SECURE
)
1820 i915_vma_unpin(params
->batch
);
1822 /* the request owns the ref now */
1823 i915_gem_context_put(ctx
);
1826 mutex_unlock(&dev
->struct_mutex
);
1829 /* intel_gpu_busy should also get a ref, so it will free when the device
1830 * is really idle. */
1831 intel_runtime_pm_put(dev_priv
);
1836 * Legacy execbuffer just creates an exec2 list from the original exec object
1837 * list array and passes it to the real function.
1840 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1841 struct drm_file
*file
)
1843 struct drm_i915_gem_execbuffer
*args
= data
;
1844 struct drm_i915_gem_execbuffer2 exec2
;
1845 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1846 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1849 if (args
->buffer_count
< 1) {
1850 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1854 /* Copy in the exec list from userland */
1855 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1856 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1857 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1858 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1859 args
->buffer_count
);
1860 drm_free_large(exec_list
);
1861 drm_free_large(exec2_list
);
1864 ret
= copy_from_user(exec_list
,
1865 u64_to_user_ptr(args
->buffers_ptr
),
1866 sizeof(*exec_list
) * args
->buffer_count
);
1868 DRM_DEBUG("copy %d exec entries failed %d\n",
1869 args
->buffer_count
, ret
);
1870 drm_free_large(exec_list
);
1871 drm_free_large(exec2_list
);
1875 for (i
= 0; i
< args
->buffer_count
; i
++) {
1876 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1877 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1878 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1879 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1880 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1881 if (INTEL_INFO(dev
)->gen
< 4)
1882 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1884 exec2_list
[i
].flags
= 0;
1887 exec2
.buffers_ptr
= args
->buffers_ptr
;
1888 exec2
.buffer_count
= args
->buffer_count
;
1889 exec2
.batch_start_offset
= args
->batch_start_offset
;
1890 exec2
.batch_len
= args
->batch_len
;
1891 exec2
.DR1
= args
->DR1
;
1892 exec2
.DR4
= args
->DR4
;
1893 exec2
.num_cliprects
= args
->num_cliprects
;
1894 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1895 exec2
.flags
= I915_EXEC_RENDER
;
1896 i915_execbuffer2_set_context_id(exec2
, 0);
1898 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1900 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1901 u64_to_user_ptr(args
->buffers_ptr
);
1903 /* Copy the new buffer offsets back to the user's exec list. */
1904 for (i
= 0; i
< args
->buffer_count
; i
++) {
1905 exec2_list
[i
].offset
=
1906 gen8_canonical_addr(exec2_list
[i
].offset
);
1907 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1908 &exec2_list
[i
].offset
,
1909 sizeof(user_exec_list
[i
].offset
));
1912 DRM_DEBUG("failed to copy %d exec entries "
1913 "back to user (%d)\n",
1914 args
->buffer_count
, ret
);
1920 drm_free_large(exec_list
);
1921 drm_free_large(exec2_list
);
1926 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1927 struct drm_file
*file
)
1929 struct drm_i915_gem_execbuffer2
*args
= data
;
1930 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1933 if (args
->buffer_count
< 1 ||
1934 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1935 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1939 if (args
->rsvd2
!= 0) {
1940 DRM_DEBUG("dirty rvsd2 field\n");
1944 exec2_list
= drm_malloc_gfp(args
->buffer_count
,
1945 sizeof(*exec2_list
),
1947 if (exec2_list
== NULL
) {
1948 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1949 args
->buffer_count
);
1952 ret
= copy_from_user(exec2_list
,
1953 u64_to_user_ptr(args
->buffers_ptr
),
1954 sizeof(*exec2_list
) * args
->buffer_count
);
1956 DRM_DEBUG("copy %d exec entries failed %d\n",
1957 args
->buffer_count
, ret
);
1958 drm_free_large(exec2_list
);
1962 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1964 /* Copy the new buffer offsets back to the user's exec list. */
1965 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1966 u64_to_user_ptr(args
->buffers_ptr
);
1969 for (i
= 0; i
< args
->buffer_count
; i
++) {
1970 exec2_list
[i
].offset
=
1971 gen8_canonical_addr(exec2_list
[i
].offset
);
1972 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1973 &exec2_list
[i
].offset
,
1974 sizeof(user_exec_list
[i
].offset
));
1977 DRM_DEBUG("failed to copy %d exec entries "
1979 args
->buffer_count
);
1985 drm_free_large(exec2_list
);