2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
98 const struct i915_ggtt_view i915_ggtt_view_normal
;
99 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
100 .type
= I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device
*dev
, int enable_ppgtt
)
105 bool has_aliasing_ppgtt
;
108 has_aliasing_ppgtt
= INTEL_INFO(dev
)->gen
>= 6;
109 has_full_ppgtt
= INTEL_INFO(dev
)->gen
>= 7;
111 if (intel_vgpu_active(dev
))
112 has_full_ppgtt
= false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev
)->gen
< 9 &&
119 (enable_ppgtt
== 0 || !has_aliasing_ppgtt
))
122 if (enable_ppgtt
== 1)
125 if (enable_ppgtt
== 2 && has_full_ppgtt
)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
138 dev
->pdev
->revision
< 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev
)->gen
>= 8 && i915
.enable_execlists
)
146 return has_aliasing_ppgtt
? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma
*vma
,
150 enum i915_cache_level cache_level
,
155 /* Currently applicable only to VLV */
157 pte_flags
|= PTE_READ_ONLY
;
159 vma
->vm
->insert_entries(vma
->vm
, vma
->obj
->pages
, vma
->node
.start
,
160 cache_level
, pte_flags
);
165 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
167 vma
->vm
->clear_range(vma
->vm
,
173 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
174 enum i915_cache_level level
,
177 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
181 case I915_CACHE_NONE
:
182 pte
|= PPAT_UNCACHED_INDEX
;
185 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
188 pte
|= PPAT_CACHED_INDEX
;
195 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
196 const enum i915_cache_level level
)
198 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
200 if (level
!= I915_CACHE_NONE
)
201 pde
|= PPAT_CACHED_PDE_INDEX
;
203 pde
|= PPAT_UNCACHED_INDEX
;
207 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
208 enum i915_cache_level level
,
209 bool valid
, u32 unused
)
211 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
212 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
215 case I915_CACHE_L3_LLC
:
217 pte
|= GEN6_PTE_CACHE_LLC
;
219 case I915_CACHE_NONE
:
220 pte
|= GEN6_PTE_UNCACHED
;
229 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
230 enum i915_cache_level level
,
231 bool valid
, u32 unused
)
233 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
234 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
237 case I915_CACHE_L3_LLC
:
238 pte
|= GEN7_PTE_CACHE_L3_LLC
;
241 pte
|= GEN6_PTE_CACHE_LLC
;
243 case I915_CACHE_NONE
:
244 pte
|= GEN6_PTE_UNCACHED
;
253 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
254 enum i915_cache_level level
,
255 bool valid
, u32 flags
)
257 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
258 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
260 if (!(flags
& PTE_READ_ONLY
))
261 pte
|= BYT_PTE_WRITEABLE
;
263 if (level
!= I915_CACHE_NONE
)
264 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
269 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
270 enum i915_cache_level level
,
271 bool valid
, u32 unused
)
273 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
274 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
276 if (level
!= I915_CACHE_NONE
)
277 pte
|= HSW_WB_LLC_AGE3
;
282 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
283 enum i915_cache_level level
,
284 bool valid
, u32 unused
)
286 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
287 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
290 case I915_CACHE_NONE
:
293 pte
|= HSW_WT_ELLC_LLC_AGE3
;
296 pte
|= HSW_WB_ELLC_LLC_AGE3
;
303 static int __setup_page_dma(struct drm_device
*dev
,
304 struct i915_page_dma
*p
, gfp_t flags
)
306 struct device
*device
= &dev
->pdev
->dev
;
308 p
->page
= alloc_page(flags
);
312 p
->daddr
= dma_map_page(device
,
313 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
315 if (dma_mapping_error(device
, p
->daddr
)) {
316 __free_page(p
->page
);
323 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
325 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
328 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
330 if (WARN_ON(!p
->page
))
333 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
334 __free_page(p
->page
);
335 memset(p
, 0, sizeof(*p
));
338 static void *kmap_page_dma(struct i915_page_dma
*p
)
340 return kmap_atomic(p
->page
);
343 /* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
346 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
351 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
352 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
354 kunmap_atomic(vaddr
);
357 #define kmap_px(px) kmap_page_dma(px_base(px))
358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
365 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
369 uint64_t * const vaddr
= kmap_page_dma(p
);
371 for (i
= 0; i
< 512; i
++)
374 kunmap_page_dma(dev
, vaddr
);
377 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
378 const uint32_t val32
)
384 fill_page_dma(dev
, p
, v
);
387 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
390 kfree(pt
->used_ptes
);
394 static void gen8_initialize_pt(struct i915_address_space
*vm
,
395 struct i915_page_table
*pt
)
397 gen8_pte_t scratch_pte
;
399 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
400 I915_CACHE_LLC
, true);
402 fill_px(vm
->dev
, pt
, scratch_pte
);
405 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
407 struct i915_page_table
*pt
;
408 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
409 GEN8_PTES
: GEN6_PTES
;
412 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
414 return ERR_PTR(-ENOMEM
);
416 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
422 ret
= setup_px(dev
, pt
);
429 kfree(pt
->used_ptes
);
436 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
440 kfree(pd
->used_pdes
);
445 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
447 struct i915_page_directory
*pd
;
450 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
452 return ERR_PTR(-ENOMEM
);
454 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
455 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
459 ret
= setup_px(dev
, pd
);
466 kfree(pd
->used_pdes
);
473 /* Broadwell Page Directory Pointer Descriptors */
474 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
478 struct intel_engine_cs
*ring
= req
->ring
;
483 ret
= intel_ring_begin(req
, 6);
487 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
488 intel_ring_emit(ring
, GEN8_RING_PDP_UDW(ring
, entry
));
489 intel_ring_emit(ring
, upper_32_bits(addr
));
490 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
491 intel_ring_emit(ring
, GEN8_RING_PDP_LDW(ring
, entry
));
492 intel_ring_emit(ring
, lower_32_bits(addr
));
493 intel_ring_advance(ring
);
498 static int gen8_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
499 struct drm_i915_gem_request
*req
)
503 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
504 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
506 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
514 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
519 struct i915_hw_ppgtt
*ppgtt
=
520 container_of(vm
, struct i915_hw_ppgtt
, base
);
521 gen8_pte_t
*pt_vaddr
, scratch_pte
;
522 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
523 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
524 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
525 unsigned num_entries
= length
>> PAGE_SHIFT
;
526 unsigned last_pte
, i
;
528 scratch_pte
= gen8_pte_encode(px_dma(ppgtt
->base
.scratch_page
),
529 I915_CACHE_LLC
, use_scratch
);
531 while (num_entries
) {
532 struct i915_page_directory
*pd
;
533 struct i915_page_table
*pt
;
535 if (WARN_ON(!ppgtt
->pdp
.page_directory
[pdpe
]))
538 pd
= ppgtt
->pdp
.page_directory
[pdpe
];
540 if (WARN_ON(!pd
->page_table
[pde
]))
543 pt
= pd
->page_table
[pde
];
545 if (WARN_ON(!px_page(pt
)))
548 last_pte
= pte
+ num_entries
;
549 if (last_pte
> GEN8_PTES
)
550 last_pte
= GEN8_PTES
;
552 pt_vaddr
= kmap_px(pt
);
554 for (i
= pte
; i
< last_pte
; i
++) {
555 pt_vaddr
[i
] = scratch_pte
;
559 kunmap_px(ppgtt
, pt
);
562 if (++pde
== I915_PDES
) {
569 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
570 struct sg_table
*pages
,
572 enum i915_cache_level cache_level
, u32 unused
)
574 struct i915_hw_ppgtt
*ppgtt
=
575 container_of(vm
, struct i915_hw_ppgtt
, base
);
576 gen8_pte_t
*pt_vaddr
;
577 unsigned pdpe
= start
>> GEN8_PDPE_SHIFT
& GEN8_PDPE_MASK
;
578 unsigned pde
= start
>> GEN8_PDE_SHIFT
& GEN8_PDE_MASK
;
579 unsigned pte
= start
>> GEN8_PTE_SHIFT
& GEN8_PTE_MASK
;
580 struct sg_page_iter sg_iter
;
584 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
585 if (WARN_ON(pdpe
>= GEN8_LEGACY_PDPES
))
588 if (pt_vaddr
== NULL
) {
589 struct i915_page_directory
*pd
= ppgtt
->pdp
.page_directory
[pdpe
];
590 struct i915_page_table
*pt
= pd
->page_table
[pde
];
591 pt_vaddr
= kmap_px(pt
);
595 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter
),
597 if (++pte
== GEN8_PTES
) {
598 kunmap_px(ppgtt
, pt_vaddr
);
600 if (++pde
== I915_PDES
) {
609 kunmap_px(ppgtt
, pt_vaddr
);
612 static void gen8_initialize_pd(struct i915_address_space
*vm
,
613 struct i915_page_directory
*pd
)
615 struct i915_hw_ppgtt
*ppgtt
=
616 container_of(vm
, struct i915_hw_ppgtt
, base
);
617 gen8_pde_t scratch_pde
;
619 scratch_pde
= gen8_pde_encode(px_dma(ppgtt
->scratch_pt
),
622 fill_px(vm
->dev
, pd
, scratch_pde
);
625 static void gen8_free_page_tables(struct i915_page_directory
*pd
, struct drm_device
*dev
)
632 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
633 if (WARN_ON(!pd
->page_table
[i
]))
636 free_pt(dev
, pd
->page_table
[i
]);
637 pd
->page_table
[i
] = NULL
;
641 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
643 struct i915_hw_ppgtt
*ppgtt
=
644 container_of(vm
, struct i915_hw_ppgtt
, base
);
647 for_each_set_bit(i
, ppgtt
->pdp
.used_pdpes
, GEN8_LEGACY_PDPES
) {
648 if (WARN_ON(!ppgtt
->pdp
.page_directory
[i
]))
651 gen8_free_page_tables(ppgtt
->pdp
.page_directory
[i
], ppgtt
->base
.dev
);
652 free_pd(ppgtt
->base
.dev
, ppgtt
->pdp
.page_directory
[i
]);
655 free_pd(ppgtt
->base
.dev
, ppgtt
->scratch_pd
);
656 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
660 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
661 * @ppgtt: Master ppgtt structure.
662 * @pd: Page directory for this address range.
663 * @start: Starting virtual address to begin allocations.
664 * @length Size of the allocations.
665 * @new_pts: Bitmap set by function with new allocations. Likely used by the
666 * caller to free on error.
668 * Allocate the required number of page tables. Extremely similar to
669 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
670 * the page directory boundary (instead of the page directory pointer). That
671 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
672 * possible, and likely that the caller will need to use multiple calls of this
673 * function to achieve the appropriate allocation.
675 * Return: 0 if success; negative error code otherwise.
677 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt
*ppgtt
,
678 struct i915_page_directory
*pd
,
681 unsigned long *new_pts
)
683 struct drm_device
*dev
= ppgtt
->base
.dev
;
684 struct i915_page_table
*pt
;
688 gen8_for_each_pde(pt
, pd
, start
, length
, temp
, pde
) {
689 /* Don't reallocate page tables */
691 /* Scratch is never allocated this way */
692 WARN_ON(pt
== ppgtt
->scratch_pt
);
700 gen8_initialize_pt(&ppgtt
->base
, pt
);
701 pd
->page_table
[pde
] = pt
;
702 set_bit(pde
, new_pts
);
708 for_each_set_bit(pde
, new_pts
, I915_PDES
)
709 free_pt(dev
, pd
->page_table
[pde
]);
715 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
716 * @ppgtt: Master ppgtt structure.
717 * @pdp: Page directory pointer for this address range.
718 * @start: Starting virtual address to begin allocations.
719 * @length Size of the allocations.
720 * @new_pds Bitmap set by function with new allocations. Likely used by the
721 * caller to free on error.
723 * Allocate the required number of page directories starting at the pde index of
724 * @start, and ending at the pde index @start + @length. This function will skip
725 * over already allocated page directories within the range, and only allocate
726 * new ones, setting the appropriate pointer within the pdp as well as the
727 * correct position in the bitmap @new_pds.
729 * The function will only allocate the pages within the range for a give page
730 * directory pointer. In other words, if @start + @length straddles a virtually
731 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
732 * required by the caller, This is not currently possible, and the BUG in the
733 * code will prevent it.
735 * Return: 0 if success; negative error code otherwise.
737 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt
*ppgtt
,
738 struct i915_page_directory_pointer
*pdp
,
741 unsigned long *new_pds
)
743 struct drm_device
*dev
= ppgtt
->base
.dev
;
744 struct i915_page_directory
*pd
;
748 WARN_ON(!bitmap_empty(new_pds
, GEN8_LEGACY_PDPES
));
750 gen8_for_each_pdpe(pd
, pdp
, start
, length
, temp
, pdpe
) {
758 gen8_initialize_pd(&ppgtt
->base
, pd
);
759 pdp
->page_directory
[pdpe
] = pd
;
760 set_bit(pdpe
, new_pds
);
766 for_each_set_bit(pdpe
, new_pds
, GEN8_LEGACY_PDPES
)
767 free_pd(dev
, pdp
->page_directory
[pdpe
]);
773 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long **new_pts
)
777 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++)
783 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
784 * of these are based on the number of PDPEs in the system.
787 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
788 unsigned long ***new_pts
)
794 pds
= kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES
), sizeof(unsigned long), GFP_KERNEL
);
798 pts
= kcalloc(GEN8_LEGACY_PDPES
, sizeof(unsigned long *), GFP_KERNEL
);
804 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
805 pts
[i
] = kcalloc(BITS_TO_LONGS(I915_PDES
),
806 sizeof(unsigned long), GFP_KERNEL
);
817 free_gen8_temp_bitmaps(pds
, pts
);
821 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
822 * the page table structures, we mark them dirty so that
823 * context switching/execlist queuing code takes extra steps
824 * to ensure that tlbs are flushed.
826 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
828 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
831 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
835 struct i915_hw_ppgtt
*ppgtt
=
836 container_of(vm
, struct i915_hw_ppgtt
, base
);
837 unsigned long *new_page_dirs
, **new_page_tables
;
838 struct i915_page_directory
*pd
;
839 const uint64_t orig_start
= start
;
840 const uint64_t orig_length
= length
;
845 /* Wrap is never okay since we can only represent 48b, and we don't
846 * actually use the other side of the canonical address space.
848 if (WARN_ON(start
+ length
< start
))
851 if (WARN_ON(start
+ length
> ppgtt
->base
.total
))
854 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
);
858 /* Do the allocations first so we can easily bail out */
859 ret
= gen8_ppgtt_alloc_page_directories(ppgtt
, &ppgtt
->pdp
, start
, length
,
862 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
866 /* For every page directory referenced, allocate page tables */
867 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
868 ret
= gen8_ppgtt_alloc_pagetabs(ppgtt
, pd
, start
, length
,
869 new_page_tables
[pdpe
]);
875 length
= orig_length
;
877 /* Allocations have completed successfully, so set the bitmaps, and do
879 gen8_for_each_pdpe(pd
, &ppgtt
->pdp
, start
, length
, temp
, pdpe
) {
880 gen8_pde_t
*const page_directory
= kmap_px(pd
);
881 struct i915_page_table
*pt
;
882 uint64_t pd_len
= gen8_clamp_pd(start
, length
);
883 uint64_t pd_start
= start
;
886 /* Every pd should be allocated, we just did that above. */
889 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, temp
, pde
) {
890 /* Same reasoning as pd */
893 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
895 /* Set our used ptes within the page table */
896 bitmap_set(pt
->used_ptes
,
897 gen8_pte_index(pd_start
),
898 gen8_pte_count(pd_start
, pd_len
));
900 /* Our pde is now pointing to the pagetable, pt */
901 set_bit(pde
, pd
->used_pdes
);
903 /* Map the PDE to the page table */
904 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
907 /* NB: We haven't yet mapped ptes to pages. At this
908 * point we're still relying on insert_entries() */
911 kunmap_px(ppgtt
, page_directory
);
913 set_bit(pdpe
, ppgtt
->pdp
.used_pdpes
);
916 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
917 mark_tlbs_dirty(ppgtt
);
922 for_each_set_bit(temp
, new_page_tables
[pdpe
], I915_PDES
)
923 free_pt(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]->page_table
[temp
]);
926 for_each_set_bit(pdpe
, new_page_dirs
, GEN8_LEGACY_PDPES
)
927 free_pd(vm
->dev
, ppgtt
->pdp
.page_directory
[pdpe
]);
929 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
930 mark_tlbs_dirty(ppgtt
);
935 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
936 * with a net effect resembling a 2-level page table in normal x86 terms. Each
937 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
941 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
943 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
944 if (IS_ERR(ppgtt
->scratch_pt
))
945 return PTR_ERR(ppgtt
->scratch_pt
);
947 ppgtt
->scratch_pd
= alloc_pd(ppgtt
->base
.dev
);
948 if (IS_ERR(ppgtt
->scratch_pd
))
949 return PTR_ERR(ppgtt
->scratch_pd
);
951 gen8_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
952 gen8_initialize_pd(&ppgtt
->base
, ppgtt
->scratch_pd
);
954 ppgtt
->base
.start
= 0;
955 ppgtt
->base
.total
= 1ULL << 32;
956 if (IS_ENABLED(CONFIG_X86_32
))
957 /* While we have a proliferation of size_t variables
958 * we cannot represent the full ppgtt size on 32bit,
959 * so limit it to the same size as the GGTT (currently
962 ppgtt
->base
.total
= to_i915(ppgtt
->base
.dev
)->gtt
.base
.total
;
963 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
964 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
965 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
966 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
967 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
968 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
970 ppgtt
->switch_mm
= gen8_mm_switch
;
975 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
977 struct i915_address_space
*vm
= &ppgtt
->base
;
978 struct i915_page_table
*unused
;
979 gen6_pte_t scratch_pte
;
981 uint32_t pte
, pde
, temp
;
982 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
984 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
), I915_CACHE_LLC
, true, 0);
986 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
988 gen6_pte_t
*pt_vaddr
;
989 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
990 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
991 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
993 if (pd_entry
!= expected
)
994 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
998 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1000 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1002 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1004 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1008 for (i
= 0; i
< 4; i
++)
1009 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1014 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1015 for (i
= 0; i
< 4; i
++) {
1016 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1017 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1019 seq_puts(m
, " SCRATCH ");
1023 kunmap_px(ppgtt
, pt_vaddr
);
1027 /* Write pde (index) from the page directory @pd to the page table @pt */
1028 static void gen6_write_pde(struct i915_page_directory
*pd
,
1029 const int pde
, struct i915_page_table
*pt
)
1031 /* Caller needs to make sure the write completes if necessary */
1032 struct i915_hw_ppgtt
*ppgtt
=
1033 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1036 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1037 pd_entry
|= GEN6_PDE_VALID
;
1039 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1042 /* Write all the page tables found in the ppgtt structure to incrementing page
1044 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1045 struct i915_page_directory
*pd
,
1046 uint32_t start
, uint32_t length
)
1048 struct i915_page_table
*pt
;
1051 gen6_for_each_pde(pt
, pd
, start
, length
, temp
, pde
)
1052 gen6_write_pde(pd
, pde
, pt
);
1054 /* Make sure write is complete before other code can use this page
1055 * table. Also require for WC mapped PTEs */
1056 readl(dev_priv
->gtt
.gsm
);
1059 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1061 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1063 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1066 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1067 struct drm_i915_gem_request
*req
)
1069 struct intel_engine_cs
*ring
= req
->ring
;
1072 /* NB: TLBs must be flushed and invalidated before a switch */
1073 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1077 ret
= intel_ring_begin(req
, 6);
1081 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1082 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1083 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1084 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1085 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1086 intel_ring_emit(ring
, MI_NOOP
);
1087 intel_ring_advance(ring
);
1092 static int vgpu_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1093 struct drm_i915_gem_request
*req
)
1095 struct intel_engine_cs
*ring
= req
->ring
;
1096 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
1098 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1099 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1103 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1104 struct drm_i915_gem_request
*req
)
1106 struct intel_engine_cs
*ring
= req
->ring
;
1109 /* NB: TLBs must be flushed and invalidated before a switch */
1110 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1114 ret
= intel_ring_begin(req
, 6);
1118 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1119 intel_ring_emit(ring
, RING_PP_DIR_DCLV(ring
));
1120 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1121 intel_ring_emit(ring
, RING_PP_DIR_BASE(ring
));
1122 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1123 intel_ring_emit(ring
, MI_NOOP
);
1124 intel_ring_advance(ring
);
1126 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1127 if (ring
->id
!= RCS
) {
1128 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
1136 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1137 struct drm_i915_gem_request
*req
)
1139 struct intel_engine_cs
*ring
= req
->ring
;
1140 struct drm_device
*dev
= ppgtt
->base
.dev
;
1141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1144 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
1145 I915_WRITE(RING_PP_DIR_BASE(ring
), get_pd_offset(ppgtt
));
1147 POSTING_READ(RING_PP_DIR_DCLV(ring
));
1152 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1155 struct intel_engine_cs
*ring
;
1158 for_each_ring(ring
, dev_priv
, j
) {
1159 I915_WRITE(RING_MODE_GEN7(ring
),
1160 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1164 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1167 struct intel_engine_cs
*ring
;
1168 uint32_t ecochk
, ecobits
;
1171 ecobits
= I915_READ(GAC_ECO_BITS
);
1172 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1174 ecochk
= I915_READ(GAM_ECOCHK
);
1175 if (IS_HASWELL(dev
)) {
1176 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1178 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1179 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1181 I915_WRITE(GAM_ECOCHK
, ecochk
);
1183 for_each_ring(ring
, dev_priv
, i
) {
1184 /* GFX_MODE is per-ring on gen7+ */
1185 I915_WRITE(RING_MODE_GEN7(ring
),
1186 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1190 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1193 uint32_t ecochk
, gab_ctl
, ecobits
;
1195 ecobits
= I915_READ(GAC_ECO_BITS
);
1196 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1197 ECOBITS_PPGTT_CACHE64B
);
1199 gab_ctl
= I915_READ(GAB_CTL
);
1200 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1202 ecochk
= I915_READ(GAM_ECOCHK
);
1203 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1205 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1208 /* PPGTT support for Sandybdrige/Gen6 and later */
1209 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1214 struct i915_hw_ppgtt
*ppgtt
=
1215 container_of(vm
, struct i915_hw_ppgtt
, base
);
1216 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1217 unsigned first_entry
= start
>> PAGE_SHIFT
;
1218 unsigned num_entries
= length
>> PAGE_SHIFT
;
1219 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1220 unsigned first_pte
= first_entry
% GEN6_PTES
;
1221 unsigned last_pte
, i
;
1223 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1224 I915_CACHE_LLC
, true, 0);
1226 while (num_entries
) {
1227 last_pte
= first_pte
+ num_entries
;
1228 if (last_pte
> GEN6_PTES
)
1229 last_pte
= GEN6_PTES
;
1231 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1233 for (i
= first_pte
; i
< last_pte
; i
++)
1234 pt_vaddr
[i
] = scratch_pte
;
1236 kunmap_px(ppgtt
, pt_vaddr
);
1238 num_entries
-= last_pte
- first_pte
;
1244 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1245 struct sg_table
*pages
,
1247 enum i915_cache_level cache_level
, u32 flags
)
1249 struct i915_hw_ppgtt
*ppgtt
=
1250 container_of(vm
, struct i915_hw_ppgtt
, base
);
1251 gen6_pte_t
*pt_vaddr
;
1252 unsigned first_entry
= start
>> PAGE_SHIFT
;
1253 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1254 unsigned act_pte
= first_entry
% GEN6_PTES
;
1255 struct sg_page_iter sg_iter
;
1258 for_each_sg_page(pages
->sgl
, &sg_iter
, pages
->nents
, 0) {
1259 if (pt_vaddr
== NULL
)
1260 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1263 vm
->pte_encode(sg_page_iter_dma_address(&sg_iter
),
1264 cache_level
, true, flags
);
1266 if (++act_pte
== GEN6_PTES
) {
1267 kunmap_px(ppgtt
, pt_vaddr
);
1274 kunmap_px(ppgtt
, pt_vaddr
);
1277 static void gen6_initialize_pt(struct i915_address_space
*vm
,
1278 struct i915_page_table
*pt
)
1280 gen6_pte_t scratch_pte
;
1282 WARN_ON(px_dma(vm
->scratch_page
) == 0);
1284 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1285 I915_CACHE_LLC
, true, 0);
1287 fill32_px(vm
->dev
, pt
, scratch_pte
);
1290 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1291 uint64_t start_in
, uint64_t length_in
)
1293 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1294 struct drm_device
*dev
= vm
->dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 struct i915_hw_ppgtt
*ppgtt
=
1297 container_of(vm
, struct i915_hw_ppgtt
, base
);
1298 struct i915_page_table
*pt
;
1299 uint32_t start
, length
, start_save
, length_save
;
1303 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1306 start
= start_save
= start_in
;
1307 length
= length_save
= length_in
;
1309 bitmap_zero(new_page_tables
, I915_PDES
);
1311 /* The allocation is done in two stages so that we can bail out with
1312 * minimal amount of pain. The first stage finds new page tables that
1313 * need allocation. The second stage marks use ptes within the page
1316 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1317 if (pt
!= ppgtt
->scratch_pt
) {
1318 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1322 /* We've already allocated a page table */
1323 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1331 gen6_initialize_pt(vm
, pt
);
1333 ppgtt
->pd
.page_table
[pde
] = pt
;
1334 set_bit(pde
, new_page_tables
);
1335 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1339 length
= length_save
;
1341 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, temp
, pde
) {
1342 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1344 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1345 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1346 gen6_pte_count(start
, length
));
1348 if (test_and_clear_bit(pde
, new_page_tables
))
1349 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1351 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1352 gen6_pte_index(start
),
1353 gen6_pte_count(start
, length
),
1355 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1359 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1361 /* Make sure write is complete before other code can use this page
1362 * table. Also require for WC mapped PTEs */
1363 readl(dev_priv
->gtt
.gsm
);
1365 mark_tlbs_dirty(ppgtt
);
1369 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1370 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1372 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1373 free_pt(vm
->dev
, pt
);
1376 mark_tlbs_dirty(ppgtt
);
1380 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1382 struct i915_hw_ppgtt
*ppgtt
=
1383 container_of(vm
, struct i915_hw_ppgtt
, base
);
1384 struct i915_page_table
*pt
;
1388 drm_mm_remove_node(&ppgtt
->node
);
1390 gen6_for_all_pdes(pt
, ppgtt
, pde
) {
1391 if (pt
!= ppgtt
->scratch_pt
)
1392 free_pt(ppgtt
->base
.dev
, pt
);
1395 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
1398 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1400 struct drm_device
*dev
= ppgtt
->base
.dev
;
1401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1402 bool retried
= false;
1405 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1406 * allocator works in address space sizes, so it's multiplied by page
1407 * size. We allocate at the top of the GTT to avoid fragmentation.
1409 BUG_ON(!drm_mm_initialized(&dev_priv
->gtt
.base
.mm
));
1410 ppgtt
->scratch_pt
= alloc_pt(ppgtt
->base
.dev
);
1411 if (IS_ERR(ppgtt
->scratch_pt
))
1412 return PTR_ERR(ppgtt
->scratch_pt
);
1414 gen6_initialize_pt(&ppgtt
->base
, ppgtt
->scratch_pt
);
1417 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->gtt
.base
.mm
,
1418 &ppgtt
->node
, GEN6_PD_SIZE
,
1420 0, dev_priv
->gtt
.base
.total
,
1422 if (ret
== -ENOSPC
&& !retried
) {
1423 ret
= i915_gem_evict_something(dev
, &dev_priv
->gtt
.base
,
1424 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1426 0, dev_priv
->gtt
.base
.total
,
1439 if (ppgtt
->node
.start
< dev_priv
->gtt
.mappable_end
)
1440 DRM_DEBUG("Forced to use aperture for PDEs\n");
1445 free_pt(ppgtt
->base
.dev
, ppgtt
->scratch_pt
);
1449 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1451 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1454 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1455 uint64_t start
, uint64_t length
)
1457 struct i915_page_table
*unused
;
1460 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, temp
, pde
)
1461 ppgtt
->pd
.page_table
[pde
] = ppgtt
->scratch_pt
;
1464 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1466 struct drm_device
*dev
= ppgtt
->base
.dev
;
1467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 ppgtt
->base
.pte_encode
= dev_priv
->gtt
.base
.pte_encode
;
1472 ppgtt
->switch_mm
= gen6_mm_switch
;
1473 } else if (IS_HASWELL(dev
)) {
1474 ppgtt
->switch_mm
= hsw_mm_switch
;
1475 } else if (IS_GEN7(dev
)) {
1476 ppgtt
->switch_mm
= gen7_mm_switch
;
1480 if (intel_vgpu_active(dev
))
1481 ppgtt
->switch_mm
= vgpu_mm_switch
;
1483 ret
= gen6_ppgtt_alloc(ppgtt
);
1487 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
1488 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1489 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1490 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1491 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1492 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1493 ppgtt
->base
.start
= 0;
1494 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1495 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1497 ppgtt
->pd
.base
.ggtt_offset
=
1498 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1500 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+
1501 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1503 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1505 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
1507 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1508 ppgtt
->node
.size
>> 20,
1509 ppgtt
->node
.start
/ PAGE_SIZE
);
1511 DRM_DEBUG("Adding PPGTT at offset %x\n",
1512 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1517 static int __hw_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1521 ppgtt
->base
.dev
= dev
;
1522 ppgtt
->base
.scratch_page
= dev_priv
->gtt
.base
.scratch_page
;
1524 if (INTEL_INFO(dev
)->gen
< 8)
1525 return gen6_ppgtt_init(ppgtt
);
1527 return gen8_ppgtt_init(ppgtt
);
1530 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
)
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1535 ret
= __hw_ppgtt_init(dev
, ppgtt
);
1537 kref_init(&ppgtt
->ref
);
1538 drm_mm_init(&ppgtt
->base
.mm
, ppgtt
->base
.start
,
1540 i915_init_vm(dev_priv
, &ppgtt
->base
);
1546 int i915_ppgtt_init_hw(struct drm_device
*dev
)
1548 /* In the case of execlists, PPGTT is enabled by the context descriptor
1549 * and the PDPs are contained within the context itself. We don't
1550 * need to do anything here. */
1551 if (i915
.enable_execlists
)
1554 if (!USES_PPGTT(dev
))
1558 gen6_ppgtt_enable(dev
);
1559 else if (IS_GEN7(dev
))
1560 gen7_ppgtt_enable(dev
);
1561 else if (INTEL_INFO(dev
)->gen
>= 8)
1562 gen8_ppgtt_enable(dev
);
1564 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1569 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
)
1571 struct drm_i915_private
*dev_priv
= req
->ring
->dev
->dev_private
;
1572 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1574 if (i915
.enable_execlists
)
1580 return ppgtt
->switch_mm(ppgtt
, req
);
1583 struct i915_hw_ppgtt
*
1584 i915_ppgtt_create(struct drm_device
*dev
, struct drm_i915_file_private
*fpriv
)
1586 struct i915_hw_ppgtt
*ppgtt
;
1589 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1591 return ERR_PTR(-ENOMEM
);
1593 ret
= i915_ppgtt_init(dev
, ppgtt
);
1596 return ERR_PTR(ret
);
1599 ppgtt
->file_priv
= fpriv
;
1601 trace_i915_ppgtt_create(&ppgtt
->base
);
1606 void i915_ppgtt_release(struct kref
*kref
)
1608 struct i915_hw_ppgtt
*ppgtt
=
1609 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1611 trace_i915_ppgtt_release(&ppgtt
->base
);
1613 /* vmas should already be unbound */
1614 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1615 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1617 list_del(&ppgtt
->base
.global_link
);
1618 drm_mm_takedown(&ppgtt
->base
.mm
);
1620 ppgtt
->base
.cleanup(&ppgtt
->base
);
1624 extern int intel_iommu_gfx_mapped
;
1625 /* Certain Gen5 chipsets require require idling the GPU before
1626 * unmapping anything from the GTT when VT-d is enabled.
1628 static bool needs_idle_maps(struct drm_device
*dev
)
1630 #ifdef CONFIG_INTEL_IOMMU
1631 /* Query intel_iommu to see if we need the workaround. Presumably that
1634 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
1640 static bool do_idling(struct drm_i915_private
*dev_priv
)
1642 bool ret
= dev_priv
->mm
.interruptible
;
1644 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
1645 dev_priv
->mm
.interruptible
= false;
1646 if (i915_gpu_idle(dev_priv
->dev
)) {
1647 DRM_ERROR("Couldn't idle GPU\n");
1648 /* Wait a bit, in hopes it avoids the hang */
1656 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
1658 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
1659 dev_priv
->mm
.interruptible
= interruptible
;
1662 void i915_check_and_clear_faults(struct drm_device
*dev
)
1664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 struct intel_engine_cs
*ring
;
1668 if (INTEL_INFO(dev
)->gen
< 6)
1671 for_each_ring(ring
, dev_priv
, i
) {
1673 fault_reg
= I915_READ(RING_FAULT_REG(ring
));
1674 if (fault_reg
& RING_FAULT_VALID
) {
1675 DRM_DEBUG_DRIVER("Unexpected fault\n"
1677 "\tAddress space: %s\n"
1680 fault_reg
& PAGE_MASK
,
1681 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
1682 RING_FAULT_SRCID(fault_reg
),
1683 RING_FAULT_FAULT_TYPE(fault_reg
));
1684 I915_WRITE(RING_FAULT_REG(ring
),
1685 fault_reg
& ~RING_FAULT_VALID
);
1688 POSTING_READ(RING_FAULT_REG(&dev_priv
->ring
[RCS
]));
1691 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
1693 if (INTEL_INFO(dev_priv
->dev
)->gen
< 6) {
1694 intel_gtt_chipset_flush();
1696 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1697 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1701 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
1703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1705 /* Don't bother messing with faults pre GEN6 as we have little
1706 * documentation supporting that it's a good idea.
1708 if (INTEL_INFO(dev
)->gen
< 6)
1711 i915_check_and_clear_faults(dev
);
1713 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
1714 dev_priv
->gtt
.base
.start
,
1715 dev_priv
->gtt
.base
.total
,
1718 i915_ggtt_flush(dev_priv
);
1721 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
1723 if (obj
->has_dma_mapping
)
1726 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
1727 obj
->pages
->sgl
, obj
->pages
->nents
,
1728 PCI_DMA_BIDIRECTIONAL
))
1734 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
1739 iowrite32((u32
)pte
, addr
);
1740 iowrite32(pte
>> 32, addr
+ 4);
1744 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
1745 struct sg_table
*st
,
1747 enum i915_cache_level level
, u32 unused
)
1749 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1750 unsigned first_entry
= start
>> PAGE_SHIFT
;
1751 gen8_pte_t __iomem
*gtt_entries
=
1752 (gen8_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1754 struct sg_page_iter sg_iter
;
1755 dma_addr_t addr
= 0; /* shut up gcc */
1757 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1758 addr
= sg_dma_address(sg_iter
.sg
) +
1759 (sg_iter
.sg_pgoffset
<< PAGE_SHIFT
);
1760 gen8_set_pte(>t_entries
[i
],
1761 gen8_pte_encode(addr
, level
, true));
1766 * XXX: This serves as a posting read to make sure that the PTE has
1767 * actually been updated. There is some concern that even though
1768 * registers and PTEs are within the same BAR that they are potentially
1769 * of NUMA access patterns. Therefore, even with the way we assume
1770 * hardware should work, we must keep this posting read for paranoia.
1773 WARN_ON(readq(>t_entries
[i
-1])
1774 != gen8_pte_encode(addr
, level
, true));
1776 /* This next bit makes the above posting read even more important. We
1777 * want to flush the TLBs only after we're certain all the PTE updates
1780 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1781 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1785 * Binds an object into the global gtt with the specified cache level. The object
1786 * will be accessible to the GPU via commands whose operands reference offsets
1787 * within the global GTT as well as accessible by the GPU through the GMADR
1788 * mapped BAR (dev_priv->mm.gtt->gtt).
1790 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
1791 struct sg_table
*st
,
1793 enum i915_cache_level level
, u32 flags
)
1795 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1796 unsigned first_entry
= start
>> PAGE_SHIFT
;
1797 gen6_pte_t __iomem
*gtt_entries
=
1798 (gen6_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
1800 struct sg_page_iter sg_iter
;
1801 dma_addr_t addr
= 0;
1803 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0) {
1804 addr
= sg_page_iter_dma_address(&sg_iter
);
1805 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), >t_entries
[i
]);
1809 /* XXX: This serves as a posting read to make sure that the PTE has
1810 * actually been updated. There is some concern that even though
1811 * registers and PTEs are within the same BAR that they are potentially
1812 * of NUMA access patterns. Therefore, even with the way we assume
1813 * hardware should work, we must keep this posting read for paranoia.
1816 unsigned long gtt
= readl(>t_entries
[i
-1]);
1817 WARN_ON(gtt
!= vm
->pte_encode(addr
, level
, true, flags
));
1820 /* This next bit makes the above posting read even more important. We
1821 * want to flush the TLBs only after we're certain all the PTE updates
1824 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
1825 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
1828 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
1833 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1834 unsigned first_entry
= start
>> PAGE_SHIFT
;
1835 unsigned num_entries
= length
>> PAGE_SHIFT
;
1836 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
1837 (gen8_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1838 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1841 if (WARN(num_entries
> max_entries
,
1842 "First entry = %d; Num entries = %d (max=%d)\n",
1843 first_entry
, num_entries
, max_entries
))
1844 num_entries
= max_entries
;
1846 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1849 for (i
= 0; i
< num_entries
; i
++)
1850 gen8_set_pte(>t_base
[i
], scratch_pte
);
1854 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
1859 struct drm_i915_private
*dev_priv
= vm
->dev
->dev_private
;
1860 unsigned first_entry
= start
>> PAGE_SHIFT
;
1861 unsigned num_entries
= length
>> PAGE_SHIFT
;
1862 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
1863 (gen6_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
1864 const int max_entries
= gtt_total_entries(dev_priv
->gtt
) - first_entry
;
1867 if (WARN(num_entries
> max_entries
,
1868 "First entry = %d; Num entries = %d (max=%d)\n",
1869 first_entry
, num_entries
, max_entries
))
1870 num_entries
= max_entries
;
1872 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1873 I915_CACHE_LLC
, use_scratch
, 0);
1875 for (i
= 0; i
< num_entries
; i
++)
1876 iowrite32(scratch_pte
, >t_base
[i
]);
1880 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
1881 struct sg_table
*pages
,
1883 enum i915_cache_level cache_level
, u32 unused
)
1885 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
1886 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
1888 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
1892 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
1897 unsigned first_entry
= start
>> PAGE_SHIFT
;
1898 unsigned num_entries
= length
>> PAGE_SHIFT
;
1899 intel_gtt_clear_range(first_entry
, num_entries
);
1902 static int ggtt_bind_vma(struct i915_vma
*vma
,
1903 enum i915_cache_level cache_level
,
1906 struct drm_device
*dev
= vma
->vm
->dev
;
1907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1908 struct drm_i915_gem_object
*obj
= vma
->obj
;
1909 struct sg_table
*pages
= obj
->pages
;
1913 ret
= i915_get_ggtt_vma_pages(vma
);
1916 pages
= vma
->ggtt_view
.pages
;
1918 /* Currently applicable only to VLV */
1920 pte_flags
|= PTE_READ_ONLY
;
1923 if (!dev_priv
->mm
.aliasing_ppgtt
|| flags
& GLOBAL_BIND
) {
1924 vma
->vm
->insert_entries(vma
->vm
, pages
,
1926 cache_level
, pte_flags
);
1929 if (dev_priv
->mm
.aliasing_ppgtt
&& flags
& LOCAL_BIND
) {
1930 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1931 appgtt
->base
.insert_entries(&appgtt
->base
, pages
,
1933 cache_level
, pte_flags
);
1939 static void ggtt_unbind_vma(struct i915_vma
*vma
)
1941 struct drm_device
*dev
= vma
->vm
->dev
;
1942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 struct drm_i915_gem_object
*obj
= vma
->obj
;
1944 const uint64_t size
= min_t(uint64_t,
1948 if (vma
->bound
& GLOBAL_BIND
) {
1949 vma
->vm
->clear_range(vma
->vm
,
1955 if (dev_priv
->mm
.aliasing_ppgtt
&& vma
->bound
& LOCAL_BIND
) {
1956 struct i915_hw_ppgtt
*appgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1958 appgtt
->base
.clear_range(&appgtt
->base
,
1965 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
1967 struct drm_device
*dev
= obj
->base
.dev
;
1968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 interruptible
= do_idling(dev_priv
);
1973 if (!obj
->has_dma_mapping
)
1974 dma_unmap_sg(&dev
->pdev
->dev
,
1975 obj
->pages
->sgl
, obj
->pages
->nents
,
1976 PCI_DMA_BIDIRECTIONAL
);
1978 undo_idling(dev_priv
, interruptible
);
1981 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
1982 unsigned long color
,
1986 if (node
->color
!= color
)
1989 if (!list_empty(&node
->node_list
)) {
1990 node
= list_entry(node
->node_list
.next
,
1993 if (node
->allocated
&& node
->color
!= color
)
1998 static int i915_gem_setup_global_gtt(struct drm_device
*dev
,
1999 unsigned long start
,
2000 unsigned long mappable_end
,
2003 /* Let GEM Manage all of the aperture.
2005 * However, leave one page at the end still bound to the scratch page.
2006 * There are a number of places where the hardware apparently prefetches
2007 * past the end of the object, and we've seen multiple hangs with the
2008 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2009 * aperture. One page should be enough to keep any prefetching inside
2012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2013 struct i915_address_space
*ggtt_vm
= &dev_priv
->gtt
.base
;
2014 struct drm_mm_node
*entry
;
2015 struct drm_i915_gem_object
*obj
;
2016 unsigned long hole_start
, hole_end
;
2019 BUG_ON(mappable_end
> end
);
2021 /* Subtract the guard page ... */
2022 drm_mm_init(&ggtt_vm
->mm
, start
, end
- start
- PAGE_SIZE
);
2024 dev_priv
->gtt
.base
.start
= start
;
2025 dev_priv
->gtt
.base
.total
= end
- start
;
2027 if (intel_vgpu_active(dev
)) {
2028 ret
= intel_vgt_balloon(dev
);
2034 dev_priv
->gtt
.base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2036 /* Mark any preallocated objects as occupied */
2037 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2038 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
, ggtt_vm
);
2040 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2041 i915_gem_obj_ggtt_offset(obj
), obj
->base
.size
);
2043 WARN_ON(i915_gem_obj_ggtt_bound(obj
));
2044 ret
= drm_mm_reserve_node(&ggtt_vm
->mm
, &vma
->node
);
2046 DRM_DEBUG_KMS("Reservation failed: %i\n", ret
);
2049 vma
->bound
|= GLOBAL_BIND
;
2052 /* Clear any non-preallocated blocks */
2053 drm_mm_for_each_hole(entry
, &ggtt_vm
->mm
, hole_start
, hole_end
) {
2054 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2055 hole_start
, hole_end
);
2056 ggtt_vm
->clear_range(ggtt_vm
, hole_start
,
2057 hole_end
- hole_start
, true);
2060 /* And finally clear the reserved guard page */
2061 ggtt_vm
->clear_range(ggtt_vm
, end
- PAGE_SIZE
, PAGE_SIZE
, true);
2063 if (USES_PPGTT(dev
) && !USES_FULL_PPGTT(dev
)) {
2064 struct i915_hw_ppgtt
*ppgtt
;
2066 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2070 ret
= __hw_ppgtt_init(dev
, ppgtt
);
2072 ppgtt
->base
.cleanup(&ppgtt
->base
);
2077 if (ppgtt
->base
.allocate_va_range
)
2078 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2081 ppgtt
->base
.cleanup(&ppgtt
->base
);
2086 ppgtt
->base
.clear_range(&ppgtt
->base
,
2091 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2097 void i915_gem_init_global_gtt(struct drm_device
*dev
)
2099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2100 u64 gtt_size
, mappable_size
;
2102 gtt_size
= dev_priv
->gtt
.base
.total
;
2103 mappable_size
= dev_priv
->gtt
.mappable_end
;
2105 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
2108 void i915_global_gtt_cleanup(struct drm_device
*dev
)
2110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2111 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
2113 if (dev_priv
->mm
.aliasing_ppgtt
) {
2114 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2116 ppgtt
->base
.cleanup(&ppgtt
->base
);
2119 if (drm_mm_initialized(&vm
->mm
)) {
2120 if (intel_vgpu_active(dev
))
2121 intel_vgt_deballoon();
2123 drm_mm_takedown(&vm
->mm
);
2124 list_del(&vm
->global_link
);
2130 static int alloc_scratch_page(struct i915_address_space
*vm
)
2132 struct i915_page_scratch
*sp
;
2135 WARN_ON(vm
->scratch_page
);
2137 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
2141 ret
= __setup_page_dma(vm
->dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
2147 set_pages_uc(px_page(sp
), 1);
2149 vm
->scratch_page
= sp
;
2154 static void free_scratch_page(struct i915_address_space
*vm
)
2156 struct i915_page_scratch
*sp
= vm
->scratch_page
;
2158 set_pages_wb(px_page(sp
), 1);
2160 cleanup_px(vm
->dev
, sp
);
2163 vm
->scratch_page
= NULL
;
2166 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2168 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2169 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2170 return snb_gmch_ctl
<< 20;
2173 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2175 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2176 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2178 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2180 #ifdef CONFIG_X86_32
2181 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2182 if (bdw_gmch_ctl
> 4)
2186 return bdw_gmch_ctl
<< 20;
2189 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2191 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2192 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2195 return 1 << (20 + gmch_ctrl
);
2200 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2202 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2203 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2204 return snb_gmch_ctl
<< 25; /* 32 MB units */
2207 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2209 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2210 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2211 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2214 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2216 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2217 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2220 * 0x0 to 0x10: 32MB increments starting at 0MB
2221 * 0x11 to 0x16: 4MB increments starting at 8MB
2222 * 0x17 to 0x1d: 4MB increments start at 36MB
2224 if (gmch_ctrl
< 0x11)
2225 return gmch_ctrl
<< 25;
2226 else if (gmch_ctrl
< 0x17)
2227 return (gmch_ctrl
- 0x11 + 2) << 22;
2229 return (gmch_ctrl
- 0x17 + 9) << 22;
2232 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2234 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2235 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2237 if (gen9_gmch_ctl
< 0xf0)
2238 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2240 /* 4MB increments starting at 0xf0 for 4MB */
2241 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2244 static int ggtt_probe_common(struct drm_device
*dev
,
2247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 phys_addr_t gtt_phys_addr
;
2251 /* For Modern GENs the PTEs and register space are split in the BAR */
2252 gtt_phys_addr
= pci_resource_start(dev
->pdev
, 0) +
2253 (pci_resource_len(dev
->pdev
, 0) / 2);
2256 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2257 * dropped. For WC mappings in general we have 64 byte burst writes
2258 * when the WC buffer is flushed, so we can't use it, but have to
2259 * resort to an uncached mapping. The WC issue is easily caught by the
2260 * readback check when writing GTT PTE entries.
2262 if (IS_BROXTON(dev
))
2263 dev_priv
->gtt
.gsm
= ioremap_nocache(gtt_phys_addr
, gtt_size
);
2265 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_phys_addr
, gtt_size
);
2266 if (!dev_priv
->gtt
.gsm
) {
2267 DRM_ERROR("Failed to map the gtt page table\n");
2271 ret
= alloc_scratch_page(&dev_priv
->gtt
.base
);
2273 DRM_ERROR("Scratch setup failed\n");
2274 /* iounmap will also get called at remove, but meh */
2275 iounmap(dev_priv
->gtt
.gsm
);
2281 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2282 * bits. When using advanced contexts each context stores its own PAT, but
2283 * writing this data shouldn't be harmful even in those cases. */
2284 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2288 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2289 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2290 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2291 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2292 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2293 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2294 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2295 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2297 if (!USES_PPGTT(dev_priv
->dev
))
2298 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2299 * so RTL will always use the value corresponding to
2301 * So let's disable cache for GGTT to avoid screen corruptions.
2302 * MOCS still can be used though.
2303 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2304 * before this patch, i.e. the same uncached + snooping access
2305 * like on gen6/7 seems to be in effect.
2306 * - So this just fixes blitter/render access. Again it looks
2307 * like it's not just uncached access, but uncached + snooping.
2308 * So we can still hold onto all our assumptions wrt cpu
2309 * clflushing on LLC machines.
2311 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2313 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2314 * write would work. */
2315 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2316 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2319 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2324 * Map WB on BDW to snooped on CHV.
2326 * Only the snoop bit has meaning for CHV, the rest is
2329 * The hardware will never snoop for certain types of accesses:
2330 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2331 * - PPGTT page tables
2332 * - some other special cycles
2334 * As with BDW, we also need to consider the following for GT accesses:
2335 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2336 * so RTL will always use the value corresponding to
2338 * Which means we must set the snoop bit in PAT entry 0
2339 * in order to keep the global status page working.
2341 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2345 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2346 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2347 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2348 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2350 I915_WRITE(GEN8_PRIVATE_PAT
, pat
);
2351 I915_WRITE(GEN8_PRIVATE_PAT
+ 4, pat
>> 32);
2354 static int gen8_gmch_probe(struct drm_device
*dev
,
2357 phys_addr_t
*mappable_base
,
2360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2365 /* TODO: We're not aware of mappable constraints on gen8 yet */
2366 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2367 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2369 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(39)))
2370 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(39));
2372 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2374 if (INTEL_INFO(dev
)->gen
>= 9) {
2375 *stolen
= gen9_get_stolen_size(snb_gmch_ctl
);
2376 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2377 } else if (IS_CHERRYVIEW(dev
)) {
2378 *stolen
= chv_get_stolen_size(snb_gmch_ctl
);
2379 gtt_size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2381 *stolen
= gen8_get_stolen_size(snb_gmch_ctl
);
2382 gtt_size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2385 *gtt_total
= (gtt_size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2387 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2388 chv_setup_private_ppat(dev_priv
);
2390 bdw_setup_private_ppat(dev_priv
);
2392 ret
= ggtt_probe_common(dev
, gtt_size
);
2394 dev_priv
->gtt
.base
.clear_range
= gen8_ggtt_clear_range
;
2395 dev_priv
->gtt
.base
.insert_entries
= gen8_ggtt_insert_entries
;
2396 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2397 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2402 static int gen6_gmch_probe(struct drm_device
*dev
,
2405 phys_addr_t
*mappable_base
,
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2409 unsigned int gtt_size
;
2413 *mappable_base
= pci_resource_start(dev
->pdev
, 2);
2414 *mappable_end
= pci_resource_len(dev
->pdev
, 2);
2416 /* 64/512MB is the current min/max we actually know of, but this is just
2417 * a coarse sanity check.
2419 if ((*mappable_end
< (64<<20) || (*mappable_end
> (512<<20)))) {
2420 DRM_ERROR("Unknown GMADR size (%llx)\n",
2421 dev_priv
->gtt
.mappable_end
);
2425 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
2426 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
2427 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2429 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
2431 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2432 *gtt_total
= (gtt_size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2434 ret
= ggtt_probe_common(dev
, gtt_size
);
2436 dev_priv
->gtt
.base
.clear_range
= gen6_ggtt_clear_range
;
2437 dev_priv
->gtt
.base
.insert_entries
= gen6_ggtt_insert_entries
;
2438 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2439 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2444 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2447 struct i915_gtt
*gtt
= container_of(vm
, struct i915_gtt
, base
);
2450 free_scratch_page(vm
);
2453 static int i915_gmch_probe(struct drm_device
*dev
,
2456 phys_addr_t
*mappable_base
,
2459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
2464 DRM_ERROR("failed to set up gmch\n");
2468 intel_gtt_get(gtt_total
, stolen
, mappable_base
, mappable_end
);
2470 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
2471 dev_priv
->gtt
.base
.insert_entries
= i915_ggtt_insert_entries
;
2472 dev_priv
->gtt
.base
.clear_range
= i915_ggtt_clear_range
;
2473 dev_priv
->gtt
.base
.bind_vma
= ggtt_bind_vma
;
2474 dev_priv
->gtt
.base
.unbind_vma
= ggtt_unbind_vma
;
2476 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
2477 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2482 static void i915_gmch_remove(struct i915_address_space
*vm
)
2484 intel_gmch_remove();
2487 int i915_gem_gtt_init(struct drm_device
*dev
)
2489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2490 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
2493 if (INTEL_INFO(dev
)->gen
<= 5) {
2494 gtt
->gtt_probe
= i915_gmch_probe
;
2495 gtt
->base
.cleanup
= i915_gmch_remove
;
2496 } else if (INTEL_INFO(dev
)->gen
< 8) {
2497 gtt
->gtt_probe
= gen6_gmch_probe
;
2498 gtt
->base
.cleanup
= gen6_gmch_remove
;
2499 if (IS_HASWELL(dev
) && dev_priv
->ellc_size
)
2500 gtt
->base
.pte_encode
= iris_pte_encode
;
2501 else if (IS_HASWELL(dev
))
2502 gtt
->base
.pte_encode
= hsw_pte_encode
;
2503 else if (IS_VALLEYVIEW(dev
))
2504 gtt
->base
.pte_encode
= byt_pte_encode
;
2505 else if (INTEL_INFO(dev
)->gen
>= 7)
2506 gtt
->base
.pte_encode
= ivb_pte_encode
;
2508 gtt
->base
.pte_encode
= snb_pte_encode
;
2510 dev_priv
->gtt
.gtt_probe
= gen8_gmch_probe
;
2511 dev_priv
->gtt
.base
.cleanup
= gen6_gmch_remove
;
2514 gtt
->base
.dev
= dev
;
2516 ret
= gtt
->gtt_probe(dev
, >t
->base
.total
, >t
->stolen_size
,
2517 >t
->mappable_base
, >t
->mappable_end
);
2521 /* GMADR is the PCI mmio aperture into the global GTT. */
2522 DRM_INFO("Memory usable by graphics device = %lluM\n",
2523 gtt
->base
.total
>> 20);
2524 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt
->mappable_end
>> 20);
2525 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt
->stolen_size
>> 20);
2526 #ifdef CONFIG_INTEL_IOMMU
2527 if (intel_iommu_gfx_mapped
)
2528 DRM_INFO("VT-d active for gfx access\n");
2531 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2532 * user's requested state against the hardware/driver capabilities. We
2533 * do this now so that we can print out any log messages once rather
2534 * than every time we check intel_enable_ppgtt().
2536 i915
.enable_ppgtt
= sanitize_enable_ppgtt(dev
, i915
.enable_ppgtt
);
2537 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
2542 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
2544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2545 struct drm_i915_gem_object
*obj
;
2546 struct i915_address_space
*vm
;
2548 i915_check_and_clear_faults(dev
);
2550 /* First fill our portion of the GTT with scratch pages */
2551 dev_priv
->gtt
.base
.clear_range(&dev_priv
->gtt
.base
,
2552 dev_priv
->gtt
.base
.start
,
2553 dev_priv
->gtt
.base
.total
,
2556 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
2557 struct i915_vma
*vma
= i915_gem_obj_to_vma(obj
,
2558 &dev_priv
->gtt
.base
);
2562 i915_gem_clflush_object(obj
, obj
->pin_display
);
2563 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
2567 if (INTEL_INFO(dev
)->gen
>= 8) {
2568 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
2569 chv_setup_private_ppat(dev_priv
);
2571 bdw_setup_private_ppat(dev_priv
);
2576 if (USES_PPGTT(dev
)) {
2577 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2578 /* TODO: Perhaps it shouldn't be gen6 specific */
2580 struct i915_hw_ppgtt
*ppgtt
=
2581 container_of(vm
, struct i915_hw_ppgtt
,
2584 if (i915_is_ggtt(vm
))
2585 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2587 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
2588 0, ppgtt
->base
.total
);
2592 i915_ggtt_flush(dev_priv
);
2595 static struct i915_vma
*
2596 __i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
2597 struct i915_address_space
*vm
,
2598 const struct i915_ggtt_view
*ggtt_view
)
2600 struct i915_vma
*vma
;
2602 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
2603 return ERR_PTR(-EINVAL
);
2605 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
2607 return ERR_PTR(-ENOMEM
);
2609 INIT_LIST_HEAD(&vma
->vma_link
);
2610 INIT_LIST_HEAD(&vma
->mm_list
);
2611 INIT_LIST_HEAD(&vma
->exec_list
);
2615 if (i915_is_ggtt(vm
))
2616 vma
->ggtt_view
= *ggtt_view
;
2618 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
2619 if (!i915_is_ggtt(vm
))
2620 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
2626 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2627 struct i915_address_space
*vm
)
2629 struct i915_vma
*vma
;
2631 vma
= i915_gem_obj_to_vma(obj
, vm
);
2633 vma
= __i915_gem_vma_create(obj
, vm
,
2634 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
);
2640 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2641 const struct i915_ggtt_view
*view
)
2643 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
2644 struct i915_vma
*vma
;
2647 return ERR_PTR(-EINVAL
);
2649 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2655 vma
= __i915_gem_vma_create(obj
, ggtt
, view
);
2662 rotate_pages(dma_addr_t
*in
, unsigned int width
, unsigned int height
,
2663 struct sg_table
*st
)
2665 unsigned int column
, row
;
2666 unsigned int src_idx
;
2667 struct scatterlist
*sg
= st
->sgl
;
2671 for (column
= 0; column
< width
; column
++) {
2672 src_idx
= width
* (height
- 1) + column
;
2673 for (row
= 0; row
< height
; row
++) {
2675 /* We don't need the pages, but need to initialize
2676 * the entries so the sg list can be happily traversed.
2677 * The only thing we need are DMA addresses.
2679 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2680 sg_dma_address(sg
) = in
[src_idx
];
2681 sg_dma_len(sg
) = PAGE_SIZE
;
2688 static struct sg_table
*
2689 intel_rotate_fb_obj_pages(struct i915_ggtt_view
*ggtt_view
,
2690 struct drm_i915_gem_object
*obj
)
2692 struct intel_rotation_info
*rot_info
= &ggtt_view
->rotation_info
;
2693 unsigned int size_pages
= rot_info
->size
>> PAGE_SHIFT
;
2694 struct sg_page_iter sg_iter
;
2696 dma_addr_t
*page_addr_list
;
2697 struct sg_table
*st
;
2700 /* Allocate a temporary list of source pages for random access. */
2701 page_addr_list
= drm_malloc_ab(obj
->base
.size
/ PAGE_SIZE
,
2702 sizeof(dma_addr_t
));
2703 if (!page_addr_list
)
2704 return ERR_PTR(ret
);
2706 /* Allocate target SG list. */
2707 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2711 ret
= sg_alloc_table(st
, size_pages
, GFP_KERNEL
);
2715 /* Populate source page list from the object. */
2717 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2718 page_addr_list
[i
] = sg_page_iter_dma_address(&sg_iter
);
2722 /* Rotate the pages. */
2723 rotate_pages(page_addr_list
,
2724 rot_info
->width_pages
, rot_info
->height_pages
,
2728 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2729 obj
->base
.size
, rot_info
->pitch
, rot_info
->height
,
2730 rot_info
->pixel_format
, rot_info
->width_pages
,
2731 rot_info
->height_pages
, size_pages
);
2733 drm_free_large(page_addr_list
);
2740 drm_free_large(page_addr_list
);
2743 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2744 obj
->base
.size
, ret
, rot_info
->pitch
, rot_info
->height
,
2745 rot_info
->pixel_format
, rot_info
->width_pages
,
2746 rot_info
->height_pages
, size_pages
);
2747 return ERR_PTR(ret
);
2750 static struct sg_table
*
2751 intel_partial_pages(const struct i915_ggtt_view
*view
,
2752 struct drm_i915_gem_object
*obj
)
2754 struct sg_table
*st
;
2755 struct scatterlist
*sg
;
2756 struct sg_page_iter obj_sg_iter
;
2759 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2763 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
2769 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
2770 view
->params
.partial
.offset
)
2772 if (st
->nents
>= view
->params
.partial
.size
)
2775 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
2776 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
2777 sg_dma_len(sg
) = PAGE_SIZE
;
2788 return ERR_PTR(ret
);
2792 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
2796 if (vma
->ggtt_view
.pages
)
2799 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
2800 vma
->ggtt_view
.pages
= vma
->obj
->pages
;
2801 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
2802 vma
->ggtt_view
.pages
=
2803 intel_rotate_fb_obj_pages(&vma
->ggtt_view
, vma
->obj
);
2804 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
2805 vma
->ggtt_view
.pages
=
2806 intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
2808 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2809 vma
->ggtt_view
.type
);
2811 if (!vma
->ggtt_view
.pages
) {
2812 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2813 vma
->ggtt_view
.type
);
2815 } else if (IS_ERR(vma
->ggtt_view
.pages
)) {
2816 ret
= PTR_ERR(vma
->ggtt_view
.pages
);
2817 vma
->ggtt_view
.pages
= NULL
;
2818 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2819 vma
->ggtt_view
.type
, ret
);
2826 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2828 * @cache_level: mapping cache level
2829 * @flags: flags like global or local mapping
2831 * DMA addresses are taken from the scatter-gather table of this object (or of
2832 * this VMA in case of non-default GGTT views) and PTE entries set up.
2833 * Note that DMA addresses are also the only part of the SG table we care about.
2835 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2841 if (WARN_ON(flags
== 0))
2845 if (flags
& PIN_GLOBAL
)
2846 bind_flags
|= GLOBAL_BIND
;
2847 if (flags
& PIN_USER
)
2848 bind_flags
|= LOCAL_BIND
;
2850 if (flags
& PIN_UPDATE
)
2851 bind_flags
|= vma
->bound
;
2853 bind_flags
&= ~vma
->bound
;
2855 if (bind_flags
== 0)
2858 if (vma
->bound
== 0 && vma
->vm
->allocate_va_range
) {
2859 trace_i915_va_alloc(vma
->vm
,
2862 VM_TO_TRACE_NAME(vma
->vm
));
2864 /* XXX: i915_vma_pin() will fix this +- hack */
2866 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
2874 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
2878 vma
->bound
|= bind_flags
;
2884 * i915_ggtt_view_size - Get the size of a GGTT view.
2885 * @obj: Object the view is of.
2886 * @view: The view in question.
2888 * @return The size of the GGTT view in bytes.
2891 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
2892 const struct i915_ggtt_view
*view
)
2894 if (view
->type
== I915_GGTT_VIEW_NORMAL
) {
2895 return obj
->base
.size
;
2896 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
2897 return view
->rotation_info
.size
;
2898 } else if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
2899 return view
->params
.partial
.size
<< PAGE_SHIFT
;
2901 WARN_ONCE(1, "GGTT view %u not implemented!\n", view
->type
);
2902 return obj
->base
.size
;