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Merge tag 'drm-intel-next-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/seq_file.h>
26 #include <drm/drmP.h>
27 #include <drm/i915_drm.h>
28 #include "i915_drv.h"
29 #include "i915_trace.h"
30 #include "intel_drv.h"
31
32 #define GEN6_PPGTT_PD_ENTRIES 512
33 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
34 typedef uint64_t gen8_gtt_pte_t;
35 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
36
37 /* PPGTT stuff */
38 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
39 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
40
41 #define GEN6_PDE_VALID (1 << 0)
42 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
43 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
44
45 #define GEN6_PTE_VALID (1 << 0)
46 #define GEN6_PTE_UNCACHED (1 << 1)
47 #define HSW_PTE_UNCACHED (0)
48 #define GEN6_PTE_CACHE_LLC (2 << 1)
49 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
51 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
52
53 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
54 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
55 */
56 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
57 (((bits) & 0x8) << (11 - 3)))
58 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
59 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
60 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
61 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
62 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
63 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
64
65 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
66 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
67 #define GEN8_LEGACY_PDPS 4
68
69 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
70 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
71 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
72 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
73
74 static void ppgtt_bind_vma(struct i915_vma *vma,
75 enum i915_cache_level cache_level,
76 u32 flags);
77 static void ppgtt_unbind_vma(struct i915_vma *vma);
78 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
79
80 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
81 enum i915_cache_level level,
82 bool valid)
83 {
84 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
85 pte |= addr;
86 if (level != I915_CACHE_NONE)
87 pte |= PPAT_CACHED_INDEX;
88 else
89 pte |= PPAT_UNCACHED_INDEX;
90 return pte;
91 }
92
93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 dma_addr_t addr,
95 enum i915_cache_level level)
96 {
97 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 pde |= addr;
99 if (level != I915_CACHE_NONE)
100 pde |= PPAT_CACHED_PDE_INDEX;
101 else
102 pde |= PPAT_UNCACHED_INDEX;
103 return pde;
104 }
105
106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
107 enum i915_cache_level level,
108 bool valid)
109 {
110 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112
113 switch (level) {
114 case I915_CACHE_L3_LLC:
115 case I915_CACHE_LLC:
116 pte |= GEN6_PTE_CACHE_LLC;
117 break;
118 case I915_CACHE_NONE:
119 pte |= GEN6_PTE_UNCACHED;
120 break;
121 default:
122 WARN_ON(1);
123 }
124
125 return pte;
126 }
127
128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
130 bool valid)
131 {
132 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
133 pte |= GEN6_PTE_ADDR_ENCODE(addr);
134
135 switch (level) {
136 case I915_CACHE_L3_LLC:
137 pte |= GEN7_PTE_CACHE_L3_LLC;
138 break;
139 case I915_CACHE_LLC:
140 pte |= GEN6_PTE_CACHE_LLC;
141 break;
142 case I915_CACHE_NONE:
143 pte |= GEN6_PTE_UNCACHED;
144 break;
145 default:
146 WARN_ON(1);
147 }
148
149 return pte;
150 }
151
152 #define BYT_PTE_WRITEABLE (1 << 1)
153 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
154
155 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
156 enum i915_cache_level level,
157 bool valid)
158 {
159 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
160 pte |= GEN6_PTE_ADDR_ENCODE(addr);
161
162 /* Mark the page as writeable. Other platforms don't have a
163 * setting for read-only/writable, so this matches that behavior.
164 */
165 pte |= BYT_PTE_WRITEABLE;
166
167 if (level != I915_CACHE_NONE)
168 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
169
170 return pte;
171 }
172
173 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
176 {
177 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
178 pte |= HSW_PTE_ADDR_ENCODE(addr);
179
180 if (level != I915_CACHE_NONE)
181 pte |= HSW_WB_LLC_AGE3;
182
183 return pte;
184 }
185
186 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= HSW_PTE_ADDR_ENCODE(addr);
192
193 switch (level) {
194 case I915_CACHE_NONE:
195 break;
196 case I915_CACHE_WT:
197 pte |= HSW_WT_ELLC_LLC_AGE3;
198 break;
199 default:
200 pte |= HSW_WB_ELLC_LLC_AGE3;
201 break;
202 }
203
204 return pte;
205 }
206
207 /* Broadwell Page Directory Pointer Descriptors */
208 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
209 uint64_t val, bool synchronous)
210 {
211 struct drm_i915_private *dev_priv = ring->dev->dev_private;
212 int ret;
213
214 BUG_ON(entry >= 4);
215
216 if (synchronous) {
217 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
218 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
219 return 0;
220 }
221
222 ret = intel_ring_begin(ring, 6);
223 if (ret)
224 return ret;
225
226 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
227 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
228 intel_ring_emit(ring, (u32)(val >> 32));
229 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
230 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
231 intel_ring_emit(ring, (u32)(val));
232 intel_ring_advance(ring);
233
234 return 0;
235 }
236
237 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
238 struct intel_ring_buffer *ring,
239 bool synchronous)
240 {
241 int i, ret;
242
243 /* bit of a hack to find the actual last used pd */
244 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
245
246 for (i = used_pd - 1; i >= 0; i--) {
247 dma_addr_t addr = ppgtt->pd_dma_addr[i];
248 ret = gen8_write_pdp(ring, i, addr, synchronous);
249 if (ret)
250 return ret;
251 }
252
253 return 0;
254 }
255
256 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
257 unsigned first_entry,
258 unsigned num_entries,
259 bool use_scratch)
260 {
261 struct i915_hw_ppgtt *ppgtt =
262 container_of(vm, struct i915_hw_ppgtt, base);
263 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
264 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
265 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
266 unsigned last_pte, i;
267
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
270
271 while (num_entries) {
272 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
273
274 last_pte = first_pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
277
278 pt_vaddr = kmap_atomic(page_table);
279
280 for (i = first_pte; i < last_pte; i++)
281 pt_vaddr[i] = scratch_pte;
282
283 kunmap_atomic(pt_vaddr);
284
285 num_entries -= last_pte - first_pte;
286 first_pte = 0;
287 act_pt++;
288 }
289 }
290
291 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
292 struct sg_table *pages,
293 unsigned first_entry,
294 enum i915_cache_level cache_level)
295 {
296 struct i915_hw_ppgtt *ppgtt =
297 container_of(vm, struct i915_hw_ppgtt, base);
298 gen8_gtt_pte_t *pt_vaddr;
299 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
300 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
301 struct sg_page_iter sg_iter;
302
303 pt_vaddr = NULL;
304 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
305 if (pt_vaddr == NULL)
306 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
307
308 pt_vaddr[act_pte] =
309 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
310 cache_level, true);
311 if (++act_pte == GEN8_PTES_PER_PAGE) {
312 kunmap_atomic(pt_vaddr);
313 pt_vaddr = NULL;
314 act_pt++;
315 act_pte = 0;
316 }
317 }
318 if (pt_vaddr)
319 kunmap_atomic(pt_vaddr);
320 }
321
322 static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
323 {
324 int i;
325
326 for (i = 0; i < ppgtt->num_pd_pages ; i++)
327 kfree(ppgtt->gen8_pt_dma_addr[i]);
328
329 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
330 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
331 }
332
333 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
334 {
335 int i, j;
336
337 for (i = 0; i < ppgtt->num_pd_pages; i++) {
338 /* TODO: In the future we'll support sparse mappings, so this
339 * will have to change. */
340 if (!ppgtt->pd_dma_addr[i])
341 continue;
342
343 pci_unmap_page(ppgtt->base.dev->pdev,
344 ppgtt->pd_dma_addr[i],
345 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
346
347 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
348 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
349 if (addr)
350 pci_unmap_page(ppgtt->base.dev->pdev,
351 addr,
352 PAGE_SIZE,
353 PCI_DMA_BIDIRECTIONAL);
354
355 }
356 }
357 }
358
359 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
360 {
361 struct i915_hw_ppgtt *ppgtt =
362 container_of(vm, struct i915_hw_ppgtt, base);
363
364 list_del(&vm->global_link);
365 drm_mm_takedown(&vm->mm);
366
367 gen8_ppgtt_unmap_pages(ppgtt);
368 gen8_ppgtt_free(ppgtt);
369 }
370
371 /**
372 * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
373 * net effect resembling a 2-level page table in normal x86 terms. Each PDP
374 * represents 1GB of memory
375 * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
376 *
377 * TODO: Do something with the size parameter
378 **/
379 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
380 {
381 struct page *pt_pages;
382 int i, j, ret = -ENOMEM;
383 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
384 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
385
386 if (size % (1<<30))
387 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
388
389 /* FIXME: split allocation into smaller pieces. For now we only ever do
390 * this once, but with full PPGTT, the multiple contiguous allocations
391 * will be bad.
392 */
393 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
394 if (!ppgtt->pd_pages)
395 return -ENOMEM;
396
397 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
398 if (!pt_pages) {
399 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
400 return -ENOMEM;
401 }
402
403 ppgtt->gen8_pt_pages = pt_pages;
404 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
405 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
406 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
407 ppgtt->enable = gen8_ppgtt_enable;
408 ppgtt->switch_mm = gen8_mm_switch;
409 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
410 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
411 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
412 ppgtt->base.start = 0;
413 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
414
415 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
416
417 /*
418 * - Create a mapping for the page directories.
419 * - For each page directory:
420 * allocate space for page table mappings.
421 * map each page table
422 */
423 for (i = 0; i < max_pdp; i++) {
424 dma_addr_t temp;
425 temp = pci_map_page(ppgtt->base.dev->pdev,
426 &ppgtt->pd_pages[i], 0,
427 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
428 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
429 goto err_out;
430
431 ppgtt->pd_dma_addr[i] = temp;
432
433 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
434 if (!ppgtt->gen8_pt_dma_addr[i])
435 goto err_out;
436
437 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
438 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
439 temp = pci_map_page(ppgtt->base.dev->pdev,
440 p, 0, PAGE_SIZE,
441 PCI_DMA_BIDIRECTIONAL);
442
443 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
444 goto err_out;
445
446 ppgtt->gen8_pt_dma_addr[i][j] = temp;
447 }
448 }
449
450 /* For now, the PPGTT helper functions all require that the PDEs are
451 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
452 * will never need to touch the PDEs again */
453 for (i = 0; i < max_pdp; i++) {
454 gen8_ppgtt_pde_t *pd_vaddr;
455 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
456 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
457 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
458 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
459 I915_CACHE_LLC);
460 }
461 kunmap_atomic(pd_vaddr);
462 }
463
464 ppgtt->base.clear_range(&ppgtt->base, 0,
465 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
466 true);
467
468 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
469 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
470 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
471 ppgtt->num_pt_pages,
472 (ppgtt->num_pt_pages - num_pt_pages) +
473 size % (1<<30));
474 return 0;
475
476 err_out:
477 ppgtt->base.cleanup(&ppgtt->base);
478 return ret;
479 }
480
481 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
482 {
483 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
484 struct i915_address_space *vm = &ppgtt->base;
485 gen6_gtt_pte_t __iomem *pd_addr;
486 gen6_gtt_pte_t scratch_pte;
487 uint32_t pd_entry;
488 int pte, pde;
489
490 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
491
492 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
493 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
494
495 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
496 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
497 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
498 u32 expected;
499 gen6_gtt_pte_t *pt_vaddr;
500 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
501 pd_entry = readl(pd_addr + pde);
502 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
503
504 if (pd_entry != expected)
505 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
506 pde,
507 pd_entry,
508 expected);
509 seq_printf(m, "\tPDE: %x\n", pd_entry);
510
511 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
512 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
513 unsigned long va =
514 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
515 (pte * PAGE_SIZE);
516 int i;
517 bool found = false;
518 for (i = 0; i < 4; i++)
519 if (pt_vaddr[pte + i] != scratch_pte)
520 found = true;
521 if (!found)
522 continue;
523
524 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
525 for (i = 0; i < 4; i++) {
526 if (pt_vaddr[pte + i] != scratch_pte)
527 seq_printf(m, " %08x", pt_vaddr[pte + i]);
528 else
529 seq_puts(m, " SCRATCH ");
530 }
531 seq_puts(m, "\n");
532 }
533 kunmap_atomic(pt_vaddr);
534 }
535 }
536
537 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
538 {
539 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
540 gen6_gtt_pte_t __iomem *pd_addr;
541 uint32_t pd_entry;
542 int i;
543
544 WARN_ON(ppgtt->pd_offset & 0x3f);
545 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
546 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
547 for (i = 0; i < ppgtt->num_pd_entries; i++) {
548 dma_addr_t pt_addr;
549
550 pt_addr = ppgtt->pt_dma_addr[i];
551 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
552 pd_entry |= GEN6_PDE_VALID;
553
554 writel(pd_entry, pd_addr + i);
555 }
556 readl(pd_addr);
557 }
558
559 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
560 {
561 BUG_ON(ppgtt->pd_offset & 0x3f);
562
563 return (ppgtt->pd_offset / 64) << 16;
564 }
565
566 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
567 struct intel_ring_buffer *ring,
568 bool synchronous)
569 {
570 struct drm_device *dev = ppgtt->base.dev;
571 struct drm_i915_private *dev_priv = dev->dev_private;
572 int ret;
573
574 /* If we're in reset, we can assume the GPU is sufficiently idle to
575 * manually frob these bits. Ideally we could use the ring functions,
576 * except our error handling makes it quite difficult (can't use
577 * intel_ring_begin, ring->flush, or intel_ring_advance)
578 *
579 * FIXME: We should try not to special case reset
580 */
581 if (synchronous ||
582 i915_reset_in_progress(&dev_priv->gpu_error)) {
583 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
584 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
585 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
586 POSTING_READ(RING_PP_DIR_BASE(ring));
587 return 0;
588 }
589
590 /* NB: TLBs must be flushed and invalidated before a switch */
591 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
592 if (ret)
593 return ret;
594
595 ret = intel_ring_begin(ring, 6);
596 if (ret)
597 return ret;
598
599 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
600 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
601 intel_ring_emit(ring, PP_DIR_DCLV_2G);
602 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
603 intel_ring_emit(ring, get_pd_offset(ppgtt));
604 intel_ring_emit(ring, MI_NOOP);
605 intel_ring_advance(ring);
606
607 return 0;
608 }
609
610 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
611 struct intel_ring_buffer *ring,
612 bool synchronous)
613 {
614 struct drm_device *dev = ppgtt->base.dev;
615 struct drm_i915_private *dev_priv = dev->dev_private;
616 int ret;
617
618 /* If we're in reset, we can assume the GPU is sufficiently idle to
619 * manually frob these bits. Ideally we could use the ring functions,
620 * except our error handling makes it quite difficult (can't use
621 * intel_ring_begin, ring->flush, or intel_ring_advance)
622 *
623 * FIXME: We should try not to special case reset
624 */
625 if (synchronous ||
626 i915_reset_in_progress(&dev_priv->gpu_error)) {
627 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
628 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
629 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
630 POSTING_READ(RING_PP_DIR_BASE(ring));
631 return 0;
632 }
633
634 /* NB: TLBs must be flushed and invalidated before a switch */
635 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
636 if (ret)
637 return ret;
638
639 ret = intel_ring_begin(ring, 6);
640 if (ret)
641 return ret;
642
643 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
644 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
645 intel_ring_emit(ring, PP_DIR_DCLV_2G);
646 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
647 intel_ring_emit(ring, get_pd_offset(ppgtt));
648 intel_ring_emit(ring, MI_NOOP);
649 intel_ring_advance(ring);
650
651 /* XXX: RCS is the only one to auto invalidate the TLBs? */
652 if (ring->id != RCS) {
653 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
654 if (ret)
655 return ret;
656 }
657
658 return 0;
659 }
660
661 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
662 struct intel_ring_buffer *ring,
663 bool synchronous)
664 {
665 struct drm_device *dev = ppgtt->base.dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
667
668 if (!synchronous)
669 return 0;
670
671 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
672 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
673
674 POSTING_READ(RING_PP_DIR_DCLV(ring));
675
676 return 0;
677 }
678
679 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
680 {
681 struct drm_device *dev = ppgtt->base.dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 struct intel_ring_buffer *ring;
684 int j, ret;
685
686 for_each_ring(ring, dev_priv, j) {
687 I915_WRITE(RING_MODE_GEN7(ring),
688 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
689
690 /* We promise to do a switch later with FULL PPGTT. If this is
691 * aliasing, this is the one and only switch we'll do */
692 if (USES_FULL_PPGTT(dev))
693 continue;
694
695 ret = ppgtt->switch_mm(ppgtt, ring, true);
696 if (ret)
697 goto err_out;
698 }
699
700 return 0;
701
702 err_out:
703 for_each_ring(ring, dev_priv, j)
704 I915_WRITE(RING_MODE_GEN7(ring),
705 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
706 return ret;
707 }
708
709 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
710 {
711 struct drm_device *dev = ppgtt->base.dev;
712 drm_i915_private_t *dev_priv = dev->dev_private;
713 struct intel_ring_buffer *ring;
714 uint32_t ecochk, ecobits;
715 int i;
716
717 ecobits = I915_READ(GAC_ECO_BITS);
718 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
719
720 ecochk = I915_READ(GAM_ECOCHK);
721 if (IS_HASWELL(dev)) {
722 ecochk |= ECOCHK_PPGTT_WB_HSW;
723 } else {
724 ecochk |= ECOCHK_PPGTT_LLC_IVB;
725 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
726 }
727 I915_WRITE(GAM_ECOCHK, ecochk);
728
729 for_each_ring(ring, dev_priv, i) {
730 int ret;
731 /* GFX_MODE is per-ring on gen7+ */
732 I915_WRITE(RING_MODE_GEN7(ring),
733 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
734
735 /* We promise to do a switch later with FULL PPGTT. If this is
736 * aliasing, this is the one and only switch we'll do */
737 if (USES_FULL_PPGTT(dev))
738 continue;
739
740 ret = ppgtt->switch_mm(ppgtt, ring, true);
741 if (ret)
742 return ret;
743 }
744
745 return 0;
746 }
747
748 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
749 {
750 struct drm_device *dev = ppgtt->base.dev;
751 drm_i915_private_t *dev_priv = dev->dev_private;
752 struct intel_ring_buffer *ring;
753 uint32_t ecochk, gab_ctl, ecobits;
754 int i;
755
756 ecobits = I915_READ(GAC_ECO_BITS);
757 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
758 ECOBITS_PPGTT_CACHE64B);
759
760 gab_ctl = I915_READ(GAB_CTL);
761 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
762
763 ecochk = I915_READ(GAM_ECOCHK);
764 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
765
766 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
767
768 for_each_ring(ring, dev_priv, i) {
769 int ret = ppgtt->switch_mm(ppgtt, ring, true);
770 if (ret)
771 return ret;
772 }
773
774 return 0;
775 }
776
777 /* PPGTT support for Sandybdrige/Gen6 and later */
778 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
779 unsigned first_entry,
780 unsigned num_entries,
781 bool use_scratch)
782 {
783 struct i915_hw_ppgtt *ppgtt =
784 container_of(vm, struct i915_hw_ppgtt, base);
785 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
786 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
787 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
788 unsigned last_pte, i;
789
790 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
791
792 while (num_entries) {
793 last_pte = first_pte + num_entries;
794 if (last_pte > I915_PPGTT_PT_ENTRIES)
795 last_pte = I915_PPGTT_PT_ENTRIES;
796
797 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
798
799 for (i = first_pte; i < last_pte; i++)
800 pt_vaddr[i] = scratch_pte;
801
802 kunmap_atomic(pt_vaddr);
803
804 num_entries -= last_pte - first_pte;
805 first_pte = 0;
806 act_pt++;
807 }
808 }
809
810 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
811 struct sg_table *pages,
812 unsigned first_entry,
813 enum i915_cache_level cache_level)
814 {
815 struct i915_hw_ppgtt *ppgtt =
816 container_of(vm, struct i915_hw_ppgtt, base);
817 gen6_gtt_pte_t *pt_vaddr;
818 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
819 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
820 struct sg_page_iter sg_iter;
821
822 pt_vaddr = NULL;
823 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
824 if (pt_vaddr == NULL)
825 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
826
827 pt_vaddr[act_pte] =
828 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
829 cache_level, true);
830 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
831 kunmap_atomic(pt_vaddr);
832 pt_vaddr = NULL;
833 act_pt++;
834 act_pte = 0;
835 }
836 }
837 if (pt_vaddr)
838 kunmap_atomic(pt_vaddr);
839 }
840
841 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
842 {
843 struct i915_hw_ppgtt *ppgtt =
844 container_of(vm, struct i915_hw_ppgtt, base);
845 int i;
846
847 list_del(&vm->global_link);
848 drm_mm_takedown(&ppgtt->base.mm);
849 drm_mm_remove_node(&ppgtt->node);
850
851 if (ppgtt->pt_dma_addr) {
852 for (i = 0; i < ppgtt->num_pd_entries; i++)
853 pci_unmap_page(ppgtt->base.dev->pdev,
854 ppgtt->pt_dma_addr[i],
855 4096, PCI_DMA_BIDIRECTIONAL);
856 }
857
858 kfree(ppgtt->pt_dma_addr);
859 for (i = 0; i < ppgtt->num_pd_entries; i++)
860 __free_page(ppgtt->pt_pages[i]);
861 kfree(ppgtt->pt_pages);
862 kfree(ppgtt);
863 }
864
865 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
866 {
867 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
868 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
869 struct drm_device *dev = ppgtt->base.dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 bool retried = false;
872 int i, ret;
873
874 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
875 * allocator works in address space sizes, so it's multiplied by page
876 * size. We allocate at the top of the GTT to avoid fragmentation.
877 */
878 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
879 alloc:
880 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
881 &ppgtt->node, GEN6_PD_SIZE,
882 GEN6_PD_ALIGN, 0,
883 0, dev_priv->gtt.base.total,
884 DRM_MM_SEARCH_DEFAULT);
885 if (ret == -ENOSPC && !retried) {
886 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
887 GEN6_PD_SIZE, GEN6_PD_ALIGN,
888 I915_CACHE_NONE, 0);
889 if (ret)
890 return ret;
891
892 retried = true;
893 goto alloc;
894 }
895
896 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
897 DRM_DEBUG("Forced to use aperture for PDEs\n");
898
899 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
900 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
901 if (IS_GEN6(dev)) {
902 ppgtt->enable = gen6_ppgtt_enable;
903 ppgtt->switch_mm = gen6_mm_switch;
904 } else if (IS_HASWELL(dev)) {
905 ppgtt->enable = gen7_ppgtt_enable;
906 ppgtt->switch_mm = hsw_mm_switch;
907 } else if (IS_GEN7(dev)) {
908 ppgtt->enable = gen7_ppgtt_enable;
909 ppgtt->switch_mm = gen7_mm_switch;
910 } else
911 BUG();
912 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
913 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
914 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
915 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
916 ppgtt->base.start = 0;
917 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
918 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
919 GFP_KERNEL);
920 if (!ppgtt->pt_pages) {
921 drm_mm_remove_node(&ppgtt->node);
922 return -ENOMEM;
923 }
924
925 for (i = 0; i < ppgtt->num_pd_entries; i++) {
926 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
927 if (!ppgtt->pt_pages[i])
928 goto err_pt_alloc;
929 }
930
931 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
932 GFP_KERNEL);
933 if (!ppgtt->pt_dma_addr)
934 goto err_pt_alloc;
935
936 for (i = 0; i < ppgtt->num_pd_entries; i++) {
937 dma_addr_t pt_addr;
938
939 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
940 PCI_DMA_BIDIRECTIONAL);
941
942 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
943 ret = -EIO;
944 goto err_pd_pin;
945
946 }
947 ppgtt->pt_dma_addr[i] = pt_addr;
948 }
949
950 ppgtt->base.clear_range(&ppgtt->base, 0,
951 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
952 ppgtt->debug_dump = gen6_dump_ppgtt;
953
954 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
955 ppgtt->node.size >> 20,
956 ppgtt->node.start / PAGE_SIZE);
957 ppgtt->pd_offset =
958 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
959
960 return 0;
961
962 err_pd_pin:
963 if (ppgtt->pt_dma_addr) {
964 for (i--; i >= 0; i--)
965 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
966 4096, PCI_DMA_BIDIRECTIONAL);
967 }
968 err_pt_alloc:
969 kfree(ppgtt->pt_dma_addr);
970 for (i = 0; i < ppgtt->num_pd_entries; i++) {
971 if (ppgtt->pt_pages[i])
972 __free_page(ppgtt->pt_pages[i]);
973 }
974 kfree(ppgtt->pt_pages);
975 drm_mm_remove_node(&ppgtt->node);
976
977 return ret;
978 }
979
980 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
981 {
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 int ret = 0;
984
985 ppgtt->base.dev = dev;
986
987 if (INTEL_INFO(dev)->gen < 8)
988 ret = gen6_ppgtt_init(ppgtt);
989 else if (IS_GEN8(dev))
990 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
991 else
992 BUG();
993
994 if (!ret) {
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 kref_init(&ppgtt->ref);
997 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
998 ppgtt->base.total);
999 i915_init_vm(dev_priv, &ppgtt->base);
1000 if (INTEL_INFO(dev)->gen < 8) {
1001 gen6_write_pdes(ppgtt);
1002 DRM_DEBUG("Adding PPGTT at offset %x\n",
1003 ppgtt->pd_offset << 10);
1004 }
1005 }
1006
1007 return ret;
1008 }
1009
1010 static void
1011 ppgtt_bind_vma(struct i915_vma *vma,
1012 enum i915_cache_level cache_level,
1013 u32 flags)
1014 {
1015 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1016
1017 WARN_ON(flags);
1018
1019 vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
1020 }
1021
1022 static void ppgtt_unbind_vma(struct i915_vma *vma)
1023 {
1024 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1025
1026 vma->vm->clear_range(vma->vm,
1027 entry,
1028 vma->obj->base.size >> PAGE_SHIFT,
1029 true);
1030 }
1031
1032 extern int intel_iommu_gfx_mapped;
1033 /* Certain Gen5 chipsets require require idling the GPU before
1034 * unmapping anything from the GTT when VT-d is enabled.
1035 */
1036 static inline bool needs_idle_maps(struct drm_device *dev)
1037 {
1038 #ifdef CONFIG_INTEL_IOMMU
1039 /* Query intel_iommu to see if we need the workaround. Presumably that
1040 * was loaded first.
1041 */
1042 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1043 return true;
1044 #endif
1045 return false;
1046 }
1047
1048 static bool do_idling(struct drm_i915_private *dev_priv)
1049 {
1050 bool ret = dev_priv->mm.interruptible;
1051
1052 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1053 dev_priv->mm.interruptible = false;
1054 if (i915_gpu_idle(dev_priv->dev)) {
1055 DRM_ERROR("Couldn't idle GPU\n");
1056 /* Wait a bit, in hopes it avoids the hang */
1057 udelay(10);
1058 }
1059 }
1060
1061 return ret;
1062 }
1063
1064 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1065 {
1066 if (unlikely(dev_priv->gtt.do_idle_maps))
1067 dev_priv->mm.interruptible = interruptible;
1068 }
1069
1070 void i915_check_and_clear_faults(struct drm_device *dev)
1071 {
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 struct intel_ring_buffer *ring;
1074 int i;
1075
1076 if (INTEL_INFO(dev)->gen < 6)
1077 return;
1078
1079 for_each_ring(ring, dev_priv, i) {
1080 u32 fault_reg;
1081 fault_reg = I915_READ(RING_FAULT_REG(ring));
1082 if (fault_reg & RING_FAULT_VALID) {
1083 DRM_DEBUG_DRIVER("Unexpected fault\n"
1084 "\tAddr: 0x%08lx\\n"
1085 "\tAddress space: %s\n"
1086 "\tSource ID: %d\n"
1087 "\tType: %d\n",
1088 fault_reg & PAGE_MASK,
1089 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1090 RING_FAULT_SRCID(fault_reg),
1091 RING_FAULT_FAULT_TYPE(fault_reg));
1092 I915_WRITE(RING_FAULT_REG(ring),
1093 fault_reg & ~RING_FAULT_VALID);
1094 }
1095 }
1096 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1097 }
1098
1099 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1100 {
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102
1103 /* Don't bother messing with faults pre GEN6 as we have little
1104 * documentation supporting that it's a good idea.
1105 */
1106 if (INTEL_INFO(dev)->gen < 6)
1107 return;
1108
1109 i915_check_and_clear_faults(dev);
1110
1111 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1112 dev_priv->gtt.base.start / PAGE_SIZE,
1113 dev_priv->gtt.base.total / PAGE_SIZE,
1114 false);
1115 }
1116
1117 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1118 {
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 struct drm_i915_gem_object *obj;
1121 struct i915_address_space *vm;
1122
1123 i915_check_and_clear_faults(dev);
1124
1125 /* First fill our portion of the GTT with scratch pages */
1126 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1127 dev_priv->gtt.base.start / PAGE_SIZE,
1128 dev_priv->gtt.base.total / PAGE_SIZE,
1129 true);
1130
1131 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1132 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1133 &dev_priv->gtt.base);
1134 if (!vma)
1135 continue;
1136
1137 i915_gem_clflush_object(obj, obj->pin_display);
1138 /* The bind_vma code tries to be smart about tracking mappings.
1139 * Unfortunately above, we've just wiped out the mappings
1140 * without telling our object about it. So we need to fake it.
1141 */
1142 obj->has_global_gtt_mapping = 0;
1143 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1144 }
1145
1146
1147 if (INTEL_INFO(dev)->gen >= 8)
1148 return;
1149
1150 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1151 /* TODO: Perhaps it shouldn't be gen6 specific */
1152 if (i915_is_ggtt(vm)) {
1153 if (dev_priv->mm.aliasing_ppgtt)
1154 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1155 continue;
1156 }
1157
1158 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1159 }
1160
1161 i915_gem_chipset_flush(dev);
1162 }
1163
1164 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1165 {
1166 if (obj->has_dma_mapping)
1167 return 0;
1168
1169 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1170 obj->pages->sgl, obj->pages->nents,
1171 PCI_DMA_BIDIRECTIONAL))
1172 return -ENOSPC;
1173
1174 return 0;
1175 }
1176
1177 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1178 {
1179 #ifdef writeq
1180 writeq(pte, addr);
1181 #else
1182 iowrite32((u32)pte, addr);
1183 iowrite32(pte >> 32, addr + 4);
1184 #endif
1185 }
1186
1187 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1188 struct sg_table *st,
1189 unsigned int first_entry,
1190 enum i915_cache_level level)
1191 {
1192 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1193 gen8_gtt_pte_t __iomem *gtt_entries =
1194 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1195 int i = 0;
1196 struct sg_page_iter sg_iter;
1197 dma_addr_t addr;
1198
1199 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1200 addr = sg_dma_address(sg_iter.sg) +
1201 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1202 gen8_set_pte(&gtt_entries[i],
1203 gen8_pte_encode(addr, level, true));
1204 i++;
1205 }
1206
1207 /*
1208 * XXX: This serves as a posting read to make sure that the PTE has
1209 * actually been updated. There is some concern that even though
1210 * registers and PTEs are within the same BAR that they are potentially
1211 * of NUMA access patterns. Therefore, even with the way we assume
1212 * hardware should work, we must keep this posting read for paranoia.
1213 */
1214 if (i != 0)
1215 WARN_ON(readq(&gtt_entries[i-1])
1216 != gen8_pte_encode(addr, level, true));
1217
1218 /* This next bit makes the above posting read even more important. We
1219 * want to flush the TLBs only after we're certain all the PTE updates
1220 * have finished.
1221 */
1222 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1223 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1224 }
1225
1226 /*
1227 * Binds an object into the global gtt with the specified cache level. The object
1228 * will be accessible to the GPU via commands whose operands reference offsets
1229 * within the global GTT as well as accessible by the GPU through the GMADR
1230 * mapped BAR (dev_priv->mm.gtt->gtt).
1231 */
1232 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1233 struct sg_table *st,
1234 unsigned int first_entry,
1235 enum i915_cache_level level)
1236 {
1237 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1238 gen6_gtt_pte_t __iomem *gtt_entries =
1239 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1240 int i = 0;
1241 struct sg_page_iter sg_iter;
1242 dma_addr_t addr;
1243
1244 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1245 addr = sg_page_iter_dma_address(&sg_iter);
1246 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1247 i++;
1248 }
1249
1250 /* XXX: This serves as a posting read to make sure that the PTE has
1251 * actually been updated. There is some concern that even though
1252 * registers and PTEs are within the same BAR that they are potentially
1253 * of NUMA access patterns. Therefore, even with the way we assume
1254 * hardware should work, we must keep this posting read for paranoia.
1255 */
1256 if (i != 0)
1257 WARN_ON(readl(&gtt_entries[i-1]) !=
1258 vm->pte_encode(addr, level, true));
1259
1260 /* This next bit makes the above posting read even more important. We
1261 * want to flush the TLBs only after we're certain all the PTE updates
1262 * have finished.
1263 */
1264 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1265 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1266 }
1267
1268 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1269 unsigned int first_entry,
1270 unsigned int num_entries,
1271 bool use_scratch)
1272 {
1273 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1274 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1275 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1276 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1277 int i;
1278
1279 if (WARN(num_entries > max_entries,
1280 "First entry = %d; Num entries = %d (max=%d)\n",
1281 first_entry, num_entries, max_entries))
1282 num_entries = max_entries;
1283
1284 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1285 I915_CACHE_LLC,
1286 use_scratch);
1287 for (i = 0; i < num_entries; i++)
1288 gen8_set_pte(&gtt_base[i], scratch_pte);
1289 readl(gtt_base);
1290 }
1291
1292 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1293 unsigned int first_entry,
1294 unsigned int num_entries,
1295 bool use_scratch)
1296 {
1297 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1298 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1299 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1300 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1301 int i;
1302
1303 if (WARN(num_entries > max_entries,
1304 "First entry = %d; Num entries = %d (max=%d)\n",
1305 first_entry, num_entries, max_entries))
1306 num_entries = max_entries;
1307
1308 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1309
1310 for (i = 0; i < num_entries; i++)
1311 iowrite32(scratch_pte, &gtt_base[i]);
1312 readl(gtt_base);
1313 }
1314
1315
1316 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1317 enum i915_cache_level cache_level,
1318 u32 unused)
1319 {
1320 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1321 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1322 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1323
1324 BUG_ON(!i915_is_ggtt(vma->vm));
1325 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1326 vma->obj->has_global_gtt_mapping = 1;
1327 }
1328
1329 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1330 unsigned int first_entry,
1331 unsigned int num_entries,
1332 bool unused)
1333 {
1334 intel_gtt_clear_range(first_entry, num_entries);
1335 }
1336
1337 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1338 {
1339 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1340 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1341
1342 BUG_ON(!i915_is_ggtt(vma->vm));
1343 vma->obj->has_global_gtt_mapping = 0;
1344 intel_gtt_clear_range(first, size);
1345 }
1346
1347 static void ggtt_bind_vma(struct i915_vma *vma,
1348 enum i915_cache_level cache_level,
1349 u32 flags)
1350 {
1351 struct drm_device *dev = vma->vm->dev;
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 struct drm_i915_gem_object *obj = vma->obj;
1354 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1355
1356 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1357 * or we have a global mapping already but the cacheability flags have
1358 * changed, set the global PTEs.
1359 *
1360 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1361 * instead if none of the above hold true.
1362 *
1363 * NB: A global mapping should only be needed for special regions like
1364 * "gtt mappable", SNB errata, or if specified via special execbuf
1365 * flags. At all other times, the GPU will use the aliasing PPGTT.
1366 */
1367 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1368 if (!obj->has_global_gtt_mapping ||
1369 (cache_level != obj->cache_level)) {
1370 vma->vm->insert_entries(vma->vm, obj->pages, entry,
1371 cache_level);
1372 obj->has_global_gtt_mapping = 1;
1373 }
1374 }
1375
1376 if (dev_priv->mm.aliasing_ppgtt &&
1377 (!obj->has_aliasing_ppgtt_mapping ||
1378 (cache_level != obj->cache_level))) {
1379 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1380 appgtt->base.insert_entries(&appgtt->base,
1381 vma->obj->pages, entry, cache_level);
1382 vma->obj->has_aliasing_ppgtt_mapping = 1;
1383 }
1384 }
1385
1386 static void ggtt_unbind_vma(struct i915_vma *vma)
1387 {
1388 struct drm_device *dev = vma->vm->dev;
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 struct drm_i915_gem_object *obj = vma->obj;
1391 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1392
1393 if (obj->has_global_gtt_mapping) {
1394 vma->vm->clear_range(vma->vm, entry,
1395 vma->obj->base.size >> PAGE_SHIFT,
1396 true);
1397 obj->has_global_gtt_mapping = 0;
1398 }
1399
1400 if (obj->has_aliasing_ppgtt_mapping) {
1401 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1402 appgtt->base.clear_range(&appgtt->base,
1403 entry,
1404 obj->base.size >> PAGE_SHIFT,
1405 true);
1406 obj->has_aliasing_ppgtt_mapping = 0;
1407 }
1408 }
1409
1410 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1411 {
1412 struct drm_device *dev = obj->base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 bool interruptible;
1415
1416 interruptible = do_idling(dev_priv);
1417
1418 if (!obj->has_dma_mapping)
1419 dma_unmap_sg(&dev->pdev->dev,
1420 obj->pages->sgl, obj->pages->nents,
1421 PCI_DMA_BIDIRECTIONAL);
1422
1423 undo_idling(dev_priv, interruptible);
1424 }
1425
1426 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1427 unsigned long color,
1428 unsigned long *start,
1429 unsigned long *end)
1430 {
1431 if (node->color != color)
1432 *start += 4096;
1433
1434 if (!list_empty(&node->node_list)) {
1435 node = list_entry(node->node_list.next,
1436 struct drm_mm_node,
1437 node_list);
1438 if (node->allocated && node->color != color)
1439 *end -= 4096;
1440 }
1441 }
1442
1443 void i915_gem_setup_global_gtt(struct drm_device *dev,
1444 unsigned long start,
1445 unsigned long mappable_end,
1446 unsigned long end)
1447 {
1448 /* Let GEM Manage all of the aperture.
1449 *
1450 * However, leave one page at the end still bound to the scratch page.
1451 * There are a number of places where the hardware apparently prefetches
1452 * past the end of the object, and we've seen multiple hangs with the
1453 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1454 * aperture. One page should be enough to keep any prefetching inside
1455 * of the aperture.
1456 */
1457 struct drm_i915_private *dev_priv = dev->dev_private;
1458 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1459 struct drm_mm_node *entry;
1460 struct drm_i915_gem_object *obj;
1461 unsigned long hole_start, hole_end;
1462
1463 BUG_ON(mappable_end > end);
1464
1465 /* Subtract the guard page ... */
1466 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1467 if (!HAS_LLC(dev))
1468 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1469
1470 /* Mark any preallocated objects as occupied */
1471 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1472 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1473 int ret;
1474 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1475 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1476
1477 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1478 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1479 if (ret)
1480 DRM_DEBUG_KMS("Reservation failed\n");
1481 obj->has_global_gtt_mapping = 1;
1482 }
1483
1484 dev_priv->gtt.base.start = start;
1485 dev_priv->gtt.base.total = end - start;
1486
1487 /* Clear any non-preallocated blocks */
1488 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1489 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1490 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1491 hole_start, hole_end);
1492 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1493 }
1494
1495 /* And finally clear the reserved guard page */
1496 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1497 }
1498
1499 void i915_gem_init_global_gtt(struct drm_device *dev)
1500 {
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 unsigned long gtt_size, mappable_size;
1503
1504 gtt_size = dev_priv->gtt.base.total;
1505 mappable_size = dev_priv->gtt.mappable_end;
1506
1507 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1508 }
1509
1510 static int setup_scratch_page(struct drm_device *dev)
1511 {
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513 struct page *page;
1514 dma_addr_t dma_addr;
1515
1516 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1517 if (page == NULL)
1518 return -ENOMEM;
1519 get_page(page);
1520 set_pages_uc(page, 1);
1521
1522 #ifdef CONFIG_INTEL_IOMMU
1523 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1524 PCI_DMA_BIDIRECTIONAL);
1525 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1526 return -EINVAL;
1527 #else
1528 dma_addr = page_to_phys(page);
1529 #endif
1530 dev_priv->gtt.base.scratch.page = page;
1531 dev_priv->gtt.base.scratch.addr = dma_addr;
1532
1533 return 0;
1534 }
1535
1536 static void teardown_scratch_page(struct drm_device *dev)
1537 {
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 struct page *page = dev_priv->gtt.base.scratch.page;
1540
1541 set_pages_wb(page, 1);
1542 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1543 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1544 put_page(page);
1545 __free_page(page);
1546 }
1547
1548 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1549 {
1550 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1551 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1552 return snb_gmch_ctl << 20;
1553 }
1554
1555 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1556 {
1557 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1558 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1559 if (bdw_gmch_ctl)
1560 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1561 if (bdw_gmch_ctl > 4) {
1562 WARN_ON(!i915.preliminary_hw_support);
1563 return 4<<20;
1564 }
1565
1566 return bdw_gmch_ctl << 20;
1567 }
1568
1569 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1570 {
1571 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1572 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1573 return snb_gmch_ctl << 25; /* 32 MB units */
1574 }
1575
1576 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1577 {
1578 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1579 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1580 return bdw_gmch_ctl << 25; /* 32 MB units */
1581 }
1582
1583 static int ggtt_probe_common(struct drm_device *dev,
1584 size_t gtt_size)
1585 {
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 phys_addr_t gtt_phys_addr;
1588 int ret;
1589
1590 /* For Modern GENs the PTEs and register space are split in the BAR */
1591 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1592 (pci_resource_len(dev->pdev, 0) / 2);
1593
1594 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1595 if (!dev_priv->gtt.gsm) {
1596 DRM_ERROR("Failed to map the gtt page table\n");
1597 return -ENOMEM;
1598 }
1599
1600 ret = setup_scratch_page(dev);
1601 if (ret) {
1602 DRM_ERROR("Scratch setup failed\n");
1603 /* iounmap will also get called at remove, but meh */
1604 iounmap(dev_priv->gtt.gsm);
1605 }
1606
1607 return ret;
1608 }
1609
1610 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1611 * bits. When using advanced contexts each context stores its own PAT, but
1612 * writing this data shouldn't be harmful even in those cases. */
1613 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1614 {
1615 #define GEN8_PPAT_UC (0<<0)
1616 #define GEN8_PPAT_WC (1<<0)
1617 #define GEN8_PPAT_WT (2<<0)
1618 #define GEN8_PPAT_WB (3<<0)
1619 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1620 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1621 #define GEN8_PPAT_LLC (1<<2)
1622 #define GEN8_PPAT_LLCELLC (2<<2)
1623 #define GEN8_PPAT_LLCeLLC (3<<2)
1624 #define GEN8_PPAT_AGE(x) (x<<4)
1625 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1626 uint64_t pat;
1627
1628 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1629 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1630 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1631 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1632 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1633 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1634 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1635 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1636
1637 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1638 * write would work. */
1639 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1640 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1641 }
1642
1643 static int gen8_gmch_probe(struct drm_device *dev,
1644 size_t *gtt_total,
1645 size_t *stolen,
1646 phys_addr_t *mappable_base,
1647 unsigned long *mappable_end)
1648 {
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 unsigned int gtt_size;
1651 u16 snb_gmch_ctl;
1652 int ret;
1653
1654 /* TODO: We're not aware of mappable constraints on gen8 yet */
1655 *mappable_base = pci_resource_start(dev->pdev, 2);
1656 *mappable_end = pci_resource_len(dev->pdev, 2);
1657
1658 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1659 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1660
1661 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1662
1663 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1664
1665 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1666 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1667
1668 gen8_setup_private_ppat(dev_priv);
1669
1670 ret = ggtt_probe_common(dev, gtt_size);
1671
1672 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1673 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1674
1675 return ret;
1676 }
1677
1678 static int gen6_gmch_probe(struct drm_device *dev,
1679 size_t *gtt_total,
1680 size_t *stolen,
1681 phys_addr_t *mappable_base,
1682 unsigned long *mappable_end)
1683 {
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 unsigned int gtt_size;
1686 u16 snb_gmch_ctl;
1687 int ret;
1688
1689 *mappable_base = pci_resource_start(dev->pdev, 2);
1690 *mappable_end = pci_resource_len(dev->pdev, 2);
1691
1692 /* 64/512MB is the current min/max we actually know of, but this is just
1693 * a coarse sanity check.
1694 */
1695 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1696 DRM_ERROR("Unknown GMADR size (%lx)\n",
1697 dev_priv->gtt.mappable_end);
1698 return -ENXIO;
1699 }
1700
1701 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1702 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1703 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1704
1705 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1706
1707 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1708 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1709
1710 ret = ggtt_probe_common(dev, gtt_size);
1711
1712 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1713 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1714
1715 return ret;
1716 }
1717
1718 static void gen6_gmch_remove(struct i915_address_space *vm)
1719 {
1720
1721 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1722
1723 drm_mm_takedown(&vm->mm);
1724 iounmap(gtt->gsm);
1725 teardown_scratch_page(vm->dev);
1726 }
1727
1728 static int i915_gmch_probe(struct drm_device *dev,
1729 size_t *gtt_total,
1730 size_t *stolen,
1731 phys_addr_t *mappable_base,
1732 unsigned long *mappable_end)
1733 {
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 int ret;
1736
1737 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1738 if (!ret) {
1739 DRM_ERROR("failed to set up gmch\n");
1740 return -EIO;
1741 }
1742
1743 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1744
1745 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1746 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1747
1748 if (unlikely(dev_priv->gtt.do_idle_maps))
1749 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1750
1751 return 0;
1752 }
1753
1754 static void i915_gmch_remove(struct i915_address_space *vm)
1755 {
1756 intel_gmch_remove();
1757 }
1758
1759 int i915_gem_gtt_init(struct drm_device *dev)
1760 {
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct i915_gtt *gtt = &dev_priv->gtt;
1763 int ret;
1764
1765 if (INTEL_INFO(dev)->gen <= 5) {
1766 gtt->gtt_probe = i915_gmch_probe;
1767 gtt->base.cleanup = i915_gmch_remove;
1768 } else if (INTEL_INFO(dev)->gen < 8) {
1769 gtt->gtt_probe = gen6_gmch_probe;
1770 gtt->base.cleanup = gen6_gmch_remove;
1771 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1772 gtt->base.pte_encode = iris_pte_encode;
1773 else if (IS_HASWELL(dev))
1774 gtt->base.pte_encode = hsw_pte_encode;
1775 else if (IS_VALLEYVIEW(dev))
1776 gtt->base.pte_encode = byt_pte_encode;
1777 else if (INTEL_INFO(dev)->gen >= 7)
1778 gtt->base.pte_encode = ivb_pte_encode;
1779 else
1780 gtt->base.pte_encode = snb_pte_encode;
1781 } else {
1782 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1783 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1784 }
1785
1786 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1787 &gtt->mappable_base, &gtt->mappable_end);
1788 if (ret)
1789 return ret;
1790
1791 gtt->base.dev = dev;
1792
1793 /* GMADR is the PCI mmio aperture into the global GTT. */
1794 DRM_INFO("Memory usable by graphics device = %zdM\n",
1795 gtt->base.total >> 20);
1796 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1797 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1798
1799 return 0;
1800 }
1801
1802 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1803 struct i915_address_space *vm)
1804 {
1805 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1806 if (vma == NULL)
1807 return ERR_PTR(-ENOMEM);
1808
1809 INIT_LIST_HEAD(&vma->vma_link);
1810 INIT_LIST_HEAD(&vma->mm_list);
1811 INIT_LIST_HEAD(&vma->exec_list);
1812 vma->vm = vm;
1813 vma->obj = obj;
1814
1815 switch (INTEL_INFO(vm->dev)->gen) {
1816 case 8:
1817 case 7:
1818 case 6:
1819 if (i915_is_ggtt(vm)) {
1820 vma->unbind_vma = ggtt_unbind_vma;
1821 vma->bind_vma = ggtt_bind_vma;
1822 } else {
1823 vma->unbind_vma = ppgtt_unbind_vma;
1824 vma->bind_vma = ppgtt_bind_vma;
1825 }
1826 break;
1827 case 5:
1828 case 4:
1829 case 3:
1830 case 2:
1831 BUG_ON(!i915_is_ggtt(vm));
1832 vma->unbind_vma = i915_ggtt_unbind_vma;
1833 vma->bind_vma = i915_ggtt_bind_vma;
1834 break;
1835 default:
1836 BUG();
1837 }
1838
1839 /* Keep GGTT vmas first to make debug easier */
1840 if (i915_is_ggtt(vm))
1841 list_add(&vma->vma_link, &obj->vma_list);
1842 else
1843 list_add_tail(&vma->vma_link, &obj->vma_list);
1844
1845 return vma;
1846 }
1847
1848 struct i915_vma *
1849 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1850 struct i915_address_space *vm)
1851 {
1852 struct i915_vma *vma;
1853
1854 vma = i915_gem_obj_to_vma(obj, vm);
1855 if (!vma)
1856 vma = __i915_gem_vma_create(obj, vm);
1857
1858 return vma;
1859 }
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