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Merge tag 'drm-intel-next-2014-02-07' of ssh://git.freedesktop.org/git/drm-intel...
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/seq_file.h>
26 #include <drm/drmP.h>
27 #include <drm/i915_drm.h>
28 #include "i915_drv.h"
29 #include "i915_trace.h"
30 #include "intel_drv.h"
31
32 #define GEN6_PPGTT_PD_ENTRIES 512
33 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
34 typedef uint64_t gen8_gtt_pte_t;
35 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
36
37 /* PPGTT stuff */
38 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
39 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
40
41 #define GEN6_PDE_VALID (1 << 0)
42 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
43 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
44
45 #define GEN6_PTE_VALID (1 << 0)
46 #define GEN6_PTE_UNCACHED (1 << 1)
47 #define HSW_PTE_UNCACHED (0)
48 #define GEN6_PTE_CACHE_LLC (2 << 1)
49 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
51 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
52
53 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
54 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
55 */
56 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
57 (((bits) & 0x8) << (11 - 3)))
58 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
59 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
60 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
61 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
62 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
63 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
64
65 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
66 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
67 #define GEN8_LEGACY_PDPS 4
68
69 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
70 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
71 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
72 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
73
74 static void ppgtt_bind_vma(struct i915_vma *vma,
75 enum i915_cache_level cache_level,
76 u32 flags);
77 static void ppgtt_unbind_vma(struct i915_vma *vma);
78 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
79
80 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
81 enum i915_cache_level level,
82 bool valid)
83 {
84 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
85 pte |= addr;
86 if (level != I915_CACHE_NONE)
87 pte |= PPAT_CACHED_INDEX;
88 else
89 pte |= PPAT_UNCACHED_INDEX;
90 return pte;
91 }
92
93 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
94 dma_addr_t addr,
95 enum i915_cache_level level)
96 {
97 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
98 pde |= addr;
99 if (level != I915_CACHE_NONE)
100 pde |= PPAT_CACHED_PDE_INDEX;
101 else
102 pde |= PPAT_UNCACHED_INDEX;
103 return pde;
104 }
105
106 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
107 enum i915_cache_level level,
108 bool valid)
109 {
110 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
111 pte |= GEN6_PTE_ADDR_ENCODE(addr);
112
113 switch (level) {
114 case I915_CACHE_L3_LLC:
115 case I915_CACHE_LLC:
116 pte |= GEN6_PTE_CACHE_LLC;
117 break;
118 case I915_CACHE_NONE:
119 pte |= GEN6_PTE_UNCACHED;
120 break;
121 default:
122 WARN_ON(1);
123 }
124
125 return pte;
126 }
127
128 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
129 enum i915_cache_level level,
130 bool valid)
131 {
132 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
133 pte |= GEN6_PTE_ADDR_ENCODE(addr);
134
135 switch (level) {
136 case I915_CACHE_L3_LLC:
137 pte |= GEN7_PTE_CACHE_L3_LLC;
138 break;
139 case I915_CACHE_LLC:
140 pte |= GEN6_PTE_CACHE_LLC;
141 break;
142 case I915_CACHE_NONE:
143 pte |= GEN6_PTE_UNCACHED;
144 break;
145 default:
146 WARN_ON(1);
147 }
148
149 return pte;
150 }
151
152 #define BYT_PTE_WRITEABLE (1 << 1)
153 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
154
155 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
156 enum i915_cache_level level,
157 bool valid)
158 {
159 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
160 pte |= GEN6_PTE_ADDR_ENCODE(addr);
161
162 /* Mark the page as writeable. Other platforms don't have a
163 * setting for read-only/writable, so this matches that behavior.
164 */
165 pte |= BYT_PTE_WRITEABLE;
166
167 if (level != I915_CACHE_NONE)
168 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
169
170 return pte;
171 }
172
173 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
176 {
177 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
178 pte |= HSW_PTE_ADDR_ENCODE(addr);
179
180 if (level != I915_CACHE_NONE)
181 pte |= HSW_WB_LLC_AGE3;
182
183 return pte;
184 }
185
186 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= HSW_PTE_ADDR_ENCODE(addr);
192
193 switch (level) {
194 case I915_CACHE_NONE:
195 break;
196 case I915_CACHE_WT:
197 pte |= HSW_WT_ELLC_LLC_AGE3;
198 break;
199 default:
200 pte |= HSW_WB_ELLC_LLC_AGE3;
201 break;
202 }
203
204 return pte;
205 }
206
207 /* Broadwell Page Directory Pointer Descriptors */
208 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
209 uint64_t val, bool synchronous)
210 {
211 struct drm_i915_private *dev_priv = ring->dev->dev_private;
212 int ret;
213
214 BUG_ON(entry >= 4);
215
216 if (synchronous) {
217 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
218 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
219 return 0;
220 }
221
222 ret = intel_ring_begin(ring, 6);
223 if (ret)
224 return ret;
225
226 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
227 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
228 intel_ring_emit(ring, (u32)(val >> 32));
229 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
230 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
231 intel_ring_emit(ring, (u32)(val));
232 intel_ring_advance(ring);
233
234 return 0;
235 }
236
237 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
238 struct intel_ring_buffer *ring,
239 bool synchronous)
240 {
241 int i, ret;
242
243 /* bit of a hack to find the actual last used pd */
244 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
245
246 for (i = used_pd - 1; i >= 0; i--) {
247 dma_addr_t addr = ppgtt->pd_dma_addr[i];
248 ret = gen8_write_pdp(ring, i, addr, synchronous);
249 if (ret)
250 return ret;
251 }
252
253 return 0;
254 }
255
256 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
257 unsigned first_entry,
258 unsigned num_entries,
259 bool use_scratch)
260 {
261 struct i915_hw_ppgtt *ppgtt =
262 container_of(vm, struct i915_hw_ppgtt, base);
263 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
264 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
265 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
266 unsigned last_pte, i;
267
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
270
271 while (num_entries) {
272 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
273
274 last_pte = first_pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
277
278 pt_vaddr = kmap_atomic(page_table);
279
280 for (i = first_pte; i < last_pte; i++)
281 pt_vaddr[i] = scratch_pte;
282
283 kunmap_atomic(pt_vaddr);
284
285 num_entries -= last_pte - first_pte;
286 first_pte = 0;
287 act_pt++;
288 }
289 }
290
291 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
292 struct sg_table *pages,
293 unsigned first_entry,
294 enum i915_cache_level cache_level)
295 {
296 struct i915_hw_ppgtt *ppgtt =
297 container_of(vm, struct i915_hw_ppgtt, base);
298 gen8_gtt_pte_t *pt_vaddr;
299 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
300 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
301 struct sg_page_iter sg_iter;
302
303 pt_vaddr = NULL;
304 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
305 if (pt_vaddr == NULL)
306 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
307
308 pt_vaddr[act_pte] =
309 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
310 cache_level, true);
311 if (++act_pte == GEN8_PTES_PER_PAGE) {
312 kunmap_atomic(pt_vaddr);
313 pt_vaddr = NULL;
314 act_pt++;
315 act_pte = 0;
316 }
317 }
318 if (pt_vaddr)
319 kunmap_atomic(pt_vaddr);
320 }
321
322 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
323 {
324 struct i915_hw_ppgtt *ppgtt =
325 container_of(vm, struct i915_hw_ppgtt, base);
326 int i, j;
327
328 list_del(&vm->global_link);
329 drm_mm_takedown(&vm->mm);
330
331 for (i = 0; i < ppgtt->num_pd_pages ; i++) {
332 if (ppgtt->pd_dma_addr[i]) {
333 pci_unmap_page(ppgtt->base.dev->pdev,
334 ppgtt->pd_dma_addr[i],
335 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
336
337 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
338 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
339 if (addr)
340 pci_unmap_page(ppgtt->base.dev->pdev,
341 addr,
342 PAGE_SIZE,
343 PCI_DMA_BIDIRECTIONAL);
344
345 }
346 }
347 kfree(ppgtt->gen8_pt_dma_addr[i]);
348 }
349
350 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
351 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
352 }
353
354 /**
355 * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
356 * net effect resembling a 2-level page table in normal x86 terms. Each PDP
357 * represents 1GB of memory
358 * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
359 *
360 * TODO: Do something with the size parameter
361 **/
362 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
363 {
364 struct page *pt_pages;
365 int i, j, ret = -ENOMEM;
366 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
367 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
368
369 if (size % (1<<30))
370 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
371
372 /* FIXME: split allocation into smaller pieces. For now we only ever do
373 * this once, but with full PPGTT, the multiple contiguous allocations
374 * will be bad.
375 */
376 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
377 if (!ppgtt->pd_pages)
378 return -ENOMEM;
379
380 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
381 if (!pt_pages) {
382 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
383 return -ENOMEM;
384 }
385
386 ppgtt->gen8_pt_pages = pt_pages;
387 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
388 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
389 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
390 ppgtt->enable = gen8_ppgtt_enable;
391 ppgtt->switch_mm = gen8_mm_switch;
392 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
393 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
394 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
395 ppgtt->base.start = 0;
396 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
397
398 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
399
400 /*
401 * - Create a mapping for the page directories.
402 * - For each page directory:
403 * allocate space for page table mappings.
404 * map each page table
405 */
406 for (i = 0; i < max_pdp; i++) {
407 dma_addr_t temp;
408 temp = pci_map_page(ppgtt->base.dev->pdev,
409 &ppgtt->pd_pages[i], 0,
410 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
411 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
412 goto err_out;
413
414 ppgtt->pd_dma_addr[i] = temp;
415
416 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
417 if (!ppgtt->gen8_pt_dma_addr[i])
418 goto err_out;
419
420 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
421 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
422 temp = pci_map_page(ppgtt->base.dev->pdev,
423 p, 0, PAGE_SIZE,
424 PCI_DMA_BIDIRECTIONAL);
425
426 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
427 goto err_out;
428
429 ppgtt->gen8_pt_dma_addr[i][j] = temp;
430 }
431 }
432
433 /* For now, the PPGTT helper functions all require that the PDEs are
434 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
435 * will never need to touch the PDEs again */
436 for (i = 0; i < max_pdp; i++) {
437 gen8_ppgtt_pde_t *pd_vaddr;
438 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
439 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
440 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
441 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
442 I915_CACHE_LLC);
443 }
444 kunmap_atomic(pd_vaddr);
445 }
446
447 ppgtt->base.clear_range(&ppgtt->base, 0,
448 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
449 true);
450
451 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
452 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
453 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
454 ppgtt->num_pt_pages,
455 (ppgtt->num_pt_pages - num_pt_pages) +
456 size % (1<<30));
457 return 0;
458
459 err_out:
460 ppgtt->base.cleanup(&ppgtt->base);
461 return ret;
462 }
463
464 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
465 {
466 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
467 struct i915_address_space *vm = &ppgtt->base;
468 gen6_gtt_pte_t __iomem *pd_addr;
469 gen6_gtt_pte_t scratch_pte;
470 uint32_t pd_entry;
471 int pte, pde;
472
473 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
474
475 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
476 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
477
478 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
479 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
480 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
481 u32 expected;
482 gen6_gtt_pte_t *pt_vaddr;
483 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
484 pd_entry = readl(pd_addr + pde);
485 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
486
487 if (pd_entry != expected)
488 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
489 pde,
490 pd_entry,
491 expected);
492 seq_printf(m, "\tPDE: %x\n", pd_entry);
493
494 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
495 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
496 unsigned long va =
497 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
498 (pte * PAGE_SIZE);
499 int i;
500 bool found = false;
501 for (i = 0; i < 4; i++)
502 if (pt_vaddr[pte + i] != scratch_pte)
503 found = true;
504 if (!found)
505 continue;
506
507 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
508 for (i = 0; i < 4; i++) {
509 if (pt_vaddr[pte + i] != scratch_pte)
510 seq_printf(m, " %08x", pt_vaddr[pte + i]);
511 else
512 seq_puts(m, " SCRATCH ");
513 }
514 seq_puts(m, "\n");
515 }
516 kunmap_atomic(pt_vaddr);
517 }
518 }
519
520 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
521 {
522 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
523 gen6_gtt_pte_t __iomem *pd_addr;
524 uint32_t pd_entry;
525 int i;
526
527 WARN_ON(ppgtt->pd_offset & 0x3f);
528 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
529 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
530 for (i = 0; i < ppgtt->num_pd_entries; i++) {
531 dma_addr_t pt_addr;
532
533 pt_addr = ppgtt->pt_dma_addr[i];
534 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
535 pd_entry |= GEN6_PDE_VALID;
536
537 writel(pd_entry, pd_addr + i);
538 }
539 readl(pd_addr);
540 }
541
542 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
543 {
544 BUG_ON(ppgtt->pd_offset & 0x3f);
545
546 return (ppgtt->pd_offset / 64) << 16;
547 }
548
549 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
550 struct intel_ring_buffer *ring,
551 bool synchronous)
552 {
553 struct drm_device *dev = ppgtt->base.dev;
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 int ret;
556
557 /* If we're in reset, we can assume the GPU is sufficiently idle to
558 * manually frob these bits. Ideally we could use the ring functions,
559 * except our error handling makes it quite difficult (can't use
560 * intel_ring_begin, ring->flush, or intel_ring_advance)
561 *
562 * FIXME: We should try not to special case reset
563 */
564 if (synchronous ||
565 i915_reset_in_progress(&dev_priv->gpu_error)) {
566 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
567 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
568 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
569 POSTING_READ(RING_PP_DIR_BASE(ring));
570 return 0;
571 }
572
573 /* NB: TLBs must be flushed and invalidated before a switch */
574 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
575 if (ret)
576 return ret;
577
578 ret = intel_ring_begin(ring, 6);
579 if (ret)
580 return ret;
581
582 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
583 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
584 intel_ring_emit(ring, PP_DIR_DCLV_2G);
585 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
586 intel_ring_emit(ring, get_pd_offset(ppgtt));
587 intel_ring_emit(ring, MI_NOOP);
588 intel_ring_advance(ring);
589
590 return 0;
591 }
592
593 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
594 struct intel_ring_buffer *ring,
595 bool synchronous)
596 {
597 struct drm_device *dev = ppgtt->base.dev;
598 struct drm_i915_private *dev_priv = dev->dev_private;
599 int ret;
600
601 /* If we're in reset, we can assume the GPU is sufficiently idle to
602 * manually frob these bits. Ideally we could use the ring functions,
603 * except our error handling makes it quite difficult (can't use
604 * intel_ring_begin, ring->flush, or intel_ring_advance)
605 *
606 * FIXME: We should try not to special case reset
607 */
608 if (synchronous ||
609 i915_reset_in_progress(&dev_priv->gpu_error)) {
610 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
611 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
612 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
613 POSTING_READ(RING_PP_DIR_BASE(ring));
614 return 0;
615 }
616
617 /* NB: TLBs must be flushed and invalidated before a switch */
618 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
619 if (ret)
620 return ret;
621
622 ret = intel_ring_begin(ring, 6);
623 if (ret)
624 return ret;
625
626 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
627 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
628 intel_ring_emit(ring, PP_DIR_DCLV_2G);
629 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
630 intel_ring_emit(ring, get_pd_offset(ppgtt));
631 intel_ring_emit(ring, MI_NOOP);
632 intel_ring_advance(ring);
633
634 /* XXX: RCS is the only one to auto invalidate the TLBs? */
635 if (ring->id != RCS) {
636 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
637 if (ret)
638 return ret;
639 }
640
641 return 0;
642 }
643
644 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
645 struct intel_ring_buffer *ring,
646 bool synchronous)
647 {
648 struct drm_device *dev = ppgtt->base.dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650
651 if (!synchronous)
652 return 0;
653
654 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
655 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
656
657 POSTING_READ(RING_PP_DIR_DCLV(ring));
658
659 return 0;
660 }
661
662 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
663 {
664 struct drm_device *dev = ppgtt->base.dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 struct intel_ring_buffer *ring;
667 int j, ret;
668
669 for_each_ring(ring, dev_priv, j) {
670 I915_WRITE(RING_MODE_GEN7(ring),
671 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
672
673 /* We promise to do a switch later with FULL PPGTT. If this is
674 * aliasing, this is the one and only switch we'll do */
675 if (USES_FULL_PPGTT(dev))
676 continue;
677
678 ret = ppgtt->switch_mm(ppgtt, ring, true);
679 if (ret)
680 goto err_out;
681 }
682
683 return 0;
684
685 err_out:
686 for_each_ring(ring, dev_priv, j)
687 I915_WRITE(RING_MODE_GEN7(ring),
688 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
689 return ret;
690 }
691
692 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
693 {
694 struct drm_device *dev = ppgtt->base.dev;
695 drm_i915_private_t *dev_priv = dev->dev_private;
696 struct intel_ring_buffer *ring;
697 uint32_t ecochk, ecobits;
698 int i;
699
700 ecobits = I915_READ(GAC_ECO_BITS);
701 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
702
703 ecochk = I915_READ(GAM_ECOCHK);
704 if (IS_HASWELL(dev)) {
705 ecochk |= ECOCHK_PPGTT_WB_HSW;
706 } else {
707 ecochk |= ECOCHK_PPGTT_LLC_IVB;
708 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
709 }
710 I915_WRITE(GAM_ECOCHK, ecochk);
711
712 for_each_ring(ring, dev_priv, i) {
713 int ret;
714 /* GFX_MODE is per-ring on gen7+ */
715 I915_WRITE(RING_MODE_GEN7(ring),
716 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
717
718 /* We promise to do a switch later with FULL PPGTT. If this is
719 * aliasing, this is the one and only switch we'll do */
720 if (USES_FULL_PPGTT(dev))
721 continue;
722
723 ret = ppgtt->switch_mm(ppgtt, ring, true);
724 if (ret)
725 return ret;
726 }
727
728 return 0;
729 }
730
731 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
732 {
733 struct drm_device *dev = ppgtt->base.dev;
734 drm_i915_private_t *dev_priv = dev->dev_private;
735 struct intel_ring_buffer *ring;
736 uint32_t ecochk, gab_ctl, ecobits;
737 int i;
738
739 ecobits = I915_READ(GAC_ECO_BITS);
740 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
741 ECOBITS_PPGTT_CACHE64B);
742
743 gab_ctl = I915_READ(GAB_CTL);
744 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
745
746 ecochk = I915_READ(GAM_ECOCHK);
747 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
748
749 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
750
751 for_each_ring(ring, dev_priv, i) {
752 int ret = ppgtt->switch_mm(ppgtt, ring, true);
753 if (ret)
754 return ret;
755 }
756
757 return 0;
758 }
759
760 /* PPGTT support for Sandybdrige/Gen6 and later */
761 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
762 unsigned first_entry,
763 unsigned num_entries,
764 bool use_scratch)
765 {
766 struct i915_hw_ppgtt *ppgtt =
767 container_of(vm, struct i915_hw_ppgtt, base);
768 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
769 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
770 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
771 unsigned last_pte, i;
772
773 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
774
775 while (num_entries) {
776 last_pte = first_pte + num_entries;
777 if (last_pte > I915_PPGTT_PT_ENTRIES)
778 last_pte = I915_PPGTT_PT_ENTRIES;
779
780 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
781
782 for (i = first_pte; i < last_pte; i++)
783 pt_vaddr[i] = scratch_pte;
784
785 kunmap_atomic(pt_vaddr);
786
787 num_entries -= last_pte - first_pte;
788 first_pte = 0;
789 act_pt++;
790 }
791 }
792
793 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
794 struct sg_table *pages,
795 unsigned first_entry,
796 enum i915_cache_level cache_level)
797 {
798 struct i915_hw_ppgtt *ppgtt =
799 container_of(vm, struct i915_hw_ppgtt, base);
800 gen6_gtt_pte_t *pt_vaddr;
801 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
802 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
803 struct sg_page_iter sg_iter;
804
805 pt_vaddr = NULL;
806 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
807 if (pt_vaddr == NULL)
808 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
809
810 pt_vaddr[act_pte] =
811 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
812 cache_level, true);
813 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
814 kunmap_atomic(pt_vaddr);
815 pt_vaddr = NULL;
816 act_pt++;
817 act_pte = 0;
818 }
819 }
820 if (pt_vaddr)
821 kunmap_atomic(pt_vaddr);
822 }
823
824 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
825 {
826 struct i915_hw_ppgtt *ppgtt =
827 container_of(vm, struct i915_hw_ppgtt, base);
828 int i;
829
830 list_del(&vm->global_link);
831 drm_mm_takedown(&ppgtt->base.mm);
832 drm_mm_remove_node(&ppgtt->node);
833
834 if (ppgtt->pt_dma_addr) {
835 for (i = 0; i < ppgtt->num_pd_entries; i++)
836 pci_unmap_page(ppgtt->base.dev->pdev,
837 ppgtt->pt_dma_addr[i],
838 4096, PCI_DMA_BIDIRECTIONAL);
839 }
840
841 kfree(ppgtt->pt_dma_addr);
842 for (i = 0; i < ppgtt->num_pd_entries; i++)
843 __free_page(ppgtt->pt_pages[i]);
844 kfree(ppgtt->pt_pages);
845 kfree(ppgtt);
846 }
847
848 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
849 {
850 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
851 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
852 struct drm_device *dev = ppgtt->base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 bool retried = false;
855 int i, ret;
856
857 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
858 * allocator works in address space sizes, so it's multiplied by page
859 * size. We allocate at the top of the GTT to avoid fragmentation.
860 */
861 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
862 alloc:
863 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
864 &ppgtt->node, GEN6_PD_SIZE,
865 GEN6_PD_ALIGN, 0,
866 0, dev_priv->gtt.base.total,
867 DRM_MM_SEARCH_DEFAULT);
868 if (ret == -ENOSPC && !retried) {
869 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
870 GEN6_PD_SIZE, GEN6_PD_ALIGN,
871 I915_CACHE_NONE, false, true);
872 if (ret)
873 return ret;
874
875 retried = true;
876 goto alloc;
877 }
878
879 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
880 DRM_DEBUG("Forced to use aperture for PDEs\n");
881
882 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
883 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
884 if (IS_GEN6(dev)) {
885 ppgtt->enable = gen6_ppgtt_enable;
886 ppgtt->switch_mm = gen6_mm_switch;
887 } else if (IS_HASWELL(dev)) {
888 ppgtt->enable = gen7_ppgtt_enable;
889 ppgtt->switch_mm = hsw_mm_switch;
890 } else if (IS_GEN7(dev)) {
891 ppgtt->enable = gen7_ppgtt_enable;
892 ppgtt->switch_mm = gen7_mm_switch;
893 } else
894 BUG();
895 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
896 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
897 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
898 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
899 ppgtt->base.start = 0;
900 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
901 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
902 GFP_KERNEL);
903 if (!ppgtt->pt_pages) {
904 drm_mm_remove_node(&ppgtt->node);
905 return -ENOMEM;
906 }
907
908 for (i = 0; i < ppgtt->num_pd_entries; i++) {
909 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
910 if (!ppgtt->pt_pages[i])
911 goto err_pt_alloc;
912 }
913
914 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
915 GFP_KERNEL);
916 if (!ppgtt->pt_dma_addr)
917 goto err_pt_alloc;
918
919 for (i = 0; i < ppgtt->num_pd_entries; i++) {
920 dma_addr_t pt_addr;
921
922 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
923 PCI_DMA_BIDIRECTIONAL);
924
925 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
926 ret = -EIO;
927 goto err_pd_pin;
928
929 }
930 ppgtt->pt_dma_addr[i] = pt_addr;
931 }
932
933 ppgtt->base.clear_range(&ppgtt->base, 0,
934 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
935 ppgtt->debug_dump = gen6_dump_ppgtt;
936
937 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
938 ppgtt->node.size >> 20,
939 ppgtt->node.start / PAGE_SIZE);
940 ppgtt->pd_offset =
941 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
942
943 return 0;
944
945 err_pd_pin:
946 if (ppgtt->pt_dma_addr) {
947 for (i--; i >= 0; i--)
948 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
949 4096, PCI_DMA_BIDIRECTIONAL);
950 }
951 err_pt_alloc:
952 kfree(ppgtt->pt_dma_addr);
953 for (i = 0; i < ppgtt->num_pd_entries; i++) {
954 if (ppgtt->pt_pages[i])
955 __free_page(ppgtt->pt_pages[i]);
956 }
957 kfree(ppgtt->pt_pages);
958 drm_mm_remove_node(&ppgtt->node);
959
960 return ret;
961 }
962
963 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
964 {
965 struct drm_i915_private *dev_priv = dev->dev_private;
966 int ret = 0;
967
968 ppgtt->base.dev = dev;
969
970 if (INTEL_INFO(dev)->gen < 8)
971 ret = gen6_ppgtt_init(ppgtt);
972 else if (IS_GEN8(dev))
973 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
974 else
975 BUG();
976
977 if (!ret) {
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 kref_init(&ppgtt->ref);
980 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
981 ppgtt->base.total);
982 i915_init_vm(dev_priv, &ppgtt->base);
983 if (INTEL_INFO(dev)->gen < 8) {
984 gen6_write_pdes(ppgtt);
985 DRM_DEBUG("Adding PPGTT at offset %x\n",
986 ppgtt->pd_offset << 10);
987 }
988 }
989
990 return ret;
991 }
992
993 static void
994 ppgtt_bind_vma(struct i915_vma *vma,
995 enum i915_cache_level cache_level,
996 u32 flags)
997 {
998 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
999
1000 WARN_ON(flags);
1001
1002 vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
1003 }
1004
1005 static void ppgtt_unbind_vma(struct i915_vma *vma)
1006 {
1007 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1008
1009 vma->vm->clear_range(vma->vm,
1010 entry,
1011 vma->obj->base.size >> PAGE_SHIFT,
1012 true);
1013 }
1014
1015 extern int intel_iommu_gfx_mapped;
1016 /* Certain Gen5 chipsets require require idling the GPU before
1017 * unmapping anything from the GTT when VT-d is enabled.
1018 */
1019 static inline bool needs_idle_maps(struct drm_device *dev)
1020 {
1021 #ifdef CONFIG_INTEL_IOMMU
1022 /* Query intel_iommu to see if we need the workaround. Presumably that
1023 * was loaded first.
1024 */
1025 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1026 return true;
1027 #endif
1028 return false;
1029 }
1030
1031 static bool do_idling(struct drm_i915_private *dev_priv)
1032 {
1033 bool ret = dev_priv->mm.interruptible;
1034
1035 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1036 dev_priv->mm.interruptible = false;
1037 if (i915_gpu_idle(dev_priv->dev)) {
1038 DRM_ERROR("Couldn't idle GPU\n");
1039 /* Wait a bit, in hopes it avoids the hang */
1040 udelay(10);
1041 }
1042 }
1043
1044 return ret;
1045 }
1046
1047 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1048 {
1049 if (unlikely(dev_priv->gtt.do_idle_maps))
1050 dev_priv->mm.interruptible = interruptible;
1051 }
1052
1053 void i915_check_and_clear_faults(struct drm_device *dev)
1054 {
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 struct intel_ring_buffer *ring;
1057 int i;
1058
1059 if (INTEL_INFO(dev)->gen < 6)
1060 return;
1061
1062 for_each_ring(ring, dev_priv, i) {
1063 u32 fault_reg;
1064 fault_reg = I915_READ(RING_FAULT_REG(ring));
1065 if (fault_reg & RING_FAULT_VALID) {
1066 DRM_DEBUG_DRIVER("Unexpected fault\n"
1067 "\tAddr: 0x%08lx\\n"
1068 "\tAddress space: %s\n"
1069 "\tSource ID: %d\n"
1070 "\tType: %d\n",
1071 fault_reg & PAGE_MASK,
1072 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1073 RING_FAULT_SRCID(fault_reg),
1074 RING_FAULT_FAULT_TYPE(fault_reg));
1075 I915_WRITE(RING_FAULT_REG(ring),
1076 fault_reg & ~RING_FAULT_VALID);
1077 }
1078 }
1079 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1080 }
1081
1082 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1083 {
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085
1086 /* Don't bother messing with faults pre GEN6 as we have little
1087 * documentation supporting that it's a good idea.
1088 */
1089 if (INTEL_INFO(dev)->gen < 6)
1090 return;
1091
1092 i915_check_and_clear_faults(dev);
1093
1094 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1095 dev_priv->gtt.base.start / PAGE_SIZE,
1096 dev_priv->gtt.base.total / PAGE_SIZE,
1097 false);
1098 }
1099
1100 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1101 {
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 struct drm_i915_gem_object *obj;
1104 struct i915_address_space *vm;
1105
1106 i915_check_and_clear_faults(dev);
1107
1108 /* First fill our portion of the GTT with scratch pages */
1109 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1110 dev_priv->gtt.base.start / PAGE_SIZE,
1111 dev_priv->gtt.base.total / PAGE_SIZE,
1112 true);
1113
1114 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1115 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1116 &dev_priv->gtt.base);
1117 if (!vma)
1118 continue;
1119
1120 i915_gem_clflush_object(obj, obj->pin_display);
1121 /* The bind_vma code tries to be smart about tracking mappings.
1122 * Unfortunately above, we've just wiped out the mappings
1123 * without telling our object about it. So we need to fake it.
1124 */
1125 obj->has_global_gtt_mapping = 0;
1126 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1127 }
1128
1129
1130 if (INTEL_INFO(dev)->gen >= 8)
1131 return;
1132
1133 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1134 /* TODO: Perhaps it shouldn't be gen6 specific */
1135 if (i915_is_ggtt(vm)) {
1136 if (dev_priv->mm.aliasing_ppgtt)
1137 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1138 continue;
1139 }
1140
1141 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1142 }
1143
1144 i915_gem_chipset_flush(dev);
1145 }
1146
1147 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1148 {
1149 if (obj->has_dma_mapping)
1150 return 0;
1151
1152 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1153 obj->pages->sgl, obj->pages->nents,
1154 PCI_DMA_BIDIRECTIONAL))
1155 return -ENOSPC;
1156
1157 return 0;
1158 }
1159
1160 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1161 {
1162 #ifdef writeq
1163 writeq(pte, addr);
1164 #else
1165 iowrite32((u32)pte, addr);
1166 iowrite32(pte >> 32, addr + 4);
1167 #endif
1168 }
1169
1170 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1171 struct sg_table *st,
1172 unsigned int first_entry,
1173 enum i915_cache_level level)
1174 {
1175 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1176 gen8_gtt_pte_t __iomem *gtt_entries =
1177 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1178 int i = 0;
1179 struct sg_page_iter sg_iter;
1180 dma_addr_t addr;
1181
1182 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1183 addr = sg_dma_address(sg_iter.sg) +
1184 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1185 gen8_set_pte(&gtt_entries[i],
1186 gen8_pte_encode(addr, level, true));
1187 i++;
1188 }
1189
1190 /*
1191 * XXX: This serves as a posting read to make sure that the PTE has
1192 * actually been updated. There is some concern that even though
1193 * registers and PTEs are within the same BAR that they are potentially
1194 * of NUMA access patterns. Therefore, even with the way we assume
1195 * hardware should work, we must keep this posting read for paranoia.
1196 */
1197 if (i != 0)
1198 WARN_ON(readq(&gtt_entries[i-1])
1199 != gen8_pte_encode(addr, level, true));
1200
1201 /* This next bit makes the above posting read even more important. We
1202 * want to flush the TLBs only after we're certain all the PTE updates
1203 * have finished.
1204 */
1205 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1206 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1207 }
1208
1209 /*
1210 * Binds an object into the global gtt with the specified cache level. The object
1211 * will be accessible to the GPU via commands whose operands reference offsets
1212 * within the global GTT as well as accessible by the GPU through the GMADR
1213 * mapped BAR (dev_priv->mm.gtt->gtt).
1214 */
1215 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1216 struct sg_table *st,
1217 unsigned int first_entry,
1218 enum i915_cache_level level)
1219 {
1220 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1221 gen6_gtt_pte_t __iomem *gtt_entries =
1222 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1223 int i = 0;
1224 struct sg_page_iter sg_iter;
1225 dma_addr_t addr;
1226
1227 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1228 addr = sg_page_iter_dma_address(&sg_iter);
1229 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1230 i++;
1231 }
1232
1233 /* XXX: This serves as a posting read to make sure that the PTE has
1234 * actually been updated. There is some concern that even though
1235 * registers and PTEs are within the same BAR that they are potentially
1236 * of NUMA access patterns. Therefore, even with the way we assume
1237 * hardware should work, we must keep this posting read for paranoia.
1238 */
1239 if (i != 0)
1240 WARN_ON(readl(&gtt_entries[i-1]) !=
1241 vm->pte_encode(addr, level, true));
1242
1243 /* This next bit makes the above posting read even more important. We
1244 * want to flush the TLBs only after we're certain all the PTE updates
1245 * have finished.
1246 */
1247 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1248 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1249 }
1250
1251 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1252 unsigned int first_entry,
1253 unsigned int num_entries,
1254 bool use_scratch)
1255 {
1256 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1257 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1258 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1259 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1260 int i;
1261
1262 if (WARN(num_entries > max_entries,
1263 "First entry = %d; Num entries = %d (max=%d)\n",
1264 first_entry, num_entries, max_entries))
1265 num_entries = max_entries;
1266
1267 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1268 I915_CACHE_LLC,
1269 use_scratch);
1270 for (i = 0; i < num_entries; i++)
1271 gen8_set_pte(&gtt_base[i], scratch_pte);
1272 readl(gtt_base);
1273 }
1274
1275 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1276 unsigned int first_entry,
1277 unsigned int num_entries,
1278 bool use_scratch)
1279 {
1280 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1281 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1282 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1283 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1284 int i;
1285
1286 if (WARN(num_entries > max_entries,
1287 "First entry = %d; Num entries = %d (max=%d)\n",
1288 first_entry, num_entries, max_entries))
1289 num_entries = max_entries;
1290
1291 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1292
1293 for (i = 0; i < num_entries; i++)
1294 iowrite32(scratch_pte, &gtt_base[i]);
1295 readl(gtt_base);
1296 }
1297
1298
1299 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1300 enum i915_cache_level cache_level,
1301 u32 unused)
1302 {
1303 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1304 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1305 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1306
1307 BUG_ON(!i915_is_ggtt(vma->vm));
1308 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1309 vma->obj->has_global_gtt_mapping = 1;
1310 }
1311
1312 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1313 unsigned int first_entry,
1314 unsigned int num_entries,
1315 bool unused)
1316 {
1317 intel_gtt_clear_range(first_entry, num_entries);
1318 }
1319
1320 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1321 {
1322 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1323 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1324
1325 BUG_ON(!i915_is_ggtt(vma->vm));
1326 vma->obj->has_global_gtt_mapping = 0;
1327 intel_gtt_clear_range(first, size);
1328 }
1329
1330 static void ggtt_bind_vma(struct i915_vma *vma,
1331 enum i915_cache_level cache_level,
1332 u32 flags)
1333 {
1334 struct drm_device *dev = vma->vm->dev;
1335 struct drm_i915_private *dev_priv = dev->dev_private;
1336 struct drm_i915_gem_object *obj = vma->obj;
1337 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1338
1339 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1340 * or we have a global mapping already but the cacheability flags have
1341 * changed, set the global PTEs.
1342 *
1343 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1344 * instead if none of the above hold true.
1345 *
1346 * NB: A global mapping should only be needed for special regions like
1347 * "gtt mappable", SNB errata, or if specified via special execbuf
1348 * flags. At all other times, the GPU will use the aliasing PPGTT.
1349 */
1350 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1351 if (!obj->has_global_gtt_mapping ||
1352 (cache_level != obj->cache_level)) {
1353 vma->vm->insert_entries(vma->vm, obj->pages, entry,
1354 cache_level);
1355 obj->has_global_gtt_mapping = 1;
1356 }
1357 }
1358
1359 if (dev_priv->mm.aliasing_ppgtt &&
1360 (!obj->has_aliasing_ppgtt_mapping ||
1361 (cache_level != obj->cache_level))) {
1362 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1363 appgtt->base.insert_entries(&appgtt->base,
1364 vma->obj->pages, entry, cache_level);
1365 vma->obj->has_aliasing_ppgtt_mapping = 1;
1366 }
1367 }
1368
1369 static void ggtt_unbind_vma(struct i915_vma *vma)
1370 {
1371 struct drm_device *dev = vma->vm->dev;
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 struct drm_i915_gem_object *obj = vma->obj;
1374 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1375
1376 if (obj->has_global_gtt_mapping) {
1377 vma->vm->clear_range(vma->vm, entry,
1378 vma->obj->base.size >> PAGE_SHIFT,
1379 true);
1380 obj->has_global_gtt_mapping = 0;
1381 }
1382
1383 if (obj->has_aliasing_ppgtt_mapping) {
1384 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1385 appgtt->base.clear_range(&appgtt->base,
1386 entry,
1387 obj->base.size >> PAGE_SHIFT,
1388 true);
1389 obj->has_aliasing_ppgtt_mapping = 0;
1390 }
1391 }
1392
1393 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1394 {
1395 struct drm_device *dev = obj->base.dev;
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 bool interruptible;
1398
1399 interruptible = do_idling(dev_priv);
1400
1401 if (!obj->has_dma_mapping)
1402 dma_unmap_sg(&dev->pdev->dev,
1403 obj->pages->sgl, obj->pages->nents,
1404 PCI_DMA_BIDIRECTIONAL);
1405
1406 undo_idling(dev_priv, interruptible);
1407 }
1408
1409 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1410 unsigned long color,
1411 unsigned long *start,
1412 unsigned long *end)
1413 {
1414 if (node->color != color)
1415 *start += 4096;
1416
1417 if (!list_empty(&node->node_list)) {
1418 node = list_entry(node->node_list.next,
1419 struct drm_mm_node,
1420 node_list);
1421 if (node->allocated && node->color != color)
1422 *end -= 4096;
1423 }
1424 }
1425
1426 void i915_gem_setup_global_gtt(struct drm_device *dev,
1427 unsigned long start,
1428 unsigned long mappable_end,
1429 unsigned long end)
1430 {
1431 /* Let GEM Manage all of the aperture.
1432 *
1433 * However, leave one page at the end still bound to the scratch page.
1434 * There are a number of places where the hardware apparently prefetches
1435 * past the end of the object, and we've seen multiple hangs with the
1436 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1437 * aperture. One page should be enough to keep any prefetching inside
1438 * of the aperture.
1439 */
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1442 struct drm_mm_node *entry;
1443 struct drm_i915_gem_object *obj;
1444 unsigned long hole_start, hole_end;
1445
1446 BUG_ON(mappable_end > end);
1447
1448 /* Subtract the guard page ... */
1449 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1450 if (!HAS_LLC(dev))
1451 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1452
1453 /* Mark any preallocated objects as occupied */
1454 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1455 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1456 int ret;
1457 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1458 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1459
1460 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1461 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1462 if (ret)
1463 DRM_DEBUG_KMS("Reservation failed\n");
1464 obj->has_global_gtt_mapping = 1;
1465 }
1466
1467 dev_priv->gtt.base.start = start;
1468 dev_priv->gtt.base.total = end - start;
1469
1470 /* Clear any non-preallocated blocks */
1471 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1472 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1473 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1474 hole_start, hole_end);
1475 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1476 }
1477
1478 /* And finally clear the reserved guard page */
1479 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1480 }
1481
1482 void i915_gem_init_global_gtt(struct drm_device *dev)
1483 {
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 unsigned long gtt_size, mappable_size;
1486
1487 gtt_size = dev_priv->gtt.base.total;
1488 mappable_size = dev_priv->gtt.mappable_end;
1489
1490 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1491 }
1492
1493 static int setup_scratch_page(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct page *page;
1497 dma_addr_t dma_addr;
1498
1499 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1500 if (page == NULL)
1501 return -ENOMEM;
1502 get_page(page);
1503 set_pages_uc(page, 1);
1504
1505 #ifdef CONFIG_INTEL_IOMMU
1506 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1507 PCI_DMA_BIDIRECTIONAL);
1508 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1509 return -EINVAL;
1510 #else
1511 dma_addr = page_to_phys(page);
1512 #endif
1513 dev_priv->gtt.base.scratch.page = page;
1514 dev_priv->gtt.base.scratch.addr = dma_addr;
1515
1516 return 0;
1517 }
1518
1519 static void teardown_scratch_page(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 struct page *page = dev_priv->gtt.base.scratch.page;
1523
1524 set_pages_wb(page, 1);
1525 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1526 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1527 put_page(page);
1528 __free_page(page);
1529 }
1530
1531 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1532 {
1533 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1534 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1535 return snb_gmch_ctl << 20;
1536 }
1537
1538 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1539 {
1540 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1541 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1542 if (bdw_gmch_ctl)
1543 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1544 if (bdw_gmch_ctl > 4) {
1545 WARN_ON(!i915.preliminary_hw_support);
1546 return 4<<20;
1547 }
1548
1549 return bdw_gmch_ctl << 20;
1550 }
1551
1552 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1553 {
1554 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1555 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1556 return snb_gmch_ctl << 25; /* 32 MB units */
1557 }
1558
1559 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1560 {
1561 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1562 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1563 return bdw_gmch_ctl << 25; /* 32 MB units */
1564 }
1565
1566 static int ggtt_probe_common(struct drm_device *dev,
1567 size_t gtt_size)
1568 {
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 phys_addr_t gtt_phys_addr;
1571 int ret;
1572
1573 /* For Modern GENs the PTEs and register space are split in the BAR */
1574 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1575 (pci_resource_len(dev->pdev, 0) / 2);
1576
1577 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1578 if (!dev_priv->gtt.gsm) {
1579 DRM_ERROR("Failed to map the gtt page table\n");
1580 return -ENOMEM;
1581 }
1582
1583 ret = setup_scratch_page(dev);
1584 if (ret) {
1585 DRM_ERROR("Scratch setup failed\n");
1586 /* iounmap will also get called at remove, but meh */
1587 iounmap(dev_priv->gtt.gsm);
1588 }
1589
1590 return ret;
1591 }
1592
1593 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1594 * bits. When using advanced contexts each context stores its own PAT, but
1595 * writing this data shouldn't be harmful even in those cases. */
1596 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1597 {
1598 #define GEN8_PPAT_UC (0<<0)
1599 #define GEN8_PPAT_WC (1<<0)
1600 #define GEN8_PPAT_WT (2<<0)
1601 #define GEN8_PPAT_WB (3<<0)
1602 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1603 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1604 #define GEN8_PPAT_LLC (1<<2)
1605 #define GEN8_PPAT_LLCELLC (2<<2)
1606 #define GEN8_PPAT_LLCeLLC (3<<2)
1607 #define GEN8_PPAT_AGE(x) (x<<4)
1608 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1609 uint64_t pat;
1610
1611 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1612 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1613 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1614 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1615 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1616 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1617 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1618 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1619
1620 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1621 * write would work. */
1622 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1623 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1624 }
1625
1626 static int gen8_gmch_probe(struct drm_device *dev,
1627 size_t *gtt_total,
1628 size_t *stolen,
1629 phys_addr_t *mappable_base,
1630 unsigned long *mappable_end)
1631 {
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633 unsigned int gtt_size;
1634 u16 snb_gmch_ctl;
1635 int ret;
1636
1637 /* TODO: We're not aware of mappable constraints on gen8 yet */
1638 *mappable_base = pci_resource_start(dev->pdev, 2);
1639 *mappable_end = pci_resource_len(dev->pdev, 2);
1640
1641 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1642 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1643
1644 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1645
1646 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1647
1648 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1649 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1650
1651 gen8_setup_private_ppat(dev_priv);
1652
1653 ret = ggtt_probe_common(dev, gtt_size);
1654
1655 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1656 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1657
1658 return ret;
1659 }
1660
1661 static int gen6_gmch_probe(struct drm_device *dev,
1662 size_t *gtt_total,
1663 size_t *stolen,
1664 phys_addr_t *mappable_base,
1665 unsigned long *mappable_end)
1666 {
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1668 unsigned int gtt_size;
1669 u16 snb_gmch_ctl;
1670 int ret;
1671
1672 *mappable_base = pci_resource_start(dev->pdev, 2);
1673 *mappable_end = pci_resource_len(dev->pdev, 2);
1674
1675 /* 64/512MB is the current min/max we actually know of, but this is just
1676 * a coarse sanity check.
1677 */
1678 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1679 DRM_ERROR("Unknown GMADR size (%lx)\n",
1680 dev_priv->gtt.mappable_end);
1681 return -ENXIO;
1682 }
1683
1684 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1685 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1686 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1687
1688 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1689
1690 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1691 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1692
1693 ret = ggtt_probe_common(dev, gtt_size);
1694
1695 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1696 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1697
1698 return ret;
1699 }
1700
1701 static void gen6_gmch_remove(struct i915_address_space *vm)
1702 {
1703
1704 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1705
1706 drm_mm_takedown(&vm->mm);
1707 iounmap(gtt->gsm);
1708 teardown_scratch_page(vm->dev);
1709 }
1710
1711 static int i915_gmch_probe(struct drm_device *dev,
1712 size_t *gtt_total,
1713 size_t *stolen,
1714 phys_addr_t *mappable_base,
1715 unsigned long *mappable_end)
1716 {
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 int ret;
1719
1720 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1721 if (!ret) {
1722 DRM_ERROR("failed to set up gmch\n");
1723 return -EIO;
1724 }
1725
1726 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1727
1728 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1729 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1730
1731 if (unlikely(dev_priv->gtt.do_idle_maps))
1732 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
1733
1734 return 0;
1735 }
1736
1737 static void i915_gmch_remove(struct i915_address_space *vm)
1738 {
1739 intel_gmch_remove();
1740 }
1741
1742 int i915_gem_gtt_init(struct drm_device *dev)
1743 {
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct i915_gtt *gtt = &dev_priv->gtt;
1746 int ret;
1747
1748 if (INTEL_INFO(dev)->gen <= 5) {
1749 gtt->gtt_probe = i915_gmch_probe;
1750 gtt->base.cleanup = i915_gmch_remove;
1751 } else if (INTEL_INFO(dev)->gen < 8) {
1752 gtt->gtt_probe = gen6_gmch_probe;
1753 gtt->base.cleanup = gen6_gmch_remove;
1754 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1755 gtt->base.pte_encode = iris_pte_encode;
1756 else if (IS_HASWELL(dev))
1757 gtt->base.pte_encode = hsw_pte_encode;
1758 else if (IS_VALLEYVIEW(dev))
1759 gtt->base.pte_encode = byt_pte_encode;
1760 else if (INTEL_INFO(dev)->gen >= 7)
1761 gtt->base.pte_encode = ivb_pte_encode;
1762 else
1763 gtt->base.pte_encode = snb_pte_encode;
1764 } else {
1765 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1766 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1767 }
1768
1769 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1770 &gtt->mappable_base, &gtt->mappable_end);
1771 if (ret)
1772 return ret;
1773
1774 gtt->base.dev = dev;
1775
1776 /* GMADR is the PCI mmio aperture into the global GTT. */
1777 DRM_INFO("Memory usable by graphics device = %zdM\n",
1778 gtt->base.total >> 20);
1779 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1780 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1781
1782 return 0;
1783 }
1784
1785 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1786 struct i915_address_space *vm)
1787 {
1788 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1789 if (vma == NULL)
1790 return ERR_PTR(-ENOMEM);
1791
1792 INIT_LIST_HEAD(&vma->vma_link);
1793 INIT_LIST_HEAD(&vma->mm_list);
1794 INIT_LIST_HEAD(&vma->exec_list);
1795 vma->vm = vm;
1796 vma->obj = obj;
1797
1798 switch (INTEL_INFO(vm->dev)->gen) {
1799 case 8:
1800 case 7:
1801 case 6:
1802 if (i915_is_ggtt(vm)) {
1803 vma->unbind_vma = ggtt_unbind_vma;
1804 vma->bind_vma = ggtt_bind_vma;
1805 } else {
1806 vma->unbind_vma = ppgtt_unbind_vma;
1807 vma->bind_vma = ppgtt_bind_vma;
1808 }
1809 break;
1810 case 5:
1811 case 4:
1812 case 3:
1813 case 2:
1814 BUG_ON(!i915_is_ggtt(vm));
1815 vma->unbind_vma = i915_ggtt_unbind_vma;
1816 vma->bind_vma = i915_ggtt_bind_vma;
1817 break;
1818 default:
1819 BUG();
1820 }
1821
1822 /* Keep GGTT vmas first to make debug easier */
1823 if (i915_is_ggtt(vm))
1824 list_add(&vma->vma_link, &obj->vma_list);
1825 else
1826 list_add_tail(&vma->vma_link, &obj->vma_list);
1827
1828 return vma;
1829 }
1830
1831 struct i915_vma *
1832 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1833 struct i915_address_space *vm)
1834 {
1835 struct i915_vma *vma;
1836
1837 vma = i915_gem_obj_to_vma(obj, vm);
1838 if (!vma)
1839 vma = __i915_gem_vma_create(obj, vm);
1840
1841 return vma;
1842 }
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