2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
36 * DOC: Global GTT views
38 * Background and previous state
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
65 * Implementation and usage
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
70 * A new flavour of core GEM functions which work with GGTT bound objects were
71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
80 * Code wanting to add or use a new GGTT view needs to:
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
96 static inline struct i915_ggtt
*
97 i915_vm_to_ggtt(struct i915_address_space
*vm
)
99 GEM_BUG_ON(!i915_is_ggtt(vm
));
100 return container_of(vm
, struct i915_ggtt
, base
);
104 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
106 const struct i915_ggtt_view i915_ggtt_view_normal
= {
107 .type
= I915_GGTT_VIEW_NORMAL
,
109 const struct i915_ggtt_view i915_ggtt_view_rotated
= {
110 .type
= I915_GGTT_VIEW_ROTATED
,
113 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
116 bool has_aliasing_ppgtt
;
118 bool has_full_48bit_ppgtt
;
120 has_aliasing_ppgtt
= INTEL_GEN(dev_priv
) >= 6;
121 has_full_ppgtt
= INTEL_GEN(dev_priv
) >= 7;
122 has_full_48bit_ppgtt
=
123 IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9;
125 if (intel_vgpu_active(dev_priv
))
126 has_full_ppgtt
= false; /* emulation is too hard */
128 if (!has_aliasing_ppgtt
)
132 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
133 * execlists, the sole mechanism available to submit work.
135 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
138 if (enable_ppgtt
== 1)
141 if (enable_ppgtt
== 2 && has_full_ppgtt
)
144 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
147 #ifdef CONFIG_INTEL_IOMMU
148 /* Disable ppgtt on SNB if VT-d is on. */
149 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
) {
150 DRM_INFO("Disabling PPGTT because VT-d is on\n");
155 /* Early VLV doesn't have this */
156 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
157 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
161 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
)
162 return has_full_48bit_ppgtt
? 3 : 2;
164 return has_aliasing_ppgtt
? 1 : 0;
167 static int ppgtt_bind_vma(struct i915_vma
*vma
,
168 enum i915_cache_level cache_level
,
173 vma
->pages
= vma
->obj
->pages
;
175 /* Currently applicable only to VLV */
177 pte_flags
|= PTE_READ_ONLY
;
179 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
180 cache_level
, pte_flags
);
185 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
187 vma
->vm
->clear_range(vma
->vm
,
193 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
194 enum i915_cache_level level
,
197 gen8_pte_t pte
= valid
? _PAGE_PRESENT
| _PAGE_RW
: 0;
201 case I915_CACHE_NONE
:
202 pte
|= PPAT_UNCACHED_INDEX
;
205 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
208 pte
|= PPAT_CACHED_INDEX
;
215 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
216 const enum i915_cache_level level
)
218 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
220 if (level
!= I915_CACHE_NONE
)
221 pde
|= PPAT_CACHED_PDE_INDEX
;
223 pde
|= PPAT_UNCACHED_INDEX
;
227 #define gen8_pdpe_encode gen8_pde_encode
228 #define gen8_pml4e_encode gen8_pde_encode
230 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
231 enum i915_cache_level level
,
232 bool valid
, u32 unused
)
234 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
235 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
238 case I915_CACHE_L3_LLC
:
240 pte
|= GEN6_PTE_CACHE_LLC
;
242 case I915_CACHE_NONE
:
243 pte
|= GEN6_PTE_UNCACHED
;
252 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
253 enum i915_cache_level level
,
254 bool valid
, u32 unused
)
256 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
257 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
260 case I915_CACHE_L3_LLC
:
261 pte
|= GEN7_PTE_CACHE_L3_LLC
;
264 pte
|= GEN6_PTE_CACHE_LLC
;
266 case I915_CACHE_NONE
:
267 pte
|= GEN6_PTE_UNCACHED
;
276 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
277 enum i915_cache_level level
,
278 bool valid
, u32 flags
)
280 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
281 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
283 if (!(flags
& PTE_READ_ONLY
))
284 pte
|= BYT_PTE_WRITEABLE
;
286 if (level
!= I915_CACHE_NONE
)
287 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
292 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
293 enum i915_cache_level level
,
294 bool valid
, u32 unused
)
296 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
297 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
299 if (level
!= I915_CACHE_NONE
)
300 pte
|= HSW_WB_LLC_AGE3
;
305 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
306 enum i915_cache_level level
,
307 bool valid
, u32 unused
)
309 gen6_pte_t pte
= valid
? GEN6_PTE_VALID
: 0;
310 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
313 case I915_CACHE_NONE
:
316 pte
|= HSW_WT_ELLC_LLC_AGE3
;
319 pte
|= HSW_WB_ELLC_LLC_AGE3
;
326 static int __setup_page_dma(struct drm_device
*dev
,
327 struct i915_page_dma
*p
, gfp_t flags
)
329 struct device
*device
= &dev
->pdev
->dev
;
331 p
->page
= alloc_page(flags
);
335 p
->daddr
= dma_map_page(device
,
336 p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
338 if (dma_mapping_error(device
, p
->daddr
)) {
339 __free_page(p
->page
);
346 static int setup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
348 return __setup_page_dma(dev
, p
, GFP_KERNEL
);
351 static void cleanup_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
)
353 if (WARN_ON(!p
->page
))
356 dma_unmap_page(&dev
->pdev
->dev
, p
->daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
357 __free_page(p
->page
);
358 memset(p
, 0, sizeof(*p
));
361 static void *kmap_page_dma(struct i915_page_dma
*p
)
363 return kmap_atomic(p
->page
);
366 /* We use the flushing unmap only with ppgtt structures:
367 * page directories, page tables and scratch pages.
369 static void kunmap_page_dma(struct drm_device
*dev
, void *vaddr
)
371 /* There are only few exceptions for gen >=6. chv and bxt.
372 * And we are not sure about the latter so play safe for now.
374 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
375 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
377 kunmap_atomic(vaddr
);
380 #define kmap_px(px) kmap_page_dma(px_base(px))
381 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
383 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
384 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
385 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
386 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
388 static void fill_page_dma(struct drm_device
*dev
, struct i915_page_dma
*p
,
392 uint64_t * const vaddr
= kmap_page_dma(p
);
394 for (i
= 0; i
< 512; i
++)
397 kunmap_page_dma(dev
, vaddr
);
400 static void fill_page_dma_32(struct drm_device
*dev
, struct i915_page_dma
*p
,
401 const uint32_t val32
)
407 fill_page_dma(dev
, p
, v
);
410 static struct i915_page_scratch
*alloc_scratch_page(struct drm_device
*dev
)
412 struct i915_page_scratch
*sp
;
415 sp
= kzalloc(sizeof(*sp
), GFP_KERNEL
);
417 return ERR_PTR(-ENOMEM
);
419 ret
= __setup_page_dma(dev
, px_base(sp
), GFP_DMA32
| __GFP_ZERO
);
425 set_pages_uc(px_page(sp
), 1);
430 static void free_scratch_page(struct drm_device
*dev
,
431 struct i915_page_scratch
*sp
)
433 set_pages_wb(px_page(sp
), 1);
439 static struct i915_page_table
*alloc_pt(struct drm_device
*dev
)
441 struct i915_page_table
*pt
;
442 const size_t count
= INTEL_INFO(dev
)->gen
>= 8 ?
443 GEN8_PTES
: GEN6_PTES
;
446 pt
= kzalloc(sizeof(*pt
), GFP_KERNEL
);
448 return ERR_PTR(-ENOMEM
);
450 pt
->used_ptes
= kcalloc(BITS_TO_LONGS(count
), sizeof(*pt
->used_ptes
),
456 ret
= setup_px(dev
, pt
);
463 kfree(pt
->used_ptes
);
470 static void free_pt(struct drm_device
*dev
, struct i915_page_table
*pt
)
473 kfree(pt
->used_ptes
);
477 static void gen8_initialize_pt(struct i915_address_space
*vm
,
478 struct i915_page_table
*pt
)
480 gen8_pte_t scratch_pte
;
482 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
483 I915_CACHE_LLC
, true);
485 fill_px(vm
->dev
, pt
, scratch_pte
);
488 static void gen6_initialize_pt(struct i915_address_space
*vm
,
489 struct i915_page_table
*pt
)
491 gen6_pte_t scratch_pte
;
493 WARN_ON(px_dma(vm
->scratch_page
) == 0);
495 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
496 I915_CACHE_LLC
, true, 0);
498 fill32_px(vm
->dev
, pt
, scratch_pte
);
501 static struct i915_page_directory
*alloc_pd(struct drm_device
*dev
)
503 struct i915_page_directory
*pd
;
506 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
508 return ERR_PTR(-ENOMEM
);
510 pd
->used_pdes
= kcalloc(BITS_TO_LONGS(I915_PDES
),
511 sizeof(*pd
->used_pdes
), GFP_KERNEL
);
515 ret
= setup_px(dev
, pd
);
522 kfree(pd
->used_pdes
);
529 static void free_pd(struct drm_device
*dev
, struct i915_page_directory
*pd
)
533 kfree(pd
->used_pdes
);
538 static void gen8_initialize_pd(struct i915_address_space
*vm
,
539 struct i915_page_directory
*pd
)
541 gen8_pde_t scratch_pde
;
543 scratch_pde
= gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
);
545 fill_px(vm
->dev
, pd
, scratch_pde
);
548 static int __pdp_init(struct drm_device
*dev
,
549 struct i915_page_directory_pointer
*pdp
)
551 size_t pdpes
= I915_PDPES_PER_PDP(dev
);
553 pdp
->used_pdpes
= kcalloc(BITS_TO_LONGS(pdpes
),
554 sizeof(unsigned long),
556 if (!pdp
->used_pdpes
)
559 pdp
->page_directory
= kcalloc(pdpes
, sizeof(*pdp
->page_directory
),
561 if (!pdp
->page_directory
) {
562 kfree(pdp
->used_pdpes
);
563 /* the PDP might be the statically allocated top level. Keep it
564 * as clean as possible */
565 pdp
->used_pdpes
= NULL
;
572 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
574 kfree(pdp
->used_pdpes
);
575 kfree(pdp
->page_directory
);
576 pdp
->page_directory
= NULL
;
580 i915_page_directory_pointer
*alloc_pdp(struct drm_device
*dev
)
582 struct i915_page_directory_pointer
*pdp
;
585 WARN_ON(!USES_FULL_48BIT_PPGTT(dev
));
587 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
589 return ERR_PTR(-ENOMEM
);
591 ret
= __pdp_init(dev
, pdp
);
595 ret
= setup_px(dev
, pdp
);
609 static void free_pdp(struct drm_device
*dev
,
610 struct i915_page_directory_pointer
*pdp
)
613 if (USES_FULL_48BIT_PPGTT(dev
)) {
614 cleanup_px(dev
, pdp
);
619 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
620 struct i915_page_directory_pointer
*pdp
)
622 gen8_ppgtt_pdpe_t scratch_pdpe
;
624 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
626 fill_px(vm
->dev
, pdp
, scratch_pdpe
);
629 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
630 struct i915_pml4
*pml4
)
632 gen8_ppgtt_pml4e_t scratch_pml4e
;
634 scratch_pml4e
= gen8_pml4e_encode(px_dma(vm
->scratch_pdp
),
637 fill_px(vm
->dev
, pml4
, scratch_pml4e
);
641 gen8_setup_page_directory(struct i915_hw_ppgtt
*ppgtt
,
642 struct i915_page_directory_pointer
*pdp
,
643 struct i915_page_directory
*pd
,
646 gen8_ppgtt_pdpe_t
*page_directorypo
;
648 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
651 page_directorypo
= kmap_px(pdp
);
652 page_directorypo
[index
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
653 kunmap_px(ppgtt
, page_directorypo
);
657 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt
*ppgtt
,
658 struct i915_pml4
*pml4
,
659 struct i915_page_directory_pointer
*pdp
,
662 gen8_ppgtt_pml4e_t
*pagemap
= kmap_px(pml4
);
664 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
));
665 pagemap
[index
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
666 kunmap_px(ppgtt
, pagemap
);
669 /* Broadwell Page Directory Pointer Descriptors */
670 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
674 struct intel_ring
*ring
= req
->ring
;
675 struct intel_engine_cs
*engine
= req
->engine
;
680 ret
= intel_ring_begin(req
, 6);
684 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
685 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(engine
, entry
));
686 intel_ring_emit(ring
, upper_32_bits(addr
));
687 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
688 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(engine
, entry
));
689 intel_ring_emit(ring
, lower_32_bits(addr
));
690 intel_ring_advance(ring
);
695 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
696 struct drm_i915_gem_request
*req
)
700 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
701 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
703 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
711 static int gen8_48b_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
712 struct drm_i915_gem_request
*req
)
714 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
717 static void gen8_ppgtt_clear_pte_range(struct i915_address_space
*vm
,
718 struct i915_page_directory_pointer
*pdp
,
721 gen8_pte_t scratch_pte
)
723 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
724 gen8_pte_t
*pt_vaddr
;
725 unsigned pdpe
= gen8_pdpe_index(start
);
726 unsigned pde
= gen8_pde_index(start
);
727 unsigned pte
= gen8_pte_index(start
);
728 unsigned num_entries
= length
>> PAGE_SHIFT
;
729 unsigned last_pte
, i
;
734 while (num_entries
) {
735 struct i915_page_directory
*pd
;
736 struct i915_page_table
*pt
;
738 if (WARN_ON(!pdp
->page_directory
[pdpe
]))
741 pd
= pdp
->page_directory
[pdpe
];
743 if (WARN_ON(!pd
->page_table
[pde
]))
746 pt
= pd
->page_table
[pde
];
748 if (WARN_ON(!px_page(pt
)))
751 last_pte
= pte
+ num_entries
;
752 if (last_pte
> GEN8_PTES
)
753 last_pte
= GEN8_PTES
;
755 pt_vaddr
= kmap_px(pt
);
757 for (i
= pte
; i
< last_pte
; i
++) {
758 pt_vaddr
[i
] = scratch_pte
;
762 kunmap_px(ppgtt
, pt_vaddr
);
765 if (++pde
== I915_PDES
) {
766 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
773 static void gen8_ppgtt_clear_range(struct i915_address_space
*vm
,
778 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
779 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
780 I915_CACHE_LLC
, use_scratch
);
782 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
783 gen8_ppgtt_clear_pte_range(vm
, &ppgtt
->pdp
, start
, length
,
787 struct i915_page_directory_pointer
*pdp
;
789 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
790 gen8_ppgtt_clear_pte_range(vm
, pdp
, start
, length
,
797 gen8_ppgtt_insert_pte_entries(struct i915_address_space
*vm
,
798 struct i915_page_directory_pointer
*pdp
,
799 struct sg_page_iter
*sg_iter
,
801 enum i915_cache_level cache_level
)
803 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
804 gen8_pte_t
*pt_vaddr
;
805 unsigned pdpe
= gen8_pdpe_index(start
);
806 unsigned pde
= gen8_pde_index(start
);
807 unsigned pte
= gen8_pte_index(start
);
811 while (__sg_page_iter_next(sg_iter
)) {
812 if (pt_vaddr
== NULL
) {
813 struct i915_page_directory
*pd
= pdp
->page_directory
[pdpe
];
814 struct i915_page_table
*pt
= pd
->page_table
[pde
];
815 pt_vaddr
= kmap_px(pt
);
819 gen8_pte_encode(sg_page_iter_dma_address(sg_iter
),
821 if (++pte
== GEN8_PTES
) {
822 kunmap_px(ppgtt
, pt_vaddr
);
824 if (++pde
== I915_PDES
) {
825 if (++pdpe
== I915_PDPES_PER_PDP(vm
->dev
))
834 kunmap_px(ppgtt
, pt_vaddr
);
837 static void gen8_ppgtt_insert_entries(struct i915_address_space
*vm
,
838 struct sg_table
*pages
,
840 enum i915_cache_level cache_level
,
843 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
844 struct sg_page_iter sg_iter
;
846 __sg_page_iter_start(&sg_iter
, pages
->sgl
, sg_nents(pages
->sgl
), 0);
848 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
849 gen8_ppgtt_insert_pte_entries(vm
, &ppgtt
->pdp
, &sg_iter
, start
,
852 struct i915_page_directory_pointer
*pdp
;
854 uint64_t length
= (uint64_t)pages
->orig_nents
<< PAGE_SHIFT
;
856 gen8_for_each_pml4e(pdp
, &ppgtt
->pml4
, start
, length
, pml4e
) {
857 gen8_ppgtt_insert_pte_entries(vm
, pdp
, &sg_iter
,
863 static void gen8_free_page_tables(struct drm_device
*dev
,
864 struct i915_page_directory
*pd
)
871 for_each_set_bit(i
, pd
->used_pdes
, I915_PDES
) {
872 if (WARN_ON(!pd
->page_table
[i
]))
875 free_pt(dev
, pd
->page_table
[i
]);
876 pd
->page_table
[i
] = NULL
;
880 static int gen8_init_scratch(struct i915_address_space
*vm
)
882 struct drm_device
*dev
= vm
->dev
;
885 vm
->scratch_page
= alloc_scratch_page(dev
);
886 if (IS_ERR(vm
->scratch_page
))
887 return PTR_ERR(vm
->scratch_page
);
889 vm
->scratch_pt
= alloc_pt(dev
);
890 if (IS_ERR(vm
->scratch_pt
)) {
891 ret
= PTR_ERR(vm
->scratch_pt
);
892 goto free_scratch_page
;
895 vm
->scratch_pd
= alloc_pd(dev
);
896 if (IS_ERR(vm
->scratch_pd
)) {
897 ret
= PTR_ERR(vm
->scratch_pd
);
901 if (USES_FULL_48BIT_PPGTT(dev
)) {
902 vm
->scratch_pdp
= alloc_pdp(dev
);
903 if (IS_ERR(vm
->scratch_pdp
)) {
904 ret
= PTR_ERR(vm
->scratch_pdp
);
909 gen8_initialize_pt(vm
, vm
->scratch_pt
);
910 gen8_initialize_pd(vm
, vm
->scratch_pd
);
911 if (USES_FULL_48BIT_PPGTT(dev
))
912 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
917 free_pd(dev
, vm
->scratch_pd
);
919 free_pt(dev
, vm
->scratch_pt
);
921 free_scratch_page(dev
, vm
->scratch_page
);
926 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
928 enum vgt_g2v_type msg
;
929 struct drm_i915_private
*dev_priv
= to_i915(ppgtt
->base
.dev
);
932 if (USES_FULL_48BIT_PPGTT(dev_priv
)) {
933 u64 daddr
= px_dma(&ppgtt
->pml4
);
935 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
936 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
938 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
939 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
941 for (i
= 0; i
< GEN8_LEGACY_PDPES
; i
++) {
942 u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
944 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
945 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
948 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
949 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
952 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
957 static void gen8_free_scratch(struct i915_address_space
*vm
)
959 struct drm_device
*dev
= vm
->dev
;
961 if (USES_FULL_48BIT_PPGTT(dev
))
962 free_pdp(dev
, vm
->scratch_pdp
);
963 free_pd(dev
, vm
->scratch_pd
);
964 free_pt(dev
, vm
->scratch_pt
);
965 free_scratch_page(dev
, vm
->scratch_page
);
968 static void gen8_ppgtt_cleanup_3lvl(struct drm_device
*dev
,
969 struct i915_page_directory_pointer
*pdp
)
973 for_each_set_bit(i
, pdp
->used_pdpes
, I915_PDPES_PER_PDP(dev
)) {
974 if (WARN_ON(!pdp
->page_directory
[i
]))
977 gen8_free_page_tables(dev
, pdp
->page_directory
[i
]);
978 free_pd(dev
, pdp
->page_directory
[i
]);
984 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
988 for_each_set_bit(i
, ppgtt
->pml4
.used_pml4es
, GEN8_PML4ES_PER_PML4
) {
989 if (WARN_ON(!ppgtt
->pml4
.pdps
[i
]))
992 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, ppgtt
->pml4
.pdps
[i
]);
995 cleanup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
998 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
1000 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1002 if (intel_vgpu_active(to_i915(vm
->dev
)))
1003 gen8_ppgtt_notify_vgt(ppgtt
, false);
1005 if (!USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
1006 gen8_ppgtt_cleanup_3lvl(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1008 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1010 gen8_free_scratch(vm
);
1014 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1015 * @vm: Master vm structure.
1016 * @pd: Page directory for this address range.
1017 * @start: Starting virtual address to begin allocations.
1018 * @length: Size of the allocations.
1019 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1020 * caller to free on error.
1022 * Allocate the required number of page tables. Extremely similar to
1023 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1024 * the page directory boundary (instead of the page directory pointer). That
1025 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1026 * possible, and likely that the caller will need to use multiple calls of this
1027 * function to achieve the appropriate allocation.
1029 * Return: 0 if success; negative error code otherwise.
1031 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space
*vm
,
1032 struct i915_page_directory
*pd
,
1035 unsigned long *new_pts
)
1037 struct drm_device
*dev
= vm
->dev
;
1038 struct i915_page_table
*pt
;
1041 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1042 /* Don't reallocate page tables */
1043 if (test_bit(pde
, pd
->used_pdes
)) {
1044 /* Scratch is never allocated this way */
1045 WARN_ON(pt
== vm
->scratch_pt
);
1053 gen8_initialize_pt(vm
, pt
);
1054 pd
->page_table
[pde
] = pt
;
1055 __set_bit(pde
, new_pts
);
1056 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN8_PDE_SHIFT
);
1062 for_each_set_bit(pde
, new_pts
, I915_PDES
)
1063 free_pt(dev
, pd
->page_table
[pde
]);
1069 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1070 * @vm: Master vm structure.
1071 * @pdp: Page directory pointer for this address range.
1072 * @start: Starting virtual address to begin allocations.
1073 * @length: Size of the allocations.
1074 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1075 * caller to free on error.
1077 * Allocate the required number of page directories starting at the pde index of
1078 * @start, and ending at the pde index @start + @length. This function will skip
1079 * over already allocated page directories within the range, and only allocate
1080 * new ones, setting the appropriate pointer within the pdp as well as the
1081 * correct position in the bitmap @new_pds.
1083 * The function will only allocate the pages within the range for a give page
1084 * directory pointer. In other words, if @start + @length straddles a virtually
1085 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1086 * required by the caller, This is not currently possible, and the BUG in the
1087 * code will prevent it.
1089 * Return: 0 if success; negative error code otherwise.
1092 gen8_ppgtt_alloc_page_directories(struct i915_address_space
*vm
,
1093 struct i915_page_directory_pointer
*pdp
,
1096 unsigned long *new_pds
)
1098 struct drm_device
*dev
= vm
->dev
;
1099 struct i915_page_directory
*pd
;
1101 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1103 WARN_ON(!bitmap_empty(new_pds
, pdpes
));
1105 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1106 if (test_bit(pdpe
, pdp
->used_pdpes
))
1113 gen8_initialize_pd(vm
, pd
);
1114 pdp
->page_directory
[pdpe
] = pd
;
1115 __set_bit(pdpe
, new_pds
);
1116 trace_i915_page_directory_entry_alloc(vm
, pdpe
, start
, GEN8_PDPE_SHIFT
);
1122 for_each_set_bit(pdpe
, new_pds
, pdpes
)
1123 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1129 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1130 * @vm: Master vm structure.
1131 * @pml4: Page map level 4 for this address range.
1132 * @start: Starting virtual address to begin allocations.
1133 * @length: Size of the allocations.
1134 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1135 * caller to free on error.
1137 * Allocate the required number of page directory pointers. Extremely similar to
1138 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1139 * The main difference is here we are limited by the pml4 boundary (instead of
1140 * the page directory pointer).
1142 * Return: 0 if success; negative error code otherwise.
1145 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space
*vm
,
1146 struct i915_pml4
*pml4
,
1149 unsigned long *new_pdps
)
1151 struct drm_device
*dev
= vm
->dev
;
1152 struct i915_page_directory_pointer
*pdp
;
1155 WARN_ON(!bitmap_empty(new_pdps
, GEN8_PML4ES_PER_PML4
));
1157 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1158 if (!test_bit(pml4e
, pml4
->used_pml4es
)) {
1159 pdp
= alloc_pdp(dev
);
1163 gen8_initialize_pdp(vm
, pdp
);
1164 pml4
->pdps
[pml4e
] = pdp
;
1165 __set_bit(pml4e
, new_pdps
);
1166 trace_i915_page_directory_pointer_entry_alloc(vm
,
1176 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1177 free_pdp(dev
, pml4
->pdps
[pml4e
]);
1183 free_gen8_temp_bitmaps(unsigned long *new_pds
, unsigned long *new_pts
)
1189 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1190 * of these are based on the number of PDPEs in the system.
1193 int __must_check
alloc_gen8_temp_bitmaps(unsigned long **new_pds
,
1194 unsigned long **new_pts
,
1200 pds
= kcalloc(BITS_TO_LONGS(pdpes
), sizeof(unsigned long), GFP_TEMPORARY
);
1204 pts
= kcalloc(pdpes
, BITS_TO_LONGS(I915_PDES
) * sizeof(unsigned long),
1215 free_gen8_temp_bitmaps(pds
, pts
);
1219 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1220 * the page table structures, we mark them dirty so that
1221 * context switching/execlist queuing code takes extra steps
1222 * to ensure that tlbs are flushed.
1224 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
1226 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.dev
)->ring_mask
;
1229 static int gen8_alloc_va_range_3lvl(struct i915_address_space
*vm
,
1230 struct i915_page_directory_pointer
*pdp
,
1234 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1235 unsigned long *new_page_dirs
, *new_page_tables
;
1236 struct drm_device
*dev
= vm
->dev
;
1237 struct i915_page_directory
*pd
;
1238 const uint64_t orig_start
= start
;
1239 const uint64_t orig_length
= length
;
1241 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1244 /* Wrap is never okay since we can only represent 48b, and we don't
1245 * actually use the other side of the canonical address space.
1247 if (WARN_ON(start
+ length
< start
))
1250 if (WARN_ON(start
+ length
> vm
->total
))
1253 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1257 /* Do the allocations first so we can easily bail out */
1258 ret
= gen8_ppgtt_alloc_page_directories(vm
, pdp
, start
, length
,
1261 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1265 /* For every page directory referenced, allocate page tables */
1266 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1267 ret
= gen8_ppgtt_alloc_pagetabs(vm
, pd
, start
, length
,
1268 new_page_tables
+ pdpe
* BITS_TO_LONGS(I915_PDES
));
1274 length
= orig_length
;
1276 /* Allocations have completed successfully, so set the bitmaps, and do
1278 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1279 gen8_pde_t
*const page_directory
= kmap_px(pd
);
1280 struct i915_page_table
*pt
;
1281 uint64_t pd_len
= length
;
1282 uint64_t pd_start
= start
;
1285 /* Every pd should be allocated, we just did that above. */
1288 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1289 /* Same reasoning as pd */
1292 WARN_ON(!gen8_pte_count(pd_start
, pd_len
));
1294 /* Set our used ptes within the page table */
1295 bitmap_set(pt
->used_ptes
,
1296 gen8_pte_index(pd_start
),
1297 gen8_pte_count(pd_start
, pd_len
));
1299 /* Our pde is now pointing to the pagetable, pt */
1300 __set_bit(pde
, pd
->used_pdes
);
1302 /* Map the PDE to the page table */
1303 page_directory
[pde
] = gen8_pde_encode(px_dma(pt
),
1305 trace_i915_page_table_entry_map(&ppgtt
->base
, pde
, pt
,
1306 gen8_pte_index(start
),
1307 gen8_pte_count(start
, length
),
1310 /* NB: We haven't yet mapped ptes to pages. At this
1311 * point we're still relying on insert_entries() */
1314 kunmap_px(ppgtt
, page_directory
);
1315 __set_bit(pdpe
, pdp
->used_pdpes
);
1316 gen8_setup_page_directory(ppgtt
, pdp
, pd
, pdpe
);
1319 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1320 mark_tlbs_dirty(ppgtt
);
1327 for_each_set_bit(temp
, new_page_tables
+ pdpe
*
1328 BITS_TO_LONGS(I915_PDES
), I915_PDES
)
1329 free_pt(dev
, pdp
->page_directory
[pdpe
]->page_table
[temp
]);
1332 for_each_set_bit(pdpe
, new_page_dirs
, pdpes
)
1333 free_pd(dev
, pdp
->page_directory
[pdpe
]);
1335 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1336 mark_tlbs_dirty(ppgtt
);
1340 static int gen8_alloc_va_range_4lvl(struct i915_address_space
*vm
,
1341 struct i915_pml4
*pml4
,
1345 DECLARE_BITMAP(new_pdps
, GEN8_PML4ES_PER_PML4
);
1346 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1347 struct i915_page_directory_pointer
*pdp
;
1351 /* Do the pml4 allocations first, so we don't need to track the newly
1352 * allocated tables below the pdp */
1353 bitmap_zero(new_pdps
, GEN8_PML4ES_PER_PML4
);
1355 /* The pagedirectory and pagetable allocations are done in the shared 3
1356 * and 4 level code. Just allocate the pdps.
1358 ret
= gen8_ppgtt_alloc_page_dirpointers(vm
, pml4
, start
, length
,
1363 WARN(bitmap_weight(new_pdps
, GEN8_PML4ES_PER_PML4
) > 2,
1364 "The allocation has spanned more than 512GB. "
1365 "It is highly likely this is incorrect.");
1367 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1370 ret
= gen8_alloc_va_range_3lvl(vm
, pdp
, start
, length
);
1374 gen8_setup_page_directory_pointer(ppgtt
, pml4
, pdp
, pml4e
);
1377 bitmap_or(pml4
->used_pml4es
, new_pdps
, pml4
->used_pml4es
,
1378 GEN8_PML4ES_PER_PML4
);
1383 for_each_set_bit(pml4e
, new_pdps
, GEN8_PML4ES_PER_PML4
)
1384 gen8_ppgtt_cleanup_3lvl(vm
->dev
, pml4
->pdps
[pml4e
]);
1389 static int gen8_alloc_va_range(struct i915_address_space
*vm
,
1390 uint64_t start
, uint64_t length
)
1392 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1394 if (USES_FULL_48BIT_PPGTT(vm
->dev
))
1395 return gen8_alloc_va_range_4lvl(vm
, &ppgtt
->pml4
, start
, length
);
1397 return gen8_alloc_va_range_3lvl(vm
, &ppgtt
->pdp
, start
, length
);
1400 static void gen8_dump_pdp(struct i915_page_directory_pointer
*pdp
,
1401 uint64_t start
, uint64_t length
,
1402 gen8_pte_t scratch_pte
,
1405 struct i915_page_directory
*pd
;
1408 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1409 struct i915_page_table
*pt
;
1410 uint64_t pd_len
= length
;
1411 uint64_t pd_start
= start
;
1414 if (!test_bit(pdpe
, pdp
->used_pdpes
))
1417 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1418 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1420 gen8_pte_t
*pt_vaddr
;
1422 if (!test_bit(pde
, pd
->used_pdes
))
1425 pt_vaddr
= kmap_px(pt
);
1426 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1428 (pdpe
<< GEN8_PDPE_SHIFT
) |
1429 (pde
<< GEN8_PDE_SHIFT
) |
1430 (pte
<< GEN8_PTE_SHIFT
);
1434 for (i
= 0; i
< 4; i
++)
1435 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1440 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1441 for (i
= 0; i
< 4; i
++) {
1442 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1443 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1445 seq_puts(m
, " SCRATCH ");
1449 /* don't use kunmap_px, it could trigger
1450 * an unnecessary flush.
1452 kunmap_atomic(pt_vaddr
);
1457 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1459 struct i915_address_space
*vm
= &ppgtt
->base
;
1460 uint64_t start
= ppgtt
->base
.start
;
1461 uint64_t length
= ppgtt
->base
.total
;
1462 gen8_pte_t scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
1463 I915_CACHE_LLC
, true);
1465 if (!USES_FULL_48BIT_PPGTT(vm
->dev
)) {
1466 gen8_dump_pdp(&ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1469 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1470 struct i915_page_directory_pointer
*pdp
;
1472 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1473 if (!test_bit(pml4e
, pml4
->used_pml4es
))
1476 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1477 gen8_dump_pdp(pdp
, start
, length
, scratch_pte
, m
);
1482 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt
*ppgtt
)
1484 unsigned long *new_page_dirs
, *new_page_tables
;
1485 uint32_t pdpes
= I915_PDPES_PER_PDP(dev
);
1488 /* We allocate temp bitmap for page tables for no gain
1489 * but as this is for init only, lets keep the things simple
1491 ret
= alloc_gen8_temp_bitmaps(&new_page_dirs
, &new_page_tables
, pdpes
);
1495 /* Allocate for all pdps regardless of how the ppgtt
1498 ret
= gen8_ppgtt_alloc_page_directories(&ppgtt
->base
, &ppgtt
->pdp
,
1502 *ppgtt
->pdp
.used_pdpes
= *new_page_dirs
;
1504 free_gen8_temp_bitmaps(new_page_dirs
, new_page_tables
);
1510 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1511 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1512 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1516 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1520 ret
= gen8_init_scratch(&ppgtt
->base
);
1524 ppgtt
->base
.start
= 0;
1525 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1526 ppgtt
->base
.allocate_va_range
= gen8_alloc_va_range
;
1527 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_entries
;
1528 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_range
;
1529 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1530 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1531 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1533 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
1534 ret
= setup_px(ppgtt
->base
.dev
, &ppgtt
->pml4
);
1538 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1540 ppgtt
->base
.total
= 1ULL << 48;
1541 ppgtt
->switch_mm
= gen8_48b_mm_switch
;
1543 ret
= __pdp_init(ppgtt
->base
.dev
, &ppgtt
->pdp
);
1547 ppgtt
->base
.total
= 1ULL << 32;
1548 ppgtt
->switch_mm
= gen8_legacy_mm_switch
;
1549 trace_i915_page_directory_pointer_entry_alloc(&ppgtt
->base
,
1553 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
))) {
1554 ret
= gen8_preallocate_top_level_pdps(ppgtt
);
1560 if (intel_vgpu_active(to_i915(ppgtt
->base
.dev
)))
1561 gen8_ppgtt_notify_vgt(ppgtt
, true);
1566 gen8_free_scratch(&ppgtt
->base
);
1570 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1572 struct i915_address_space
*vm
= &ppgtt
->base
;
1573 struct i915_page_table
*unused
;
1574 gen6_pte_t scratch_pte
;
1577 uint32_t start
= ppgtt
->base
.start
, length
= ppgtt
->base
.total
;
1579 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1580 I915_CACHE_LLC
, true, 0);
1582 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1584 gen6_pte_t
*pt_vaddr
;
1585 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1586 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1587 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1589 if (pd_entry
!= expected
)
1590 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1594 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1596 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[pde
]);
1598 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1600 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1604 for (i
= 0; i
< 4; i
++)
1605 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1610 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1611 for (i
= 0; i
< 4; i
++) {
1612 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1613 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1615 seq_puts(m
, " SCRATCH ");
1619 kunmap_px(ppgtt
, pt_vaddr
);
1623 /* Write pde (index) from the page directory @pd to the page table @pt */
1624 static void gen6_write_pde(struct i915_page_directory
*pd
,
1625 const int pde
, struct i915_page_table
*pt
)
1627 /* Caller needs to make sure the write completes if necessary */
1628 struct i915_hw_ppgtt
*ppgtt
=
1629 container_of(pd
, struct i915_hw_ppgtt
, pd
);
1632 pd_entry
= GEN6_PDE_ADDR_ENCODE(px_dma(pt
));
1633 pd_entry
|= GEN6_PDE_VALID
;
1635 writel(pd_entry
, ppgtt
->pd_addr
+ pde
);
1638 /* Write all the page tables found in the ppgtt structure to incrementing page
1640 static void gen6_write_page_range(struct drm_i915_private
*dev_priv
,
1641 struct i915_page_directory
*pd
,
1642 uint32_t start
, uint32_t length
)
1644 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1645 struct i915_page_table
*pt
;
1648 gen6_for_each_pde(pt
, pd
, start
, length
, pde
)
1649 gen6_write_pde(pd
, pde
, pt
);
1651 /* Make sure write is complete before other code can use this page
1652 * table. Also require for WC mapped PTEs */
1656 static uint32_t get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1658 BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1660 return (ppgtt
->pd
.base
.ggtt_offset
/ 64) << 16;
1663 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1664 struct drm_i915_gem_request
*req
)
1666 struct intel_ring
*ring
= req
->ring
;
1667 struct intel_engine_cs
*engine
= req
->engine
;
1670 /* NB: TLBs must be flushed and invalidated before a switch */
1671 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1675 ret
= intel_ring_begin(req
, 6);
1679 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1680 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1681 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1682 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1683 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1684 intel_ring_emit(ring
, MI_NOOP
);
1685 intel_ring_advance(ring
);
1690 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1691 struct drm_i915_gem_request
*req
)
1693 struct intel_ring
*ring
= req
->ring
;
1694 struct intel_engine_cs
*engine
= req
->engine
;
1697 /* NB: TLBs must be flushed and invalidated before a switch */
1698 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1702 ret
= intel_ring_begin(req
, 6);
1706 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(2));
1707 intel_ring_emit_reg(ring
, RING_PP_DIR_DCLV(engine
));
1708 intel_ring_emit(ring
, PP_DIR_DCLV_2G
);
1709 intel_ring_emit_reg(ring
, RING_PP_DIR_BASE(engine
));
1710 intel_ring_emit(ring
, get_pd_offset(ppgtt
));
1711 intel_ring_emit(ring
, MI_NOOP
);
1712 intel_ring_advance(ring
);
1714 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1715 if (engine
->id
!= RCS
) {
1716 ret
= engine
->emit_flush(req
, EMIT_INVALIDATE
| EMIT_FLUSH
);
1724 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1725 struct drm_i915_gem_request
*req
)
1727 struct intel_engine_cs
*engine
= req
->engine
;
1728 struct drm_i915_private
*dev_priv
= req
->i915
;
1730 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1731 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1735 static void gen8_ppgtt_enable(struct drm_device
*dev
)
1737 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1738 struct intel_engine_cs
*engine
;
1740 for_each_engine(engine
, dev_priv
) {
1741 u32 four_level
= USES_FULL_48BIT_PPGTT(dev
) ? GEN8_GFX_PPGTT_48B
: 0;
1742 I915_WRITE(RING_MODE_GEN7(engine
),
1743 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1747 static void gen7_ppgtt_enable(struct drm_device
*dev
)
1749 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1750 struct intel_engine_cs
*engine
;
1751 uint32_t ecochk
, ecobits
;
1753 ecobits
= I915_READ(GAC_ECO_BITS
);
1754 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1756 ecochk
= I915_READ(GAM_ECOCHK
);
1757 if (IS_HASWELL(dev
)) {
1758 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1760 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1761 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1763 I915_WRITE(GAM_ECOCHK
, ecochk
);
1765 for_each_engine(engine
, dev_priv
) {
1766 /* GFX_MODE is per-ring on gen7+ */
1767 I915_WRITE(RING_MODE_GEN7(engine
),
1768 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1772 static void gen6_ppgtt_enable(struct drm_device
*dev
)
1774 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1775 uint32_t ecochk
, gab_ctl
, ecobits
;
1777 ecobits
= I915_READ(GAC_ECO_BITS
);
1778 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1779 ECOBITS_PPGTT_CACHE64B
);
1781 gab_ctl
= I915_READ(GAB_CTL
);
1782 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1784 ecochk
= I915_READ(GAM_ECOCHK
);
1785 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1787 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1790 /* PPGTT support for Sandybdrige/Gen6 and later */
1791 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1796 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1797 gen6_pte_t
*pt_vaddr
, scratch_pte
;
1798 unsigned first_entry
= start
>> PAGE_SHIFT
;
1799 unsigned num_entries
= length
>> PAGE_SHIFT
;
1800 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1801 unsigned first_pte
= first_entry
% GEN6_PTES
;
1802 unsigned last_pte
, i
;
1804 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
1805 I915_CACHE_LLC
, true, 0);
1807 while (num_entries
) {
1808 last_pte
= first_pte
+ num_entries
;
1809 if (last_pte
> GEN6_PTES
)
1810 last_pte
= GEN6_PTES
;
1812 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1814 for (i
= first_pte
; i
< last_pte
; i
++)
1815 pt_vaddr
[i
] = scratch_pte
;
1817 kunmap_px(ppgtt
, pt_vaddr
);
1819 num_entries
-= last_pte
- first_pte
;
1825 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1826 struct sg_table
*pages
,
1828 enum i915_cache_level cache_level
, u32 flags
)
1830 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1831 unsigned first_entry
= start
>> PAGE_SHIFT
;
1832 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1833 unsigned act_pte
= first_entry
% GEN6_PTES
;
1834 gen6_pte_t
*pt_vaddr
= NULL
;
1835 struct sgt_iter sgt_iter
;
1838 for_each_sgt_dma(addr
, sgt_iter
, pages
) {
1839 if (pt_vaddr
== NULL
)
1840 pt_vaddr
= kmap_px(ppgtt
->pd
.page_table
[act_pt
]);
1843 vm
->pte_encode(addr
, cache_level
, true, flags
);
1845 if (++act_pte
== GEN6_PTES
) {
1846 kunmap_px(ppgtt
, pt_vaddr
);
1854 kunmap_px(ppgtt
, pt_vaddr
);
1857 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1858 uint64_t start_in
, uint64_t length_in
)
1860 DECLARE_BITMAP(new_page_tables
, I915_PDES
);
1861 struct drm_device
*dev
= vm
->dev
;
1862 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1863 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1864 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1865 struct i915_page_table
*pt
;
1866 uint32_t start
, length
, start_save
, length_save
;
1870 if (WARN_ON(start_in
+ length_in
> ppgtt
->base
.total
))
1873 start
= start_save
= start_in
;
1874 length
= length_save
= length_in
;
1876 bitmap_zero(new_page_tables
, I915_PDES
);
1878 /* The allocation is done in two stages so that we can bail out with
1879 * minimal amount of pain. The first stage finds new page tables that
1880 * need allocation. The second stage marks use ptes within the page
1883 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1884 if (pt
!= vm
->scratch_pt
) {
1885 WARN_ON(bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1889 /* We've already allocated a page table */
1890 WARN_ON(!bitmap_empty(pt
->used_ptes
, GEN6_PTES
));
1898 gen6_initialize_pt(vm
, pt
);
1900 ppgtt
->pd
.page_table
[pde
] = pt
;
1901 __set_bit(pde
, new_page_tables
);
1902 trace_i915_page_table_entry_alloc(vm
, pde
, start
, GEN6_PDE_SHIFT
);
1906 length
= length_save
;
1908 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1909 DECLARE_BITMAP(tmp_bitmap
, GEN6_PTES
);
1911 bitmap_zero(tmp_bitmap
, GEN6_PTES
);
1912 bitmap_set(tmp_bitmap
, gen6_pte_index(start
),
1913 gen6_pte_count(start
, length
));
1915 if (__test_and_clear_bit(pde
, new_page_tables
))
1916 gen6_write_pde(&ppgtt
->pd
, pde
, pt
);
1918 trace_i915_page_table_entry_map(vm
, pde
, pt
,
1919 gen6_pte_index(start
),
1920 gen6_pte_count(start
, length
),
1922 bitmap_or(pt
->used_ptes
, tmp_bitmap
, pt
->used_ptes
,
1926 WARN_ON(!bitmap_empty(new_page_tables
, I915_PDES
));
1928 /* Make sure write is complete before other code can use this page
1929 * table. Also require for WC mapped PTEs */
1932 mark_tlbs_dirty(ppgtt
);
1936 for_each_set_bit(pde
, new_page_tables
, I915_PDES
) {
1937 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
];
1939 ppgtt
->pd
.page_table
[pde
] = vm
->scratch_pt
;
1940 free_pt(vm
->dev
, pt
);
1943 mark_tlbs_dirty(ppgtt
);
1947 static int gen6_init_scratch(struct i915_address_space
*vm
)
1949 struct drm_device
*dev
= vm
->dev
;
1951 vm
->scratch_page
= alloc_scratch_page(dev
);
1952 if (IS_ERR(vm
->scratch_page
))
1953 return PTR_ERR(vm
->scratch_page
);
1955 vm
->scratch_pt
= alloc_pt(dev
);
1956 if (IS_ERR(vm
->scratch_pt
)) {
1957 free_scratch_page(dev
, vm
->scratch_page
);
1958 return PTR_ERR(vm
->scratch_pt
);
1961 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1966 static void gen6_free_scratch(struct i915_address_space
*vm
)
1968 struct drm_device
*dev
= vm
->dev
;
1970 free_pt(dev
, vm
->scratch_pt
);
1971 free_scratch_page(dev
, vm
->scratch_page
);
1974 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1976 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1977 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1978 struct drm_device
*dev
= vm
->dev
;
1979 struct i915_page_table
*pt
;
1982 drm_mm_remove_node(&ppgtt
->node
);
1984 gen6_for_all_pdes(pt
, pd
, pde
)
1985 if (pt
!= vm
->scratch_pt
)
1988 gen6_free_scratch(vm
);
1991 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1993 struct i915_address_space
*vm
= &ppgtt
->base
;
1994 struct drm_device
*dev
= ppgtt
->base
.dev
;
1995 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1996 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1997 bool retried
= false;
2000 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2001 * allocator works in address space sizes, so it's multiplied by page
2002 * size. We allocate at the top of the GTT to avoid fragmentation.
2004 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
2006 ret
= gen6_init_scratch(vm
);
2011 ret
= drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
,
2012 &ppgtt
->node
, GEN6_PD_SIZE
,
2014 0, ggtt
->base
.total
,
2016 if (ret
== -ENOSPC
&& !retried
) {
2017 ret
= i915_gem_evict_something(&ggtt
->base
,
2018 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
2020 0, ggtt
->base
.total
,
2033 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
2034 DRM_DEBUG("Forced to use aperture for PDEs\n");
2039 gen6_free_scratch(vm
);
2043 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2045 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2048 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2049 uint64_t start
, uint64_t length
)
2051 struct i915_page_table
*unused
;
2054 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
2055 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
2058 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2060 struct drm_device
*dev
= ppgtt
->base
.dev
;
2061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2062 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2065 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
2066 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev
))
2067 ppgtt
->switch_mm
= gen6_mm_switch
;
2068 else if (IS_HASWELL(dev
))
2069 ppgtt
->switch_mm
= hsw_mm_switch
;
2070 else if (IS_GEN7(dev
))
2071 ppgtt
->switch_mm
= gen7_mm_switch
;
2075 ret
= gen6_ppgtt_alloc(ppgtt
);
2079 ppgtt
->base
.allocate_va_range
= gen6_alloc_va_range
;
2080 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
2081 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
2082 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
2083 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
2084 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
2085 ppgtt
->base
.start
= 0;
2086 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2087 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2089 ppgtt
->pd
.base
.ggtt_offset
=
2090 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2092 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2093 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2095 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
2097 gen6_write_page_range(dev_priv
, &ppgtt
->pd
, 0, ppgtt
->base
.total
);
2099 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2100 ppgtt
->node
.size
>> 20,
2101 ppgtt
->node
.start
/ PAGE_SIZE
);
2103 DRM_DEBUG("Adding PPGTT at offset %x\n",
2104 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2109 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2110 struct drm_i915_private
*dev_priv
)
2112 ppgtt
->base
.dev
= &dev_priv
->drm
;
2114 if (INTEL_INFO(dev_priv
)->gen
< 8)
2115 return gen6_ppgtt_init(ppgtt
);
2117 return gen8_ppgtt_init(ppgtt
);
2120 static void i915_address_space_init(struct i915_address_space
*vm
,
2121 struct drm_i915_private
*dev_priv
)
2123 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
2124 INIT_LIST_HEAD(&vm
->active_list
);
2125 INIT_LIST_HEAD(&vm
->inactive_list
);
2126 INIT_LIST_HEAD(&vm
->unbound_list
);
2127 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2130 static void gtt_write_workarounds(struct drm_device
*dev
)
2132 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2134 /* This function is for gtt related workarounds. This function is
2135 * called on driver load and after a GPU reset, so you can place
2136 * workarounds here even if they get overwritten by GPU reset.
2138 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2139 if (IS_BROADWELL(dev
))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2141 else if (IS_CHERRYVIEW(dev
))
2142 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2143 else if (IS_SKYLAKE(dev
))
2144 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2145 else if (IS_BROXTON(dev
))
2146 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2149 static int i915_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2150 struct drm_i915_private
*dev_priv
,
2151 struct drm_i915_file_private
*file_priv
)
2155 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2157 kref_init(&ppgtt
->ref
);
2158 i915_address_space_init(&ppgtt
->base
, dev_priv
);
2159 ppgtt
->base
.file
= file_priv
;
2165 int i915_ppgtt_init_hw(struct drm_device
*dev
)
2167 gtt_write_workarounds(dev
);
2169 /* In the case of execlists, PPGTT is enabled by the context descriptor
2170 * and the PDPs are contained within the context itself. We don't
2171 * need to do anything here. */
2172 if (i915
.enable_execlists
)
2175 if (!USES_PPGTT(dev
))
2179 gen6_ppgtt_enable(dev
);
2180 else if (IS_GEN7(dev
))
2181 gen7_ppgtt_enable(dev
);
2182 else if (INTEL_INFO(dev
)->gen
>= 8)
2183 gen8_ppgtt_enable(dev
);
2185 MISSING_CASE(INTEL_INFO(dev
)->gen
);
2190 struct i915_hw_ppgtt
*
2191 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
2192 struct drm_i915_file_private
*fpriv
)
2194 struct i915_hw_ppgtt
*ppgtt
;
2197 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2199 return ERR_PTR(-ENOMEM
);
2201 ret
= i915_ppgtt_init(ppgtt
, dev_priv
, fpriv
);
2204 return ERR_PTR(ret
);
2207 trace_i915_ppgtt_create(&ppgtt
->base
);
2212 void i915_ppgtt_release(struct kref
*kref
)
2214 struct i915_hw_ppgtt
*ppgtt
=
2215 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2217 trace_i915_ppgtt_release(&ppgtt
->base
);
2219 /* vmas should already be unbound and destroyed */
2220 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
2221 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
2222 WARN_ON(!list_empty(&ppgtt
->base
.unbound_list
));
2224 list_del(&ppgtt
->base
.global_link
);
2225 drm_mm_takedown(&ppgtt
->base
.mm
);
2227 ppgtt
->base
.cleanup(&ppgtt
->base
);
2231 /* Certain Gen5 chipsets require require idling the GPU before
2232 * unmapping anything from the GTT when VT-d is enabled.
2234 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
2236 #ifdef CONFIG_INTEL_IOMMU
2237 /* Query intel_iommu to see if we need the workaround. Presumably that
2240 if (IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_iommu_gfx_mapped
)
2246 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2248 struct intel_engine_cs
*engine
;
2250 if (INTEL_INFO(dev_priv
)->gen
< 6)
2253 for_each_engine(engine
, dev_priv
) {
2255 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2256 if (fault_reg
& RING_FAULT_VALID
) {
2257 DRM_DEBUG_DRIVER("Unexpected fault\n"
2259 "\tAddress space: %s\n"
2262 fault_reg
& PAGE_MASK
,
2263 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2264 RING_FAULT_SRCID(fault_reg
),
2265 RING_FAULT_FAULT_TYPE(fault_reg
));
2266 I915_WRITE(RING_FAULT_REG(engine
),
2267 fault_reg
& ~RING_FAULT_VALID
);
2270 POSTING_READ(RING_FAULT_REG(&dev_priv
->engine
[RCS
]));
2273 static void i915_ggtt_flush(struct drm_i915_private
*dev_priv
)
2275 if (INTEL_INFO(dev_priv
)->gen
< 6) {
2276 intel_gtt_chipset_flush();
2278 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2279 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2283 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
)
2285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2286 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2288 /* Don't bother messing with faults pre GEN6 as we have little
2289 * documentation supporting that it's a good idea.
2291 if (INTEL_INFO(dev
)->gen
< 6)
2294 i915_check_and_clear_faults(dev_priv
);
2296 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
2299 i915_ggtt_flush(dev_priv
);
2302 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
2304 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2305 obj
->pages
->sgl
, obj
->pages
->nents
,
2306 PCI_DMA_BIDIRECTIONAL
))
2312 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2317 iowrite32((u32
)pte
, addr
);
2318 iowrite32(pte
>> 32, addr
+ 4);
2322 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2325 enum i915_cache_level level
,
2328 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2329 gen8_pte_t __iomem
*pte
=
2330 (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2331 (offset
>> PAGE_SHIFT
);
2334 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2336 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
, true));
2338 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2339 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2341 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2344 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2345 struct sg_table
*st
,
2347 enum i915_cache_level level
, u32 unused
)
2349 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2350 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2351 struct sgt_iter sgt_iter
;
2352 gen8_pte_t __iomem
*gtt_entries
;
2353 gen8_pte_t gtt_entry
;
2358 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2360 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2362 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2363 gtt_entry
= gen8_pte_encode(addr
, level
, true);
2364 gen8_set_pte(>t_entries
[i
++], gtt_entry
);
2368 * XXX: This serves as a posting read to make sure that the PTE has
2369 * actually been updated. There is some concern that even though
2370 * registers and PTEs are within the same BAR that they are potentially
2371 * of NUMA access patterns. Therefore, even with the way we assume
2372 * hardware should work, we must keep this posting read for paranoia.
2375 WARN_ON(readq(>t_entries
[i
-1]) != gtt_entry
);
2377 /* This next bit makes the above posting read even more important. We
2378 * want to flush the TLBs only after we're certain all the PTE updates
2381 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2382 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2384 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2387 struct insert_entries
{
2388 struct i915_address_space
*vm
;
2389 struct sg_table
*st
;
2391 enum i915_cache_level level
;
2395 static int gen8_ggtt_insert_entries__cb(void *_arg
)
2397 struct insert_entries
*arg
= _arg
;
2398 gen8_ggtt_insert_entries(arg
->vm
, arg
->st
,
2399 arg
->start
, arg
->level
, arg
->flags
);
2403 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2404 struct sg_table
*st
,
2406 enum i915_cache_level level
,
2409 struct insert_entries arg
= { vm
, st
, start
, level
, flags
};
2410 stop_machine(gen8_ggtt_insert_entries__cb
, &arg
, NULL
);
2413 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2416 enum i915_cache_level level
,
2419 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2420 gen6_pte_t __iomem
*pte
=
2421 (gen6_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+
2422 (offset
>> PAGE_SHIFT
);
2425 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2427 iowrite32(vm
->pte_encode(addr
, level
, true, flags
), pte
);
2429 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2430 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2432 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2436 * Binds an object into the global gtt with the specified cache level. The object
2437 * will be accessible to the GPU via commands whose operands reference offsets
2438 * within the global GTT as well as accessible by the GPU through the GMADR
2439 * mapped BAR (dev_priv->mm.gtt->gtt).
2441 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2442 struct sg_table
*st
,
2444 enum i915_cache_level level
, u32 flags
)
2446 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2447 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2448 struct sgt_iter sgt_iter
;
2449 gen6_pte_t __iomem
*gtt_entries
;
2450 gen6_pte_t gtt_entry
;
2455 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2457 gtt_entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
+ (start
>> PAGE_SHIFT
);
2459 for_each_sgt_dma(addr
, sgt_iter
, st
) {
2460 gtt_entry
= vm
->pte_encode(addr
, level
, true, flags
);
2461 iowrite32(gtt_entry
, >t_entries
[i
++]);
2464 /* XXX: This serves as a posting read to make sure that the PTE has
2465 * actually been updated. There is some concern that even though
2466 * registers and PTEs are within the same BAR that they are potentially
2467 * of NUMA access patterns. Therefore, even with the way we assume
2468 * hardware should work, we must keep this posting read for paranoia.
2471 WARN_ON(readl(>t_entries
[i
-1]) != gtt_entry
);
2473 /* This next bit makes the above posting read even more important. We
2474 * want to flush the TLBs only after we're certain all the PTE updates
2477 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
2478 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2480 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2483 static void nop_clear_range(struct i915_address_space
*vm
,
2490 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2495 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2496 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2497 unsigned first_entry
= start
>> PAGE_SHIFT
;
2498 unsigned num_entries
= length
>> PAGE_SHIFT
;
2499 gen8_pte_t scratch_pte
, __iomem
*gtt_base
=
2500 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2501 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2505 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2507 if (WARN(num_entries
> max_entries
,
2508 "First entry = %d; Num entries = %d (max=%d)\n",
2509 first_entry
, num_entries
, max_entries
))
2510 num_entries
= max_entries
;
2512 scratch_pte
= gen8_pte_encode(px_dma(vm
->scratch_page
),
2515 for (i
= 0; i
< num_entries
; i
++)
2516 gen8_set_pte(>t_base
[i
], scratch_pte
);
2519 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2522 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2527 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2528 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2529 unsigned first_entry
= start
>> PAGE_SHIFT
;
2530 unsigned num_entries
= length
>> PAGE_SHIFT
;
2531 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2532 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2533 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2537 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2539 if (WARN(num_entries
> max_entries
,
2540 "First entry = %d; Num entries = %d (max=%d)\n",
2541 first_entry
, num_entries
, max_entries
))
2542 num_entries
= max_entries
;
2544 scratch_pte
= vm
->pte_encode(px_dma(vm
->scratch_page
),
2545 I915_CACHE_LLC
, use_scratch
, 0);
2547 for (i
= 0; i
< num_entries
; i
++)
2548 iowrite32(scratch_pte
, >t_base
[i
]);
2551 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2554 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2557 enum i915_cache_level cache_level
,
2560 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2561 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2562 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2565 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2567 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2569 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2572 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2573 struct sg_table
*pages
,
2575 enum i915_cache_level cache_level
, u32 unused
)
2577 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2578 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2579 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2582 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2584 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2586 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2590 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2595 struct drm_i915_private
*dev_priv
= to_i915(vm
->dev
);
2596 unsigned first_entry
= start
>> PAGE_SHIFT
;
2597 unsigned num_entries
= length
>> PAGE_SHIFT
;
2600 rpm_atomic_seq
= assert_rpm_atomic_begin(dev_priv
);
2602 intel_gtt_clear_range(first_entry
, num_entries
);
2604 assert_rpm_atomic_end(dev_priv
, rpm_atomic_seq
);
2607 static int ggtt_bind_vma(struct i915_vma
*vma
,
2608 enum i915_cache_level cache_level
,
2611 struct drm_i915_gem_object
*obj
= vma
->obj
;
2615 ret
= i915_get_ggtt_vma_pages(vma
);
2619 /* Currently applicable only to VLV */
2621 pte_flags
|= PTE_READ_ONLY
;
2623 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
2624 cache_level
, pte_flags
);
2627 * Without aliasing PPGTT there's no difference between
2628 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2629 * upgrade to both bound if we bind either to avoid double-binding.
2631 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2636 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2637 enum i915_cache_level cache_level
,
2643 ret
= i915_get_ggtt_vma_pages(vma
);
2647 /* Currently applicable only to VLV */
2649 if (vma
->obj
->gt_ro
)
2650 pte_flags
|= PTE_READ_ONLY
;
2653 if (flags
& I915_VMA_GLOBAL_BIND
) {
2654 vma
->vm
->insert_entries(vma
->vm
,
2655 vma
->pages
, vma
->node
.start
,
2656 cache_level
, pte_flags
);
2659 if (flags
& I915_VMA_LOCAL_BIND
) {
2660 struct i915_hw_ppgtt
*appgtt
=
2661 to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2662 appgtt
->base
.insert_entries(&appgtt
->base
,
2663 vma
->pages
, vma
->node
.start
,
2664 cache_level
, pte_flags
);
2670 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2672 struct i915_hw_ppgtt
*appgtt
= to_i915(vma
->vm
->dev
)->mm
.aliasing_ppgtt
;
2673 const u64 size
= min(vma
->size
, vma
->node
.size
);
2675 if (vma
->flags
& I915_VMA_GLOBAL_BIND
)
2676 vma
->vm
->clear_range(vma
->vm
,
2677 vma
->node
.start
, size
,
2680 if (vma
->flags
& I915_VMA_LOCAL_BIND
&& appgtt
)
2681 appgtt
->base
.clear_range(&appgtt
->base
,
2682 vma
->node
.start
, size
,
2686 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
2688 struct drm_device
*dev
= obj
->base
.dev
;
2689 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2690 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2692 if (unlikely(ggtt
->do_idle_maps
)) {
2693 if (i915_gem_wait_for_idle(dev_priv
, false)) {
2694 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2695 /* Wait a bit, in hopes it avoids the hang */
2700 dma_unmap_sg(&dev
->pdev
->dev
, obj
->pages
->sgl
, obj
->pages
->nents
,
2701 PCI_DMA_BIDIRECTIONAL
);
2704 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
2705 unsigned long color
,
2709 if (node
->color
!= color
)
2712 node
= list_first_entry_or_null(&node
->node_list
,
2715 if (node
&& node
->allocated
&& node
->color
!= color
)
2719 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2721 /* Let GEM Manage all of the aperture.
2723 * However, leave one page at the end still bound to the scratch page.
2724 * There are a number of places where the hardware apparently prefetches
2725 * past the end of the object, and we've seen multiple hangs with the
2726 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2727 * aperture. One page should be enough to keep any prefetching inside
2730 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2731 unsigned long hole_start
, hole_end
;
2732 struct drm_mm_node
*entry
;
2735 ret
= intel_vgt_balloon(dev_priv
);
2739 /* Clear any non-preallocated blocks */
2740 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2741 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2742 hole_start
, hole_end
);
2743 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2744 hole_end
- hole_start
, true);
2747 /* And finally clear the reserved guard page */
2748 ggtt
->base
.clear_range(&ggtt
->base
,
2749 ggtt
->base
.total
- PAGE_SIZE
, PAGE_SIZE
,
2752 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2753 struct i915_hw_ppgtt
*ppgtt
;
2755 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2759 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2765 if (ppgtt
->base
.allocate_va_range
)
2766 ret
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
, 0,
2769 ppgtt
->base
.cleanup(&ppgtt
->base
);
2774 ppgtt
->base
.clear_range(&ppgtt
->base
,
2779 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
2780 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2781 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2788 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2789 * @dev_priv: i915 device
2791 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2793 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2795 if (dev_priv
->mm
.aliasing_ppgtt
) {
2796 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2797 ppgtt
->base
.cleanup(&ppgtt
->base
);
2801 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2803 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2804 intel_vgt_deballoon(dev_priv
);
2806 drm_mm_takedown(&ggtt
->base
.mm
);
2807 list_del(&ggtt
->base
.global_link
);
2810 ggtt
->base
.cleanup(&ggtt
->base
);
2812 arch_phys_wc_del(ggtt
->mtrr
);
2813 io_mapping_fini(&ggtt
->mappable
);
2816 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2818 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2819 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2820 return snb_gmch_ctl
<< 20;
2823 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2825 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2826 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2828 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2830 #ifdef CONFIG_X86_32
2831 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2832 if (bdw_gmch_ctl
> 4)
2836 return bdw_gmch_ctl
<< 20;
2839 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2841 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2842 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2845 return 1 << (20 + gmch_ctrl
);
2850 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2852 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2853 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2854 return snb_gmch_ctl
<< 25; /* 32 MB units */
2857 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2859 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2860 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2861 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2864 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2866 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2867 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2870 * 0x0 to 0x10: 32MB increments starting at 0MB
2871 * 0x11 to 0x16: 4MB increments starting at 8MB
2872 * 0x17 to 0x1d: 4MB increments start at 36MB
2874 if (gmch_ctrl
< 0x11)
2875 return gmch_ctrl
<< 25;
2876 else if (gmch_ctrl
< 0x17)
2877 return (gmch_ctrl
- 0x11 + 2) << 22;
2879 return (gmch_ctrl
- 0x17 + 9) << 22;
2882 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2884 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2885 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2887 if (gen9_gmch_ctl
< 0xf0)
2888 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2890 /* 4MB increments starting at 0xf0 for 4MB */
2891 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2894 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2896 struct pci_dev
*pdev
= ggtt
->base
.dev
->pdev
;
2897 struct i915_page_scratch
*scratch_page
;
2898 phys_addr_t phys_addr
;
2900 /* For Modern GENs the PTEs and register space are split in the BAR */
2901 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2904 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2905 * dropped. For WC mappings in general we have 64 byte burst writes
2906 * when the WC buffer is flushed, so we can't use it, but have to
2907 * resort to an uncached mapping. The WC issue is easily caught by the
2908 * readback check when writing GTT PTE entries.
2910 if (IS_BROXTON(ggtt
->base
.dev
))
2911 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2913 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2915 DRM_ERROR("Failed to map the ggtt page table\n");
2919 scratch_page
= alloc_scratch_page(ggtt
->base
.dev
);
2920 if (IS_ERR(scratch_page
)) {
2921 DRM_ERROR("Scratch setup failed\n");
2922 /* iounmap will also get called at remove, but meh */
2924 return PTR_ERR(scratch_page
);
2927 ggtt
->base
.scratch_page
= scratch_page
;
2932 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2933 * bits. When using advanced contexts each context stores its own PAT, but
2934 * writing this data shouldn't be harmful even in those cases. */
2935 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2939 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2940 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2941 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2942 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2943 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2944 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2945 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2946 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2948 if (!USES_PPGTT(dev_priv
))
2949 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2950 * so RTL will always use the value corresponding to
2952 * So let's disable cache for GGTT to avoid screen corruptions.
2953 * MOCS still can be used though.
2954 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2955 * before this patch, i.e. the same uncached + snooping access
2956 * like on gen6/7 seems to be in effect.
2957 * - So this just fixes blitter/render access. Again it looks
2958 * like it's not just uncached access, but uncached + snooping.
2959 * So we can still hold onto all our assumptions wrt cpu
2960 * clflushing on LLC machines.
2962 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2964 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2965 * write would work. */
2966 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2967 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2970 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2975 * Map WB on BDW to snooped on CHV.
2977 * Only the snoop bit has meaning for CHV, the rest is
2980 * The hardware will never snoop for certain types of accesses:
2981 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2982 * - PPGTT page tables
2983 * - some other special cycles
2985 * As with BDW, we also need to consider the following for GT accesses:
2986 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2987 * so RTL will always use the value corresponding to
2989 * Which means we must set the snoop bit in PAT entry 0
2990 * in order to keep the global status page working.
2992 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2996 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2997 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2998 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2999 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
3001 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
3002 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
3005 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3007 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
3010 free_scratch_page(vm
->dev
, vm
->scratch_page
);
3013 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3015 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3016 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3020 /* TODO: We're not aware of mappable constraints on gen8 yet */
3021 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3022 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3024 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(39)))
3025 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
3027 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3029 if (INTEL_GEN(dev_priv
) >= 9) {
3030 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
3031 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3032 } else if (IS_CHERRYVIEW(dev_priv
)) {
3033 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
3034 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3036 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
3037 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3040 ggtt
->base
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3042 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
3043 chv_setup_private_ppat(dev_priv
);
3045 bdw_setup_private_ppat(dev_priv
);
3047 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3048 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3049 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3050 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
3051 ggtt
->base
.clear_range
= nop_clear_range
;
3052 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
3053 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
3055 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
3056 if (IS_CHERRYVIEW(dev_priv
))
3057 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries__BKL
;
3059 return ggtt_probe_common(ggtt
, size
);
3062 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3064 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3065 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3069 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
3070 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
3072 /* 64/512MB is the current min/max we actually know of, but this is just
3073 * a coarse sanity check.
3075 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
3076 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
3080 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
3081 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
3082 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3084 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
3086 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3087 ggtt
->base
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3089 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
3090 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
3091 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
3092 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3093 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3094 ggtt
->base
.cleanup
= gen6_gmch_remove
;
3096 if (HAS_EDRAM(dev_priv
))
3097 ggtt
->base
.pte_encode
= iris_pte_encode
;
3098 else if (IS_HASWELL(dev_priv
))
3099 ggtt
->base
.pte_encode
= hsw_pte_encode
;
3100 else if (IS_VALLEYVIEW(dev_priv
))
3101 ggtt
->base
.pte_encode
= byt_pte_encode
;
3102 else if (INTEL_GEN(dev_priv
) >= 7)
3103 ggtt
->base
.pte_encode
= ivb_pte_encode
;
3105 ggtt
->base
.pte_encode
= snb_pte_encode
;
3107 return ggtt_probe_common(ggtt
, size
);
3110 static void i915_gmch_remove(struct i915_address_space
*vm
)
3112 intel_gmch_remove();
3115 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3117 struct drm_i915_private
*dev_priv
= to_i915(ggtt
->base
.dev
);
3120 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
3122 DRM_ERROR("failed to set up gmch\n");
3126 intel_gtt_get(&ggtt
->base
.total
, &ggtt
->stolen_size
,
3127 &ggtt
->mappable_base
, &ggtt
->mappable_end
);
3129 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
3130 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
3131 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
3132 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
3133 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
3134 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
3135 ggtt
->base
.cleanup
= i915_gmch_remove
;
3137 if (unlikely(ggtt
->do_idle_maps
))
3138 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3144 * i915_ggtt_probe_hw - Probe GGTT hardware location
3145 * @dev_priv: i915 device
3147 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
3149 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3152 ggtt
->base
.dev
= &dev_priv
->drm
;
3154 if (INTEL_GEN(dev_priv
) <= 5)
3155 ret
= i915_gmch_probe(ggtt
);
3156 else if (INTEL_GEN(dev_priv
) < 8)
3157 ret
= gen6_gmch_probe(ggtt
);
3159 ret
= gen8_gmch_probe(ggtt
);
3163 if ((ggtt
->base
.total
- 1) >> 32) {
3164 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3165 " of address space! Found %lldM!\n",
3166 ggtt
->base
.total
>> 20);
3167 ggtt
->base
.total
= 1ULL << 32;
3168 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
3171 if (ggtt
->mappable_end
> ggtt
->base
.total
) {
3172 DRM_ERROR("mappable aperture extends past end of GGTT,"
3173 " aperture=%llx, total=%llx\n",
3174 ggtt
->mappable_end
, ggtt
->base
.total
);
3175 ggtt
->mappable_end
= ggtt
->base
.total
;
3178 /* GMADR is the PCI mmio aperture into the global GTT. */
3179 DRM_INFO("Memory usable by graphics device = %lluM\n",
3180 ggtt
->base
.total
>> 20);
3181 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
3182 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt
->stolen_size
>> 20);
3183 #ifdef CONFIG_INTEL_IOMMU
3184 if (intel_iommu_gfx_mapped
)
3185 DRM_INFO("VT-d active for gfx access\n");
3192 * i915_ggtt_init_hw - Initialize GGTT hardware
3193 * @dev_priv: i915 device
3195 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
3197 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3200 INIT_LIST_HEAD(&dev_priv
->vm_list
);
3202 /* Subtract the guard page before address space initialization to
3203 * shrink the range used by drm_mm.
3205 ggtt
->base
.total
-= PAGE_SIZE
;
3206 i915_address_space_init(&ggtt
->base
, dev_priv
);
3207 ggtt
->base
.total
+= PAGE_SIZE
;
3208 if (!HAS_LLC(dev_priv
))
3209 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
3211 if (!io_mapping_init_wc(&dev_priv
->ggtt
.mappable
,
3212 dev_priv
->ggtt
.mappable_base
,
3213 dev_priv
->ggtt
.mappable_end
)) {
3215 goto out_gtt_cleanup
;
3218 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
, ggtt
->mappable_end
);
3221 * Initialise stolen early so that we may reserve preallocated
3222 * objects for the BIOS to KMS transition.
3224 ret
= i915_gem_init_stolen(&dev_priv
->drm
);
3226 goto out_gtt_cleanup
;
3231 ggtt
->base
.cleanup(&ggtt
->base
);
3235 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
3237 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
3243 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
3245 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3246 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3247 struct drm_i915_gem_object
*obj
;
3248 struct i915_vma
*vma
;
3250 i915_check_and_clear_faults(dev_priv
);
3252 /* First fill our portion of the GTT with scratch pages */
3253 ggtt
->base
.clear_range(&ggtt
->base
, ggtt
->base
.start
, ggtt
->base
.total
,
3256 /* Cache flush objects bound into GGTT and rebind them. */
3257 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
3258 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3259 if (vma
->vm
!= &ggtt
->base
)
3262 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3266 if (obj
->pin_display
)
3267 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3270 if (INTEL_INFO(dev
)->gen
>= 8) {
3271 if (IS_CHERRYVIEW(dev
) || IS_BROXTON(dev
))
3272 chv_setup_private_ppat(dev_priv
);
3274 bdw_setup_private_ppat(dev_priv
);
3279 if (USES_PPGTT(dev
)) {
3280 struct i915_address_space
*vm
;
3282 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3283 /* TODO: Perhaps it shouldn't be gen6 specific */
3285 struct i915_hw_ppgtt
*ppgtt
;
3287 if (i915_is_ggtt(vm
))
3288 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3290 ppgtt
= i915_vm_to_ppgtt(vm
);
3292 gen6_write_page_range(dev_priv
, &ppgtt
->pd
,
3293 0, ppgtt
->base
.total
);
3297 i915_ggtt_flush(dev_priv
);
3301 i915_vma_retire(struct i915_gem_active
*active
,
3302 struct drm_i915_gem_request
*rq
)
3304 const unsigned int idx
= rq
->engine
->id
;
3305 struct i915_vma
*vma
=
3306 container_of(active
, struct i915_vma
, last_read
[idx
]);
3308 GEM_BUG_ON(!i915_vma_has_active_engine(vma
, idx
));
3310 i915_vma_clear_active(vma
, idx
);
3311 if (i915_vma_is_active(vma
))
3314 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
3315 if (unlikely(i915_vma_is_closed(vma
) && !i915_vma_is_pinned(vma
)))
3316 WARN_ON(i915_vma_unbind(vma
));
3319 void i915_vma_destroy(struct i915_vma
*vma
)
3321 GEM_BUG_ON(vma
->node
.allocated
);
3322 GEM_BUG_ON(i915_vma_is_active(vma
));
3323 GEM_BUG_ON(!i915_vma_is_closed(vma
));
3324 GEM_BUG_ON(vma
->fence
);
3326 list_del(&vma
->vm_link
);
3327 if (!i915_vma_is_ggtt(vma
))
3328 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
3330 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
3333 void i915_vma_close(struct i915_vma
*vma
)
3335 GEM_BUG_ON(i915_vma_is_closed(vma
));
3336 vma
->flags
|= I915_VMA_CLOSED
;
3338 list_del_init(&vma
->obj_link
);
3339 if (!i915_vma_is_active(vma
) && !i915_vma_is_pinned(vma
))
3340 WARN_ON(i915_vma_unbind(vma
));
3343 static struct i915_vma
*
3344 __i915_vma_create(struct drm_i915_gem_object
*obj
,
3345 struct i915_address_space
*vm
,
3346 const struct i915_ggtt_view
*view
)
3348 struct i915_vma
*vma
;
3351 GEM_BUG_ON(vm
->closed
);
3353 vma
= kmem_cache_zalloc(to_i915(obj
->base
.dev
)->vmas
, GFP_KERNEL
);
3355 return ERR_PTR(-ENOMEM
);
3357 INIT_LIST_HEAD(&vma
->exec_list
);
3358 for (i
= 0; i
< ARRAY_SIZE(vma
->last_read
); i
++)
3359 init_request_active(&vma
->last_read
[i
], i915_vma_retire
);
3360 init_request_active(&vma
->last_fence
, NULL
);
3361 list_add(&vma
->vm_link
, &vm
->unbound_list
);
3364 vma
->size
= obj
->base
.size
;
3367 vma
->ggtt_view
= *view
;
3368 if (view
->type
== I915_GGTT_VIEW_PARTIAL
) {
3369 vma
->size
= view
->params
.partial
.size
;
3370 vma
->size
<<= PAGE_SHIFT
;
3371 } else if (view
->type
== I915_GGTT_VIEW_ROTATED
) {
3373 intel_rotation_info_size(&view
->params
.rotated
);
3374 vma
->size
<<= PAGE_SHIFT
;
3378 if (i915_is_ggtt(vm
)) {
3379 vma
->flags
|= I915_VMA_GGTT
;
3381 i915_ppgtt_get(i915_vm_to_ppgtt(vm
));
3384 list_add_tail(&vma
->obj_link
, &obj
->vma_list
);
3388 static inline bool vma_matches(struct i915_vma
*vma
,
3389 struct i915_address_space
*vm
,
3390 const struct i915_ggtt_view
*view
)
3395 if (!i915_vma_is_ggtt(vma
))
3399 return vma
->ggtt_view
.type
== 0;
3401 if (vma
->ggtt_view
.type
!= view
->type
)
3404 return memcmp(&vma
->ggtt_view
.params
,
3406 sizeof(view
->params
)) == 0;
3410 i915_vma_create(struct drm_i915_gem_object
*obj
,
3411 struct i915_address_space
*vm
,
3412 const struct i915_ggtt_view
*view
)
3414 GEM_BUG_ON(view
&& !i915_is_ggtt(vm
));
3415 GEM_BUG_ON(i915_gem_obj_to_vma(obj
, vm
, view
));
3417 return __i915_vma_create(obj
, vm
, view
);
3421 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3422 struct i915_address_space
*vm
,
3423 const struct i915_ggtt_view
*view
)
3425 struct i915_vma
*vma
;
3427 list_for_each_entry_reverse(vma
, &obj
->vma_list
, obj_link
)
3428 if (vma_matches(vma
, vm
, view
))
3435 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3436 struct i915_address_space
*vm
,
3437 const struct i915_ggtt_view
*view
)
3439 struct i915_vma
*vma
;
3441 GEM_BUG_ON(view
&& !i915_is_ggtt(vm
));
3443 vma
= i915_gem_obj_to_vma(obj
, vm
, view
);
3445 vma
= __i915_vma_create(obj
, vm
, view
);
3447 GEM_BUG_ON(i915_vma_is_closed(vma
));
3451 static struct scatterlist
*
3452 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3453 unsigned int width
, unsigned int height
,
3454 unsigned int stride
,
3455 struct sg_table
*st
, struct scatterlist
*sg
)
3457 unsigned int column
, row
;
3458 unsigned int src_idx
;
3460 for (column
= 0; column
< width
; column
++) {
3461 src_idx
= stride
* (height
- 1) + column
;
3462 for (row
= 0; row
< height
; row
++) {
3464 /* We don't need the pages, but need to initialize
3465 * the entries so the sg list can be happily traversed.
3466 * The only thing we need are DMA addresses.
3468 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3469 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3470 sg_dma_len(sg
) = PAGE_SIZE
;
3479 static struct sg_table
*
3480 intel_rotate_fb_obj_pages(const struct intel_rotation_info
*rot_info
,
3481 struct drm_i915_gem_object
*obj
)
3483 const size_t n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3484 unsigned int size
= intel_rotation_info_size(rot_info
);
3485 struct sgt_iter sgt_iter
;
3486 dma_addr_t dma_addr
;
3488 dma_addr_t
*page_addr_list
;
3489 struct sg_table
*st
;
3490 struct scatterlist
*sg
;
3493 /* Allocate a temporary list of source pages for random access. */
3494 page_addr_list
= drm_malloc_gfp(n_pages
,
3497 if (!page_addr_list
)
3498 return ERR_PTR(ret
);
3500 /* Allocate target SG list. */
3501 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3505 ret
= sg_alloc_table(st
, size
, GFP_KERNEL
);
3509 /* Populate source page list from the object. */
3511 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->pages
)
3512 page_addr_list
[i
++] = dma_addr
;
3514 GEM_BUG_ON(i
!= n_pages
);
3518 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++) {
3519 sg
= rotate_pages(page_addr_list
, rot_info
->plane
[i
].offset
,
3520 rot_info
->plane
[i
].width
, rot_info
->plane
[i
].height
,
3521 rot_info
->plane
[i
].stride
, st
, sg
);
3524 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3525 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3527 drm_free_large(page_addr_list
);
3534 drm_free_large(page_addr_list
);
3536 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3537 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3539 return ERR_PTR(ret
);
3542 static struct sg_table
*
3543 intel_partial_pages(const struct i915_ggtt_view
*view
,
3544 struct drm_i915_gem_object
*obj
)
3546 struct sg_table
*st
;
3547 struct scatterlist
*sg
;
3548 struct sg_page_iter obj_sg_iter
;
3551 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3555 ret
= sg_alloc_table(st
, view
->params
.partial
.size
, GFP_KERNEL
);
3561 for_each_sg_page(obj
->pages
->sgl
, &obj_sg_iter
, obj
->pages
->nents
,
3562 view
->params
.partial
.offset
)
3564 if (st
->nents
>= view
->params
.partial
.size
)
3567 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3568 sg_dma_address(sg
) = sg_page_iter_dma_address(&obj_sg_iter
);
3569 sg_dma_len(sg
) = PAGE_SIZE
;
3580 return ERR_PTR(ret
);
3584 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3591 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
3592 vma
->pages
= vma
->obj
->pages
;
3593 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_ROTATED
)
3595 intel_rotate_fb_obj_pages(&vma
->ggtt_view
.params
.rotated
, vma
->obj
);
3596 else if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_PARTIAL
)
3597 vma
->pages
= intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3599 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3600 vma
->ggtt_view
.type
);
3603 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3604 vma
->ggtt_view
.type
);
3606 } else if (IS_ERR(vma
->pages
)) {
3607 ret
= PTR_ERR(vma
->pages
);
3609 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3610 vma
->ggtt_view
.type
, ret
);
3617 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3619 * @cache_level: mapping cache level
3620 * @flags: flags like global or local mapping
3622 * DMA addresses are taken from the scatter-gather table of this object (or of
3623 * this VMA in case of non-default GGTT views) and PTE entries set up.
3624 * Note that DMA addresses are also the only part of the SG table we care about.
3626 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3633 if (WARN_ON(flags
== 0))
3637 if (flags
& PIN_GLOBAL
)
3638 bind_flags
|= I915_VMA_GLOBAL_BIND
;
3639 if (flags
& PIN_USER
)
3640 bind_flags
|= I915_VMA_LOCAL_BIND
;
3642 vma_flags
= vma
->flags
& (I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
);
3643 if (flags
& PIN_UPDATE
)
3644 bind_flags
|= vma_flags
;
3646 bind_flags
&= ~vma_flags
;
3647 if (bind_flags
== 0)
3650 if (vma_flags
== 0 && vma
->vm
->allocate_va_range
) {
3651 trace_i915_va_alloc(vma
);
3652 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3659 ret
= vma
->vm
->bind_vma(vma
, cache_level
, bind_flags
);
3663 vma
->flags
|= bind_flags
;
3667 void __iomem
*i915_vma_pin_iomap(struct i915_vma
*vma
)
3671 /* Access through the GTT requires the device to be awake. */
3672 assert_rpm_wakelock_held(to_i915(vma
->vm
->dev
));
3674 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3675 if (WARN_ON(!i915_vma_is_map_and_fenceable(vma
)))
3676 return IO_ERR_PTR(-ENODEV
);
3678 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
3679 GEM_BUG_ON((vma
->flags
& I915_VMA_GLOBAL_BIND
) == 0);
3683 ptr
= io_mapping_map_wc(&i915_vm_to_ggtt(vma
->vm
)->mappable
,
3687 return IO_ERR_PTR(-ENOMEM
);
3692 __i915_vma_pin(vma
);
3696 void i915_vma_unpin_and_release(struct i915_vma
**p_vma
)
3698 struct i915_vma
*vma
;
3700 vma
= fetch_and_zero(p_vma
);
3704 i915_vma_unpin(vma
);