2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
35 #include <drm/i915_drm.h>
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include "intel_drv.h"
41 #include "intel_frontbuffer.h"
43 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
46 * DOC: Global GTT views
48 * Background and previous state
50 * Historically objects could exists (be bound) in global GTT space only as
51 * singular instances with a view representing all of the object's backing pages
52 * in a linear fashion. This view will be called a normal view.
54 * To support multiple views of the same object, where the number of mapped
55 * pages is not equal to the backing store, or where the layout of the pages
56 * is not linear, concept of a GGTT view was added.
58 * One example of an alternative view is a stereo display driven by a single
59 * image. In this case we would have a framebuffer looking like this
65 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
66 * rendering. In contrast, fed to the display engine would be an alternative
67 * view which could look something like this:
72 * In this example both the size and layout of pages in the alternative view is
73 * different from the normal view.
75 * Implementation and usage
77 * GGTT views are implemented using VMAs and are distinguished via enum
78 * i915_ggtt_view_type and struct i915_ggtt_view.
80 * A new flavour of core GEM functions which work with GGTT bound objects were
81 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
82 * renaming in large amounts of code. They take the struct i915_ggtt_view
83 * parameter encapsulating all metadata required to implement a view.
85 * As a helper for callers which are only interested in the normal view,
86 * globally const i915_ggtt_view_normal singleton instance exists. All old core
87 * GEM API functions, the ones not taking the view parameter, are operating on,
88 * or with the normal GGTT view.
90 * Code wanting to add or use a new GGTT view needs to:
92 * 1. Add a new enum with a suitable name.
93 * 2. Extend the metadata in the i915_ggtt_view structure if required.
94 * 3. Add support to i915_get_vma_pages().
96 * New views are required to build a scatter-gather table from within the
97 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
98 * exists for the lifetime of an VMA.
100 * Core API is designed to have copy semantics which means that passed in
101 * struct i915_ggtt_view does not need to be persistent (left around after
102 * calling the core API functions).
107 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
109 static void gen6_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
111 /* Note that as an uncached mmio write, this should flush the
112 * WCB of the writes into the GGTT before it triggers the invalidate.
114 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
117 static void guc_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
119 gen6_ggtt_invalidate(dev_priv
);
120 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
123 static void gmch_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
125 intel_gtt_chipset_flush();
128 static inline void i915_ggtt_invalidate(struct drm_i915_private
*i915
)
130 i915
->ggtt
.invalidate(i915
);
133 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
136 bool has_aliasing_ppgtt
;
138 bool has_full_48bit_ppgtt
;
140 has_aliasing_ppgtt
= dev_priv
->info
.has_aliasing_ppgtt
;
141 has_full_ppgtt
= dev_priv
->info
.has_full_ppgtt
;
142 has_full_48bit_ppgtt
= dev_priv
->info
.has_full_48bit_ppgtt
;
144 if (intel_vgpu_active(dev_priv
)) {
145 /* emulation is too hard */
146 has_full_ppgtt
= false;
147 has_full_48bit_ppgtt
= false;
150 if (!has_aliasing_ppgtt
)
154 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
155 * execlists, the sole mechanism available to submit work.
157 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
160 if (enable_ppgtt
== 1)
163 if (enable_ppgtt
== 2 && has_full_ppgtt
)
166 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
169 #ifdef CONFIG_INTEL_IOMMU
170 /* Disable ppgtt on SNB if VT-d is on. */
171 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
) {
172 DRM_INFO("Disabling PPGTT because VT-d is on\n");
177 /* Early VLV doesn't have this */
178 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
179 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
183 if (INTEL_GEN(dev_priv
) >= 8 && i915
.enable_execlists
&& has_full_ppgtt
)
184 return has_full_48bit_ppgtt
? 3 : 2;
186 return has_aliasing_ppgtt
? 1 : 0;
189 static int ppgtt_bind_vma(struct i915_vma
*vma
,
190 enum i915_cache_level cache_level
,
196 ret
= vma
->vm
->allocate_va_range(vma
->vm
, vma
->node
.start
, vma
->size
);
200 vma
->pages
= vma
->obj
->mm
.pages
;
202 /* Currently applicable only to VLV */
205 pte_flags
|= PTE_READ_ONLY
;
207 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
208 cache_level
, pte_flags
);
213 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
215 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
218 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
219 enum i915_cache_level level
)
221 gen8_pte_t pte
= _PAGE_PRESENT
| _PAGE_RW
;
225 case I915_CACHE_NONE
:
226 pte
|= PPAT_UNCACHED_INDEX
;
229 pte
|= PPAT_DISPLAY_ELLC_INDEX
;
232 pte
|= PPAT_CACHED_INDEX
;
239 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
240 const enum i915_cache_level level
)
242 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
244 if (level
!= I915_CACHE_NONE
)
245 pde
|= PPAT_CACHED_PDE_INDEX
;
247 pde
|= PPAT_UNCACHED_INDEX
;
251 #define gen8_pdpe_encode gen8_pde_encode
252 #define gen8_pml4e_encode gen8_pde_encode
254 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
255 enum i915_cache_level level
,
258 gen6_pte_t pte
= GEN6_PTE_VALID
;
259 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
262 case I915_CACHE_L3_LLC
:
264 pte
|= GEN6_PTE_CACHE_LLC
;
266 case I915_CACHE_NONE
:
267 pte
|= GEN6_PTE_UNCACHED
;
276 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
277 enum i915_cache_level level
,
280 gen6_pte_t pte
= GEN6_PTE_VALID
;
281 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
284 case I915_CACHE_L3_LLC
:
285 pte
|= GEN7_PTE_CACHE_L3_LLC
;
288 pte
|= GEN6_PTE_CACHE_LLC
;
290 case I915_CACHE_NONE
:
291 pte
|= GEN6_PTE_UNCACHED
;
300 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
301 enum i915_cache_level level
,
304 gen6_pte_t pte
= GEN6_PTE_VALID
;
305 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
307 if (!(flags
& PTE_READ_ONLY
))
308 pte
|= BYT_PTE_WRITEABLE
;
310 if (level
!= I915_CACHE_NONE
)
311 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
316 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
317 enum i915_cache_level level
,
320 gen6_pte_t pte
= GEN6_PTE_VALID
;
321 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
323 if (level
!= I915_CACHE_NONE
)
324 pte
|= HSW_WB_LLC_AGE3
;
329 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
330 enum i915_cache_level level
,
333 gen6_pte_t pte
= GEN6_PTE_VALID
;
334 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
337 case I915_CACHE_NONE
:
340 pte
|= HSW_WT_ELLC_LLC_AGE3
;
343 pte
|= HSW_WB_ELLC_LLC_AGE3
;
350 static struct page
*vm_alloc_page(struct i915_address_space
*vm
, gfp_t gfp
)
354 if (I915_SELFTEST_ONLY(should_fail(&vm
->fault_attr
, 1)))
355 i915_gem_shrink_all(vm
->i915
);
357 if (vm
->free_pages
.nr
)
358 return vm
->free_pages
.pages
[--vm
->free_pages
.nr
];
360 page
= alloc_page(gfp
);
365 set_pages_array_wc(&page
, 1);
370 static void vm_free_pages_release(struct i915_address_space
*vm
)
372 GEM_BUG_ON(!pagevec_count(&vm
->free_pages
));
375 set_pages_array_wb(vm
->free_pages
.pages
,
376 pagevec_count(&vm
->free_pages
));
378 __pagevec_release(&vm
->free_pages
);
381 static void vm_free_page(struct i915_address_space
*vm
, struct page
*page
)
383 if (!pagevec_add(&vm
->free_pages
, page
))
384 vm_free_pages_release(vm
);
387 static int __setup_page_dma(struct i915_address_space
*vm
,
388 struct i915_page_dma
*p
,
391 p
->page
= vm_alloc_page(vm
, gfp
| __GFP_NOWARN
| __GFP_NORETRY
);
392 if (unlikely(!p
->page
))
395 p
->daddr
= dma_map_page(vm
->dma
, p
->page
, 0, PAGE_SIZE
,
396 PCI_DMA_BIDIRECTIONAL
);
397 if (unlikely(dma_mapping_error(vm
->dma
, p
->daddr
))) {
398 vm_free_page(vm
, p
->page
);
405 static int setup_page_dma(struct i915_address_space
*vm
,
406 struct i915_page_dma
*p
)
408 return __setup_page_dma(vm
, p
, I915_GFP_DMA
);
411 static void cleanup_page_dma(struct i915_address_space
*vm
,
412 struct i915_page_dma
*p
)
414 dma_unmap_page(vm
->dma
, p
->daddr
, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
415 vm_free_page(vm
, p
->page
);
418 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
420 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
421 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
422 #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v))
423 #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v))
425 static void fill_page_dma(struct i915_address_space
*vm
,
426 struct i915_page_dma
*p
,
429 u64
* const vaddr
= kmap_atomic(p
->page
);
432 for (i
= 0; i
< 512; i
++)
435 kunmap_atomic(vaddr
);
438 static void fill_page_dma_32(struct i915_address_space
*vm
,
439 struct i915_page_dma
*p
,
442 fill_page_dma(vm
, p
, (u64
)v
<< 32 | v
);
446 setup_scratch_page(struct i915_address_space
*vm
, gfp_t gfp
)
448 return __setup_page_dma(vm
, &vm
->scratch_page
, gfp
| __GFP_ZERO
);
451 static void cleanup_scratch_page(struct i915_address_space
*vm
)
453 cleanup_page_dma(vm
, &vm
->scratch_page
);
456 static struct i915_page_table
*alloc_pt(struct i915_address_space
*vm
)
458 struct i915_page_table
*pt
;
460 pt
= kmalloc(sizeof(*pt
), GFP_KERNEL
| __GFP_NOWARN
);
462 return ERR_PTR(-ENOMEM
);
464 if (unlikely(setup_px(vm
, pt
))) {
466 return ERR_PTR(-ENOMEM
);
473 static void free_pt(struct i915_address_space
*vm
, struct i915_page_table
*pt
)
479 static void gen8_initialize_pt(struct i915_address_space
*vm
,
480 struct i915_page_table
*pt
)
483 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
));
486 static void gen6_initialize_pt(struct i915_address_space
*vm
,
487 struct i915_page_table
*pt
)
490 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0));
493 static struct i915_page_directory
*alloc_pd(struct i915_address_space
*vm
)
495 struct i915_page_directory
*pd
;
497 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
| __GFP_NOWARN
);
499 return ERR_PTR(-ENOMEM
);
501 if (unlikely(setup_px(vm
, pd
))) {
503 return ERR_PTR(-ENOMEM
);
510 static void free_pd(struct i915_address_space
*vm
,
511 struct i915_page_directory
*pd
)
517 static void gen8_initialize_pd(struct i915_address_space
*vm
,
518 struct i915_page_directory
*pd
)
523 gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
));
524 for (i
= 0; i
< I915_PDES
; i
++)
525 pd
->page_table
[i
] = vm
->scratch_pt
;
528 static int __pdp_init(struct i915_address_space
*vm
,
529 struct i915_page_directory_pointer
*pdp
)
531 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
534 pdp
->page_directory
= kmalloc_array(pdpes
, sizeof(*pdp
->page_directory
),
535 GFP_KERNEL
| __GFP_NOWARN
);
536 if (unlikely(!pdp
->page_directory
))
539 for (i
= 0; i
< pdpes
; i
++)
540 pdp
->page_directory
[i
] = vm
->scratch_pd
;
545 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
547 kfree(pdp
->page_directory
);
548 pdp
->page_directory
= NULL
;
551 static inline bool use_4lvl(const struct i915_address_space
*vm
)
553 return i915_vm_is_48bit(vm
);
556 static struct i915_page_directory_pointer
*
557 alloc_pdp(struct i915_address_space
*vm
)
559 struct i915_page_directory_pointer
*pdp
;
562 WARN_ON(!use_4lvl(vm
));
564 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
566 return ERR_PTR(-ENOMEM
);
568 ret
= __pdp_init(vm
, pdp
);
572 ret
= setup_px(vm
, pdp
);
586 static void free_pdp(struct i915_address_space
*vm
,
587 struct i915_page_directory_pointer
*pdp
)
598 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
599 struct i915_page_directory_pointer
*pdp
)
601 gen8_ppgtt_pdpe_t scratch_pdpe
;
603 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
605 fill_px(vm
, pdp
, scratch_pdpe
);
608 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
609 struct i915_pml4
*pml4
)
614 gen8_pml4e_encode(px_dma(vm
->scratch_pdp
), I915_CACHE_LLC
));
615 for (i
= 0; i
< GEN8_PML4ES_PER_PML4
; i
++)
616 pml4
->pdps
[i
] = vm
->scratch_pdp
;
619 /* Broadwell Page Directory Pointer Descriptors */
620 static int gen8_write_pdp(struct drm_i915_gem_request
*req
,
624 struct intel_engine_cs
*engine
= req
->engine
;
629 cs
= intel_ring_begin(req
, 6);
633 *cs
++ = MI_LOAD_REGISTER_IMM(1);
634 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine
, entry
));
635 *cs
++ = upper_32_bits(addr
);
636 *cs
++ = MI_LOAD_REGISTER_IMM(1);
637 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine
, entry
));
638 *cs
++ = lower_32_bits(addr
);
639 intel_ring_advance(req
, cs
);
644 static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt
*ppgtt
,
645 struct drm_i915_gem_request
*req
)
649 for (i
= GEN8_3LVL_PDPES
- 1; i
>= 0; i
--) {
650 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
652 ret
= gen8_write_pdp(req
, i
, pd_daddr
);
660 static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt
*ppgtt
,
661 struct drm_i915_gem_request
*req
)
663 return gen8_write_pdp(req
, 0, px_dma(&ppgtt
->pml4
));
666 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
667 * the page table structures, we mark them dirty so that
668 * context switching/execlist queuing code takes extra steps
669 * to ensure that tlbs are flushed.
671 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
673 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->base
.i915
)->ring_mask
;
676 /* Removes entries from a single page table, releasing it if it's empty.
677 * Caller can use the return value to update higher-level entries.
679 static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm
,
680 struct i915_page_table
*pt
,
681 u64 start
, u64 length
)
683 unsigned int num_entries
= gen8_pte_count(start
, length
);
684 unsigned int pte
= gen8_pte_index(start
);
685 unsigned int pte_end
= pte
+ num_entries
;
686 const gen8_pte_t scratch_pte
=
687 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
690 GEM_BUG_ON(num_entries
> pt
->used_ptes
);
692 pt
->used_ptes
-= num_entries
;
696 vaddr
= kmap_atomic_px(pt
);
697 while (pte
< pte_end
)
698 vaddr
[pte
++] = scratch_pte
;
699 kunmap_atomic(vaddr
);
704 static void gen8_ppgtt_set_pde(struct i915_address_space
*vm
,
705 struct i915_page_directory
*pd
,
706 struct i915_page_table
*pt
,
711 pd
->page_table
[pde
] = pt
;
713 vaddr
= kmap_atomic_px(pd
);
714 vaddr
[pde
] = gen8_pde_encode(px_dma(pt
), I915_CACHE_LLC
);
715 kunmap_atomic(vaddr
);
718 static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm
,
719 struct i915_page_directory
*pd
,
720 u64 start
, u64 length
)
722 struct i915_page_table
*pt
;
725 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
726 GEM_BUG_ON(pt
== vm
->scratch_pt
);
728 if (!gen8_ppgtt_clear_pt(vm
, pt
, start
, length
))
731 gen8_ppgtt_set_pde(vm
, pd
, vm
->scratch_pt
, pde
);
732 GEM_BUG_ON(!pd
->used_pdes
);
738 return !pd
->used_pdes
;
741 static void gen8_ppgtt_set_pdpe(struct i915_address_space
*vm
,
742 struct i915_page_directory_pointer
*pdp
,
743 struct i915_page_directory
*pd
,
746 gen8_ppgtt_pdpe_t
*vaddr
;
748 pdp
->page_directory
[pdpe
] = pd
;
752 vaddr
= kmap_atomic_px(pdp
);
753 vaddr
[pdpe
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
754 kunmap_atomic(vaddr
);
757 /* Removes entries from a single page dir pointer, releasing it if it's empty.
758 * Caller can use the return value to update higher-level entries
760 static bool gen8_ppgtt_clear_pdp(struct i915_address_space
*vm
,
761 struct i915_page_directory_pointer
*pdp
,
762 u64 start
, u64 length
)
764 struct i915_page_directory
*pd
;
767 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
768 GEM_BUG_ON(pd
== vm
->scratch_pd
);
770 if (!gen8_ppgtt_clear_pd(vm
, pd
, start
, length
))
773 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
774 GEM_BUG_ON(!pdp
->used_pdpes
);
780 return !pdp
->used_pdpes
;
783 static void gen8_ppgtt_clear_3lvl(struct i915_address_space
*vm
,
784 u64 start
, u64 length
)
786 gen8_ppgtt_clear_pdp(vm
, &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
789 static void gen8_ppgtt_set_pml4e(struct i915_pml4
*pml4
,
790 struct i915_page_directory_pointer
*pdp
,
793 gen8_ppgtt_pml4e_t
*vaddr
;
795 pml4
->pdps
[pml4e
] = pdp
;
797 vaddr
= kmap_atomic_px(pml4
);
798 vaddr
[pml4e
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
799 kunmap_atomic(vaddr
);
802 /* Removes entries from a single pml4.
803 * This is the top-level structure in 4-level page tables used on gen8+.
804 * Empty entries are always scratch pml4e.
806 static void gen8_ppgtt_clear_4lvl(struct i915_address_space
*vm
,
807 u64 start
, u64 length
)
809 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
810 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
811 struct i915_page_directory_pointer
*pdp
;
814 GEM_BUG_ON(!use_4lvl(vm
));
816 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
817 GEM_BUG_ON(pdp
== vm
->scratch_pdp
);
819 if (!gen8_ppgtt_clear_pdp(vm
, pdp
, start
, length
))
822 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
829 struct scatterlist
*sg
;
833 struct gen8_insert_pte
{
840 static __always_inline
struct gen8_insert_pte
gen8_insert_pte(u64 start
)
842 return (struct gen8_insert_pte
) {
843 gen8_pml4e_index(start
),
844 gen8_pdpe_index(start
),
845 gen8_pde_index(start
),
846 gen8_pte_index(start
),
850 static __always_inline
bool
851 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt
*ppgtt
,
852 struct i915_page_directory_pointer
*pdp
,
853 struct sgt_dma
*iter
,
854 struct gen8_insert_pte
*idx
,
855 enum i915_cache_level cache_level
)
857 struct i915_page_directory
*pd
;
858 const gen8_pte_t pte_encode
= gen8_pte_encode(0, cache_level
);
862 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->base
));
863 pd
= pdp
->page_directory
[idx
->pdpe
];
864 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
866 vaddr
[idx
->pte
] = pte_encode
| iter
->dma
;
868 iter
->dma
+= PAGE_SIZE
;
869 if (iter
->dma
>= iter
->max
) {
870 iter
->sg
= __sg_next(iter
->sg
);
876 iter
->dma
= sg_dma_address(iter
->sg
);
877 iter
->max
= iter
->dma
+ iter
->sg
->length
;
880 if (++idx
->pte
== GEN8_PTES
) {
883 if (++idx
->pde
== I915_PDES
) {
886 /* Limited by sg length for 3lvl */
887 if (++idx
->pdpe
== GEN8_PML4ES_PER_PML4
) {
893 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->base
));
894 pd
= pdp
->page_directory
[idx
->pdpe
];
897 kunmap_atomic(vaddr
);
898 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
901 kunmap_atomic(vaddr
);
906 static void gen8_ppgtt_insert_3lvl(struct i915_address_space
*vm
,
907 struct sg_table
*pages
,
909 enum i915_cache_level cache_level
,
912 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
913 struct sgt_dma iter
= {
915 .dma
= sg_dma_address(iter
.sg
),
916 .max
= iter
.dma
+ iter
.sg
->length
,
918 struct gen8_insert_pte idx
= gen8_insert_pte(start
);
920 gen8_ppgtt_insert_pte_entries(ppgtt
, &ppgtt
->pdp
, &iter
, &idx
,
924 static void gen8_ppgtt_insert_4lvl(struct i915_address_space
*vm
,
925 struct sg_table
*pages
,
927 enum i915_cache_level cache_level
,
930 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
931 struct sgt_dma iter
= {
933 .dma
= sg_dma_address(iter
.sg
),
934 .max
= iter
.dma
+ iter
.sg
->length
,
936 struct i915_page_directory_pointer
**pdps
= ppgtt
->pml4
.pdps
;
937 struct gen8_insert_pte idx
= gen8_insert_pte(start
);
939 while (gen8_ppgtt_insert_pte_entries(ppgtt
, pdps
[idx
.pml4e
++], &iter
,
941 GEM_BUG_ON(idx
.pml4e
>= GEN8_PML4ES_PER_PML4
);
944 static void gen8_free_page_tables(struct i915_address_space
*vm
,
945 struct i915_page_directory
*pd
)
952 for (i
= 0; i
< I915_PDES
; i
++) {
953 if (pd
->page_table
[i
] != vm
->scratch_pt
)
954 free_pt(vm
, pd
->page_table
[i
]);
958 static int gen8_init_scratch(struct i915_address_space
*vm
)
962 ret
= setup_scratch_page(vm
, I915_GFP_DMA
);
966 vm
->scratch_pt
= alloc_pt(vm
);
967 if (IS_ERR(vm
->scratch_pt
)) {
968 ret
= PTR_ERR(vm
->scratch_pt
);
969 goto free_scratch_page
;
972 vm
->scratch_pd
= alloc_pd(vm
);
973 if (IS_ERR(vm
->scratch_pd
)) {
974 ret
= PTR_ERR(vm
->scratch_pd
);
979 vm
->scratch_pdp
= alloc_pdp(vm
);
980 if (IS_ERR(vm
->scratch_pdp
)) {
981 ret
= PTR_ERR(vm
->scratch_pdp
);
986 gen8_initialize_pt(vm
, vm
->scratch_pt
);
987 gen8_initialize_pd(vm
, vm
->scratch_pd
);
989 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
994 free_pd(vm
, vm
->scratch_pd
);
996 free_pt(vm
, vm
->scratch_pt
);
998 cleanup_scratch_page(vm
);
1003 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
1005 struct i915_address_space
*vm
= &ppgtt
->base
;
1006 struct drm_i915_private
*dev_priv
= vm
->i915
;
1007 enum vgt_g2v_type msg
;
1011 const u64 daddr
= px_dma(&ppgtt
->pml4
);
1013 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
1014 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
1016 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
1017 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
1019 for (i
= 0; i
< GEN8_3LVL_PDPES
; i
++) {
1020 const u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1022 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
1023 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
1026 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
1027 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
1030 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
1035 static void gen8_free_scratch(struct i915_address_space
*vm
)
1038 free_pdp(vm
, vm
->scratch_pdp
);
1039 free_pd(vm
, vm
->scratch_pd
);
1040 free_pt(vm
, vm
->scratch_pt
);
1041 cleanup_scratch_page(vm
);
1044 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space
*vm
,
1045 struct i915_page_directory_pointer
*pdp
)
1047 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
1050 for (i
= 0; i
< pdpes
; i
++) {
1051 if (pdp
->page_directory
[i
] == vm
->scratch_pd
)
1054 gen8_free_page_tables(vm
, pdp
->page_directory
[i
]);
1055 free_pd(vm
, pdp
->page_directory
[i
]);
1061 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
1065 for (i
= 0; i
< GEN8_PML4ES_PER_PML4
; i
++) {
1066 if (ppgtt
->pml4
.pdps
[i
] == ppgtt
->base
.scratch_pdp
)
1069 gen8_ppgtt_cleanup_3lvl(&ppgtt
->base
, ppgtt
->pml4
.pdps
[i
]);
1072 cleanup_px(&ppgtt
->base
, &ppgtt
->pml4
);
1075 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
1077 struct drm_i915_private
*dev_priv
= vm
->i915
;
1078 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1080 if (intel_vgpu_active(dev_priv
))
1081 gen8_ppgtt_notify_vgt(ppgtt
, false);
1084 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1086 gen8_ppgtt_cleanup_3lvl(&ppgtt
->base
, &ppgtt
->pdp
);
1088 gen8_free_scratch(vm
);
1091 static int gen8_ppgtt_alloc_pd(struct i915_address_space
*vm
,
1092 struct i915_page_directory
*pd
,
1093 u64 start
, u64 length
)
1095 struct i915_page_table
*pt
;
1099 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1100 if (pt
== vm
->scratch_pt
) {
1105 gen8_initialize_pt(vm
, pt
);
1107 gen8_ppgtt_set_pde(vm
, pd
, pt
, pde
);
1109 GEM_BUG_ON(pd
->used_pdes
> I915_PDES
);
1112 pt
->used_ptes
+= gen8_pte_count(start
, length
);
1117 gen8_ppgtt_clear_pd(vm
, pd
, from
, start
- from
);
1121 static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm
,
1122 struct i915_page_directory_pointer
*pdp
,
1123 u64 start
, u64 length
)
1125 struct i915_page_directory
*pd
;
1130 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1131 if (pd
== vm
->scratch_pd
) {
1136 gen8_initialize_pd(vm
, pd
);
1137 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1139 GEM_BUG_ON(pdp
->used_pdpes
> i915_pdpes_per_pdp(vm
));
1141 mark_tlbs_dirty(i915_vm_to_ppgtt(vm
));
1144 ret
= gen8_ppgtt_alloc_pd(vm
, pd
, start
, length
);
1152 if (!pd
->used_pdes
) {
1153 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1154 GEM_BUG_ON(!pdp
->used_pdpes
);
1159 gen8_ppgtt_clear_pdp(vm
, pdp
, from
, start
- from
);
1163 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space
*vm
,
1164 u64 start
, u64 length
)
1166 return gen8_ppgtt_alloc_pdp(vm
,
1167 &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
1170 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space
*vm
,
1171 u64 start
, u64 length
)
1173 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1174 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1175 struct i915_page_directory_pointer
*pdp
;
1180 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1181 if (pml4
->pdps
[pml4e
] == vm
->scratch_pdp
) {
1182 pdp
= alloc_pdp(vm
);
1186 gen8_initialize_pdp(vm
, pdp
);
1187 gen8_ppgtt_set_pml4e(pml4
, pdp
, pml4e
);
1190 ret
= gen8_ppgtt_alloc_pdp(vm
, pdp
, start
, length
);
1198 if (!pdp
->used_pdpes
) {
1199 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
1203 gen8_ppgtt_clear_4lvl(vm
, from
, start
- from
);
1207 static void gen8_dump_pdp(struct i915_hw_ppgtt
*ppgtt
,
1208 struct i915_page_directory_pointer
*pdp
,
1209 u64 start
, u64 length
,
1210 gen8_pte_t scratch_pte
,
1213 struct i915_address_space
*vm
= &ppgtt
->base
;
1214 struct i915_page_directory
*pd
;
1217 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1218 struct i915_page_table
*pt
;
1219 u64 pd_len
= length
;
1220 u64 pd_start
= start
;
1223 if (pdp
->page_directory
[pdpe
] == ppgtt
->base
.scratch_pd
)
1226 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1227 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1229 gen8_pte_t
*pt_vaddr
;
1231 if (pd
->page_table
[pde
] == ppgtt
->base
.scratch_pt
)
1234 pt_vaddr
= kmap_atomic_px(pt
);
1235 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1236 u64 va
= (pdpe
<< GEN8_PDPE_SHIFT
|
1237 pde
<< GEN8_PDE_SHIFT
|
1238 pte
<< GEN8_PTE_SHIFT
);
1242 for (i
= 0; i
< 4; i
++)
1243 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1248 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1249 for (i
= 0; i
< 4; i
++) {
1250 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1251 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1253 seq_puts(m
, " SCRATCH ");
1257 kunmap_atomic(pt_vaddr
);
1262 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1264 struct i915_address_space
*vm
= &ppgtt
->base
;
1265 const gen8_pte_t scratch_pte
=
1266 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
1267 u64 start
= 0, length
= ppgtt
->base
.total
;
1271 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1272 struct i915_page_directory_pointer
*pdp
;
1274 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1275 if (pml4
->pdps
[pml4e
] == ppgtt
->base
.scratch_pdp
)
1278 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1279 gen8_dump_pdp(ppgtt
, pdp
, start
, length
, scratch_pte
, m
);
1282 gen8_dump_pdp(ppgtt
, &ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1286 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt
*ppgtt
)
1288 struct i915_address_space
*vm
= &ppgtt
->base
;
1289 struct i915_page_directory_pointer
*pdp
= &ppgtt
->pdp
;
1290 struct i915_page_directory
*pd
;
1291 u64 start
= 0, length
= ppgtt
->base
.total
;
1295 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1300 gen8_initialize_pd(vm
, pd
);
1301 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1305 pdp
->used_pdpes
++; /* never remove */
1310 gen8_for_each_pdpe(pd
, pdp
, from
, start
, pdpe
) {
1311 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1314 pdp
->used_pdpes
= 0;
1319 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1320 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1321 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1325 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1327 struct i915_address_space
*vm
= &ppgtt
->base
;
1328 struct drm_i915_private
*dev_priv
= vm
->i915
;
1331 ppgtt
->base
.total
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1335 ret
= gen8_init_scratch(&ppgtt
->base
);
1337 ppgtt
->base
.total
= 0;
1341 /* There are only few exceptions for gen >=6. chv and bxt.
1342 * And we are not sure about the latter so play safe for now.
1344 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
1345 ppgtt
->base
.pt_kmap_wc
= true;
1348 ret
= setup_px(&ppgtt
->base
, &ppgtt
->pml4
);
1352 gen8_initialize_pml4(&ppgtt
->base
, &ppgtt
->pml4
);
1354 ppgtt
->switch_mm
= gen8_mm_switch_4lvl
;
1355 ppgtt
->base
.allocate_va_range
= gen8_ppgtt_alloc_4lvl
;
1356 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_4lvl
;
1357 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_4lvl
;
1359 ret
= __pdp_init(&ppgtt
->base
, &ppgtt
->pdp
);
1363 if (intel_vgpu_active(dev_priv
)) {
1364 ret
= gen8_preallocate_top_level_pdp(ppgtt
);
1366 __pdp_fini(&ppgtt
->pdp
);
1371 ppgtt
->switch_mm
= gen8_mm_switch_3lvl
;
1372 ppgtt
->base
.allocate_va_range
= gen8_ppgtt_alloc_3lvl
;
1373 ppgtt
->base
.insert_entries
= gen8_ppgtt_insert_3lvl
;
1374 ppgtt
->base
.clear_range
= gen8_ppgtt_clear_3lvl
;
1377 if (intel_vgpu_active(dev_priv
))
1378 gen8_ppgtt_notify_vgt(ppgtt
, true);
1380 ppgtt
->base
.cleanup
= gen8_ppgtt_cleanup
;
1381 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1382 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1383 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1388 gen8_free_scratch(&ppgtt
->base
);
1392 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1394 struct i915_address_space
*vm
= &ppgtt
->base
;
1395 struct i915_page_table
*unused
;
1396 gen6_pte_t scratch_pte
;
1397 u32 pd_entry
, pte
, pde
;
1398 u32 start
= 0, length
= ppgtt
->base
.total
;
1400 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
1403 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1405 gen6_pte_t
*pt_vaddr
;
1406 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1407 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1408 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1410 if (pd_entry
!= expected
)
1411 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1415 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1417 pt_vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[pde
]);
1419 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1421 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1425 for (i
= 0; i
< 4; i
++)
1426 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1431 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1432 for (i
= 0; i
< 4; i
++) {
1433 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1434 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1436 seq_puts(m
, " SCRATCH ");
1440 kunmap_atomic(pt_vaddr
);
1444 /* Write pde (index) from the page directory @pd to the page table @pt */
1445 static inline void gen6_write_pde(const struct i915_hw_ppgtt
*ppgtt
,
1446 const unsigned int pde
,
1447 const struct i915_page_table
*pt
)
1449 /* Caller needs to make sure the write completes if necessary */
1450 writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt
)) | GEN6_PDE_VALID
,
1451 ppgtt
->pd_addr
+ pde
);
1454 /* Write all the page tables found in the ppgtt structure to incrementing page
1456 static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt
,
1457 u32 start
, u32 length
)
1459 struct i915_page_table
*pt
;
1462 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
)
1463 gen6_write_pde(ppgtt
, pde
, pt
);
1465 mark_tlbs_dirty(ppgtt
);
1469 static inline u32
get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1471 GEM_BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1472 return ppgtt
->pd
.base
.ggtt_offset
<< 10;
1475 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1476 struct drm_i915_gem_request
*req
)
1478 struct intel_engine_cs
*engine
= req
->engine
;
1481 /* NB: TLBs must be flushed and invalidated before a switch */
1482 cs
= intel_ring_begin(req
, 6);
1486 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1487 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1488 *cs
++ = PP_DIR_DCLV_2G
;
1489 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1490 *cs
++ = get_pd_offset(ppgtt
);
1492 intel_ring_advance(req
, cs
);
1497 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1498 struct drm_i915_gem_request
*req
)
1500 struct intel_engine_cs
*engine
= req
->engine
;
1503 /* NB: TLBs must be flushed and invalidated before a switch */
1504 cs
= intel_ring_begin(req
, 6);
1508 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1509 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1510 *cs
++ = PP_DIR_DCLV_2G
;
1511 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1512 *cs
++ = get_pd_offset(ppgtt
);
1514 intel_ring_advance(req
, cs
);
1519 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1520 struct drm_i915_gem_request
*req
)
1522 struct intel_engine_cs
*engine
= req
->engine
;
1523 struct drm_i915_private
*dev_priv
= req
->i915
;
1525 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1526 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1530 static void gen8_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1532 struct intel_engine_cs
*engine
;
1533 enum intel_engine_id id
;
1535 for_each_engine(engine
, dev_priv
, id
) {
1536 u32 four_level
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1537 GEN8_GFX_PPGTT_48B
: 0;
1538 I915_WRITE(RING_MODE_GEN7(engine
),
1539 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1543 static void gen7_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1545 struct intel_engine_cs
*engine
;
1546 u32 ecochk
, ecobits
;
1547 enum intel_engine_id id
;
1549 ecobits
= I915_READ(GAC_ECO_BITS
);
1550 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1552 ecochk
= I915_READ(GAM_ECOCHK
);
1553 if (IS_HASWELL(dev_priv
)) {
1554 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1556 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1557 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1559 I915_WRITE(GAM_ECOCHK
, ecochk
);
1561 for_each_engine(engine
, dev_priv
, id
) {
1562 /* GFX_MODE is per-ring on gen7+ */
1563 I915_WRITE(RING_MODE_GEN7(engine
),
1564 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1568 static void gen6_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1570 u32 ecochk
, gab_ctl
, ecobits
;
1572 ecobits
= I915_READ(GAC_ECO_BITS
);
1573 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1574 ECOBITS_PPGTT_CACHE64B
);
1576 gab_ctl
= I915_READ(GAB_CTL
);
1577 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1579 ecochk
= I915_READ(GAM_ECOCHK
);
1580 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1582 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1585 /* PPGTT support for Sandybdrige/Gen6 and later */
1586 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1587 u64 start
, u64 length
)
1589 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1590 unsigned int first_entry
= start
>> PAGE_SHIFT
;
1591 unsigned int pde
= first_entry
/ GEN6_PTES
;
1592 unsigned int pte
= first_entry
% GEN6_PTES
;
1593 unsigned int num_entries
= length
>> PAGE_SHIFT
;
1594 gen6_pte_t scratch_pte
=
1595 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0);
1597 while (num_entries
) {
1598 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
++];
1599 unsigned int end
= min(pte
+ num_entries
, GEN6_PTES
);
1602 num_entries
-= end
- pte
;
1604 /* Note that the hw doesn't support removing PDE on the fly
1605 * (they are cached inside the context with no means to
1606 * invalidate the cache), so we can only reset the PTE
1607 * entries back to scratch.
1610 vaddr
= kmap_atomic_px(pt
);
1612 vaddr
[pte
++] = scratch_pte
;
1613 } while (pte
< end
);
1614 kunmap_atomic(vaddr
);
1620 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1621 struct sg_table
*pages
,
1623 enum i915_cache_level cache_level
,
1626 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1627 unsigned first_entry
= start
>> PAGE_SHIFT
;
1628 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1629 unsigned act_pte
= first_entry
% GEN6_PTES
;
1630 const u32 pte_encode
= vm
->pte_encode(0, cache_level
, flags
);
1631 struct sgt_dma iter
;
1634 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[act_pt
]);
1635 iter
.sg
= pages
->sgl
;
1636 iter
.dma
= sg_dma_address(iter
.sg
);
1637 iter
.max
= iter
.dma
+ iter
.sg
->length
;
1639 vaddr
[act_pte
] = pte_encode
| GEN6_PTE_ADDR_ENCODE(iter
.dma
);
1641 iter
.dma
+= PAGE_SIZE
;
1642 if (iter
.dma
== iter
.max
) {
1643 iter
.sg
= __sg_next(iter
.sg
);
1647 iter
.dma
= sg_dma_address(iter
.sg
);
1648 iter
.max
= iter
.dma
+ iter
.sg
->length
;
1651 if (++act_pte
== GEN6_PTES
) {
1652 kunmap_atomic(vaddr
);
1653 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[++act_pt
]);
1657 kunmap_atomic(vaddr
);
1660 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1661 u64 start
, u64 length
)
1663 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1664 struct i915_page_table
*pt
;
1669 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1670 if (pt
== vm
->scratch_pt
) {
1675 gen6_initialize_pt(vm
, pt
);
1676 ppgtt
->pd
.page_table
[pde
] = pt
;
1677 gen6_write_pde(ppgtt
, pde
, pt
);
1683 mark_tlbs_dirty(ppgtt
);
1690 gen6_ppgtt_clear_range(vm
, from
, start
);
1694 static int gen6_init_scratch(struct i915_address_space
*vm
)
1698 ret
= setup_scratch_page(vm
, I915_GFP_DMA
);
1702 vm
->scratch_pt
= alloc_pt(vm
);
1703 if (IS_ERR(vm
->scratch_pt
)) {
1704 cleanup_scratch_page(vm
);
1705 return PTR_ERR(vm
->scratch_pt
);
1708 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1713 static void gen6_free_scratch(struct i915_address_space
*vm
)
1715 free_pt(vm
, vm
->scratch_pt
);
1716 cleanup_scratch_page(vm
);
1719 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1721 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1722 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1723 struct i915_page_table
*pt
;
1726 drm_mm_remove_node(&ppgtt
->node
);
1728 gen6_for_all_pdes(pt
, pd
, pde
)
1729 if (pt
!= vm
->scratch_pt
)
1732 gen6_free_scratch(vm
);
1735 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1737 struct i915_address_space
*vm
= &ppgtt
->base
;
1738 struct drm_i915_private
*dev_priv
= ppgtt
->base
.i915
;
1739 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1742 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1743 * allocator works in address space sizes, so it's multiplied by page
1744 * size. We allocate at the top of the GTT to avoid fragmentation.
1746 BUG_ON(!drm_mm_initialized(&ggtt
->base
.mm
));
1748 ret
= gen6_init_scratch(vm
);
1752 ret
= i915_gem_gtt_insert(&ggtt
->base
, &ppgtt
->node
,
1753 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1754 I915_COLOR_UNEVICTABLE
,
1755 0, ggtt
->base
.total
,
1760 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
1761 DRM_DEBUG("Forced to use aperture for PDEs\n");
1763 ppgtt
->pd
.base
.ggtt_offset
=
1764 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
1766 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
1767 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
1772 gen6_free_scratch(vm
);
1776 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
1778 return gen6_ppgtt_allocate_page_directories(ppgtt
);
1781 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
1782 u64 start
, u64 length
)
1784 struct i915_page_table
*unused
;
1787 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
1788 ppgtt
->pd
.page_table
[pde
] = ppgtt
->base
.scratch_pt
;
1791 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1793 struct drm_i915_private
*dev_priv
= ppgtt
->base
.i915
;
1794 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1797 ppgtt
->base
.pte_encode
= ggtt
->base
.pte_encode
;
1798 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev_priv
))
1799 ppgtt
->switch_mm
= gen6_mm_switch
;
1800 else if (IS_HASWELL(dev_priv
))
1801 ppgtt
->switch_mm
= hsw_mm_switch
;
1802 else if (IS_GEN7(dev_priv
))
1803 ppgtt
->switch_mm
= gen7_mm_switch
;
1807 ret
= gen6_ppgtt_alloc(ppgtt
);
1811 ppgtt
->base
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
1813 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->base
.total
);
1814 gen6_write_page_range(ppgtt
, 0, ppgtt
->base
.total
);
1816 ret
= gen6_alloc_va_range(&ppgtt
->base
, 0, ppgtt
->base
.total
);
1818 gen6_ppgtt_cleanup(&ppgtt
->base
);
1822 ppgtt
->base
.clear_range
= gen6_ppgtt_clear_range
;
1823 ppgtt
->base
.insert_entries
= gen6_ppgtt_insert_entries
;
1824 ppgtt
->base
.unbind_vma
= ppgtt_unbind_vma
;
1825 ppgtt
->base
.bind_vma
= ppgtt_bind_vma
;
1826 ppgtt
->base
.cleanup
= gen6_ppgtt_cleanup
;
1827 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
1829 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1830 ppgtt
->node
.size
>> 20,
1831 ppgtt
->node
.start
/ PAGE_SIZE
);
1833 DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
1834 ppgtt
->pd
.base
.ggtt_offset
<< 10);
1839 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
1840 struct drm_i915_private
*dev_priv
)
1842 ppgtt
->base
.i915
= dev_priv
;
1843 ppgtt
->base
.dma
= &dev_priv
->drm
.pdev
->dev
;
1845 if (INTEL_INFO(dev_priv
)->gen
< 8)
1846 return gen6_ppgtt_init(ppgtt
);
1848 return gen8_ppgtt_init(ppgtt
);
1851 static void i915_address_space_init(struct i915_address_space
*vm
,
1852 struct drm_i915_private
*dev_priv
,
1855 i915_gem_timeline_init(dev_priv
, &vm
->timeline
, name
);
1857 drm_mm_init(&vm
->mm
, 0, vm
->total
);
1858 vm
->mm
.head_node
.color
= I915_COLOR_UNEVICTABLE
;
1860 INIT_LIST_HEAD(&vm
->active_list
);
1861 INIT_LIST_HEAD(&vm
->inactive_list
);
1862 INIT_LIST_HEAD(&vm
->unbound_list
);
1864 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
1865 pagevec_init(&vm
->free_pages
, false);
1868 static void i915_address_space_fini(struct i915_address_space
*vm
)
1870 if (pagevec_count(&vm
->free_pages
))
1871 vm_free_pages_release(vm
);
1873 i915_gem_timeline_fini(&vm
->timeline
);
1874 drm_mm_takedown(&vm
->mm
);
1875 list_del(&vm
->global_link
);
1878 static void gtt_write_workarounds(struct drm_i915_private
*dev_priv
)
1880 /* This function is for gtt related workarounds. This function is
1881 * called on driver load and after a GPU reset, so you can place
1882 * workarounds here even if they get overwritten by GPU reset.
1884 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
1885 if (IS_BROADWELL(dev_priv
))
1886 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
1887 else if (IS_CHERRYVIEW(dev_priv
))
1888 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
1889 else if (IS_GEN9_BC(dev_priv
))
1890 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
1891 else if (IS_GEN9_LP(dev_priv
))
1892 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
1895 int i915_ppgtt_init_hw(struct drm_i915_private
*dev_priv
)
1897 gtt_write_workarounds(dev_priv
);
1899 /* In the case of execlists, PPGTT is enabled by the context descriptor
1900 * and the PDPs are contained within the context itself. We don't
1901 * need to do anything here. */
1902 if (i915
.enable_execlists
)
1905 if (!USES_PPGTT(dev_priv
))
1908 if (IS_GEN6(dev_priv
))
1909 gen6_ppgtt_enable(dev_priv
);
1910 else if (IS_GEN7(dev_priv
))
1911 gen7_ppgtt_enable(dev_priv
);
1912 else if (INTEL_GEN(dev_priv
) >= 8)
1913 gen8_ppgtt_enable(dev_priv
);
1915 MISSING_CASE(INTEL_GEN(dev_priv
));
1920 struct i915_hw_ppgtt
*
1921 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
1922 struct drm_i915_file_private
*fpriv
,
1925 struct i915_hw_ppgtt
*ppgtt
;
1928 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
1930 return ERR_PTR(-ENOMEM
);
1932 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
1935 return ERR_PTR(ret
);
1938 kref_init(&ppgtt
->ref
);
1939 i915_address_space_init(&ppgtt
->base
, dev_priv
, name
);
1940 ppgtt
->base
.file
= fpriv
;
1942 trace_i915_ppgtt_create(&ppgtt
->base
);
1947 void i915_ppgtt_close(struct i915_address_space
*vm
)
1949 struct list_head
*phases
[] = {
1956 GEM_BUG_ON(vm
->closed
);
1959 for (phase
= phases
; *phase
; phase
++) {
1960 struct i915_vma
*vma
, *vn
;
1962 list_for_each_entry_safe(vma
, vn
, *phase
, vm_link
)
1963 if (!i915_vma_is_closed(vma
))
1964 i915_vma_close(vma
);
1968 void i915_ppgtt_release(struct kref
*kref
)
1970 struct i915_hw_ppgtt
*ppgtt
=
1971 container_of(kref
, struct i915_hw_ppgtt
, ref
);
1973 trace_i915_ppgtt_release(&ppgtt
->base
);
1975 /* vmas should already be unbound and destroyed */
1976 WARN_ON(!list_empty(&ppgtt
->base
.active_list
));
1977 WARN_ON(!list_empty(&ppgtt
->base
.inactive_list
));
1978 WARN_ON(!list_empty(&ppgtt
->base
.unbound_list
));
1980 ppgtt
->base
.cleanup(&ppgtt
->base
);
1981 i915_address_space_fini(&ppgtt
->base
);
1985 /* Certain Gen5 chipsets require require idling the GPU before
1986 * unmapping anything from the GTT when VT-d is enabled.
1988 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
1990 #ifdef CONFIG_INTEL_IOMMU
1991 /* Query intel_iommu to see if we need the workaround. Presumably that
1994 if (IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_iommu_gfx_mapped
)
2000 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2002 struct intel_engine_cs
*engine
;
2003 enum intel_engine_id id
;
2005 if (INTEL_INFO(dev_priv
)->gen
< 6)
2008 for_each_engine(engine
, dev_priv
, id
) {
2010 fault_reg
= I915_READ(RING_FAULT_REG(engine
));
2011 if (fault_reg
& RING_FAULT_VALID
) {
2012 DRM_DEBUG_DRIVER("Unexpected fault\n"
2014 "\tAddress space: %s\n"
2017 fault_reg
& PAGE_MASK
,
2018 fault_reg
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2019 RING_FAULT_SRCID(fault_reg
),
2020 RING_FAULT_FAULT_TYPE(fault_reg
));
2021 I915_WRITE(RING_FAULT_REG(engine
),
2022 fault_reg
& ~RING_FAULT_VALID
);
2026 /* Engine specific init may not have been done till this point. */
2027 if (dev_priv
->engine
[RCS
])
2028 POSTING_READ(RING_FAULT_REG(dev_priv
->engine
[RCS
]));
2031 void i915_gem_suspend_gtt_mappings(struct drm_i915_private
*dev_priv
)
2033 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2035 /* Don't bother messing with faults pre GEN6 as we have little
2036 * documentation supporting that it's a good idea.
2038 if (INTEL_GEN(dev_priv
) < 6)
2041 i915_check_and_clear_faults(dev_priv
);
2043 ggtt
->base
.clear_range(&ggtt
->base
, 0, ggtt
->base
.total
);
2045 i915_ggtt_invalidate(dev_priv
);
2048 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object
*obj
,
2049 struct sg_table
*pages
)
2052 if (dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
2053 pages
->sgl
, pages
->nents
,
2054 PCI_DMA_BIDIRECTIONAL
))
2057 /* If the DMA remap fails, one cause can be that we have
2058 * too many objects pinned in a small remapping table,
2059 * such as swiotlb. Incrementally purge all other objects and
2060 * try again - if there are no more pages to remove from
2061 * the DMA remapper, i915_gem_shrink will return 0.
2063 GEM_BUG_ON(obj
->mm
.pages
== pages
);
2064 } while (i915_gem_shrink(to_i915(obj
->base
.dev
),
2065 obj
->base
.size
>> PAGE_SHIFT
,
2067 I915_SHRINK_UNBOUND
|
2068 I915_SHRINK_ACTIVE
));
2073 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2078 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2081 enum i915_cache_level level
,
2084 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2085 gen8_pte_t __iomem
*pte
=
2086 (gen8_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2088 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
));
2090 ggtt
->invalidate(vm
->i915
);
2093 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2094 struct sg_table
*st
,
2096 enum i915_cache_level level
,
2099 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2100 struct sgt_iter sgt_iter
;
2101 gen8_pte_t __iomem
*gtt_entries
;
2102 const gen8_pte_t pte_encode
= gen8_pte_encode(0, level
);
2105 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
;
2106 gtt_entries
+= start
>> PAGE_SHIFT
;
2107 for_each_sgt_dma(addr
, sgt_iter
, st
)
2108 gen8_set_pte(gtt_entries
++, pte_encode
| addr
);
2112 /* This next bit makes the above posting read even more important. We
2113 * want to flush the TLBs only after we're certain all the PTE updates
2116 ggtt
->invalidate(vm
->i915
);
2119 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2122 enum i915_cache_level level
,
2125 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2126 gen6_pte_t __iomem
*pte
=
2127 (gen6_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2129 iowrite32(vm
->pte_encode(addr
, level
, flags
), pte
);
2131 ggtt
->invalidate(vm
->i915
);
2135 * Binds an object into the global gtt with the specified cache level. The object
2136 * will be accessible to the GPU via commands whose operands reference offsets
2137 * within the global GTT as well as accessible by the GPU through the GMADR
2138 * mapped BAR (dev_priv->mm.gtt->gtt).
2140 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2141 struct sg_table
*st
,
2143 enum i915_cache_level level
,
2146 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2147 gen6_pte_t __iomem
*entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
;
2148 unsigned int i
= start
>> PAGE_SHIFT
;
2149 struct sgt_iter iter
;
2151 for_each_sgt_dma(addr
, iter
, st
)
2152 iowrite32(vm
->pte_encode(addr
, level
, flags
), &entries
[i
++]);
2155 /* This next bit makes the above posting read even more important. We
2156 * want to flush the TLBs only after we're certain all the PTE updates
2159 ggtt
->invalidate(vm
->i915
);
2162 static void nop_clear_range(struct i915_address_space
*vm
,
2163 u64 start
, u64 length
)
2167 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2168 u64 start
, u64 length
)
2170 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2171 unsigned first_entry
= start
>> PAGE_SHIFT
;
2172 unsigned num_entries
= length
>> PAGE_SHIFT
;
2173 const gen8_pte_t scratch_pte
=
2174 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
2175 gen8_pte_t __iomem
*gtt_base
=
2176 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2177 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2180 if (WARN(num_entries
> max_entries
,
2181 "First entry = %d; Num entries = %d (max=%d)\n",
2182 first_entry
, num_entries
, max_entries
))
2183 num_entries
= max_entries
;
2185 for (i
= 0; i
< num_entries
; i
++)
2186 gen8_set_pte(>t_base
[i
], scratch_pte
);
2189 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2190 u64 start
, u64 length
)
2192 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2193 unsigned first_entry
= start
>> PAGE_SHIFT
;
2194 unsigned num_entries
= length
>> PAGE_SHIFT
;
2195 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2196 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2197 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2200 if (WARN(num_entries
> max_entries
,
2201 "First entry = %d; Num entries = %d (max=%d)\n",
2202 first_entry
, num_entries
, max_entries
))
2203 num_entries
= max_entries
;
2205 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
2208 for (i
= 0; i
< num_entries
; i
++)
2209 iowrite32(scratch_pte
, >t_base
[i
]);
2212 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2215 enum i915_cache_level cache_level
,
2218 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2219 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2221 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2224 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2225 struct sg_table
*pages
,
2227 enum i915_cache_level cache_level
,
2230 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2231 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2233 intel_gtt_insert_sg_entries(pages
, start
>> PAGE_SHIFT
, flags
);
2236 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2237 u64 start
, u64 length
)
2239 intel_gtt_clear_range(start
>> PAGE_SHIFT
, length
>> PAGE_SHIFT
);
2242 static int ggtt_bind_vma(struct i915_vma
*vma
,
2243 enum i915_cache_level cache_level
,
2246 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2247 struct drm_i915_gem_object
*obj
= vma
->obj
;
2250 if (unlikely(!vma
->pages
)) {
2251 int ret
= i915_get_ggtt_vma_pages(vma
);
2256 /* Currently applicable only to VLV */
2259 pte_flags
|= PTE_READ_ONLY
;
2261 intel_runtime_pm_get(i915
);
2262 vma
->vm
->insert_entries(vma
->vm
, vma
->pages
, vma
->node
.start
,
2263 cache_level
, pte_flags
);
2264 intel_runtime_pm_put(i915
);
2267 * Without aliasing PPGTT there's no difference between
2268 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2269 * upgrade to both bound if we bind either to avoid double-binding.
2271 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2276 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2278 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2280 intel_runtime_pm_get(i915
);
2281 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2282 intel_runtime_pm_put(i915
);
2285 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2286 enum i915_cache_level cache_level
,
2289 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2293 if (unlikely(!vma
->pages
)) {
2294 ret
= i915_get_ggtt_vma_pages(vma
);
2299 /* Currently applicable only to VLV */
2301 if (vma
->obj
->gt_ro
)
2302 pte_flags
|= PTE_READ_ONLY
;
2304 if (flags
& I915_VMA_LOCAL_BIND
) {
2305 struct i915_hw_ppgtt
*appgtt
= i915
->mm
.aliasing_ppgtt
;
2307 if (appgtt
->base
.allocate_va_range
) {
2308 ret
= appgtt
->base
.allocate_va_range(&appgtt
->base
,
2315 appgtt
->base
.insert_entries(&appgtt
->base
,
2316 vma
->pages
, vma
->node
.start
,
2317 cache_level
, pte_flags
);
2320 if (flags
& I915_VMA_GLOBAL_BIND
) {
2321 intel_runtime_pm_get(i915
);
2322 vma
->vm
->insert_entries(vma
->vm
,
2323 vma
->pages
, vma
->node
.start
,
2324 cache_level
, pte_flags
);
2325 intel_runtime_pm_put(i915
);
2331 if (!(vma
->flags
& (I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
))) {
2332 if (vma
->pages
!= vma
->obj
->mm
.pages
) {
2333 GEM_BUG_ON(!vma
->pages
);
2334 sg_free_table(vma
->pages
);
2342 static void aliasing_gtt_unbind_vma(struct i915_vma
*vma
)
2344 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2346 if (vma
->flags
& I915_VMA_GLOBAL_BIND
) {
2347 intel_runtime_pm_get(i915
);
2348 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2349 intel_runtime_pm_put(i915
);
2352 if (vma
->flags
& I915_VMA_LOCAL_BIND
) {
2353 struct i915_address_space
*vm
= &i915
->mm
.aliasing_ppgtt
->base
;
2355 vm
->clear_range(vm
, vma
->node
.start
, vma
->size
);
2359 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object
*obj
,
2360 struct sg_table
*pages
)
2362 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2363 struct device
*kdev
= &dev_priv
->drm
.pdev
->dev
;
2364 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2366 if (unlikely(ggtt
->do_idle_maps
)) {
2367 if (i915_gem_wait_for_idle(dev_priv
, 0)) {
2368 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2369 /* Wait a bit, in hopes it avoids the hang */
2374 dma_unmap_sg(kdev
, pages
->sgl
, pages
->nents
, PCI_DMA_BIDIRECTIONAL
);
2377 static void i915_gtt_color_adjust(const struct drm_mm_node
*node
,
2378 unsigned long color
,
2382 if (node
->allocated
&& node
->color
!= color
)
2383 *start
+= I915_GTT_PAGE_SIZE
;
2385 /* Also leave a space between the unallocated reserved node after the
2386 * GTT and any objects within the GTT, i.e. we use the color adjustment
2387 * to insert a guard page to prevent prefetches crossing over the
2390 node
= list_next_entry(node
, node_list
);
2391 if (node
->color
!= color
)
2392 *end
-= I915_GTT_PAGE_SIZE
;
2395 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915
)
2397 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2398 struct i915_hw_ppgtt
*ppgtt
;
2401 ppgtt
= i915_ppgtt_create(i915
, ERR_PTR(-EPERM
), "[alias]");
2403 return PTR_ERR(ppgtt
);
2405 if (WARN_ON(ppgtt
->base
.total
< ggtt
->base
.total
)) {
2410 if (ppgtt
->base
.allocate_va_range
) {
2411 /* Note we only pre-allocate as far as the end of the global
2412 * GTT. On 48b / 4-level page-tables, the difference is very,
2413 * very significant! We have to preallocate as GVT/vgpu does
2414 * not like the page directory disappearing.
2416 err
= ppgtt
->base
.allocate_va_range(&ppgtt
->base
,
2417 0, ggtt
->base
.total
);
2422 i915
->mm
.aliasing_ppgtt
= ppgtt
;
2424 WARN_ON(ggtt
->base
.bind_vma
!= ggtt_bind_vma
);
2425 ggtt
->base
.bind_vma
= aliasing_gtt_bind_vma
;
2427 WARN_ON(ggtt
->base
.unbind_vma
!= ggtt_unbind_vma
);
2428 ggtt
->base
.unbind_vma
= aliasing_gtt_unbind_vma
;
2433 i915_ppgtt_put(ppgtt
);
2437 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915
)
2439 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2440 struct i915_hw_ppgtt
*ppgtt
;
2442 ppgtt
= fetch_and_zero(&i915
->mm
.aliasing_ppgtt
);
2446 i915_ppgtt_put(ppgtt
);
2448 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2449 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2452 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2454 /* Let GEM Manage all of the aperture.
2456 * However, leave one page at the end still bound to the scratch page.
2457 * There are a number of places where the hardware apparently prefetches
2458 * past the end of the object, and we've seen multiple hangs with the
2459 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2460 * aperture. One page should be enough to keep any prefetching inside
2463 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2464 unsigned long hole_start
, hole_end
;
2465 struct drm_mm_node
*entry
;
2468 ret
= intel_vgt_balloon(dev_priv
);
2472 /* Reserve a mappable slot for our lockless error capture */
2473 ret
= drm_mm_insert_node_in_range(&ggtt
->base
.mm
, &ggtt
->error_capture
,
2474 PAGE_SIZE
, 0, I915_COLOR_UNEVICTABLE
,
2475 0, ggtt
->mappable_end
,
2480 /* Clear any non-preallocated blocks */
2481 drm_mm_for_each_hole(entry
, &ggtt
->base
.mm
, hole_start
, hole_end
) {
2482 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2483 hole_start
, hole_end
);
2484 ggtt
->base
.clear_range(&ggtt
->base
, hole_start
,
2485 hole_end
- hole_start
);
2488 /* And finally clear the reserved guard page */
2489 ggtt
->base
.clear_range(&ggtt
->base
,
2490 ggtt
->base
.total
- PAGE_SIZE
, PAGE_SIZE
);
2492 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2493 ret
= i915_gem_init_aliasing_ppgtt(dev_priv
);
2501 drm_mm_remove_node(&ggtt
->error_capture
);
2506 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2507 * @dev_priv: i915 device
2509 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2511 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2512 struct i915_vma
*vma
, *vn
;
2514 ggtt
->base
.closed
= true;
2516 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2517 WARN_ON(!list_empty(&ggtt
->base
.active_list
));
2518 list_for_each_entry_safe(vma
, vn
, &ggtt
->base
.inactive_list
, vm_link
)
2519 WARN_ON(i915_vma_unbind(vma
));
2520 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2522 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2524 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2525 i915_gem_fini_aliasing_ppgtt(dev_priv
);
2527 if (drm_mm_node_allocated(&ggtt
->error_capture
))
2528 drm_mm_remove_node(&ggtt
->error_capture
);
2530 if (drm_mm_initialized(&ggtt
->base
.mm
)) {
2531 intel_vgt_deballoon(dev_priv
);
2532 i915_address_space_fini(&ggtt
->base
);
2535 ggtt
->base
.cleanup(&ggtt
->base
);
2536 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2538 arch_phys_wc_del(ggtt
->mtrr
);
2539 io_mapping_fini(&ggtt
->mappable
);
2542 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2544 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2545 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2546 return snb_gmch_ctl
<< 20;
2549 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2551 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2552 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2554 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2556 #ifdef CONFIG_X86_32
2557 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2558 if (bdw_gmch_ctl
> 4)
2562 return bdw_gmch_ctl
<< 20;
2565 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2567 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2568 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2571 return 1 << (20 + gmch_ctrl
);
2576 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
2578 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
2579 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
2580 return snb_gmch_ctl
<< 25; /* 32 MB units */
2583 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl
)
2585 bdw_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2586 bdw_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2587 return bdw_gmch_ctl
<< 25; /* 32 MB units */
2590 static size_t chv_get_stolen_size(u16 gmch_ctrl
)
2592 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
2593 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
2596 * 0x0 to 0x10: 32MB increments starting at 0MB
2597 * 0x11 to 0x16: 4MB increments starting at 8MB
2598 * 0x17 to 0x1d: 4MB increments start at 36MB
2600 if (gmch_ctrl
< 0x11)
2601 return gmch_ctrl
<< 25;
2602 else if (gmch_ctrl
< 0x17)
2603 return (gmch_ctrl
- 0x11 + 2) << 22;
2605 return (gmch_ctrl
- 0x17 + 9) << 22;
2608 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl
)
2610 gen9_gmch_ctl
>>= BDW_GMCH_GMS_SHIFT
;
2611 gen9_gmch_ctl
&= BDW_GMCH_GMS_MASK
;
2613 if (gen9_gmch_ctl
< 0xf0)
2614 return gen9_gmch_ctl
<< 25; /* 32 MB units */
2616 /* 4MB increments starting at 0xf0 for 4MB */
2617 return (gen9_gmch_ctl
- 0xf0 + 1) << 22;
2620 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2622 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2623 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2624 phys_addr_t phys_addr
;
2627 /* For Modern GENs the PTEs and register space are split in the BAR */
2628 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2631 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2632 * dropped. For WC mappings in general we have 64 byte burst writes
2633 * when the WC buffer is flushed, so we can't use it, but have to
2634 * resort to an uncached mapping. The WC issue is easily caught by the
2635 * readback check when writing GTT PTE entries.
2637 if (IS_GEN9_LP(dev_priv
))
2638 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2640 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2642 DRM_ERROR("Failed to map the ggtt page table\n");
2646 ret
= setup_scratch_page(&ggtt
->base
, GFP_DMA32
);
2648 DRM_ERROR("Scratch setup failed\n");
2649 /* iounmap will also get called at remove, but meh */
2657 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2658 * bits. When using advanced contexts each context stores its own PAT, but
2659 * writing this data shouldn't be harmful even in those cases. */
2660 static void bdw_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2664 pat
= GEN8_PPAT(0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
) | /* for normal objects, no eLLC */
2665 GEN8_PPAT(1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
) | /* for something pointing to ptes? */
2666 GEN8_PPAT(2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
) | /* for scanout with eLLC */
2667 GEN8_PPAT(3, GEN8_PPAT_UC
) | /* Uncached objects, mostly for scanout */
2668 GEN8_PPAT(4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0)) |
2669 GEN8_PPAT(5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1)) |
2670 GEN8_PPAT(6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2)) |
2671 GEN8_PPAT(7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
2673 if (!USES_PPGTT(dev_priv
))
2674 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2675 * so RTL will always use the value corresponding to
2677 * So let's disable cache for GGTT to avoid screen corruptions.
2678 * MOCS still can be used though.
2679 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2680 * before this patch, i.e. the same uncached + snooping access
2681 * like on gen6/7 seems to be in effect.
2682 * - So this just fixes blitter/render access. Again it looks
2683 * like it's not just uncached access, but uncached + snooping.
2684 * So we can still hold onto all our assumptions wrt cpu
2685 * clflushing on LLC machines.
2687 pat
= GEN8_PPAT(0, GEN8_PPAT_UC
);
2689 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2690 * write would work. */
2691 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2692 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2695 static void chv_setup_private_ppat(struct drm_i915_private
*dev_priv
)
2700 * Map WB on BDW to snooped on CHV.
2702 * Only the snoop bit has meaning for CHV, the rest is
2705 * The hardware will never snoop for certain types of accesses:
2706 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2707 * - PPGTT page tables
2708 * - some other special cycles
2710 * As with BDW, we also need to consider the following for GT accesses:
2711 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2712 * so RTL will always use the value corresponding to
2714 * Which means we must set the snoop bit in PAT entry 0
2715 * in order to keep the global status page working.
2717 pat
= GEN8_PPAT(0, CHV_PPAT_SNOOP
) |
2721 GEN8_PPAT(4, CHV_PPAT_SNOOP
) |
2722 GEN8_PPAT(5, CHV_PPAT_SNOOP
) |
2723 GEN8_PPAT(6, CHV_PPAT_SNOOP
) |
2724 GEN8_PPAT(7, CHV_PPAT_SNOOP
);
2726 I915_WRITE(GEN8_PRIVATE_PAT_LO
, pat
);
2727 I915_WRITE(GEN8_PRIVATE_PAT_HI
, pat
>> 32);
2730 static void gen6_gmch_remove(struct i915_address_space
*vm
)
2732 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2735 cleanup_scratch_page(vm
);
2738 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
2740 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2741 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2745 /* TODO: We're not aware of mappable constraints on gen8 yet */
2746 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
2747 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
2749 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(39)))
2750 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
2752 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2754 if (INTEL_GEN(dev_priv
) >= 9) {
2755 ggtt
->stolen_size
= gen9_get_stolen_size(snb_gmch_ctl
);
2756 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2757 } else if (IS_CHERRYVIEW(dev_priv
)) {
2758 ggtt
->stolen_size
= chv_get_stolen_size(snb_gmch_ctl
);
2759 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
2761 ggtt
->stolen_size
= gen8_get_stolen_size(snb_gmch_ctl
);
2762 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
2765 ggtt
->base
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
2767 if (IS_CHERRYVIEW(dev_priv
) || IS_GEN9_LP(dev_priv
))
2768 chv_setup_private_ppat(dev_priv
);
2770 bdw_setup_private_ppat(dev_priv
);
2772 ggtt
->base
.cleanup
= gen6_gmch_remove
;
2773 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2774 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2775 ggtt
->base
.insert_page
= gen8_ggtt_insert_page
;
2776 ggtt
->base
.clear_range
= nop_clear_range
;
2777 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
2778 ggtt
->base
.clear_range
= gen8_ggtt_clear_range
;
2780 ggtt
->base
.insert_entries
= gen8_ggtt_insert_entries
;
2782 ggtt
->invalidate
= gen6_ggtt_invalidate
;
2784 return ggtt_probe_common(ggtt
, size
);
2787 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
2789 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2790 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2794 ggtt
->mappable_base
= pci_resource_start(pdev
, 2);
2795 ggtt
->mappable_end
= pci_resource_len(pdev
, 2);
2797 /* 64/512MB is the current min/max we actually know of, but this is just
2798 * a coarse sanity check.
2800 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
2801 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt
->mappable_end
);
2805 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
2806 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
2807 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
2809 ggtt
->stolen_size
= gen6_get_stolen_size(snb_gmch_ctl
);
2811 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
2812 ggtt
->base
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
2814 ggtt
->base
.clear_range
= gen6_ggtt_clear_range
;
2815 ggtt
->base
.insert_page
= gen6_ggtt_insert_page
;
2816 ggtt
->base
.insert_entries
= gen6_ggtt_insert_entries
;
2817 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2818 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2819 ggtt
->base
.cleanup
= gen6_gmch_remove
;
2821 ggtt
->invalidate
= gen6_ggtt_invalidate
;
2823 if (HAS_EDRAM(dev_priv
))
2824 ggtt
->base
.pte_encode
= iris_pte_encode
;
2825 else if (IS_HASWELL(dev_priv
))
2826 ggtt
->base
.pte_encode
= hsw_pte_encode
;
2827 else if (IS_VALLEYVIEW(dev_priv
))
2828 ggtt
->base
.pte_encode
= byt_pte_encode
;
2829 else if (INTEL_GEN(dev_priv
) >= 7)
2830 ggtt
->base
.pte_encode
= ivb_pte_encode
;
2832 ggtt
->base
.pte_encode
= snb_pte_encode
;
2834 return ggtt_probe_common(ggtt
, size
);
2837 static void i915_gmch_remove(struct i915_address_space
*vm
)
2839 intel_gmch_remove();
2842 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
2844 struct drm_i915_private
*dev_priv
= ggtt
->base
.i915
;
2847 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
2849 DRM_ERROR("failed to set up gmch\n");
2853 intel_gtt_get(&ggtt
->base
.total
,
2855 &ggtt
->mappable_base
,
2856 &ggtt
->mappable_end
);
2858 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
2859 ggtt
->base
.insert_page
= i915_ggtt_insert_page
;
2860 ggtt
->base
.insert_entries
= i915_ggtt_insert_entries
;
2861 ggtt
->base
.clear_range
= i915_ggtt_clear_range
;
2862 ggtt
->base
.bind_vma
= ggtt_bind_vma
;
2863 ggtt
->base
.unbind_vma
= ggtt_unbind_vma
;
2864 ggtt
->base
.cleanup
= i915_gmch_remove
;
2866 ggtt
->invalidate
= gmch_ggtt_invalidate
;
2868 if (unlikely(ggtt
->do_idle_maps
))
2869 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2875 * i915_ggtt_probe_hw - Probe GGTT hardware location
2876 * @dev_priv: i915 device
2878 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
2880 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2883 ggtt
->base
.i915
= dev_priv
;
2884 ggtt
->base
.dma
= &dev_priv
->drm
.pdev
->dev
;
2886 if (INTEL_GEN(dev_priv
) <= 5)
2887 ret
= i915_gmch_probe(ggtt
);
2888 else if (INTEL_GEN(dev_priv
) < 8)
2889 ret
= gen6_gmch_probe(ggtt
);
2891 ret
= gen8_gmch_probe(ggtt
);
2895 /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
2896 * This is easier than doing range restriction on the fly, as we
2897 * currently don't have any bits spare to pass in this upper
2900 if (HAS_GUC(dev_priv
) && i915
.enable_guc_loading
) {
2901 ggtt
->base
.total
= min_t(u64
, ggtt
->base
.total
, GUC_GGTT_TOP
);
2902 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
2905 if ((ggtt
->base
.total
- 1) >> 32) {
2906 DRM_ERROR("We never expected a Global GTT with more than 32bits"
2907 " of address space! Found %lldM!\n",
2908 ggtt
->base
.total
>> 20);
2909 ggtt
->base
.total
= 1ULL << 32;
2910 ggtt
->mappable_end
= min(ggtt
->mappable_end
, ggtt
->base
.total
);
2913 if (ggtt
->mappable_end
> ggtt
->base
.total
) {
2914 DRM_ERROR("mappable aperture extends past end of GGTT,"
2915 " aperture=%llx, total=%llx\n",
2916 ggtt
->mappable_end
, ggtt
->base
.total
);
2917 ggtt
->mappable_end
= ggtt
->base
.total
;
2920 /* GMADR is the PCI mmio aperture into the global GTT. */
2921 DRM_INFO("Memory usable by graphics device = %lluM\n",
2922 ggtt
->base
.total
>> 20);
2923 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt
->mappable_end
>> 20);
2924 DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt
->stolen_size
>> 20);
2925 #ifdef CONFIG_INTEL_IOMMU
2926 if (intel_iommu_gfx_mapped
)
2927 DRM_INFO("VT-d active for gfx access\n");
2934 * i915_ggtt_init_hw - Initialize GGTT hardware
2935 * @dev_priv: i915 device
2937 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
2939 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2942 INIT_LIST_HEAD(&dev_priv
->vm_list
);
2944 /* Note that we use page colouring to enforce a guard page at the
2945 * end of the address space. This is required as the CS may prefetch
2946 * beyond the end of the batch buffer, across the page boundary,
2947 * and beyond the end of the GTT if we do not provide a guard.
2949 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2950 i915_address_space_init(&ggtt
->base
, dev_priv
, "[global]");
2951 if (!HAS_LLC(dev_priv
) && !USES_PPGTT(dev_priv
))
2952 ggtt
->base
.mm
.color_adjust
= i915_gtt_color_adjust
;
2953 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2955 if (!io_mapping_init_wc(&dev_priv
->ggtt
.mappable
,
2956 dev_priv
->ggtt
.mappable_base
,
2957 dev_priv
->ggtt
.mappable_end
)) {
2959 goto out_gtt_cleanup
;
2962 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
, ggtt
->mappable_end
);
2965 * Initialise stolen early so that we may reserve preallocated
2966 * objects for the BIOS to KMS transition.
2968 ret
= i915_gem_init_stolen(dev_priv
);
2970 goto out_gtt_cleanup
;
2975 ggtt
->base
.cleanup(&ggtt
->base
);
2979 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
2981 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
2987 void i915_ggtt_enable_guc(struct drm_i915_private
*i915
)
2989 i915
->ggtt
.invalidate
= guc_ggtt_invalidate
;
2992 void i915_ggtt_disable_guc(struct drm_i915_private
*i915
)
2994 i915
->ggtt
.invalidate
= gen6_ggtt_invalidate
;
2997 void i915_gem_restore_gtt_mappings(struct drm_i915_private
*dev_priv
)
2999 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3000 struct drm_i915_gem_object
*obj
, *on
;
3002 i915_check_and_clear_faults(dev_priv
);
3004 /* First fill our portion of the GTT with scratch pages */
3005 ggtt
->base
.clear_range(&ggtt
->base
, 0, ggtt
->base
.total
);
3007 ggtt
->base
.closed
= true; /* skip rewriting PTE on VMA unbind */
3009 /* clflush objects bound into the GGTT and rebind them. */
3010 list_for_each_entry_safe(obj
, on
,
3011 &dev_priv
->mm
.bound_list
, global_link
) {
3012 bool ggtt_bound
= false;
3013 struct i915_vma
*vma
;
3015 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3016 if (vma
->vm
!= &ggtt
->base
)
3019 if (!i915_vma_unbind(vma
))
3022 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
,
3028 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3031 ggtt
->base
.closed
= false;
3033 if (INTEL_GEN(dev_priv
) >= 8) {
3034 if (IS_CHERRYVIEW(dev_priv
) || IS_GEN9_LP(dev_priv
))
3035 chv_setup_private_ppat(dev_priv
);
3037 bdw_setup_private_ppat(dev_priv
);
3042 if (USES_PPGTT(dev_priv
)) {
3043 struct i915_address_space
*vm
;
3045 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3046 struct i915_hw_ppgtt
*ppgtt
;
3048 if (i915_is_ggtt(vm
))
3049 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3051 ppgtt
= i915_vm_to_ppgtt(vm
);
3053 gen6_write_page_range(ppgtt
, 0, ppgtt
->base
.total
);
3057 i915_ggtt_invalidate(dev_priv
);
3060 static struct scatterlist
*
3061 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3062 unsigned int width
, unsigned int height
,
3063 unsigned int stride
,
3064 struct sg_table
*st
, struct scatterlist
*sg
)
3066 unsigned int column
, row
;
3067 unsigned int src_idx
;
3069 for (column
= 0; column
< width
; column
++) {
3070 src_idx
= stride
* (height
- 1) + column
;
3071 for (row
= 0; row
< height
; row
++) {
3073 /* We don't need the pages, but need to initialize
3074 * the entries so the sg list can be happily traversed.
3075 * The only thing we need are DMA addresses.
3077 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3078 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3079 sg_dma_len(sg
) = PAGE_SIZE
;
3088 static noinline
struct sg_table
*
3089 intel_rotate_pages(struct intel_rotation_info
*rot_info
,
3090 struct drm_i915_gem_object
*obj
)
3092 const unsigned long n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3093 unsigned int size
= intel_rotation_info_size(rot_info
);
3094 struct sgt_iter sgt_iter
;
3095 dma_addr_t dma_addr
;
3097 dma_addr_t
*page_addr_list
;
3098 struct sg_table
*st
;
3099 struct scatterlist
*sg
;
3102 /* Allocate a temporary list of source pages for random access. */
3103 page_addr_list
= drm_malloc_gfp(n_pages
,
3106 if (!page_addr_list
)
3107 return ERR_PTR(ret
);
3109 /* Allocate target SG list. */
3110 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3114 ret
= sg_alloc_table(st
, size
, GFP_KERNEL
);
3118 /* Populate source page list from the object. */
3120 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->mm
.pages
)
3121 page_addr_list
[i
++] = dma_addr
;
3123 GEM_BUG_ON(i
!= n_pages
);
3127 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++) {
3128 sg
= rotate_pages(page_addr_list
, rot_info
->plane
[i
].offset
,
3129 rot_info
->plane
[i
].width
, rot_info
->plane
[i
].height
,
3130 rot_info
->plane
[i
].stride
, st
, sg
);
3133 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3134 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3136 drm_free_large(page_addr_list
);
3143 drm_free_large(page_addr_list
);
3145 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3146 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3148 return ERR_PTR(ret
);
3151 static noinline
struct sg_table
*
3152 intel_partial_pages(const struct i915_ggtt_view
*view
,
3153 struct drm_i915_gem_object
*obj
)
3155 struct sg_table
*st
;
3156 struct scatterlist
*sg
, *iter
;
3157 unsigned int count
= view
->partial
.size
;
3158 unsigned int offset
;
3161 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3165 ret
= sg_alloc_table(st
, count
, GFP_KERNEL
);
3169 iter
= i915_gem_object_get_sg(obj
, view
->partial
.offset
, &offset
);
3177 len
= min(iter
->length
- (offset
<< PAGE_SHIFT
),
3178 count
<< PAGE_SHIFT
);
3179 sg_set_page(sg
, NULL
, len
, 0);
3180 sg_dma_address(sg
) =
3181 sg_dma_address(iter
) + (offset
<< PAGE_SHIFT
);
3182 sg_dma_len(sg
) = len
;
3185 count
-= len
>> PAGE_SHIFT
;
3192 iter
= __sg_next(iter
);
3199 return ERR_PTR(ret
);
3203 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3207 /* The vma->pages are only valid within the lifespan of the borrowed
3208 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3209 * must be the vma->pages. A simple rule is that vma->pages must only
3210 * be accessed when the obj->mm.pages are pinned.
3212 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma
->obj
));
3214 switch (vma
->ggtt_view
.type
) {
3215 case I915_GGTT_VIEW_NORMAL
:
3216 vma
->pages
= vma
->obj
->mm
.pages
;
3219 case I915_GGTT_VIEW_ROTATED
:
3221 intel_rotate_pages(&vma
->ggtt_view
.rotated
, vma
->obj
);
3224 case I915_GGTT_VIEW_PARTIAL
:
3225 vma
->pages
= intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3229 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3230 vma
->ggtt_view
.type
);
3235 if (unlikely(IS_ERR(vma
->pages
))) {
3236 ret
= PTR_ERR(vma
->pages
);
3238 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3239 vma
->ggtt_view
.type
, ret
);
3245 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3246 * @vm: the &struct i915_address_space
3247 * @node: the &struct drm_mm_node (typically i915_vma.mode)
3248 * @size: how much space to allocate inside the GTT,
3249 * must be #I915_GTT_PAGE_SIZE aligned
3250 * @offset: where to insert inside the GTT,
3251 * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3252 * (@offset + @size) must fit within the address space
3253 * @color: color to apply to node, if this node is not from a VMA,
3254 * color must be #I915_COLOR_UNEVICTABLE
3255 * @flags: control search and eviction behaviour
3257 * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3258 * the address space (using @size and @color). If the @node does not fit, it
3259 * tries to evict any overlapping nodes from the GTT, including any
3260 * neighbouring nodes if the colors do not match (to ensure guard pages between
3261 * differing domains). See i915_gem_evict_for_node() for the gory details
3262 * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3263 * evicting active overlapping objects, and any overlapping node that is pinned
3264 * or marked as unevictable will also result in failure.
3266 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3267 * asked to wait for eviction and interrupted.
3269 int i915_gem_gtt_reserve(struct i915_address_space
*vm
,
3270 struct drm_mm_node
*node
,
3271 u64 size
, u64 offset
, unsigned long color
,
3277 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3278 GEM_BUG_ON(!IS_ALIGNED(offset
, I915_GTT_MIN_ALIGNMENT
));
3279 GEM_BUG_ON(range_overflows(offset
, size
, vm
->total
));
3280 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->base
);
3281 GEM_BUG_ON(drm_mm_node_allocated(node
));
3284 node
->start
= offset
;
3285 node
->color
= color
;
3287 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3291 err
= i915_gem_evict_for_node(vm
, node
, flags
);
3293 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3298 static u64
random_offset(u64 start
, u64 end
, u64 len
, u64 align
)
3302 GEM_BUG_ON(range_overflows(start
, len
, end
));
3303 GEM_BUG_ON(round_up(start
, align
) > round_down(end
- len
, align
));
3305 range
= round_down(end
- len
, align
) - round_up(start
, align
);
3307 if (sizeof(unsigned long) == sizeof(u64
)) {
3308 addr
= get_random_long();
3310 addr
= get_random_int();
3311 if (range
> U32_MAX
) {
3313 addr
|= get_random_int();
3316 div64_u64_rem(addr
, range
, &addr
);
3320 return round_up(start
, align
);
3324 * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3325 * @vm: the &struct i915_address_space
3326 * @node: the &struct drm_mm_node (typically i915_vma.node)
3327 * @size: how much space to allocate inside the GTT,
3328 * must be #I915_GTT_PAGE_SIZE aligned
3329 * @alignment: required alignment of starting offset, may be 0 but
3330 * if specified, this must be a power-of-two and at least
3331 * #I915_GTT_MIN_ALIGNMENT
3332 * @color: color to apply to node
3333 * @start: start of any range restriction inside GTT (0 for all),
3334 * must be #I915_GTT_PAGE_SIZE aligned
3335 * @end: end of any range restriction inside GTT (U64_MAX for all),
3336 * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3337 * @flags: control search and eviction behaviour
3339 * i915_gem_gtt_insert() first searches for an available hole into which
3340 * is can insert the node. The hole address is aligned to @alignment and
3341 * its @size must then fit entirely within the [@start, @end] bounds. The
3342 * nodes on either side of the hole must match @color, or else a guard page
3343 * will be inserted between the two nodes (or the node evicted). If no
3344 * suitable hole is found, first a victim is randomly selected and tested
3345 * for eviction, otherwise then the LRU list of objects within the GTT
3346 * is scanned to find the first set of replacement nodes to create the hole.
3347 * Those old overlapping nodes are evicted from the GTT (and so must be
3348 * rebound before any future use). Any node that is currently pinned cannot
3349 * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3350 * active and #PIN_NONBLOCK is specified, that node is also skipped when
3351 * searching for an eviction candidate. See i915_gem_evict_something() for
3352 * the gory details on the eviction algorithm.
3354 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3355 * asked to wait for eviction and interrupted.
3357 int i915_gem_gtt_insert(struct i915_address_space
*vm
,
3358 struct drm_mm_node
*node
,
3359 u64 size
, u64 alignment
, unsigned long color
,
3360 u64 start
, u64 end
, unsigned int flags
)
3362 enum drm_mm_insert_mode mode
;
3366 lockdep_assert_held(&vm
->i915
->drm
.struct_mutex
);
3368 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3369 GEM_BUG_ON(alignment
&& !is_power_of_2(alignment
));
3370 GEM_BUG_ON(alignment
&& !IS_ALIGNED(alignment
, I915_GTT_MIN_ALIGNMENT
));
3371 GEM_BUG_ON(start
>= end
);
3372 GEM_BUG_ON(start
> 0 && !IS_ALIGNED(start
, I915_GTT_PAGE_SIZE
));
3373 GEM_BUG_ON(end
< U64_MAX
&& !IS_ALIGNED(end
, I915_GTT_PAGE_SIZE
));
3374 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->base
);
3375 GEM_BUG_ON(drm_mm_node_allocated(node
));
3377 if (unlikely(range_overflows(start
, size
, end
)))
3380 if (unlikely(round_up(start
, alignment
) > round_down(end
- size
, alignment
)))
3383 mode
= DRM_MM_INSERT_BEST
;
3384 if (flags
& PIN_HIGH
)
3385 mode
= DRM_MM_INSERT_HIGH
;
3386 if (flags
& PIN_MAPPABLE
)
3387 mode
= DRM_MM_INSERT_LOW
;
3389 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3390 * so we know that we always have a minimum alignment of 4096.
3391 * The drm_mm range manager is optimised to return results
3392 * with zero alignment, so where possible use the optimal
3395 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT
> I915_GTT_PAGE_SIZE
);
3396 if (alignment
<= I915_GTT_MIN_ALIGNMENT
)
3399 err
= drm_mm_insert_node_in_range(&vm
->mm
, node
,
3400 size
, alignment
, color
,
3405 /* No free space, pick a slot at random.
3407 * There is a pathological case here using a GTT shared between
3408 * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3410 * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3411 * (64k objects) (448k objects)
3413 * Now imagine that the eviction LRU is ordered top-down (just because
3414 * pathology meets real life), and that we need to evict an object to
3415 * make room inside the aperture. The eviction scan then has to walk
3416 * the 448k list before it finds one within range. And now imagine that
3417 * it has to search for a new hole between every byte inside the memcpy,
3418 * for several simultaneous clients.
3420 * On a full-ppgtt system, if we have run out of available space, there
3421 * will be lots and lots of objects in the eviction list! Again,
3422 * searching that LRU list may be slow if we are also applying any
3423 * range restrictions (e.g. restriction to low 4GiB) and so, for
3424 * simplicity and similarilty between different GTT, try the single
3425 * random replacement first.
3427 offset
= random_offset(start
, end
,
3428 size
, alignment
?: I915_GTT_MIN_ALIGNMENT
);
3429 err
= i915_gem_gtt_reserve(vm
, node
, size
, offset
, color
, flags
);
3433 /* Randomly selected placement is pinned, do a search */
3434 err
= i915_gem_evict_something(vm
, size
, alignment
, color
,
3439 return drm_mm_insert_node_in_range(&vm
->mm
, node
,
3440 size
, alignment
, color
,
3441 start
, end
, DRM_MM_INSERT_EVICT
);
3444 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3445 #include "selftests/mock_gtt.c"
3446 #include "selftests/i915_gem_gtt.c"