2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 #include <linux/io-mapping.h>
39 #include <linux/pagevec.h>
41 #include "i915_gem_timeline.h"
42 #include "i915_gem_request.h"
43 #include "i915_selftest.h"
45 #define I915_GTT_PAGE_SIZE 4096UL
46 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
48 #define I915_FENCE_REG_NONE -1
49 #define I915_MAX_NUM_FENCES 32
50 /* 32 fences + sign bit for FENCE_REG_NONE */
51 #define I915_MAX_NUM_FENCE_BITS 6
53 struct drm_i915_file_private
;
54 struct drm_i915_fence_reg
;
56 typedef u32 gen6_pte_t
;
57 typedef u64 gen8_pte_t
;
58 typedef u64 gen8_pde_t
;
59 typedef u64 gen8_ppgtt_pdpe_t
;
60 typedef u64 gen8_ppgtt_pml4e_t
;
62 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
64 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
65 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
66 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
67 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
68 #define GEN6_PTE_CACHE_LLC (2 << 1)
69 #define GEN6_PTE_UNCACHED (1 << 1)
70 #define GEN6_PTE_VALID (1 << 0)
72 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
73 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
75 #define I915_PDE_MASK (I915_PDES - 1)
76 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
78 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
79 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
80 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
81 #define GEN6_PDE_SHIFT 22
82 #define GEN6_PDE_VALID (1 << 0)
84 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
86 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
87 #define BYT_PTE_WRITEABLE (1 << 1)
89 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
90 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
92 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
93 (((bits) & 0x8) << (11 - 3)))
94 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
95 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
96 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
97 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
98 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
99 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
100 #define HSW_PTE_UNCACHED (0)
101 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
102 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
104 /* GEN8 32b style address is defined as a 3 level page table:
105 * 31:30 | 29:21 | 20:12 | 11:0
106 * PDPE | PDE | PTE | offset
107 * The difference as compared to normal x86 3 level page table is the PDPEs are
108 * programmed via register.
110 #define GEN8_3LVL_PDPES 4
111 #define GEN8_PDE_SHIFT 21
112 #define GEN8_PDE_MASK 0x1ff
113 #define GEN8_PTE_SHIFT 12
114 #define GEN8_PTE_MASK 0x1ff
115 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
117 /* GEN8 48b style address is defined as a 4 level page table:
118 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
119 * PML4E | PDPE | PDE | PTE | offset
121 #define GEN8_PML4ES_PER_PML4 512
122 #define GEN8_PML4E_SHIFT 39
123 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
124 #define GEN8_PDPE_SHIFT 30
125 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
127 #define GEN8_PDPE_MASK 0x1ff
129 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
130 #define PPAT_CACHED_PDE 0 /* WB LLC */
131 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
132 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
134 #define CHV_PPAT_SNOOP (1<<6)
135 #define GEN8_PPAT_AGE(x) ((x)<<4)
136 #define GEN8_PPAT_LLCeLLC (3<<2)
137 #define GEN8_PPAT_LLCELLC (2<<2)
138 #define GEN8_PPAT_LLC (1<<2)
139 #define GEN8_PPAT_WB (3<<0)
140 #define GEN8_PPAT_WT (2<<0)
141 #define GEN8_PPAT_WC (1<<0)
142 #define GEN8_PPAT_UC (0<<0)
143 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
144 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
146 #define GEN8_PPAT_GET_CA(x) ((x) & 3)
147 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
148 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
149 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
153 struct intel_rotation_info
{
154 struct intel_rotation_plane_info
{
156 unsigned int width
, height
, stride
, offset
;
160 static inline void assert_intel_rotation_info_is_packed(void)
162 BUILD_BUG_ON(sizeof(struct intel_rotation_info
) != 8*sizeof(unsigned int));
165 struct intel_partial_info
{
170 static inline void assert_intel_partial_info_is_packed(void)
172 BUILD_BUG_ON(sizeof(struct intel_partial_info
) != sizeof(u64
) + sizeof(unsigned int));
175 enum i915_ggtt_view_type
{
176 I915_GGTT_VIEW_NORMAL
= 0,
177 I915_GGTT_VIEW_ROTATED
= sizeof(struct intel_rotation_info
),
178 I915_GGTT_VIEW_PARTIAL
= sizeof(struct intel_partial_info
),
181 static inline void assert_i915_ggtt_view_type_is_unique(void)
183 /* As we encode the size of each branch inside the union into its type,
184 * we have to be careful that each branch has a unique size.
186 switch ((enum i915_ggtt_view_type
)0) {
187 case I915_GGTT_VIEW_NORMAL
:
188 case I915_GGTT_VIEW_PARTIAL
:
189 case I915_GGTT_VIEW_ROTATED
:
190 /* gcc complains if these are identical cases */
195 struct i915_ggtt_view
{
196 enum i915_ggtt_view_type type
;
198 /* Members need to contain no holes/padding */
199 struct intel_partial_info partial
;
200 struct intel_rotation_info rotated
;
204 enum i915_cache_level
;
208 struct i915_page_dma
{
213 /* For gen6/gen7 only. This is the offset in the GGTT
214 * where the page directory entries for PPGTT begin
220 #define px_base(px) (&(px)->base)
221 #define px_page(px) (px_base(px)->page)
222 #define px_dma(px) (px_base(px)->daddr)
224 struct i915_page_table
{
225 struct i915_page_dma base
;
226 unsigned int used_ptes
;
229 struct i915_page_directory
{
230 struct i915_page_dma base
;
232 struct i915_page_table
*page_table
[I915_PDES
]; /* PDEs */
233 unsigned int used_pdes
;
236 struct i915_page_directory_pointer
{
237 struct i915_page_dma base
;
238 struct i915_page_directory
**page_directory
;
239 unsigned int used_pdpes
;
243 struct i915_page_dma base
;
244 struct i915_page_directory_pointer
*pdps
[GEN8_PML4ES_PER_PML4
];
247 struct i915_address_space
{
249 struct i915_gem_timeline timeline
;
250 struct drm_i915_private
*i915
;
252 /* Every address space belongs to a struct file - except for the global
253 * GTT that is owned by the driver (and so @file is set to NULL). In
254 * principle, no information should leak from one context to another
255 * (or between files/processes etc) unless explicitly shared by the
256 * owner. Tracking the owner is important in order to free up per-file
257 * objects along with the file, to aide resource tracking, and to
260 struct drm_i915_file_private
*file
;
261 struct list_head global_link
;
262 u64 total
; /* size addr space maps (ex. 2GB for ggtt) */
263 u64 reserved
; /* size addr space reserved */
267 struct i915_page_dma scratch_page
;
268 struct i915_page_table
*scratch_pt
;
269 struct i915_page_directory
*scratch_pd
;
270 struct i915_page_directory_pointer
*scratch_pdp
; /* GEN8+ & 48b PPGTT */
273 * List of objects currently involved in rendering.
275 * Includes buffers having the contents of their GPU caches
276 * flushed, not necessarily primitives. last_read_req
277 * represents when the rendering involved will be completed.
279 * A reference is held on the buffer while on this list.
281 struct list_head active_list
;
284 * LRU list of objects which are not in the ringbuffer and
285 * are ready to unbind, but are still in the GTT.
287 * last_read_req is NULL while an object is in this list.
289 * A reference is not held on the buffer while on this list,
290 * as merely being GTT-bound shouldn't prevent its being
291 * freed, and we'll pull it off the list in the free path.
293 struct list_head inactive_list
;
296 * List of vma that have been unbound.
298 * A reference is not held on the buffer while on this list.
300 struct list_head unbound_list
;
302 struct pagevec free_pages
;
305 /* FIXME: Need a more generic return type */
306 gen6_pte_t (*pte_encode
)(dma_addr_t addr
,
307 enum i915_cache_level level
,
308 u32 flags
); /* Create a valid PTE */
309 /* flags for pte_encode */
310 #define PTE_READ_ONLY (1<<0)
311 int (*allocate_va_range
)(struct i915_address_space
*vm
,
312 u64 start
, u64 length
);
313 void (*clear_range
)(struct i915_address_space
*vm
,
314 u64 start
, u64 length
);
315 void (*insert_page
)(struct i915_address_space
*vm
,
318 enum i915_cache_level cache_level
,
320 void (*insert_entries
)(struct i915_address_space
*vm
,
321 struct i915_vma
*vma
,
322 enum i915_cache_level cache_level
,
324 void (*cleanup
)(struct i915_address_space
*vm
);
325 /** Unmap an object from an address space. This usually consists of
326 * setting the valid PTE entries to a reserved scratch page. */
327 void (*unbind_vma
)(struct i915_vma
*vma
);
328 /* Map an object into an address space with the given cache flags. */
329 int (*bind_vma
)(struct i915_vma
*vma
,
330 enum i915_cache_level cache_level
,
333 I915_SELFTEST_DECLARE(struct fault_attr fault_attr
);
336 #define i915_is_ggtt(V) (!(V)->file)
339 i915_vm_is_48bit(const struct i915_address_space
*vm
)
341 return (vm
->total
- 1) >> 32;
344 /* The Graphics Translation Table is the way in which GEN hardware translates a
345 * Graphics Virtual Address into a Physical Address. In addition to the normal
346 * collateral associated with any va->pa translations GEN hardware also has a
347 * portion of the GTT which can be mapped by the CPU and remain both coherent
348 * and correct (in cases like swizzling). That region is referred to as GMADR in
352 struct i915_address_space base
;
353 struct io_mapping mappable
; /* Mapping to our CPU mappable region */
355 phys_addr_t mappable_base
; /* PA of our GMADR */
356 u64 mappable_end
; /* End offset that we can CPU map */
358 /* Stolen memory is segmented in hardware with different portions
359 * offlimits to certain functions.
361 * The drm_mm is initialised to the total accessible range, as found
362 * from the PCI config. On Broadwell+, this is further restricted to
363 * avoid the first page! The upper end of stolen memory is reserved for
364 * hardware functions and similarly removed from the accessible range.
366 u32 stolen_size
; /* Total size of stolen memory */
367 u32 stolen_usable_size
; /* Total size minus reserved ranges */
368 u32 stolen_reserved_base
;
369 u32 stolen_reserved_size
;
371 /** "Graphics Stolen Memory" holds the global PTEs */
373 void (*invalidate
)(struct drm_i915_private
*dev_priv
);
379 struct drm_mm_node error_capture
;
382 struct i915_hw_ppgtt
{
383 struct i915_address_space base
;
385 struct drm_mm_node node
;
386 unsigned long pd_dirty_rings
;
388 struct i915_pml4 pml4
; /* GEN8+ & 48b PPGTT */
389 struct i915_page_directory_pointer pdp
; /* GEN8+ */
390 struct i915_page_directory pd
; /* GEN6-7 */
393 gen6_pte_t __iomem
*pd_addr
;
395 int (*switch_mm
)(struct i915_hw_ppgtt
*ppgtt
,
396 struct drm_i915_gem_request
*req
);
397 void (*debug_dump
)(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
);
401 * gen6_for_each_pde() iterates over every pde from start until start+length.
402 * If start and start+length are not perfectly divisible, the macro will round
403 * down and up as needed. Start=0 and length=2G effectively iterates over
404 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
405 * so each of the other parameters should preferably be a simple variable, or
406 * at most an lvalue with no side-effects!
408 #define gen6_for_each_pde(pt, pd, start, length, iter) \
409 for (iter = gen6_pde_index(start); \
410 length > 0 && iter < I915_PDES && \
411 (pt = (pd)->page_table[iter], true); \
412 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
413 temp = min(temp - start, length); \
414 start += temp, length -= temp; }), ++iter)
416 #define gen6_for_all_pdes(pt, pd, iter) \
418 iter < I915_PDES && \
419 (pt = (pd)->page_table[iter], true); \
422 static inline u32
i915_pte_index(u64 address
, unsigned int pde_shift
)
424 const u32 mask
= NUM_PTE(pde_shift
) - 1;
426 return (address
>> PAGE_SHIFT
) & mask
;
429 /* Helper to counts the number of PTEs within the given length. This count
430 * does not cross a page table boundary, so the max value would be
431 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
433 static inline u32
i915_pte_count(u64 addr
, u64 length
, unsigned int pde_shift
)
435 const u64 mask
= ~((1ULL << pde_shift
) - 1);
438 WARN_ON(length
== 0);
439 WARN_ON(offset_in_page(addr
|length
));
443 if ((addr
& mask
) != (end
& mask
))
444 return NUM_PTE(pde_shift
) - i915_pte_index(addr
, pde_shift
);
446 return i915_pte_index(end
, pde_shift
) - i915_pte_index(addr
, pde_shift
);
449 static inline u32
i915_pde_index(u64 addr
, u32 shift
)
451 return (addr
>> shift
) & I915_PDE_MASK
;
454 static inline u32
gen6_pte_index(u32 addr
)
456 return i915_pte_index(addr
, GEN6_PDE_SHIFT
);
459 static inline u32
gen6_pte_count(u32 addr
, u32 length
)
461 return i915_pte_count(addr
, length
, GEN6_PDE_SHIFT
);
464 static inline u32
gen6_pde_index(u32 addr
)
466 return i915_pde_index(addr
, GEN6_PDE_SHIFT
);
469 static inline unsigned int
470 i915_pdpes_per_pdp(const struct i915_address_space
*vm
)
472 if (i915_vm_is_48bit(vm
))
473 return GEN8_PML4ES_PER_PML4
;
475 return GEN8_3LVL_PDPES
;
478 /* Equivalent to the gen6 version, For each pde iterates over every pde
479 * between from start until start + length. On gen8+ it simply iterates
480 * over every page directory entry in a page directory.
482 #define gen8_for_each_pde(pt, pd, start, length, iter) \
483 for (iter = gen8_pde_index(start); \
484 length > 0 && iter < I915_PDES && \
485 (pt = (pd)->page_table[iter], true); \
486 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
487 temp = min(temp - start, length); \
488 start += temp, length -= temp; }), ++iter)
490 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
491 for (iter = gen8_pdpe_index(start); \
492 length > 0 && iter < i915_pdpes_per_pdp(vm) && \
493 (pd = (pdp)->page_directory[iter], true); \
494 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
495 temp = min(temp - start, length); \
496 start += temp, length -= temp; }), ++iter)
498 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
499 for (iter = gen8_pml4e_index(start); \
500 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
501 (pdp = (pml4)->pdps[iter], true); \
502 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
503 temp = min(temp - start, length); \
504 start += temp, length -= temp; }), ++iter)
506 static inline u32
gen8_pte_index(u64 address
)
508 return i915_pte_index(address
, GEN8_PDE_SHIFT
);
511 static inline u32
gen8_pde_index(u64 address
)
513 return i915_pde_index(address
, GEN8_PDE_SHIFT
);
516 static inline u32
gen8_pdpe_index(u64 address
)
518 return (address
>> GEN8_PDPE_SHIFT
) & GEN8_PDPE_MASK
;
521 static inline u32
gen8_pml4e_index(u64 address
)
523 return (address
>> GEN8_PML4E_SHIFT
) & GEN8_PML4E_MASK
;
526 static inline u64
gen8_pte_count(u64 address
, u64 length
)
528 return i915_pte_count(address
, length
, GEN8_PDE_SHIFT
);
531 static inline dma_addr_t
532 i915_page_dir_dma_addr(const struct i915_hw_ppgtt
*ppgtt
, const unsigned n
)
534 return px_dma(ppgtt
->pdp
.page_directory
[n
]);
537 static inline struct i915_ggtt
*
538 i915_vm_to_ggtt(struct i915_address_space
*vm
)
540 GEM_BUG_ON(!i915_is_ggtt(vm
));
541 return container_of(vm
, struct i915_ggtt
, base
);
544 #define INTEL_MAX_PPAT_ENTRIES 8
545 #define INTEL_PPAT_PERFECT_MATCH (~0U)
549 struct intel_ppat_entry
{
550 struct intel_ppat
*ppat
;
556 struct intel_ppat_entry entries
[INTEL_MAX_PPAT_ENTRIES
];
557 DECLARE_BITMAP(used
, INTEL_MAX_PPAT_ENTRIES
);
558 DECLARE_BITMAP(dirty
, INTEL_MAX_PPAT_ENTRIES
);
559 unsigned int max_entries
;
562 * Return a score to show how two PPAT values match,
563 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
565 unsigned int (*match
)(u8 src
, u8 dst
);
566 void (*update_hw
)(struct drm_i915_private
*i915
);
568 struct drm_i915_private
*i915
;
571 const struct intel_ppat_entry
*
572 intel_ppat_get(struct drm_i915_private
*i915
, u8 value
);
573 void intel_ppat_put(const struct intel_ppat_entry
*entry
);
575 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915
);
576 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915
);
578 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
);
579 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
);
580 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
);
581 void i915_ggtt_enable_guc(struct drm_i915_private
*i915
);
582 void i915_ggtt_disable_guc(struct drm_i915_private
*i915
);
583 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
);
584 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
);
586 int i915_ppgtt_init_hw(struct drm_i915_private
*dev_priv
);
587 void i915_ppgtt_release(struct kref
*kref
);
588 struct i915_hw_ppgtt
*i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
589 struct drm_i915_file_private
*fpriv
,
591 void i915_ppgtt_close(struct i915_address_space
*vm
);
592 static inline void i915_ppgtt_get(struct i915_hw_ppgtt
*ppgtt
)
595 kref_get(&ppgtt
->ref
);
597 static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt
)
600 kref_put(&ppgtt
->ref
, i915_ppgtt_release
);
603 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
);
604 void i915_gem_suspend_gtt_mappings(struct drm_i915_private
*dev_priv
);
605 void i915_gem_restore_gtt_mappings(struct drm_i915_private
*dev_priv
);
607 int __must_check
i915_gem_gtt_prepare_pages(struct drm_i915_gem_object
*obj
,
608 struct sg_table
*pages
);
609 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object
*obj
,
610 struct sg_table
*pages
);
612 int i915_gem_gtt_reserve(struct i915_address_space
*vm
,
613 struct drm_mm_node
*node
,
614 u64 size
, u64 offset
, unsigned long color
,
617 int i915_gem_gtt_insert(struct i915_address_space
*vm
,
618 struct drm_mm_node
*node
,
619 u64 size
, u64 alignment
, unsigned long color
,
620 u64 start
, u64 end
, unsigned int flags
);
622 /* Flags used by pin/bind&friends. */
623 #define PIN_NONBLOCK BIT(0)
624 #define PIN_MAPPABLE BIT(1)
625 #define PIN_ZONE_4G BIT(2)
626 #define PIN_NONFAULT BIT(3)
627 #define PIN_NOEVICT BIT(4)
629 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
630 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
631 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
632 #define PIN_UPDATE BIT(8)
634 #define PIN_HIGH BIT(9)
635 #define PIN_OFFSET_BIAS BIT(10)
636 #define PIN_OFFSET_FIXED BIT(11)
637 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)