drivers/gpu/drm/i915/i915_gem_render_state.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Mika Kuoppala <mika.kuoppala@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_renderstate.h"
  30
  31 struct render_state {
  32         const struct intel_renderstate_rodata *rodata;
  33         struct drm_i915_gem_object *obj;
  34         u64 ggtt_offset;
  35         int gen;
  36 };
  37
  38 static const struct intel_renderstate_rodata *
  39 render_state_get_rodata(struct drm_device *dev, const int gen)
  40 {
  41         switch (gen) {
  42         case 6:
  43                 return &gen6_null_state;
  44         case 7:
  45                 return &gen7_null_state;
  46         case 8:
  47                 return &gen8_null_state;
  48         }
  49
  50         return NULL;
  51 }
  52
  53 static int render_state_init(struct render_state *so, struct drm_device *dev)
  54 {
  55         int ret;
  56
  57         so->gen = INTEL_INFO(dev)->gen;
  58         so->rodata = render_state_get_rodata(dev, so->gen);
  59         if (so->rodata == NULL)
  60                 return 0;
  61
  62         if (so->rodata->batch_items * 4 > 4096)
  63                 return -EINVAL;
  64
  65         so->obj = i915_gem_alloc_object(dev, 4096);
  66         if (so->obj == NULL)
  67                 return -ENOMEM;
  68
  69         ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
  70         if (ret)
  71                 goto free_gem;
  72
  73         so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);
  74         return 0;
  75
  76 free_gem:
  77         drm_gem_object_unreference(&so->obj->base);
  78         return ret;
  79 }
  80
  81 static int render_state_setup(struct render_state *so)
  82 {
  83         const struct intel_renderstate_rodata *rodata = so->rodata;
  84         unsigned int i = 0, reloc_index = 0;
  85         struct page *page;
  86         u32 *d;
  87         int ret;
  88
  89         ret = i915_gem_object_set_to_cpu_domain(so->obj, true);
  90         if (ret)
  91                 return ret;
  92
  93         page = sg_page(so->obj->pages->sgl);
  94         d = kmap(page);
  95
  96         while (i < rodata->batch_items) {
  97                 u32 s = rodata->batch[i];
  98
  99                 if (i * 4  == rodata->reloc[reloc_index]) {
 100                         u64 r = s + so->ggtt_offset;
 101                         s = lower_32_bits(r);
 102                         if (so->gen >= 8) {
 103                                 if (i + 1 >= rodata->batch_items ||
 104                                     rodata->batch[i + 1] != 0)
 105                                         return -EINVAL;
 106
 107                                 d[i++] = s;
 108                                 s = upper_32_bits(r);
 109                         }
 110
 111                         reloc_index++;
 112                 }
 113
 114                 d[i++] = s;
 115         }
 116         kunmap(page);
 117
 118         ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
 119         if (ret)
 120                 return ret;
 121
 122         if (rodata->reloc[reloc_index] != -1) {
 123                 DRM_ERROR("only %d relocs resolved\n", reloc_index);
 124                 return -EINVAL;
 125         }
 126
 127         return 0;
 128 }
 129
 130 static void render_state_fini(struct render_state *so)
 131 {
 132         i915_gem_object_ggtt_unpin(so->obj);
 133         drm_gem_object_unreference(&so->obj->base);
 134 }
 135
 136 int i915_gem_render_state_init(struct intel_engine_cs *ring)
 137 {
 138         struct render_state so;
 139         int ret;
 140
 141         if (WARN_ON(ring->id != RCS))
 142                 return -ENOENT;
 143
 144         ret = render_state_init(&so, ring->dev);
 145         if (ret)
 146                 return ret;
 147
 148         if (so.rodata == NULL)
 149                 return 0;
 150
 151         ret = render_state_setup(&so);
 152         if (ret)
 153                 goto out;
 154
 155         ret = ring->dispatch_execbuffer(ring,
 156                                         so.ggtt_offset,
 157                                         so.rodata->batch_items * 4,
 158                                         I915_DISPATCH_SECURE);
 159         if (ret)
 160                 goto out;
 161
 162         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
 163
 164         ret = __i915_add_request(ring, NULL, so.obj, NULL);
 165         /* __i915_add_request moves object to inactive if it fails */
 166 out:
 167         render_state_fini(&so);
 168         return ret;
 169 }