2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
27 #include <linux/sched.h>
28 #include <linux/sched/clock.h>
29 #include <linux/sched/signal.h>
33 static const char *i915_fence_get_driver_name(struct dma_fence
*fence
)
38 static const char *i915_fence_get_timeline_name(struct dma_fence
*fence
)
40 /* The timeline struct (as part of the ppgtt underneath a context)
41 * may be freed when the request is no longer in use by the GPU.
42 * We could extend the life of a context to beyond that of all
43 * fences, possibly keeping the hw resource around indefinitely,
44 * or we just give them a false name. Since
45 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
46 * lie seems justifiable.
48 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
51 return to_request(fence
)->timeline
->common
->name
;
54 static bool i915_fence_signaled(struct dma_fence
*fence
)
56 return i915_gem_request_completed(to_request(fence
));
59 static bool i915_fence_enable_signaling(struct dma_fence
*fence
)
61 if (i915_fence_signaled(fence
))
64 intel_engine_enable_signaling(to_request(fence
), true);
65 return !i915_fence_signaled(fence
);
68 static signed long i915_fence_wait(struct dma_fence
*fence
,
72 return i915_wait_request(to_request(fence
), interruptible
, timeout
);
75 static void i915_fence_release(struct dma_fence
*fence
)
77 struct drm_i915_gem_request
*req
= to_request(fence
);
79 /* The request is put onto a RCU freelist (i.e. the address
80 * is immediately reused), mark the fences as being freed now.
81 * Otherwise the debugobjects for the fences are only marked as
82 * freed when the slab cache itself is freed, and so we would get
83 * caught trying to reuse dead objects.
85 i915_sw_fence_fini(&req
->submit
);
87 kmem_cache_free(req
->i915
->requests
, req
);
90 const struct dma_fence_ops i915_fence_ops
= {
91 .get_driver_name
= i915_fence_get_driver_name
,
92 .get_timeline_name
= i915_fence_get_timeline_name
,
93 .enable_signaling
= i915_fence_enable_signaling
,
94 .signaled
= i915_fence_signaled
,
95 .wait
= i915_fence_wait
,
96 .release
= i915_fence_release
,
100 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
102 struct drm_i915_file_private
*file_priv
;
104 file_priv
= request
->file_priv
;
108 spin_lock(&file_priv
->mm
.lock
);
109 if (request
->file_priv
) {
110 list_del(&request
->client_link
);
111 request
->file_priv
= NULL
;
113 spin_unlock(&file_priv
->mm
.lock
);
116 static struct i915_dependency
*
117 i915_dependency_alloc(struct drm_i915_private
*i915
)
119 return kmem_cache_alloc(i915
->dependencies
, GFP_KERNEL
);
123 i915_dependency_free(struct drm_i915_private
*i915
,
124 struct i915_dependency
*dep
)
126 kmem_cache_free(i915
->dependencies
, dep
);
130 __i915_priotree_add_dependency(struct i915_priotree
*pt
,
131 struct i915_priotree
*signal
,
132 struct i915_dependency
*dep
,
135 INIT_LIST_HEAD(&dep
->dfs_link
);
136 list_add(&dep
->wait_link
, &signal
->waiters_list
);
137 list_add(&dep
->signal_link
, &pt
->signalers_list
);
138 dep
->signaler
= signal
;
143 i915_priotree_add_dependency(struct drm_i915_private
*i915
,
144 struct i915_priotree
*pt
,
145 struct i915_priotree
*signal
)
147 struct i915_dependency
*dep
;
149 dep
= i915_dependency_alloc(i915
);
153 __i915_priotree_add_dependency(pt
, signal
, dep
, I915_DEPENDENCY_ALLOC
);
158 i915_priotree_fini(struct drm_i915_private
*i915
, struct i915_priotree
*pt
)
160 struct i915_dependency
*dep
, *next
;
162 GEM_BUG_ON(!list_empty(&pt
->link
));
164 /* Everyone we depended upon (the fences we wait to be signaled)
165 * should retire before us and remove themselves from our list.
166 * However, retirement is run independently on each timeline and
167 * so we may be called out-of-order.
169 list_for_each_entry_safe(dep
, next
, &pt
->signalers_list
, signal_link
) {
170 list_del(&dep
->wait_link
);
171 if (dep
->flags
& I915_DEPENDENCY_ALLOC
)
172 i915_dependency_free(i915
, dep
);
175 /* Remove ourselves from everyone who depends upon us */
176 list_for_each_entry_safe(dep
, next
, &pt
->waiters_list
, wait_link
) {
177 list_del(&dep
->signal_link
);
178 if (dep
->flags
& I915_DEPENDENCY_ALLOC
)
179 i915_dependency_free(i915
, dep
);
184 i915_priotree_init(struct i915_priotree
*pt
)
186 INIT_LIST_HEAD(&pt
->signalers_list
);
187 INIT_LIST_HEAD(&pt
->waiters_list
);
188 INIT_LIST_HEAD(&pt
->link
);
189 pt
->priority
= INT_MIN
;
192 static int reset_all_global_seqno(struct drm_i915_private
*i915
, u32 seqno
)
194 struct intel_engine_cs
*engine
;
195 enum intel_engine_id id
;
198 /* Carefully retire all requests without writing to the rings */
199 ret
= i915_gem_wait_for_idle(i915
,
200 I915_WAIT_INTERRUPTIBLE
|
205 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
206 for_each_engine(engine
, i915
, id
) {
207 struct i915_gem_timeline
*timeline
;
208 struct intel_timeline
*tl
= engine
->timeline
;
210 if (!i915_seqno_passed(seqno
, tl
->seqno
)) {
211 /* spin until threads are complete */
212 while (intel_breadcrumbs_busy(engine
))
216 /* Finally reset hw state */
217 intel_engine_init_global_seqno(engine
, seqno
);
220 list_for_each_entry(timeline
, &i915
->gt
.timelines
, link
)
221 memset(timeline
->engine
[id
].global_sync
, 0,
222 sizeof(timeline
->engine
[id
].global_sync
));
228 int i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
)
230 struct drm_i915_private
*dev_priv
= to_i915(dev
);
232 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
237 /* HWS page needs to be set less than what we
238 * will inject to ring
240 return reset_all_global_seqno(dev_priv
, seqno
- 1);
243 static int reserve_seqno(struct intel_engine_cs
*engine
)
245 u32 active
= ++engine
->timeline
->inflight_seqnos
;
246 u32 seqno
= engine
->timeline
->seqno
;
249 /* Reservation is fine until we need to wrap around */
250 if (likely(!add_overflows(seqno
, active
)))
253 ret
= reset_all_global_seqno(engine
->i915
, 0);
255 engine
->timeline
->inflight_seqnos
--;
262 static void unreserve_seqno(struct intel_engine_cs
*engine
)
264 GEM_BUG_ON(!engine
->timeline
->inflight_seqnos
);
265 engine
->timeline
->inflight_seqnos
--;
268 void i915_gem_retire_noop(struct i915_gem_active
*active
,
269 struct drm_i915_gem_request
*request
)
271 /* Space left intentionally blank */
274 static void advance_ring(struct drm_i915_gem_request
*request
)
278 /* We know the GPU must have read the request to have
279 * sent us the seqno + interrupt, so use the position
280 * of tail of the request to update the last known position
283 * Note this requires that we are always called in request
286 if (list_is_last(&request
->ring_link
, &request
->ring
->request_list
)) {
287 /* We may race here with execlists resubmitting this request
288 * as we retire it. The resubmission will move the ring->tail
289 * forwards (to request->wa_tail). We either read the
290 * current value that was written to hw, or the value that
291 * is just about to be. Either works, if we miss the last two
292 * noops - they are safe to be replayed on a reset.
294 tail
= READ_ONCE(request
->ring
->tail
);
296 tail
= request
->postfix
;
298 list_del(&request
->ring_link
);
300 request
->ring
->head
= tail
;
303 static void free_capture_list(struct drm_i915_gem_request
*request
)
305 struct i915_gem_capture_list
*capture
;
307 capture
= request
->capture_list
;
309 struct i915_gem_capture_list
*next
= capture
->next
;
316 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
318 struct intel_engine_cs
*engine
= request
->engine
;
319 struct i915_gem_active
*active
, *next
;
321 lockdep_assert_held(&request
->i915
->drm
.struct_mutex
);
322 GEM_BUG_ON(!i915_sw_fence_signaled(&request
->submit
));
323 GEM_BUG_ON(!i915_gem_request_completed(request
));
324 GEM_BUG_ON(!request
->i915
->gt
.active_requests
);
326 trace_i915_gem_request_retire(request
);
328 spin_lock_irq(&engine
->timeline
->lock
);
329 list_del_init(&request
->link
);
330 spin_unlock_irq(&engine
->timeline
->lock
);
332 if (!--request
->i915
->gt
.active_requests
) {
333 GEM_BUG_ON(!request
->i915
->gt
.awake
);
334 mod_delayed_work(request
->i915
->wq
,
335 &request
->i915
->gt
.idle_work
,
336 msecs_to_jiffies(100));
338 unreserve_seqno(request
->engine
);
339 advance_ring(request
);
341 free_capture_list(request
);
343 /* Walk through the active list, calling retire on each. This allows
344 * objects to track their GPU activity and mark themselves as idle
345 * when their *last* active request is completed (updating state
346 * tracking lists for eviction, active references for GEM, etc).
348 * As the ->retire() may free the node, we decouple it first and
349 * pass along the auxiliary information (to avoid dereferencing
350 * the node after the callback).
352 list_for_each_entry_safe(active
, next
, &request
->active_list
, link
) {
353 /* In microbenchmarks or focusing upon time inside the kernel,
354 * we may spend an inordinate amount of time simply handling
355 * the retirement of requests and processing their callbacks.
356 * Of which, this loop itself is particularly hot due to the
357 * cache misses when jumping around the list of i915_gem_active.
358 * So we try to keep this loop as streamlined as possible and
359 * also prefetch the next i915_gem_active to try and hide
360 * the likely cache miss.
364 INIT_LIST_HEAD(&active
->link
);
365 RCU_INIT_POINTER(active
->request
, NULL
);
367 active
->retire(active
, request
);
370 i915_gem_request_remove_from_client(request
);
372 /* Retirement decays the ban score as it is a sign of ctx progress */
373 if (request
->ctx
->ban_score
> 0)
374 request
->ctx
->ban_score
--;
376 /* The backing object for the context is done after switching to the
377 * *next* context. Therefore we cannot retire the previous context until
378 * the next context has already started running. However, since we
379 * cannot take the required locks at i915_gem_request_submit() we
380 * defer the unpinning of the active context to now, retirement of
381 * the subsequent request.
383 if (engine
->last_retired_context
)
384 engine
->context_unpin(engine
, engine
->last_retired_context
);
385 engine
->last_retired_context
= request
->ctx
;
387 spin_lock_irq(&request
->lock
);
388 if (request
->waitboost
)
389 atomic_dec(&request
->i915
->rps
.num_waiters
);
390 dma_fence_signal_locked(&request
->fence
);
391 spin_unlock_irq(&request
->lock
);
393 i915_priotree_fini(request
->i915
, &request
->priotree
);
394 i915_gem_request_put(request
);
397 void i915_gem_request_retire_upto(struct drm_i915_gem_request
*req
)
399 struct intel_engine_cs
*engine
= req
->engine
;
400 struct drm_i915_gem_request
*tmp
;
402 lockdep_assert_held(&req
->i915
->drm
.struct_mutex
);
403 GEM_BUG_ON(!i915_gem_request_completed(req
));
405 if (list_empty(&req
->link
))
409 tmp
= list_first_entry(&engine
->timeline
->requests
,
412 i915_gem_request_retire(tmp
);
413 } while (tmp
!= req
);
416 static u32
timeline_get_seqno(struct intel_timeline
*tl
)
421 void __i915_gem_request_submit(struct drm_i915_gem_request
*request
)
423 struct intel_engine_cs
*engine
= request
->engine
;
424 struct intel_timeline
*timeline
;
427 GEM_BUG_ON(!irqs_disabled());
428 lockdep_assert_held(&engine
->timeline
->lock
);
430 trace_i915_gem_request_execute(request
);
432 /* Transfer from per-context onto the global per-engine timeline */
433 timeline
= engine
->timeline
;
434 GEM_BUG_ON(timeline
== request
->timeline
);
436 seqno
= timeline_get_seqno(timeline
);
438 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine
), seqno
));
440 /* We may be recursing from the signal callback of another i915 fence */
441 spin_lock_nested(&request
->lock
, SINGLE_DEPTH_NESTING
);
442 request
->global_seqno
= seqno
;
443 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
, &request
->fence
.flags
))
444 intel_engine_enable_signaling(request
, false);
445 spin_unlock(&request
->lock
);
447 engine
->emit_breadcrumb(request
,
448 request
->ring
->vaddr
+ request
->postfix
);
450 spin_lock(&request
->timeline
->lock
);
451 list_move_tail(&request
->link
, &timeline
->requests
);
452 spin_unlock(&request
->timeline
->lock
);
454 wake_up_all(&request
->execute
);
457 void i915_gem_request_submit(struct drm_i915_gem_request
*request
)
459 struct intel_engine_cs
*engine
= request
->engine
;
462 /* Will be called from irq-context when using foreign fences. */
463 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
465 __i915_gem_request_submit(request
);
467 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
470 void __i915_gem_request_unsubmit(struct drm_i915_gem_request
*request
)
472 struct intel_engine_cs
*engine
= request
->engine
;
473 struct intel_timeline
*timeline
;
475 GEM_BUG_ON(!irqs_disabled());
476 lockdep_assert_held(&engine
->timeline
->lock
);
478 /* Only unwind in reverse order, required so that the per-context list
479 * is kept in seqno/ring order.
481 GEM_BUG_ON(request
->global_seqno
!= engine
->timeline
->seqno
);
482 engine
->timeline
->seqno
--;
484 /* We may be recursing from the signal callback of another i915 fence */
485 spin_lock_nested(&request
->lock
, SINGLE_DEPTH_NESTING
);
486 request
->global_seqno
= 0;
487 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
, &request
->fence
.flags
))
488 intel_engine_cancel_signaling(request
);
489 spin_unlock(&request
->lock
);
491 /* Transfer back from the global per-engine timeline to per-context */
492 timeline
= request
->timeline
;
493 GEM_BUG_ON(timeline
== engine
->timeline
);
495 spin_lock(&timeline
->lock
);
496 list_move(&request
->link
, &timeline
->requests
);
497 spin_unlock(&timeline
->lock
);
499 /* We don't need to wake_up any waiters on request->execute, they
500 * will get woken by any other event or us re-adding this request
501 * to the engine timeline (__i915_gem_request_submit()). The waiters
502 * should be quite adapt at finding that the request now has a new
503 * global_seqno to the one they went to sleep on.
507 void i915_gem_request_unsubmit(struct drm_i915_gem_request
*request
)
509 struct intel_engine_cs
*engine
= request
->engine
;
512 /* Will be called from irq-context when using foreign fences. */
513 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
515 __i915_gem_request_unsubmit(request
);
517 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
520 static int __i915_sw_fence_call
521 submit_notify(struct i915_sw_fence
*fence
, enum i915_sw_fence_notify state
)
523 struct drm_i915_gem_request
*request
=
524 container_of(fence
, typeof(*request
), submit
);
528 trace_i915_gem_request_submit(request
);
529 request
->engine
->submit_request(request
);
533 i915_gem_request_put(request
);
541 * i915_gem_request_alloc - allocate a request structure
543 * @engine: engine that we wish to issue the request on.
544 * @ctx: context that the request will be associated with.
546 * Returns a pointer to the allocated request if successful,
547 * or an error code if not.
549 struct drm_i915_gem_request
*
550 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
551 struct i915_gem_context
*ctx
)
553 struct drm_i915_private
*dev_priv
= engine
->i915
;
554 struct drm_i915_gem_request
*req
;
555 struct intel_ring
*ring
;
558 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
560 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
561 * EIO if the GPU is already wedged.
563 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
564 return ERR_PTR(-EIO
);
566 /* Pinning the contexts may generate requests in order to acquire
567 * GGTT space, so do this first before we reserve a seqno for
570 ring
= engine
->context_pin(engine
, ctx
);
572 return ERR_CAST(ring
);
575 ret
= reserve_seqno(engine
);
579 /* Move the oldest request to the slab-cache (if not in use!) */
580 req
= list_first_entry_or_null(&engine
->timeline
->requests
,
582 if (req
&& i915_gem_request_completed(req
))
583 i915_gem_request_retire(req
);
585 /* Beware: Dragons be flying overhead.
587 * We use RCU to look up requests in flight. The lookups may
588 * race with the request being allocated from the slab freelist.
589 * That is the request we are writing to here, may be in the process
590 * of being read by __i915_gem_active_get_rcu(). As such,
591 * we have to be very careful when overwriting the contents. During
592 * the RCU lookup, we change chase the request->engine pointer,
593 * read the request->global_seqno and increment the reference count.
595 * The reference count is incremented atomically. If it is zero,
596 * the lookup knows the request is unallocated and complete. Otherwise,
597 * it is either still in use, or has been reallocated and reset
598 * with dma_fence_init(). This increment is safe for release as we
599 * check that the request we have a reference to and matches the active
602 * Before we increment the refcount, we chase the request->engine
603 * pointer. We must not call kmem_cache_zalloc() or else we set
604 * that pointer to NULL and cause a crash during the lookup. If
605 * we see the request is completed (based on the value of the
606 * old engine and seqno), the lookup is complete and reports NULL.
607 * If we decide the request is not completed (new engine or seqno),
608 * then we grab a reference and double check that it is still the
609 * active request - which it won't be and restart the lookup.
611 * Do not use kmem_cache_zalloc() here!
613 req
= kmem_cache_alloc(dev_priv
->requests
, GFP_KERNEL
);
619 req
->timeline
= i915_gem_context_lookup_timeline(ctx
, engine
);
620 GEM_BUG_ON(req
->timeline
== engine
->timeline
);
622 spin_lock_init(&req
->lock
);
623 dma_fence_init(&req
->fence
,
626 req
->timeline
->fence_context
,
627 timeline_get_seqno(req
->timeline
));
629 /* We bump the ref for the fence chain */
630 i915_sw_fence_init(&i915_gem_request_get(req
)->submit
, submit_notify
);
631 init_waitqueue_head(&req
->execute
);
633 i915_priotree_init(&req
->priotree
);
635 INIT_LIST_HEAD(&req
->active_list
);
636 req
->i915
= dev_priv
;
637 req
->engine
= engine
;
641 /* No zalloc, must clear what we need by hand */
642 req
->global_seqno
= 0;
643 req
->file_priv
= NULL
;
645 req
->capture_list
= NULL
;
646 req
->waitboost
= false;
649 * Reserve space in the ring buffer for all the commands required to
650 * eventually emit this request. This is to guarantee that the
651 * i915_add_request() call can't fail. Note that the reserve may need
652 * to be redone if the request is not actually submitted straight
653 * away, e.g. because a GPU scheduler has deferred it.
655 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
656 GEM_BUG_ON(req
->reserved_space
< engine
->emit_breadcrumb_sz
);
658 ret
= engine
->request_alloc(req
);
662 /* Record the position of the start of the request so that
663 * should we detect the updated seqno part-way through the
664 * GPU processing the request, we never over-estimate the
665 * position of the head.
667 req
->head
= req
->ring
->emit
;
669 /* Check that we didn't interrupt ourselves with a new request */
670 GEM_BUG_ON(req
->timeline
->seqno
!= req
->fence
.seqno
);
674 /* Make sure we didn't add ourselves to external state before freeing */
675 GEM_BUG_ON(!list_empty(&req
->active_list
));
676 GEM_BUG_ON(!list_empty(&req
->priotree
.signalers_list
));
677 GEM_BUG_ON(!list_empty(&req
->priotree
.waiters_list
));
679 kmem_cache_free(dev_priv
->requests
, req
);
681 unreserve_seqno(engine
);
683 engine
->context_unpin(engine
, ctx
);
688 i915_gem_request_await_request(struct drm_i915_gem_request
*to
,
689 struct drm_i915_gem_request
*from
)
693 GEM_BUG_ON(to
== from
);
694 GEM_BUG_ON(to
->timeline
== from
->timeline
);
696 if (i915_gem_request_completed(from
))
699 if (to
->engine
->schedule
) {
700 ret
= i915_priotree_add_dependency(to
->i915
,
707 if (to
->engine
== from
->engine
) {
708 ret
= i915_sw_fence_await_sw_fence_gfp(&to
->submit
,
711 return ret
< 0 ? ret
: 0;
714 if (to
->engine
->semaphore
.sync_to
) {
717 GEM_BUG_ON(!from
->engine
->semaphore
.signal
);
719 seqno
= i915_gem_request_global_seqno(from
);
721 goto await_dma_fence
;
723 if (seqno
<= to
->timeline
->global_sync
[from
->engine
->id
])
726 trace_i915_gem_ring_sync_to(to
, from
);
727 ret
= to
->engine
->semaphore
.sync_to(to
, from
);
731 to
->timeline
->global_sync
[from
->engine
->id
] = seqno
;
736 ret
= i915_sw_fence_await_dma_fence(&to
->submit
,
739 return ret
< 0 ? ret
: 0;
743 i915_gem_request_await_dma_fence(struct drm_i915_gem_request
*req
,
744 struct dma_fence
*fence
)
746 struct dma_fence
**child
= &fence
;
747 unsigned int nchild
= 1;
750 /* Note that if the fence-array was created in signal-on-any mode,
751 * we should *not* decompose it into its individual fences. However,
752 * we don't currently store which mode the fence-array is operating
753 * in. Fortunately, the only user of signal-on-any is private to
754 * amdgpu and we should not see any incoming fence-array from
755 * sync-file being in signal-on-any mode.
757 if (dma_fence_is_array(fence
)) {
758 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
760 child
= array
->fences
;
761 nchild
= array
->num_fences
;
767 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
771 * Requests on the same timeline are explicitly ordered, along
772 * with their dependencies, by i915_add_request() which ensures
773 * that requests are submitted in-order through each ring.
775 if (fence
->context
== req
->fence
.context
)
778 /* Squash repeated waits to the same timelines */
779 if (fence
->context
!= req
->i915
->mm
.unordered_timeline
&&
780 intel_timeline_sync_is_later(req
->timeline
, fence
))
783 if (dma_fence_is_i915(fence
))
784 ret
= i915_gem_request_await_request(req
,
787 ret
= i915_sw_fence_await_dma_fence(&req
->submit
, fence
,
793 /* Record the latest fence used against each timeline */
794 if (fence
->context
!= req
->i915
->mm
.unordered_timeline
)
795 intel_timeline_sync_set(req
->timeline
, fence
);
802 * i915_gem_request_await_object - set this request to (async) wait upon a bo
804 * @to: request we are wishing to use
805 * @obj: object which may be in use on another ring.
807 * This code is meant to abstract object synchronization with the GPU.
808 * Conceptually we serialise writes between engines inside the GPU.
809 * We only allow one engine to write into a buffer at any time, but
810 * multiple readers. To ensure each has a coherent view of memory, we must:
812 * - If there is an outstanding write request to the object, the new
813 * request must wait for it to complete (either CPU or in hw, requests
814 * on the same ring will be naturally ordered).
816 * - If we are a write request (pending_write_domain is set), the new
817 * request must wait for outstanding read requests to complete.
819 * Returns 0 if successful, else propagates up the lower layer error.
822 i915_gem_request_await_object(struct drm_i915_gem_request
*to
,
823 struct drm_i915_gem_object
*obj
,
826 struct dma_fence
*excl
;
830 struct dma_fence
**shared
;
831 unsigned int count
, i
;
833 ret
= reservation_object_get_fences_rcu(obj
->resv
,
834 &excl
, &count
, &shared
);
838 for (i
= 0; i
< count
; i
++) {
839 ret
= i915_gem_request_await_dma_fence(to
, shared
[i
]);
843 dma_fence_put(shared
[i
]);
846 for (; i
< count
; i
++)
847 dma_fence_put(shared
[i
]);
850 excl
= reservation_object_get_excl_rcu(obj
->resv
);
855 ret
= i915_gem_request_await_dma_fence(to
, excl
);
863 static void i915_gem_mark_busy(const struct intel_engine_cs
*engine
)
865 struct drm_i915_private
*dev_priv
= engine
->i915
;
867 if (dev_priv
->gt
.awake
)
870 GEM_BUG_ON(!dev_priv
->gt
.active_requests
);
872 intel_runtime_pm_get_noresume(dev_priv
);
873 dev_priv
->gt
.awake
= true;
875 intel_enable_gt_powersave(dev_priv
);
876 i915_update_gfx_val(dev_priv
);
877 if (INTEL_GEN(dev_priv
) >= 6)
878 gen6_rps_busy(dev_priv
);
880 queue_delayed_work(dev_priv
->wq
,
881 &dev_priv
->gt
.retire_work
,
882 round_jiffies_up_relative(HZ
));
886 * NB: This function is not allowed to fail. Doing so would mean the the
887 * request is not being tracked for completion but the work itself is
888 * going to happen on the hardware. This would be a Bad Thing(tm).
890 void __i915_add_request(struct drm_i915_gem_request
*request
, bool flush_caches
)
892 struct intel_engine_cs
*engine
= request
->engine
;
893 struct intel_ring
*ring
= request
->ring
;
894 struct intel_timeline
*timeline
= request
->timeline
;
895 struct drm_i915_gem_request
*prev
;
899 lockdep_assert_held(&request
->i915
->drm
.struct_mutex
);
900 trace_i915_gem_request_add(request
);
902 /* Make sure that no request gazumped us - if it was allocated after
903 * our i915_gem_request_alloc() and called __i915_add_request() before
904 * us, the timeline will hold its seqno which is later than ours.
906 GEM_BUG_ON(timeline
->seqno
!= request
->fence
.seqno
);
909 * To ensure that this call will not fail, space for its emissions
910 * should already have been reserved in the ring buffer. Let the ring
911 * know that it is time to use that space up.
913 request
->reserved_space
= 0;
916 * Emit any outstanding flushes - execbuf can fail to emit the flush
917 * after having emitted the batchbuffer command. Hence we need to fix
918 * things up similar to emitting the lazy request. The difference here
919 * is that the flush _must_ happen before the next request, no matter
923 err
= engine
->emit_flush(request
, EMIT_FLUSH
);
925 /* Not allowed to fail! */
926 WARN(err
, "engine->emit_flush() failed: %d!\n", err
);
929 /* Record the position of the start of the breadcrumb so that
930 * should we detect the updated seqno part-way through the
931 * GPU processing the request, we never over-estimate the
932 * position of the ring's HEAD.
934 cs
= intel_ring_begin(request
, engine
->emit_breadcrumb_sz
);
935 GEM_BUG_ON(IS_ERR(cs
));
936 request
->postfix
= intel_ring_offset(request
, cs
);
938 /* Seal the request and mark it as pending execution. Note that
939 * we may inspect this state, without holding any locks, during
940 * hangcheck. Hence we apply the barrier to ensure that we do not
941 * see a more recent value in the hws than we are tracking.
944 prev
= i915_gem_active_raw(&timeline
->last_request
,
945 &request
->i915
->drm
.struct_mutex
);
947 i915_sw_fence_await_sw_fence(&request
->submit
, &prev
->submit
,
949 if (engine
->schedule
)
950 __i915_priotree_add_dependency(&request
->priotree
,
956 spin_lock_irq(&timeline
->lock
);
957 list_add_tail(&request
->link
, &timeline
->requests
);
958 spin_unlock_irq(&timeline
->lock
);
960 GEM_BUG_ON(timeline
->seqno
!= request
->fence
.seqno
);
961 i915_gem_active_set(&timeline
->last_request
, request
);
963 list_add_tail(&request
->ring_link
, &ring
->request_list
);
964 request
->emitted_jiffies
= jiffies
;
966 if (!request
->i915
->gt
.active_requests
++)
967 i915_gem_mark_busy(engine
);
969 /* Let the backend know a new request has arrived that may need
970 * to adjust the existing execution schedule due to a high priority
971 * request - i.e. we may want to preempt the current request in order
972 * to run a high priority dependency chain *before* we can execute this
975 * This is called before the request is ready to run so that we can
976 * decide whether to preempt the entire chain so that it is ready to
977 * run at the earliest possible convenience.
979 if (engine
->schedule
)
980 engine
->schedule(request
, request
->ctx
->priority
);
983 i915_sw_fence_commit(&request
->submit
);
984 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
987 static unsigned long local_clock_us(unsigned int *cpu
)
991 /* Cheaply and approximately convert from nanoseconds to microseconds.
992 * The result and subsequent calculations are also defined in the same
993 * approximate microseconds units. The principal source of timing
994 * error here is from the simple truncation.
996 * Note that local_clock() is only defined wrt to the current CPU;
997 * the comparisons are no longer valid if we switch CPUs. Instead of
998 * blocking preemption for the entire busywait, we can detect the CPU
999 * switch and use that as indicator of system load and a reason to
1000 * stop busywaiting, see busywait_stop().
1003 t
= local_clock() >> 10;
1009 static bool busywait_stop(unsigned long timeout
, unsigned int cpu
)
1011 unsigned int this_cpu
;
1013 if (time_after(local_clock_us(&this_cpu
), timeout
))
1016 return this_cpu
!= cpu
;
1019 bool __i915_spin_request(const struct drm_i915_gem_request
*req
,
1020 u32 seqno
, int state
, unsigned long timeout_us
)
1022 struct intel_engine_cs
*engine
= req
->engine
;
1023 unsigned int irq
, cpu
;
1025 /* When waiting for high frequency requests, e.g. during synchronous
1026 * rendering split between the CPU and GPU, the finite amount of time
1027 * required to set up the irq and wait upon it limits the response
1028 * rate. By busywaiting on the request completion for a short while we
1029 * can service the high frequency waits as quick as possible. However,
1030 * if it is a slow request, we want to sleep as quickly as possible.
1031 * The tradeoff between waiting and sleeping is roughly the time it
1032 * takes to sleep on a request, on the order of a microsecond.
1035 irq
= atomic_read(&engine
->irq_count
);
1036 timeout_us
+= local_clock_us(&cpu
);
1038 if (seqno
!= i915_gem_request_global_seqno(req
))
1041 if (i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
1045 /* Seqno are meant to be ordered *before* the interrupt. If
1046 * we see an interrupt without a corresponding seqno advance,
1047 * assume we won't see one in the near future but require
1048 * the engine->seqno_barrier() to fixup coherency.
1050 if (atomic_read(&engine
->irq_count
) != irq
)
1053 if (signal_pending_state(state
, current
))
1056 if (busywait_stop(timeout_us
, cpu
))
1060 } while (!need_resched());
1065 static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request
*request
)
1067 if (likely(!i915_reset_handoff(&request
->i915
->gpu_error
)))
1070 __set_current_state(TASK_RUNNING
);
1071 i915_reset(request
->i915
);
1076 * i915_wait_request - wait until execution of request has finished
1077 * @req: the request to wait upon
1078 * @flags: how to wait
1079 * @timeout: how long to wait in jiffies
1081 * i915_wait_request() waits for the request to be completed, for a
1082 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1085 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1086 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1087 * must not specify that the wait is locked.
1089 * Returns the remaining time (in jiffies) if the request completed, which may
1090 * be zero or -ETIME if the request is unfinished after the timeout expires.
1091 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1092 * pending before the request completes.
1094 long i915_wait_request(struct drm_i915_gem_request
*req
,
1098 const int state
= flags
& I915_WAIT_INTERRUPTIBLE
?
1099 TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1100 wait_queue_head_t
*errq
= &req
->i915
->gpu_error
.wait_queue
;
1101 DEFINE_WAIT_FUNC(reset
, default_wake_function
);
1102 DEFINE_WAIT_FUNC(exec
, default_wake_function
);
1103 struct intel_wait wait
;
1106 #if IS_ENABLED(CONFIG_LOCKDEP)
1107 GEM_BUG_ON(debug_locks
&&
1108 !!lockdep_is_held(&req
->i915
->drm
.struct_mutex
) !=
1109 !!(flags
& I915_WAIT_LOCKED
));
1111 GEM_BUG_ON(timeout
< 0);
1113 if (i915_gem_request_completed(req
))
1119 trace_i915_gem_request_wait_begin(req
, flags
);
1121 add_wait_queue(&req
->execute
, &exec
);
1122 if (flags
& I915_WAIT_LOCKED
)
1123 add_wait_queue(errq
, &reset
);
1125 intel_wait_init(&wait
, req
);
1129 set_current_state(state
);
1130 if (intel_wait_update_request(&wait
, req
))
1133 if (flags
& I915_WAIT_LOCKED
&&
1134 __i915_wait_request_check_and_reset(req
))
1137 if (signal_pending_state(state
, current
)) {
1138 timeout
= -ERESTARTSYS
;
1147 timeout
= io_schedule_timeout(timeout
);
1150 GEM_BUG_ON(!intel_wait_has_seqno(&wait
));
1151 GEM_BUG_ON(!i915_sw_fence_signaled(&req
->submit
));
1153 /* Optimistic short spin before touching IRQs */
1154 if (i915_spin_request(req
, state
, 5))
1157 set_current_state(state
);
1158 if (intel_engine_add_wait(req
->engine
, &wait
))
1159 /* In order to check that we haven't missed the interrupt
1160 * as we enabled it, we need to kick ourselves to do a
1161 * coherent check on the seqno before we sleep.
1165 if (flags
& I915_WAIT_LOCKED
)
1166 __i915_wait_request_check_and_reset(req
);
1169 if (signal_pending_state(state
, current
)) {
1170 timeout
= -ERESTARTSYS
;
1179 timeout
= io_schedule_timeout(timeout
);
1181 if (intel_wait_complete(&wait
) &&
1182 intel_wait_check_request(&wait
, req
))
1185 set_current_state(state
);
1188 /* Carefully check if the request is complete, giving time
1189 * for the seqno to be visible following the interrupt.
1190 * We also have to check in case we are kicked by the GPU
1191 * reset in order to drop the struct_mutex.
1193 if (__i915_request_irq_complete(req
))
1196 /* If the GPU is hung, and we hold the lock, reset the GPU
1197 * and then check for completion. On a full reset, the engine's
1198 * HW seqno will be advanced passed us and we are complete.
1199 * If we do a partial reset, we have to wait for the GPU to
1200 * resume and update the breadcrumb.
1202 * If we don't hold the mutex, we can just wait for the worker
1203 * to come along and update the breadcrumb (either directly
1204 * itself, or indirectly by recovering the GPU).
1206 if (flags
& I915_WAIT_LOCKED
&&
1207 __i915_wait_request_check_and_reset(req
))
1210 /* Only spin if we know the GPU is processing this request */
1211 if (i915_spin_request(req
, state
, 2))
1214 if (!intel_wait_check_request(&wait
, req
)) {
1215 intel_engine_remove_wait(req
->engine
, &wait
);
1220 intel_engine_remove_wait(req
->engine
, &wait
);
1222 __set_current_state(TASK_RUNNING
);
1223 if (flags
& I915_WAIT_LOCKED
)
1224 remove_wait_queue(errq
, &reset
);
1225 remove_wait_queue(&req
->execute
, &exec
);
1226 trace_i915_gem_request_wait_end(req
);
1231 static void engine_retire_requests(struct intel_engine_cs
*engine
)
1233 struct drm_i915_gem_request
*request
, *next
;
1234 u32 seqno
= intel_engine_get_seqno(engine
);
1237 spin_lock_irq(&engine
->timeline
->lock
);
1238 list_for_each_entry_safe(request
, next
,
1239 &engine
->timeline
->requests
, link
) {
1240 if (!i915_seqno_passed(seqno
, request
->global_seqno
))
1243 list_move_tail(&request
->link
, &retire
);
1245 spin_unlock_irq(&engine
->timeline
->lock
);
1247 list_for_each_entry_safe(request
, next
, &retire
, link
)
1248 i915_gem_request_retire(request
);
1251 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
1253 struct intel_engine_cs
*engine
;
1254 enum intel_engine_id id
;
1256 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
1258 if (!dev_priv
->gt
.active_requests
)
1261 for_each_engine(engine
, dev_priv
, id
)
1262 engine_retire_requests(engine
);
1265 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1266 #include "selftests/mock_request.c"
1267 #include "selftests/i915_gem_request.c"