drivers/gpu/drm/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <linux/string.h>
  29 #include <linux/bitops.h>
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33
  34 /** @file i915_gem_tiling.c
  35  *
  36  * Support for managing tiling state of buffer objects.
  37  *
  38  * The idea behind tiling is to increase cache hit rates by rearranging
  39  * pixel data so that a group of pixel accesses are in the same cacheline.
  40  * Performance improvement from doing this on the back/depth buffer are on
  41  * the order of 30%.
  42  *
  43  * Intel architectures make this somewhat more complicated, though, by
  44  * adjustments made to addressing of data when the memory is in interleaved
  45  * mode (matched pairs of DIMMS) to improve memory bandwidth.
  46  * For interleaved memory, the CPU sends every sequential 64 bytes
  47  * to an alternate memory channel so it can get the bandwidth from both.
  48  *
  49  * The GPU also rearranges its accesses for increased bandwidth to interleaved
  50  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
  51  * it does it a little differently, since one walks addresses not just in the
  52  * X direction but also Y.  So, along with alternating channels when bit
  53  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
  54  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
  55  * are common to both the 915 and 965-class hardware.
  56  *
  57  * The CPU also sometimes XORs in higher bits as well, to improve
  58  * bandwidth doing strided access like we do so frequently in graphics.  This
  59  * is called "Channel XOR Randomization" in the MCH documentation.  The result
  60  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
  61  * decode.
  62  *
  63  * All of this bit 6 XORing has an effect on our memory management,
  64  * as we need to make sure that the 3d driver can correctly address object
  65  * contents.
  66  *
  67  * If we don't have interleaved memory, all tiling is safe and no swizzling is
  68  * required.
  69  *
  70  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
  71  * 17 is not just a page offset, so as we page an objet out and back in,
  72  * individual pages in it will have different bit 17 addresses, resulting in
  73  * each 64 bytes being swapped with its neighbor!
  74  *
  75  * Otherwise, if interleaved, we have to tell the 3d driver what the address
  76  * swizzling it needs to do is, since it's writing with the CPU to the pages
  77  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
  78  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
  79  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
  80  * to match what the GPU expects.
  81  */
  82
  83 /* Check pitch constriants for all chips & tiling formats */
  84 static bool
  85 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
  86 {
  87         int tile_width;
  88
  89         /* Linear is always fine */
  90         if (tiling_mode == I915_TILING_NONE)
  91                 return true;
  92
  93         if (IS_GEN2(dev) ||
  94             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
  95                 tile_width = 128;
  96         else
  97                 tile_width = 512;
  98
  99         /* check maximum stride & object size */
 100         /* i965+ stores the end address of the gtt mapping in the fence
 101          * reg, so dont bother to check the size */
 102         if (INTEL_INFO(dev)->gen >= 7) {
 103                 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
 104                         return false;
 105         } else if (INTEL_INFO(dev)->gen >= 4) {
 106                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 107                         return false;
 108         } else {
 109                 if (stride > 8192)
 110                         return false;
 111
 112                 if (IS_GEN3(dev)) {
 113                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
 114                                 return false;
 115                 } else {
 116                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
 117                                 return false;
 118                 }
 119         }
 120
 121         if (stride < tile_width)
 122                 return false;
 123
 124         /* 965+ just needs multiples of tile width */
 125         if (INTEL_INFO(dev)->gen >= 4) {
 126                 if (stride & (tile_width - 1))
 127                         return false;
 128                 return true;
 129         }
 130
 131         /* Pre-965 needs power of two tile widths */
 132         if (stride & (stride - 1))
 133                 return false;
 134
 135         return true;
 136 }
 137
 138 /* Is the current GTT allocation valid for the change in tiling? */
 139 static bool
 140 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 141 {
 142         u32 size;
 143
 144         if (tiling_mode == I915_TILING_NONE)
 145                 return true;
 146
 147         if (INTEL_INFO(obj->base.dev)->gen >= 4)
 148                 return true;
 149
 150         if (INTEL_INFO(obj->base.dev)->gen == 3) {
 151                 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
 152                         return false;
 153         } else {
 154                 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
 155                         return false;
 156         }
 157
 158         size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
 159         if (i915_gem_obj_ggtt_size(obj) != size)
 160                 return false;
 161
 162         if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
 163                 return false;
 164
 165         return true;
 166 }
 167
 168 /**
 169  * Sets the tiling mode of an object, returning the required swizzling of
 170  * bit 6 of addresses in the object.
 171  */
 172 int
 173 i915_gem_set_tiling(struct drm_device *dev, void *data,
 174                    struct drm_file *file)
 175 {
 176         struct drm_i915_gem_set_tiling *args = data;
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         struct drm_i915_gem_object *obj;
 179         int ret = 0;
 180
 181         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 182         if (&obj->base == NULL)
 183                 return -ENOENT;
 184
 185         if (!i915_tiling_ok(dev,
 186                             args->stride, obj->base.size, args->tiling_mode)) {
 187                 drm_gem_object_unreference_unlocked(&obj->base);
 188                 return -EINVAL;
 189         }
 190
 191         mutex_lock(&dev->struct_mutex);
 192         if (obj->pin_display || obj->framebuffer_references) {
 193                 ret = -EBUSY;
 194                 goto err;
 195         }
 196
 197         if (args->tiling_mode == I915_TILING_NONE) {
 198                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 199                 args->stride = 0;
 200         } else {
 201                 if (args->tiling_mode == I915_TILING_X)
 202                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 203                 else
 204                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 205
 206                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 207                  * from aborting the application on sw fallbacks to bit 17,
 208                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 209                  * If there was a user that was relying on the swizzle
 210                  * information for drm_intel_bo_map()ed reads/writes this would
 211                  * break it, but we don't have any of those.
 212                  */
 213                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 214                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 215                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 216                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 217
 218                 /* If we can't handle the swizzling, make it untiled. */
 219                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 220                         args->tiling_mode = I915_TILING_NONE;
 221                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 222                         args->stride = 0;
 223                 }
 224         }
 225
 226         if (args->tiling_mode != obj->tiling_mode ||
 227             args->stride != obj->stride) {
 228                 /* We need to rebind the object if its current allocation
 229                  * no longer meets the alignment restrictions for its new
 230                  * tiling mode. Otherwise we can just leave it alone, but
 231                  * need to ensure that any fence register is updated before
 232                  * the next fenced (either through the GTT or by the BLT unit
 233                  * on older GPUs) access.
 234                  *
 235                  * After updating the tiling parameters, we then flag whether
 236                  * we need to update an associated fence register. Note this
 237                  * has to also include the unfenced register the GPU uses
 238                  * whilst executing a fenced command for an untiled object.
 239                  */
 240                 if (obj->map_and_fenceable &&
 241                     !i915_gem_object_fence_ok(obj, args->tiling_mode))
 242                         ret = i915_gem_object_ggtt_unbind(obj);
 243
 244                 if (ret == 0) {
 245                         if (obj->pages &&
 246                             obj->madv == I915_MADV_WILLNEED &&
 247                             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
 248                                 if (args->tiling_mode == I915_TILING_NONE)
 249                                         i915_gem_object_unpin_pages(obj);
 250                                 if (obj->tiling_mode == I915_TILING_NONE)
 251                                         i915_gem_object_pin_pages(obj);
 252                         }
 253
 254                         obj->fence_dirty =
 255                                 obj->last_fenced_req ||
 256                                 obj->fence_reg != I915_FENCE_REG_NONE;
 257
 258                         obj->tiling_mode = args->tiling_mode;
 259                         obj->stride = args->stride;
 260
 261                         /* Force the fence to be reacquired for GTT access */
 262                         i915_gem_release_mmap(obj);
 263                 }
 264         }
 265         /* we have to maintain this existing ABI... */
 266         args->stride = obj->stride;
 267         args->tiling_mode = obj->tiling_mode;
 268
 269         /* Try to preallocate memory required to save swizzling on put-pages */
 270         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 271                 if (obj->bit_17 == NULL) {
 272                         obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
 273                                               sizeof(long), GFP_KERNEL);
 274                 }
 275         } else {
 276                 kfree(obj->bit_17);
 277                 obj->bit_17 = NULL;
 278         }
 279
 280 err:
 281         drm_gem_object_unreference(&obj->base);
 282         mutex_unlock(&dev->struct_mutex);
 283
 284         return ret;
 285 }
 286
 287 /**
 288  * Returns the current tiling mode and required bit 6 swizzling for the object.
 289  */
 290 int
 291 i915_gem_get_tiling(struct drm_device *dev, void *data,
 292                    struct drm_file *file)
 293 {
 294         struct drm_i915_gem_get_tiling *args = data;
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         struct drm_i915_gem_object *obj;
 297
 298         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 299         if (&obj->base == NULL)
 300                 return -ENOENT;
 301
 302         mutex_lock(&dev->struct_mutex);
 303
 304         args->tiling_mode = obj->tiling_mode;
 305         switch (obj->tiling_mode) {
 306         case I915_TILING_X:
 307                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 308                 break;
 309         case I915_TILING_Y:
 310                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 311                 break;
 312         case I915_TILING_NONE:
 313                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 314                 break;
 315         default:
 316                 DRM_ERROR("unknown tiling mode\n");
 317         }
 318
 319         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 320         args->phys_swizzle_mode = args->swizzle_mode;
 321         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 322                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 323         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 324                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 325
 326         drm_gem_object_unreference(&obj->base);
 327         mutex_unlock(&dev->struct_mutex);
 328
 329         return 0;
 330 }