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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/gpu/drm/i915/i915_guc_reg.h
2 * Copyright © 2014 Intel Corporation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef _I915_GUC_REG_H_
25 #define _I915_GUC_REG_H_
27 /* Definitions of GuC H/W registers, bits, etc */
29 #define GUC_STATUS 0xc000
30 #define GS_BOOTROM_SHIFT 1
31 #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
32 #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
33 #define GS_UKERNEL_SHIFT 8
34 #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
35 #define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
36 #define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
37 #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
38 #define GS_MIA_SHIFT 16
39 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
40 #define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT)
42 #define SOFT_SCRATCH(n) (0xc180 + ((n) * 4))
44 #define UOS_RSA_SCRATCH(i) (0xc200 + (i) * 4)
45 #define DMA_ADDR_0_LOW 0xc300
46 #define DMA_ADDR_0_HIGH 0xc304
47 #define DMA_ADDR_1_LOW 0xc308
48 #define DMA_ADDR_1_HIGH 0xc30c
49 #define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
50 #define DMA_ADDRESS_SPACE_GTT (8 << 16)
51 #define DMA_COPY_SIZE 0xc310
52 #define DMA_CTRL 0xc314
53 #define UOS_MOVE (1<<4)
54 #define START_DMA (1<<0)
55 #define DMA_GUC_WOPCM_OFFSET 0xc340
56 #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
57 #define GUC_MAX_IDLE_COUNT 0xC3E4
59 #define GUC_WOPCM_SIZE 0xc050
60 #define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
62 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
63 #define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
65 #define GEN8_GT_PM_CONFIG 0x138140
66 #define GEN9LP_GT_PM_CONFIG 0x138140
67 #define GEN9_GT_PM_CONFIG 0x13816c
68 #define GT_DOORBELL_ENABLE (1<<0)
70 #define GEN8_GTCR 0x4274
71 #define GEN8_GTCR_INVALIDATE (1<<0)
73 #define GUC_ARAT_C6DIS 0xA178
75 #define GUC_SHIM_CONTROL 0xc064
76 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
77 #define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
78 #define GUC_ENABLE_MIA_CACHING (1<<2)
79 #define GUC_GEN10_MSGCH_ENABLE (1<<4)
80 #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
81 #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
82 #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
83 #define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
85 #define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \
86 GUC_ENABLE_READ_CACHE_LOGIC | \
87 GUC_ENABLE_MIA_CACHING | \
88 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
89 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
90 GUC_ENABLE_MIA_CLOCK_GATING)
92 #define HOST2GUC_INTERRUPT 0xc4c8
93 #define HOST2GUC_TRIGGER (1<<0)
95 #define DRBMISC1 0x1984
96 #define DOORBELL_ENABLE (1<<0)
98 #define GEN8_DRBREGL(x) (0x1000 + (x) * 8)
99 #define GEN8_DRB_VALID (1<<0)
100 #define GEN8_DRBREGU(x) (GEN8_DRBREGL(x) + 4)
102 #define DE_GUCRMR 0x44054
104 #define GUC_BCS_RCS_IER 0xC550
105 #define GUC_VCS2_VCS1_IER 0xC554
106 #define GUC_WD_VECS_IER 0xC558
107 #define GUC_PM_P24C_IER 0xC55C