2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/circ_buf.h>
28 #include <trace/events/dma_fence.h>
31 * DOC: GuC-based command submission
34 * A i915_guc_client refers to a submission path through GuC. Currently, there
35 * is only one of these (the execbuf_client) and this one is charged with all
36 * submissions to the GuC. This struct is the owner of a doorbell, a process
37 * descriptor and a workqueue (all of them inside a single gem object that
38 * contains all required pages for these elements).
40 * GuC stage descriptor:
41 * During initialization, the driver allocates a static pool of 1024 such
42 * descriptors, and shares them with the GuC.
43 * Currently, there exists a 1:1 mapping between a i915_guc_client and a
44 * guc_stage_desc (via the client's stage_id), so effectively only one
45 * gets used. This stage descriptor lets the GuC know about the doorbell,
46 * workqueue and process descriptor. Theoretically, it also lets the GuC
47 * know about our HW contexts (context ID, etc...), but we actually
48 * employ a kind of submission where the GuC uses the LRCA sent via the work
49 * item instead (the single guc_stage_desc associated to execbuf client
50 * contains information about the default kernel context only, but this is
51 * essentially unused). This is called a "proxy" submission.
53 * The Scratch registers:
54 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
55 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
56 * triggers an interrupt on the GuC via another register write (0xC4C8).
57 * Firmware writes a success/fail code back to the action register after
58 * processes the request. The kernel driver polls waiting for this update and
60 * See intel_guc_send()
63 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
64 * mapped into process space.
67 * There are several types of work items that the host may place into a
68 * workqueue, each with its own requirements and limitations. Currently only
69 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
70 * represents in-order queue. The kernel driver packs ring tail pointer and an
71 * ELSP context descriptor dword into Work Item.
72 * See guc_wq_item_append()
75 * The Additional Data Struct (ADS) has pointers for different buffers used by
76 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
77 * scheduling policies (guc_policies), a structure describing a collection of
78 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
79 * its internal state for sleep.
83 static inline bool is_high_priority(struct i915_guc_client
* client
)
85 return client
->priority
<= GUC_CLIENT_PRIORITY_HIGH
;
88 static int __reserve_doorbell(struct i915_guc_client
*client
)
94 GEM_BUG_ON(client
->doorbell_id
!= GUC_DOORBELL_INVALID
);
97 * The bitmap tracks which doorbell registers are currently in use.
98 * It is split into two halves; the first half is used for normal
99 * priority contexts, the second half for high-priority ones.
102 end
= GUC_NUM_DOORBELLS
/2;
103 if (is_high_priority(client
)) {
108 id
= find_next_zero_bit(client
->guc
->doorbell_bitmap
, end
, offset
);
112 __set_bit(id
, client
->guc
->doorbell_bitmap
);
113 client
->doorbell_id
= id
;
114 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
115 client
->stage_id
, yesno(is_high_priority(client
)),
120 static void __unreserve_doorbell(struct i915_guc_client
*client
)
122 GEM_BUG_ON(client
->doorbell_id
== GUC_DOORBELL_INVALID
);
124 __clear_bit(client
->doorbell_id
, client
->guc
->doorbell_bitmap
);
125 client
->doorbell_id
= GUC_DOORBELL_INVALID
;
129 * Tell the GuC to allocate or deallocate a specific doorbell
132 static int __guc_allocate_doorbell(struct intel_guc
*guc
, u32 stage_id
)
135 INTEL_GUC_ACTION_ALLOCATE_DOORBELL
,
139 return intel_guc_send(guc
, action
, ARRAY_SIZE(action
));
142 static int __guc_deallocate_doorbell(struct intel_guc
*guc
, u32 stage_id
)
145 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL
,
149 return intel_guc_send(guc
, action
, ARRAY_SIZE(action
));
152 static struct guc_stage_desc
*__get_stage_desc(struct i915_guc_client
*client
)
154 struct guc_stage_desc
*base
= client
->guc
->stage_desc_pool_vaddr
;
156 return &base
[client
->stage_id
];
160 * Initialise, update, or clear doorbell data shared with the GuC
162 * These functions modify shared data and so need access to the mapped
163 * client object which contains the page being used for the doorbell
166 static void __update_doorbell_desc(struct i915_guc_client
*client
, u16 new_id
)
168 struct guc_stage_desc
*desc
;
170 /* Update the GuC's idea of the doorbell ID */
171 desc
= __get_stage_desc(client
);
172 desc
->db_id
= new_id
;
175 static struct guc_doorbell_info
*__get_doorbell(struct i915_guc_client
*client
)
177 return client
->vaddr
+ client
->doorbell_offset
;
180 static bool has_doorbell(struct i915_guc_client
*client
)
182 if (client
->doorbell_id
== GUC_DOORBELL_INVALID
)
185 return test_bit(client
->doorbell_id
, client
->guc
->doorbell_bitmap
);
188 static int __create_doorbell(struct i915_guc_client
*client
)
190 struct guc_doorbell_info
*doorbell
;
193 doorbell
= __get_doorbell(client
);
194 doorbell
->db_status
= GUC_DOORBELL_ENABLED
;
195 doorbell
->cookie
= 0;
197 err
= __guc_allocate_doorbell(client
->guc
, client
->stage_id
);
199 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
204 static int __destroy_doorbell(struct i915_guc_client
*client
)
206 struct drm_i915_private
*dev_priv
= guc_to_i915(client
->guc
);
207 struct guc_doorbell_info
*doorbell
;
208 u16 db_id
= client
->doorbell_id
;
210 GEM_BUG_ON(db_id
>= GUC_DOORBELL_INVALID
);
212 doorbell
= __get_doorbell(client
);
213 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
214 doorbell
->cookie
= 0;
216 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
217 * to go to zero after updating db_status before we call the GuC to
218 * release the doorbell */
219 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id
)) & GEN8_DRB_VALID
), 10))
220 WARN_ONCE(true, "Doorbell never became invalid after disable\n");
222 return __guc_deallocate_doorbell(client
->guc
, client
->stage_id
);
225 static int create_doorbell(struct i915_guc_client
*client
)
229 ret
= __reserve_doorbell(client
);
233 __update_doorbell_desc(client
, client
->doorbell_id
);
235 ret
= __create_doorbell(client
);
242 __update_doorbell_desc(client
, GUC_DOORBELL_INVALID
);
243 __unreserve_doorbell(client
);
247 static int destroy_doorbell(struct i915_guc_client
*client
)
251 GEM_BUG_ON(!has_doorbell(client
));
253 /* XXX: wait for any interrupts */
254 /* XXX: wait for workqueue to drain */
256 err
= __destroy_doorbell(client
);
260 __update_doorbell_desc(client
, GUC_DOORBELL_INVALID
);
262 __unreserve_doorbell(client
);
267 static unsigned long __select_cacheline(struct intel_guc
* guc
)
269 unsigned long offset
;
271 /* Doorbell uses a single cache line within a page */
272 offset
= offset_in_page(guc
->db_cacheline
);
274 /* Moving to next cache line to reduce contention */
275 guc
->db_cacheline
+= cache_line_size();
277 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
278 offset
, guc
->db_cacheline
, cache_line_size());
282 static inline struct guc_process_desc
*
283 __get_process_desc(struct i915_guc_client
*client
)
285 return client
->vaddr
+ client
->proc_desc_offset
;
289 * Initialise the process descriptor shared with the GuC firmware.
291 static void guc_proc_desc_init(struct intel_guc
*guc
,
292 struct i915_guc_client
*client
)
294 struct guc_process_desc
*desc
;
296 desc
= memset(__get_process_desc(client
), 0, sizeof(*desc
));
299 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
300 * space for ring3 clients (set them as in mmap_ioctl) or kernel
301 * space for kernel clients (map on demand instead? May make debug
302 * easier to have it mapped).
304 desc
->wq_base_addr
= 0;
305 desc
->db_base_addr
= 0;
307 desc
->stage_id
= client
->stage_id
;
308 desc
->wq_size_bytes
= GUC_WQ_SIZE
;
309 desc
->wq_status
= WQ_STATUS_ACTIVE
;
310 desc
->priority
= client
->priority
;
314 * Initialise/clear the stage descriptor shared with the GuC firmware.
316 * This descriptor tells the GuC where (in GGTT space) to find the important
317 * data structures relating to this client (doorbell, process descriptor,
320 static void guc_stage_desc_init(struct intel_guc
*guc
,
321 struct i915_guc_client
*client
)
323 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
324 struct intel_engine_cs
*engine
;
325 struct i915_gem_context
*ctx
= client
->owner
;
326 struct guc_stage_desc
*desc
;
330 desc
= __get_stage_desc(client
);
331 memset(desc
, 0, sizeof(*desc
));
333 desc
->attribute
= GUC_STAGE_DESC_ATTR_ACTIVE
| GUC_STAGE_DESC_ATTR_KERNEL
;
334 desc
->stage_id
= client
->stage_id
;
335 desc
->priority
= client
->priority
;
336 desc
->db_id
= client
->doorbell_id
;
338 for_each_engine_masked(engine
, dev_priv
, client
->engines
, tmp
) {
339 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
340 uint32_t guc_engine_id
= engine
->guc_id
;
341 struct guc_execlist_context
*lrc
= &desc
->lrc
[guc_engine_id
];
343 /* TODO: We have a design issue to be solved here. Only when we
344 * receive the first batch, we know which engine is used by the
345 * user. But here GuC expects the lrc and ring to be pinned. It
346 * is not an issue for default context, which is the only one
347 * for now who owns a GuC client. But for future owner of GuC
348 * client, need to make sure lrc is pinned prior to enter here.
351 break; /* XXX: continue? */
354 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
355 * submission or, in other words, not using a direct submission
356 * model) the KMD's LRCA is not used for any work submission.
357 * Instead, the GuC uses the LRCA of the user mode context (see
358 * guc_wq_item_append below).
360 lrc
->context_desc
= lower_32_bits(ce
->lrc_desc
);
362 /* The state page is after PPHWSP */
364 guc_ggtt_offset(ce
->state
) + LRC_STATE_PN
* PAGE_SIZE
;
366 /* XXX: In direct submission, the GuC wants the HW context id
367 * here. In proxy submission, it wants the stage id */
368 lrc
->context_id
= (client
->stage_id
<< GUC_ELC_CTXID_OFFSET
) |
369 (guc_engine_id
<< GUC_ELC_ENGINE_OFFSET
);
371 lrc
->ring_begin
= guc_ggtt_offset(ce
->ring
->vma
);
372 lrc
->ring_end
= lrc
->ring_begin
+ ce
->ring
->size
- 1;
373 lrc
->ring_next_free_location
= lrc
->ring_begin
;
374 lrc
->ring_current_tail_pointer_value
= 0;
376 desc
->engines_used
|= (1 << guc_engine_id
);
379 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
380 client
->engines
, desc
->engines_used
);
381 WARN_ON(desc
->engines_used
== 0);
384 * The doorbell, process descriptor, and workqueue are all parts
385 * of the client object, which the GuC will reference via the GGTT
387 gfx_addr
= guc_ggtt_offset(client
->vma
);
388 desc
->db_trigger_phy
= sg_dma_address(client
->vma
->pages
->sgl
) +
389 client
->doorbell_offset
;
390 desc
->db_trigger_cpu
= (uintptr_t)__get_doorbell(client
);
391 desc
->db_trigger_uk
= gfx_addr
+ client
->doorbell_offset
;
392 desc
->process_desc
= gfx_addr
+ client
->proc_desc_offset
;
393 desc
->wq_addr
= gfx_addr
+ GUC_DB_SIZE
;
394 desc
->wq_size
= GUC_WQ_SIZE
;
396 desc
->desc_private
= (uintptr_t)client
;
399 static void guc_stage_desc_fini(struct intel_guc
*guc
,
400 struct i915_guc_client
*client
)
402 struct guc_stage_desc
*desc
;
404 desc
= __get_stage_desc(client
);
405 memset(desc
, 0, sizeof(*desc
));
408 /* Construct a Work Item and append it to the GuC's Work Queue */
409 static void guc_wq_item_append(struct i915_guc_client
*client
,
410 struct drm_i915_gem_request
*rq
)
412 /* wqi_len is in DWords, and does not include the one-word header */
413 const size_t wqi_size
= sizeof(struct guc_wq_item
);
414 const u32 wqi_len
= wqi_size
/ sizeof(u32
) - 1;
415 struct intel_engine_cs
*engine
= rq
->engine
;
416 struct i915_gem_context
*ctx
= rq
->ctx
;
417 struct guc_process_desc
*desc
= __get_process_desc(client
);
418 struct guc_wq_item
*wqi
;
419 u32 ring_tail
, wq_off
;
421 lockdep_assert_held(&client
->wq_lock
);
423 ring_tail
= intel_ring_set_tail(rq
->ring
, rq
->tail
) / sizeof(u64
);
424 GEM_BUG_ON(ring_tail
> WQ_RING_TAIL_MAX
);
426 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
427 * should not have the case where structure wqi is across page, neither
428 * wrapped to the beginning. This simplifies the implementation below.
430 * XXX: if not the case, we need save data to a temp wqi and copy it to
431 * workqueue buffer dw by dw.
433 BUILD_BUG_ON(wqi_size
!= 16);
435 /* Free space is guaranteed. */
436 wq_off
= READ_ONCE(desc
->tail
);
437 GEM_BUG_ON(CIRC_SPACE(wq_off
, READ_ONCE(desc
->head
),
438 GUC_WQ_SIZE
) < wqi_size
);
439 GEM_BUG_ON(wq_off
& (wqi_size
- 1));
441 /* WQ starts from the page after doorbell / process_desc */
442 wqi
= client
->vaddr
+ wq_off
+ GUC_DB_SIZE
;
444 /* Now fill in the 4-word work queue item */
445 wqi
->header
= WQ_TYPE_INORDER
|
446 (wqi_len
<< WQ_LEN_SHIFT
) |
447 (engine
->guc_id
<< WQ_TARGET_SHIFT
) |
450 wqi
->context_desc
= lower_32_bits(intel_lr_context_descriptor(ctx
, engine
));
452 wqi
->submit_element_info
= ring_tail
<< WQ_RING_TAIL_SHIFT
;
453 wqi
->fence_id
= rq
->global_seqno
;
455 /* Postincrement WQ tail for next time. */
456 WRITE_ONCE(desc
->tail
, (wq_off
+ wqi_size
) & (GUC_WQ_SIZE
- 1));
459 static void guc_reset_wq(struct i915_guc_client
*client
)
461 struct guc_process_desc
*desc
= __get_process_desc(client
);
467 static void guc_ring_doorbell(struct i915_guc_client
*client
)
469 struct guc_doorbell_info
*db
;
472 lockdep_assert_held(&client
->wq_lock
);
474 /* pointer of current doorbell cacheline */
475 db
= __get_doorbell(client
);
477 /* we're not expecting the doorbell cookie to change behind our back */
478 cookie
= READ_ONCE(db
->cookie
);
479 WARN_ON_ONCE(xchg(&db
->cookie
, cookie
+ 1) != cookie
);
481 /* XXX: doorbell was lost and need to acquire it again */
482 GEM_BUG_ON(db
->db_status
!= GUC_DOORBELL_ENABLED
);
486 * i915_guc_submit() - Submit commands through GuC
487 * @engine: engine associated with the commands
489 * The only error here arises if the doorbell hardware isn't functioning
490 * as expected, which really shouln't happen.
492 static void i915_guc_submit(struct intel_engine_cs
*engine
)
494 struct drm_i915_private
*dev_priv
= engine
->i915
;
495 struct intel_guc
*guc
= &dev_priv
->guc
;
496 struct i915_guc_client
*client
= guc
->execbuf_client
;
497 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
498 struct execlist_port
*port
= execlists
->port
;
499 const unsigned int engine_id
= engine
->id
;
502 for (n
= 0; n
< ARRAY_SIZE(execlists
->port
); n
++) {
503 struct drm_i915_gem_request
*rq
;
506 rq
= port_unpack(&port
[n
], &count
);
507 if (rq
&& count
== 0) {
508 port_set(&port
[n
], port_pack(rq
, ++count
));
510 if (i915_vma_is_map_and_fenceable(rq
->ring
->vma
))
511 POSTING_READ_FW(GUC_STATUS
);
513 spin_lock(&client
->wq_lock
);
515 guc_wq_item_append(client
, rq
);
516 guc_ring_doorbell(client
);
518 client
->submissions
[engine_id
] += 1;
520 spin_unlock(&client
->wq_lock
);
525 static void nested_enable_signaling(struct drm_i915_gem_request
*rq
)
527 /* If we use dma_fence_enable_sw_signaling() directly, lockdep
528 * detects an ordering issue between the fence lockclass and the
529 * global_timeline. This circular dependency can only occur via 2
530 * different fences (but same fence lockclass), so we use the nesting
531 * annotation here to prevent the warn, equivalent to the nesting
532 * inside i915_gem_request_submit() for when we also enable the
536 if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
,
540 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &rq
->fence
.flags
));
541 trace_dma_fence_enable_signal(&rq
->fence
);
543 spin_lock_nested(&rq
->lock
, SINGLE_DEPTH_NESTING
);
544 intel_engine_enable_signaling(rq
, true);
545 spin_unlock(&rq
->lock
);
548 static void port_assign(struct execlist_port
*port
,
549 struct drm_i915_gem_request
*rq
)
551 GEM_BUG_ON(rq
== port_request(port
));
553 if (port_isset(port
))
554 i915_gem_request_put(port_request(port
));
556 port_set(port
, port_pack(i915_gem_request_get(rq
), port_count(port
)));
557 nested_enable_signaling(rq
);
560 static void i915_guc_dequeue(struct intel_engine_cs
*engine
)
562 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
563 struct execlist_port
*port
= execlists
->port
;
564 struct drm_i915_gem_request
*last
= NULL
;
565 const struct execlist_port
* const last_port
=
566 &execlists
->port
[execlists
->port_mask
];
570 if (port_isset(port
))
573 spin_lock_irq(&engine
->timeline
->lock
);
574 rb
= execlists
->first
;
575 GEM_BUG_ON(rb_first(&execlists
->queue
) != rb
);
577 struct i915_priolist
*p
= rb_entry(rb
, typeof(*p
), node
);
578 struct drm_i915_gem_request
*rq
, *rn
;
580 list_for_each_entry_safe(rq
, rn
, &p
->requests
, priotree
.link
) {
581 if (last
&& rq
->ctx
!= last
->ctx
) {
582 if (port
== last_port
) {
583 __list_del_many(&p
->requests
,
589 port_assign(port
, last
);
593 INIT_LIST_HEAD(&rq
->priotree
.link
);
594 rq
->priotree
.priority
= INT_MAX
;
596 __i915_gem_request_submit(rq
);
597 trace_i915_gem_request_in(rq
, port_index(port
, execlists
));
603 rb_erase(&p
->node
, &execlists
->queue
);
604 INIT_LIST_HEAD(&p
->requests
);
605 if (p
->priority
!= I915_PRIORITY_NORMAL
)
606 kmem_cache_free(engine
->i915
->priorities
, p
);
609 execlists
->first
= rb
;
611 port_assign(port
, last
);
612 i915_guc_submit(engine
);
614 spin_unlock_irq(&engine
->timeline
->lock
);
617 static void i915_guc_irq_handler(unsigned long data
)
619 struct intel_engine_cs
* const engine
= (struct intel_engine_cs
*)data
;
620 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
621 struct execlist_port
*port
= execlists
->port
;
622 const struct execlist_port
* const last_port
=
623 &execlists
->port
[execlists
->port_mask
];
624 struct drm_i915_gem_request
*rq
;
626 rq
= port_request(&port
[0]);
627 while (rq
&& i915_gem_request_completed(rq
)) {
628 trace_i915_gem_request_out(rq
);
629 i915_gem_request_put(rq
);
631 execlists_port_complete(execlists
, port
);
633 rq
= port_request(&port
[0]);
636 if (!port_isset(last_port
))
637 i915_guc_dequeue(engine
);
641 * Everything below here is concerned with setup & teardown, and is
642 * therefore not part of the somewhat time-critical batch-submission
643 * path of i915_guc_submit() above.
647 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
649 * @size: size of area to allocate (both virtual space and memory)
651 * This is a wrapper to create an object for use with the GuC. In order to
652 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
653 * both some backing storage and a range inside the Global GTT. We must pin
654 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
655 * range is reserved inside GuC.
657 * Return: A i915_vma if successful, otherwise an ERR_PTR.
659 struct i915_vma
*intel_guc_allocate_vma(struct intel_guc
*guc
, u32 size
)
661 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
662 struct drm_i915_gem_object
*obj
;
663 struct i915_vma
*vma
;
666 obj
= i915_gem_object_create(dev_priv
, size
);
668 return ERR_CAST(obj
);
670 vma
= i915_vma_instance(obj
, &dev_priv
->ggtt
.base
, NULL
);
674 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
,
675 PIN_GLOBAL
| PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
684 i915_gem_object_put(obj
);
688 /* Check that a doorbell register is in the expected state */
689 static bool doorbell_ok(struct intel_guc
*guc
, u16 db_id
)
691 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
695 GEM_BUG_ON(db_id
>= GUC_DOORBELL_INVALID
);
697 drbregl
= I915_READ(GEN8_DRBREGL(db_id
));
698 valid
= drbregl
& GEN8_DRB_VALID
;
700 if (test_bit(db_id
, guc
->doorbell_bitmap
) == valid
)
703 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n",
704 db_id
, drbregl
, yesno(valid
));
710 * If the GuC thinks that the doorbell is unassigned (e.g. because we reset and
711 * reloaded the GuC FW) we can use this function to tell the GuC to reassign the
712 * doorbell to the rightful owner.
714 static int __reset_doorbell(struct i915_guc_client
* client
, u16 db_id
)
718 __update_doorbell_desc(client
, db_id
);
719 err
= __create_doorbell(client
);
721 err
= __destroy_doorbell(client
);
727 * Set up & tear down each unused doorbell in turn, to ensure that all doorbell
728 * HW is (re)initialised. For that end, we might have to borrow the first
729 * client. Also, tell GuC about all the doorbells in use by all clients.
730 * We do this because the KMD, the GuC and the doorbell HW can easily go out of
731 * sync (e.g. we can reset the GuC, but not the doorbel HW).
733 static int guc_init_doorbell_hw(struct intel_guc
*guc
)
735 struct i915_guc_client
*client
= guc
->execbuf_client
;
736 bool recreate_first_client
= false;
740 /* For unused doorbells, make sure they are disabled */
741 for_each_clear_bit(db_id
, guc
->doorbell_bitmap
, GUC_NUM_DOORBELLS
) {
742 if (doorbell_ok(guc
, db_id
))
745 if (has_doorbell(client
)) {
746 /* Borrow execbuf_client (we will recreate it later) */
747 destroy_doorbell(client
);
748 recreate_first_client
= true;
751 ret
= __reset_doorbell(client
, db_id
);
752 WARN(ret
, "Doorbell %u reset failed, err %d\n", db_id
, ret
);
755 if (recreate_first_client
) {
756 ret
= __reserve_doorbell(client
);
758 DRM_ERROR("Couldn't re-reserve first client db: %d\n", ret
);
762 __update_doorbell_desc(client
, client
->doorbell_id
);
765 /* Now for every client (and not only execbuf_client) make sure their
766 * doorbells are known by the GuC */
767 //for (client = client_list; client != NULL; client = client->next)
769 ret
= __create_doorbell(client
);
771 DRM_ERROR("Couldn't recreate client %u doorbell: %d\n",
772 client
->stage_id
, ret
);
777 /* Read back & verify all (used & unused) doorbell registers */
778 for (db_id
= 0; db_id
< GUC_NUM_DOORBELLS
; ++db_id
)
779 WARN_ON(!doorbell_ok(guc
, db_id
));
785 * guc_client_alloc() - Allocate an i915_guc_client
786 * @dev_priv: driver private data structure
787 * @engines: The set of engines to enable for this client
788 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
789 * The kernel client to replace ExecList submission is created with
790 * NORMAL priority. Priority of a client for scheduler can be HIGH,
791 * while a preemption context can use CRITICAL.
792 * @ctx: the context that owns the client (we use the default render
795 * Return: An i915_guc_client object if success, else NULL.
797 static struct i915_guc_client
*
798 guc_client_alloc(struct drm_i915_private
*dev_priv
,
801 struct i915_gem_context
*ctx
)
803 struct i915_guc_client
*client
;
804 struct intel_guc
*guc
= &dev_priv
->guc
;
805 struct i915_vma
*vma
;
809 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
811 return ERR_PTR(-ENOMEM
);
815 client
->engines
= engines
;
816 client
->priority
= priority
;
817 client
->doorbell_id
= GUC_DOORBELL_INVALID
;
818 spin_lock_init(&client
->wq_lock
);
820 ret
= ida_simple_get(&guc
->stage_ids
, 0, GUC_MAX_STAGE_DESCRIPTORS
,
825 client
->stage_id
= ret
;
827 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
828 vma
= intel_guc_allocate_vma(guc
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
834 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
837 vaddr
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
839 ret
= PTR_ERR(vaddr
);
842 client
->vaddr
= vaddr
;
844 client
->doorbell_offset
= __select_cacheline(guc
);
847 * Since the doorbell only requires a single cacheline, we can save
848 * space by putting the application process descriptor in the same
849 * page. Use the half of the page that doesn't include the doorbell.
851 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
852 client
->proc_desc_offset
= 0;
854 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
856 guc_proc_desc_init(guc
, client
);
857 guc_stage_desc_init(guc
, client
);
859 ret
= create_doorbell(client
);
863 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
864 priority
, client
, client
->engines
, client
->stage_id
);
865 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
866 client
->doorbell_id
, client
->doorbell_offset
);
871 i915_gem_object_unpin_map(client
->vma
->obj
);
873 i915_vma_unpin_and_release(&client
->vma
);
875 ida_simple_remove(&guc
->stage_ids
, client
->stage_id
);
881 static void guc_client_free(struct i915_guc_client
*client
)
884 * XXX: wait for any outstanding submissions before freeing memory.
885 * Be sure to drop any locks
888 /* FIXME: in many cases, by the time we get here the GuC has been
889 * reset, so we cannot destroy the doorbell properly. Ignore the
890 * error message for now */
891 destroy_doorbell(client
);
892 guc_stage_desc_fini(client
->guc
, client
);
893 i915_gem_object_unpin_map(client
->vma
->obj
);
894 i915_vma_unpin_and_release(&client
->vma
);
895 ida_simple_remove(&client
->guc
->stage_ids
, client
->stage_id
);
899 static void guc_policy_init(struct guc_policy
*policy
)
901 policy
->execution_quantum
= POLICY_DEFAULT_EXECUTION_QUANTUM_US
;
902 policy
->preemption_time
= POLICY_DEFAULT_PREEMPTION_TIME_US
;
903 policy
->fault_time
= POLICY_DEFAULT_FAULT_TIME_US
;
904 policy
->policy_flags
= 0;
907 static void guc_policies_init(struct guc_policies
*policies
)
909 struct guc_policy
*policy
;
912 policies
->dpc_promote_time
= POLICY_DEFAULT_DPC_PROMOTE_TIME_US
;
913 policies
->max_num_work_items
= POLICY_MAX_NUM_WI
;
915 for (p
= 0; p
< GUC_CLIENT_PRIORITY_NUM
; p
++) {
916 for (i
= GUC_RENDER_ENGINE
; i
< GUC_MAX_ENGINES_NUM
; i
++) {
917 policy
= &policies
->policy
[p
][i
];
919 guc_policy_init(policy
);
923 policies
->is_valid
= 1;
927 * The first 80 dwords of the register state context, containing the
928 * execlists and ppgtt registers.
930 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
932 static int guc_ads_create(struct intel_guc
*guc
)
934 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
935 struct i915_vma
*vma
;
937 /* The ads obj includes the struct itself and buffers passed to GuC */
940 struct guc_policies policies
;
941 struct guc_mmio_reg_state reg_state
;
942 u8 reg_state_buffer
[GUC_S3_SAVE_SPACE_PAGES
* PAGE_SIZE
];
944 struct intel_engine_cs
*engine
;
945 enum intel_engine_id id
;
946 const u32 skipped_offset
= LRC_HEADER_PAGES
* PAGE_SIZE
;
947 const u32 skipped_size
= LRC_PPHWSP_SZ
* PAGE_SIZE
+ LR_HW_CONTEXT_SIZE
;
950 GEM_BUG_ON(guc
->ads_vma
);
952 vma
= intel_guc_allocate_vma(guc
, PAGE_ALIGN(sizeof(*blob
)));
958 page
= i915_vma_first_page(vma
);
961 /* GuC scheduling policies */
962 guc_policies_init(&blob
->policies
);
965 for_each_engine(engine
, dev_priv
, id
) {
966 blob
->reg_state
.white_list
[engine
->guc_id
].mmio_start
=
967 engine
->mmio_base
+ GUC_MMIO_WHITE_LIST_START
;
969 /* Nothing to be saved or restored for now. */
970 blob
->reg_state
.white_list
[engine
->guc_id
].count
= 0;
974 * The GuC requires a "Golden Context" when it reinitialises
975 * engines after a reset. Here we use the Render ring default
976 * context, which must already exist and be pinned in the GGTT,
977 * so its address won't change after we've told the GuC where
978 * to find it. Note that we have to skip our header (1 page),
979 * because our GuC shared data is there.
981 blob
->ads
.golden_context_lrca
=
982 guc_ggtt_offset(dev_priv
->kernel_context
->engine
[RCS
].state
) + skipped_offset
;
985 * The GuC expects us to exclude the portion of the context image that
986 * it skips from the size it is to read. It starts reading from after
987 * the execlist context (so skipping the first page [PPHWSP] and 80
988 * dwords). Weird guc is weird.
990 for_each_engine(engine
, dev_priv
, id
)
991 blob
->ads
.eng_state_size
[engine
->guc_id
] = engine
->context_size
- skipped_size
;
993 base
= guc_ggtt_offset(vma
);
994 blob
->ads
.scheduler_policies
= base
+ ptr_offset(blob
, policies
);
995 blob
->ads
.reg_state_buffer
= base
+ ptr_offset(blob
, reg_state_buffer
);
996 blob
->ads
.reg_state_addr
= base
+ ptr_offset(blob
, reg_state
);
1003 static void guc_ads_destroy(struct intel_guc
*guc
)
1005 i915_vma_unpin_and_release(&guc
->ads_vma
);
1009 * Set up the memory resources to be shared with the GuC (via the GGTT)
1010 * at firmware loading time.
1012 int i915_guc_submission_init(struct drm_i915_private
*dev_priv
)
1014 struct intel_guc
*guc
= &dev_priv
->guc
;
1015 struct i915_vma
*vma
;
1019 if (guc
->stage_desc_pool
)
1022 vma
= intel_guc_allocate_vma(guc
,
1023 PAGE_ALIGN(sizeof(struct guc_stage_desc
) *
1024 GUC_MAX_STAGE_DESCRIPTORS
));
1026 return PTR_ERR(vma
);
1028 guc
->stage_desc_pool
= vma
;
1030 vaddr
= i915_gem_object_pin_map(guc
->stage_desc_pool
->obj
, I915_MAP_WB
);
1031 if (IS_ERR(vaddr
)) {
1032 ret
= PTR_ERR(vaddr
);
1036 guc
->stage_desc_pool_vaddr
= vaddr
;
1038 ret
= intel_guc_log_create(guc
);
1042 ret
= guc_ads_create(guc
);
1046 ida_init(&guc
->stage_ids
);
1051 intel_guc_log_destroy(guc
);
1053 i915_gem_object_unpin_map(guc
->stage_desc_pool
->obj
);
1055 i915_vma_unpin_and_release(&guc
->stage_desc_pool
);
1059 void i915_guc_submission_fini(struct drm_i915_private
*dev_priv
)
1061 struct intel_guc
*guc
= &dev_priv
->guc
;
1063 ida_destroy(&guc
->stage_ids
);
1064 guc_ads_destroy(guc
);
1065 intel_guc_log_destroy(guc
);
1066 i915_gem_object_unpin_map(guc
->stage_desc_pool
->obj
);
1067 i915_vma_unpin_and_release(&guc
->stage_desc_pool
);
1070 static void guc_interrupts_capture(struct drm_i915_private
*dev_priv
)
1072 struct intel_engine_cs
*engine
;
1073 enum intel_engine_id id
;
1076 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
1077 irqs
= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
1078 for_each_engine(engine
, dev_priv
, id
)
1079 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
1081 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
1082 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
1083 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1084 /* These three registers have the same bit definitions */
1085 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
1086 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
1087 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
1090 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
1091 * (unmasked) PM interrupts to the GuC. All other bits of this
1092 * register *disable* generation of a specific interrupt.
1094 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
1095 * writing to the PM interrupt mask register, i.e. interrupts
1096 * that must not be disabled.
1098 * If the GuC is handling these interrupts, then we must not let
1099 * the PM code disable ANY interrupt that the GuC is expecting.
1100 * So for each ENABLED (0) bit in this register, we must SET the
1101 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
1102 * GuC needs ARAT expired interrupt unmasked hence it is set in
1105 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
1106 * result in the register bit being left SET!
1108 dev_priv
->rps
.pm_intrmsk_mbz
|= ARAT_EXPIRED_INTRMSK
;
1109 dev_priv
->rps
.pm_intrmsk_mbz
&= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
;
1112 static void guc_interrupts_release(struct drm_i915_private
*dev_priv
)
1114 struct intel_engine_cs
*engine
;
1115 enum intel_engine_id id
;
1119 * tell all command streamers NOT to forward interrupts or vblank
1122 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
1123 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
1124 for_each_engine(engine
, dev_priv
, id
)
1125 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
1127 /* route all GT interrupts to the host */
1128 I915_WRITE(GUC_BCS_RCS_IER
, 0);
1129 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
1130 I915_WRITE(GUC_WD_VECS_IER
, 0);
1132 dev_priv
->rps
.pm_intrmsk_mbz
|= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
;
1133 dev_priv
->rps
.pm_intrmsk_mbz
&= ~ARAT_EXPIRED_INTRMSK
;
1136 int i915_guc_submission_enable(struct drm_i915_private
*dev_priv
)
1138 struct intel_guc
*guc
= &dev_priv
->guc
;
1139 struct i915_guc_client
*client
= guc
->execbuf_client
;
1140 struct intel_engine_cs
*engine
;
1141 enum intel_engine_id id
;
1145 * We're using GuC work items for submitting work through GuC. Since
1146 * we're coalescing multiple requests from a single context into a
1147 * single work item prior to assigning it to execlist_port, we can
1148 * never have more work items than the total number of ports (for all
1149 * engines). The GuC firmware is controlling the HEAD of work queue,
1150 * and it is guaranteed that it will remove the work item from the
1151 * queue before our request is completed.
1153 BUILD_BUG_ON(ARRAY_SIZE(engine
->execlists
.port
) *
1154 sizeof(struct guc_wq_item
) *
1155 I915_NUM_ENGINES
> GUC_WQ_SIZE
);
1158 client
= guc_client_alloc(dev_priv
,
1159 INTEL_INFO(dev_priv
)->ring_mask
,
1160 GUC_CLIENT_PRIORITY_KMD_NORMAL
,
1161 dev_priv
->kernel_context
);
1162 if (IS_ERR(client
)) {
1163 DRM_ERROR("Failed to create GuC client for execbuf!\n");
1164 return PTR_ERR(client
);
1167 guc
->execbuf_client
= client
;
1170 err
= intel_guc_sample_forcewake(guc
);
1172 goto err_execbuf_client
;
1174 guc_reset_wq(client
);
1176 err
= guc_init_doorbell_hw(guc
);
1178 goto err_execbuf_client
;
1180 /* Take over from manual control of ELSP (execlists) */
1181 guc_interrupts_capture(dev_priv
);
1183 for_each_engine(engine
, dev_priv
, id
) {
1184 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
1185 /* The tasklet was initialised by execlists, and may be in
1186 * a state of flux (across a reset) and so we just want to
1187 * take over the callback without changing any other state
1190 execlists
->irq_tasklet
.func
= i915_guc_irq_handler
;
1191 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1192 tasklet_schedule(&execlists
->irq_tasklet
);
1198 guc_client_free(guc
->execbuf_client
);
1199 guc
->execbuf_client
= NULL
;
1203 void i915_guc_submission_disable(struct drm_i915_private
*dev_priv
)
1205 struct intel_guc
*guc
= &dev_priv
->guc
;
1207 guc_interrupts_release(dev_priv
);
1209 /* Revert back to manual ELSP submission */
1210 intel_engines_reset_default_submission(dev_priv
);
1212 guc_client_free(guc
->execbuf_client
);
1213 guc
->execbuf_client
= NULL
;
1217 * intel_guc_suspend() - notify GuC entering suspend state
1218 * @dev_priv: i915 device private
1220 int intel_guc_suspend(struct drm_i915_private
*dev_priv
)
1222 struct intel_guc
*guc
= &dev_priv
->guc
;
1223 struct i915_gem_context
*ctx
;
1226 if (guc
->fw
.load_status
!= INTEL_UC_FIRMWARE_SUCCESS
)
1229 gen9_disable_guc_interrupts(dev_priv
);
1231 ctx
= dev_priv
->kernel_context
;
1233 data
[0] = INTEL_GUC_ACTION_ENTER_S_STATE
;
1234 /* any value greater than GUC_POWER_D0 */
1235 data
[1] = GUC_POWER_D1
;
1236 /* first page is shared data with GuC */
1237 data
[2] = guc_ggtt_offset(ctx
->engine
[RCS
].state
) + LRC_GUCSHR_PN
* PAGE_SIZE
;
1239 return intel_guc_send(guc
, data
, ARRAY_SIZE(data
));
1243 * intel_guc_resume() - notify GuC resuming from suspend state
1244 * @dev_priv: i915 device private
1246 int intel_guc_resume(struct drm_i915_private
*dev_priv
)
1248 struct intel_guc
*guc
= &dev_priv
->guc
;
1249 struct i915_gem_context
*ctx
;
1252 if (guc
->fw
.load_status
!= INTEL_UC_FIRMWARE_SUCCESS
)
1255 if (i915_modparams
.guc_log_level
>= 0)
1256 gen9_enable_guc_interrupts(dev_priv
);
1258 ctx
= dev_priv
->kernel_context
;
1260 data
[0] = INTEL_GUC_ACTION_EXIT_S_STATE
;
1261 data
[1] = GUC_POWER_D0
;
1262 /* first page is shared data with GuC */
1263 data
[2] = guc_ggtt_offset(ctx
->engine
[RCS
].state
) + LRC_GUCSHR_PN
* PAGE_SIZE
;
1265 return intel_guc_send(guc
, data
, ARRAY_SIZE(data
));