1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
173 static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
175 /* For display hotplug interrupt */
177 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
183 assert_spin_locked(&dev_priv
->irq_lock
);
184 WARN_ON(bits
& ~mask
);
186 val
= I915_READ(PORT_HOTPLUG_EN
);
189 I915_WRITE(PORT_HOTPLUG_EN
, val
);
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
204 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
208 spin_lock_irq(&dev_priv
->irq_lock
);
209 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
210 spin_unlock_irq(&dev_priv
->irq_lock
);
214 * ilk_update_display_irq - update DEIMR
215 * @dev_priv: driver private
216 * @interrupt_mask: mask of interrupt bits to update
217 * @enabled_irq_mask: mask of interrupt bits to enable
219 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
220 uint32_t interrupt_mask
,
221 uint32_t enabled_irq_mask
)
225 assert_spin_locked(&dev_priv
->irq_lock
);
227 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
229 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
232 new_val
= dev_priv
->irq_mask
;
233 new_val
&= ~interrupt_mask
;
234 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
236 if (new_val
!= dev_priv
->irq_mask
) {
237 dev_priv
->irq_mask
= new_val
;
238 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
244 * ilk_update_gt_irq - update GTIMR
245 * @dev_priv: driver private
246 * @interrupt_mask: mask of interrupt bits to update
247 * @enabled_irq_mask: mask of interrupt bits to enable
249 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
250 uint32_t interrupt_mask
,
251 uint32_t enabled_irq_mask
)
253 assert_spin_locked(&dev_priv
->irq_lock
);
255 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
257 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
260 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
261 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
262 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
268 POSTING_READ_FW(GTIMR
);
271 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
273 ilk_update_gt_irq(dev_priv
, mask
, 0);
276 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
278 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
281 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
283 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
286 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
288 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
292 * snb_update_pm_irq - update GEN6_PMIMR
293 * @dev_priv: driver private
294 * @interrupt_mask: mask of interrupt bits to update
295 * @enabled_irq_mask: mask of interrupt bits to enable
297 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
298 uint32_t interrupt_mask
,
299 uint32_t enabled_irq_mask
)
303 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
305 assert_spin_locked(&dev_priv
->irq_lock
);
307 new_val
= dev_priv
->pm_imr
;
308 new_val
&= ~interrupt_mask
;
309 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
311 if (new_val
!= dev_priv
->pm_imr
) {
312 dev_priv
->pm_imr
= new_val
;
313 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_imr
);
314 POSTING_READ(gen6_pm_imr(dev_priv
));
318 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
320 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
323 snb_update_pm_irq(dev_priv
, mask
, mask
);
326 static void __gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_mask_pm_irq(dev_priv
, mask
);
339 void gen6_reset_pm_iir(struct drm_i915_private
*dev_priv
, u32 reset_mask
)
341 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
343 assert_spin_locked(&dev_priv
->irq_lock
);
345 I915_WRITE(reg
, reset_mask
);
346 I915_WRITE(reg
, reset_mask
);
350 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, u32 enable_mask
)
352 assert_spin_locked(&dev_priv
->irq_lock
);
354 dev_priv
->pm_ier
|= enable_mask
;
355 I915_WRITE(gen6_pm_ier(dev_priv
), dev_priv
->pm_ier
);
356 gen6_unmask_pm_irq(dev_priv
, enable_mask
);
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
360 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, u32 disable_mask
)
362 assert_spin_locked(&dev_priv
->irq_lock
);
364 dev_priv
->pm_ier
&= ~disable_mask
;
365 __gen6_mask_pm_irq(dev_priv
, disable_mask
);
366 I915_WRITE(gen6_pm_ier(dev_priv
), dev_priv
->pm_ier
);
367 /* though a barrier is missing here, but don't really need a one */
370 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
)
372 spin_lock_irq(&dev_priv
->irq_lock
);
373 gen6_reset_pm_iir(dev_priv
, dev_priv
->pm_rps_events
);
374 dev_priv
->rps
.pm_iir
= 0;
375 spin_unlock_irq(&dev_priv
->irq_lock
);
378 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
380 if (READ_ONCE(dev_priv
->rps
.interrupts_enabled
))
383 spin_lock_irq(&dev_priv
->irq_lock
);
384 WARN_ON_ONCE(dev_priv
->rps
.pm_iir
);
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
386 dev_priv
->rps
.interrupts_enabled
= true;
387 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
389 spin_unlock_irq(&dev_priv
->irq_lock
);
392 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
394 return (mask
& ~dev_priv
->rps
.pm_intr_keep
);
397 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
399 if (!READ_ONCE(dev_priv
->rps
.interrupts_enabled
))
402 spin_lock_irq(&dev_priv
->irq_lock
);
403 dev_priv
->rps
.interrupts_enabled
= false;
405 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0u));
407 gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
409 spin_unlock_irq(&dev_priv
->irq_lock
);
410 synchronize_irq(dev_priv
->drm
.irq
);
412 /* Now that we will not be generating any more work, flush any
413 * outsanding tasks. As we are called on the RPS idle path,
414 * we will reset the GPU to minimum frequencies, so the current
415 * state of the worker can be discarded.
417 cancel_work_sync(&dev_priv
->rps
.work
);
418 gen6_reset_rps_interrupts(dev_priv
);
421 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
)
423 spin_lock_irq(&dev_priv
->irq_lock
);
424 gen6_reset_pm_iir(dev_priv
, dev_priv
->pm_guc_events
);
425 spin_unlock_irq(&dev_priv
->irq_lock
);
428 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
)
430 spin_lock_irq(&dev_priv
->irq_lock
);
431 if (!dev_priv
->guc
.interrupts_enabled
) {
432 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) &
433 dev_priv
->pm_guc_events
);
434 dev_priv
->guc
.interrupts_enabled
= true;
435 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_guc_events
);
437 spin_unlock_irq(&dev_priv
->irq_lock
);
440 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
)
442 spin_lock_irq(&dev_priv
->irq_lock
);
443 dev_priv
->guc
.interrupts_enabled
= false;
445 gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_guc_events
);
447 spin_unlock_irq(&dev_priv
->irq_lock
);
448 synchronize_irq(dev_priv
->drm
.irq
);
450 gen9_reset_guc_interrupts(dev_priv
);
454 * bdw_update_port_irq - update DE port interrupt
455 * @dev_priv: driver private
456 * @interrupt_mask: mask of interrupt bits to update
457 * @enabled_irq_mask: mask of interrupt bits to enable
459 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
460 uint32_t interrupt_mask
,
461 uint32_t enabled_irq_mask
)
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
470 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
473 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
476 new_val
&= ~interrupt_mask
;
477 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
479 if (new_val
!= old_val
) {
480 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
481 POSTING_READ(GEN8_DE_PORT_IMR
);
486 * bdw_update_pipe_irq - update DE pipe interrupt
487 * @dev_priv: driver private
488 * @pipe: pipe whose interrupt to update
489 * @interrupt_mask: mask of interrupt bits to update
490 * @enabled_irq_mask: mask of interrupt bits to enable
492 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
494 uint32_t interrupt_mask
,
495 uint32_t enabled_irq_mask
)
499 assert_spin_locked(&dev_priv
->irq_lock
);
501 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
503 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
506 new_val
= dev_priv
->de_irq_mask
[pipe
];
507 new_val
&= ~interrupt_mask
;
508 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
510 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
511 dev_priv
->de_irq_mask
[pipe
] = new_val
;
512 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
513 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
518 * ibx_display_interrupt_update - update SDEIMR
519 * @dev_priv: driver private
520 * @interrupt_mask: mask of interrupt bits to update
521 * @enabled_irq_mask: mask of interrupt bits to enable
523 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
524 uint32_t interrupt_mask
,
525 uint32_t enabled_irq_mask
)
527 uint32_t sdeimr
= I915_READ(SDEIMR
);
528 sdeimr
&= ~interrupt_mask
;
529 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
531 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
533 assert_spin_locked(&dev_priv
->irq_lock
);
535 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
538 I915_WRITE(SDEIMR
, sdeimr
);
539 POSTING_READ(SDEIMR
);
543 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
544 u32 enable_mask
, u32 status_mask
)
546 i915_reg_t reg
= PIPESTAT(pipe
);
547 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
549 assert_spin_locked(&dev_priv
->irq_lock
);
550 WARN_ON(!intel_irqs_enabled(dev_priv
));
552 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
553 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
554 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
555 pipe_name(pipe
), enable_mask
, status_mask
))
558 if ((pipestat
& enable_mask
) == enable_mask
)
561 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
563 /* Enable the interrupt, clear any pending status */
564 pipestat
|= enable_mask
| status_mask
;
565 I915_WRITE(reg
, pipestat
);
570 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
571 u32 enable_mask
, u32 status_mask
)
573 i915_reg_t reg
= PIPESTAT(pipe
);
574 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
576 assert_spin_locked(&dev_priv
->irq_lock
);
577 WARN_ON(!intel_irqs_enabled(dev_priv
));
579 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
580 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
581 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
582 pipe_name(pipe
), enable_mask
, status_mask
))
585 if ((pipestat
& enable_mask
) == 0)
588 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
590 pipestat
&= ~enable_mask
;
591 I915_WRITE(reg
, pipestat
);
595 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
597 u32 enable_mask
= status_mask
<< 16;
600 * On pipe A we don't support the PSR interrupt yet,
601 * on pipe B and C the same bit MBZ.
603 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
606 * On pipe B and C we don't support the PSR interrupt yet, on pipe
607 * A the same bit is for perf counters which we don't use either.
609 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
612 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
613 SPRITE0_FLIP_DONE_INT_EN_VLV
|
614 SPRITE1_FLIP_DONE_INT_EN_VLV
);
615 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
616 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
617 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
618 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
624 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
629 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
630 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
633 enable_mask
= status_mask
<< 16;
634 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
638 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
643 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
644 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
647 enable_mask
= status_mask
<< 16;
648 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
652 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
653 * @dev_priv: i915 device private
655 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
657 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
660 spin_lock_irq(&dev_priv
->irq_lock
);
662 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
663 if (INTEL_GEN(dev_priv
) >= 4)
664 i915_enable_pipestat(dev_priv
, PIPE_A
,
665 PIPE_LEGACY_BLC_EVENT_STATUS
);
667 spin_unlock_irq(&dev_priv
->irq_lock
);
671 * This timing diagram depicts the video signal in and
672 * around the vertical blanking period.
674 * Assumptions about the fictitious mode used in this example:
676 * vsync_start = vblank_start + 1
677 * vsync_end = vblank_start + 2
678 * vtotal = vblank_start + 3
681 * latch double buffered registers
682 * increment frame counter (ctg+)
683 * generate start of vblank interrupt (gen4+)
686 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
687 * | may be shifted forward 1-3 extra lines via PIPECONF
689 * | | start of vsync:
690 * | | generate vsync interrupt
692 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
693 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
694 * ----va---> <-----------------vb--------------------> <--------va-------------
695 * | | <----vs-----> |
696 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
697 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
698 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
700 * last visible pixel first visible pixel
701 * | increment frame counter (gen3/4)
702 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
704 * x = horizontal active
705 * _ = horizontal blanking
706 * hs = horizontal sync
707 * va = vertical active
708 * vb = vertical blanking
710 * vbs = vblank_start (number)
713 * - most events happen at the start of horizontal sync
714 * - frame start happens at the start of horizontal blank, 1-4 lines
715 * (depending on PIPECONF settings) after the start of vblank
716 * - gen3/4 pixel and frame counter are synchronized with the start
717 * of horizontal active on the first line of vertical active
720 /* Called from drm generic code, passed a 'crtc', which
721 * we use as a pipe index
723 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
725 struct drm_i915_private
*dev_priv
= to_i915(dev
);
726 i915_reg_t high_frame
, low_frame
;
727 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
728 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
730 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
732 htotal
= mode
->crtc_htotal
;
733 hsync_start
= mode
->crtc_hsync_start
;
734 vbl_start
= mode
->crtc_vblank_start
;
735 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
736 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
738 /* Convert to pixel count */
741 /* Start of vblank event occurs at start of hsync */
742 vbl_start
-= htotal
- hsync_start
;
744 high_frame
= PIPEFRAME(pipe
);
745 low_frame
= PIPEFRAMEPIXEL(pipe
);
748 * High & low register fields aren't synchronized, so make sure
749 * we get a low value that's stable across two reads of the high
753 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
754 low
= I915_READ(low_frame
);
755 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
756 } while (high1
!= high2
);
758 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
759 pixel
= low
& PIPE_PIXEL_MASK
;
760 low
>>= PIPE_FRAME_LOW_SHIFT
;
763 * The frame counter increments at beginning of active.
764 * Cook up a vblank counter by also checking the pixel
765 * counter against vblank start.
767 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
770 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
772 struct drm_i915_private
*dev_priv
= to_i915(dev
);
774 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
778 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
780 struct drm_device
*dev
= crtc
->base
.dev
;
781 struct drm_i915_private
*dev_priv
= to_i915(dev
);
782 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
783 enum pipe pipe
= crtc
->pipe
;
784 int position
, vtotal
;
786 vtotal
= mode
->crtc_vtotal
;
787 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
790 if (IS_GEN2(dev_priv
))
791 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
793 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
796 * On HSW, the DSL reg (0x70000) appears to return 0 if we
797 * read it just before the start of vblank. So try it again
798 * so we don't accidentally end up spanning a vblank frame
799 * increment, causing the pipe_update_end() code to squak at us.
801 * The nature of this problem means we can't simply check the ISR
802 * bit and return the vblank start value; nor can we use the scanline
803 * debug register in the transcoder as it appears to have the same
804 * problem. We may need to extend this to include other platforms,
805 * but so far testing only shows the problem on HSW.
807 if (HAS_DDI(dev_priv
) && !position
) {
810 for (i
= 0; i
< 100; i
++) {
812 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
814 if (temp
!= position
) {
822 * See update_scanline_offset() for the details on the
823 * scanline_offset adjustment.
825 return (position
+ crtc
->scanline_offset
) % vtotal
;
828 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
829 unsigned int flags
, int *vpos
, int *hpos
,
830 ktime_t
*stime
, ktime_t
*etime
,
831 const struct drm_display_mode
*mode
)
833 struct drm_i915_private
*dev_priv
= to_i915(dev
);
834 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
837 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
840 unsigned long irqflags
;
842 if (WARN_ON(!mode
->crtc_clock
)) {
843 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
844 "pipe %c\n", pipe_name(pipe
));
848 htotal
= mode
->crtc_htotal
;
849 hsync_start
= mode
->crtc_hsync_start
;
850 vtotal
= mode
->crtc_vtotal
;
851 vbl_start
= mode
->crtc_vblank_start
;
852 vbl_end
= mode
->crtc_vblank_end
;
854 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
855 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
860 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
863 * Lock uncore.lock, as we will do multiple timing critical raw
864 * register reads, potentially with preemption disabled, so the
865 * following code must not block on uncore.lock.
867 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
869 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
871 /* Get optional system timestamp before query. */
873 *stime
= ktime_get();
875 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
876 /* No obvious pixelcount register. Only query vertical
877 * scanout position from Display scan line register.
879 position
= __intel_get_crtc_scanline(intel_crtc
);
881 /* Have access to pixelcount since start of frame.
882 * We can split this into vertical and horizontal
885 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
887 /* convert to pixel counts */
893 * In interlaced modes, the pixel counter counts all pixels,
894 * so one field will have htotal more pixels. In order to avoid
895 * the reported position from jumping backwards when the pixel
896 * counter is beyond the length of the shorter field, just
897 * clamp the position the length of the shorter field. This
898 * matches how the scanline counter based position works since
899 * the scanline counter doesn't count the two half lines.
901 if (position
>= vtotal
)
902 position
= vtotal
- 1;
905 * Start of vblank interrupt is triggered at start of hsync,
906 * just prior to the first active line of vblank. However we
907 * consider lines to start at the leading edge of horizontal
908 * active. So, should we get here before we've crossed into
909 * the horizontal active of the first line in vblank, we would
910 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
911 * always add htotal-hsync_start to the current pixel position.
913 position
= (position
+ htotal
- hsync_start
) % vtotal
;
916 /* Get optional system timestamp after query. */
918 *etime
= ktime_get();
920 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
922 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
924 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
927 * While in vblank, position will be negative
928 * counting up towards 0 at vbl_end. And outside
929 * vblank, position will be positive counting
932 if (position
>= vbl_start
)
935 position
+= vtotal
- vbl_end
;
937 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
941 *vpos
= position
/ htotal
;
942 *hpos
= position
- (*vpos
* htotal
);
947 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
952 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
954 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
955 unsigned long irqflags
;
958 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
959 position
= __intel_get_crtc_scanline(crtc
);
960 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
965 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
967 struct timeval
*vblank_time
,
970 struct drm_i915_private
*dev_priv
= to_i915(dev
);
971 struct intel_crtc
*crtc
;
973 if (pipe
>= INTEL_INFO(dev_priv
)->num_pipes
) {
974 DRM_ERROR("Invalid crtc %u\n", pipe
);
978 /* Get drm_crtc to timestamp: */
979 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
981 DRM_ERROR("Invalid crtc %u\n", pipe
);
985 if (!crtc
->base
.hwmode
.crtc_clock
) {
986 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
990 /* Helper routine in DRM core does all the work: */
991 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
996 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
998 u32 busy_up
, busy_down
, max_avg
, min_avg
;
1001 spin_lock(&mchdev_lock
);
1003 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
1005 new_delay
= dev_priv
->ips
.cur_delay
;
1007 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
1008 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
1009 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
1010 max_avg
= I915_READ(RCBMAXAVG
);
1011 min_avg
= I915_READ(RCBMINAVG
);
1013 /* Handle RCS change request from hw */
1014 if (busy_up
> max_avg
) {
1015 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
1016 new_delay
= dev_priv
->ips
.cur_delay
- 1;
1017 if (new_delay
< dev_priv
->ips
.max_delay
)
1018 new_delay
= dev_priv
->ips
.max_delay
;
1019 } else if (busy_down
< min_avg
) {
1020 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
1021 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
1022 if (new_delay
> dev_priv
->ips
.min_delay
)
1023 new_delay
= dev_priv
->ips
.min_delay
;
1026 if (ironlake_set_drps(dev_priv
, new_delay
))
1027 dev_priv
->ips
.cur_delay
= new_delay
;
1029 spin_unlock(&mchdev_lock
);
1034 static void notify_ring(struct intel_engine_cs
*engine
)
1036 smp_store_mb(engine
->breadcrumbs
.irq_posted
, true);
1037 if (intel_engine_wakeup(engine
))
1038 trace_i915_gem_request_notify(engine
);
1041 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1042 struct intel_rps_ei
*ei
)
1044 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1045 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1046 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1049 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
1050 const struct intel_rps_ei
*old
,
1051 const struct intel_rps_ei
*now
,
1055 unsigned int mul
= 100;
1057 if (old
->cz_clock
== 0)
1060 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1063 time
= now
->cz_clock
- old
->cz_clock
;
1064 time
*= threshold
* dev_priv
->czclk_freq
;
1066 /* Workload can be split between render + media, e.g. SwapBuffers
1067 * being blitted in X after being rendered in mesa. To account for
1068 * this we need to combine both engines into our activity counter.
1070 c0
= now
->render_c0
- old
->render_c0
;
1071 c0
+= now
->media_c0
- old
->media_c0
;
1072 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1077 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1079 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1080 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1083 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1085 struct intel_rps_ei now
;
1088 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1091 vlv_c0_read(dev_priv
, &now
);
1092 if (now
.cz_clock
== 0)
1095 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1096 if (!vlv_c0_above(dev_priv
,
1097 &dev_priv
->rps
.down_ei
, &now
,
1098 dev_priv
->rps
.down_threshold
))
1099 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1100 dev_priv
->rps
.down_ei
= now
;
1103 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1104 if (vlv_c0_above(dev_priv
,
1105 &dev_priv
->rps
.up_ei
, &now
,
1106 dev_priv
->rps
.up_threshold
))
1107 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1108 dev_priv
->rps
.up_ei
= now
;
1114 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1116 struct intel_engine_cs
*engine
;
1117 enum intel_engine_id id
;
1119 for_each_engine(engine
, dev_priv
, id
)
1120 if (intel_engine_has_waiter(engine
))
1126 static void gen6_pm_rps_work(struct work_struct
*work
)
1128 struct drm_i915_private
*dev_priv
=
1129 container_of(work
, struct drm_i915_private
, rps
.work
);
1131 int new_delay
, adj
, min
, max
;
1134 spin_lock_irq(&dev_priv
->irq_lock
);
1135 /* Speed up work cancelation during disabling rps interrupts. */
1136 if (!dev_priv
->rps
.interrupts_enabled
) {
1137 spin_unlock_irq(&dev_priv
->irq_lock
);
1141 pm_iir
= dev_priv
->rps
.pm_iir
;
1142 dev_priv
->rps
.pm_iir
= 0;
1143 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1144 gen6_unmask_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1145 client_boost
= dev_priv
->rps
.client_boost
;
1146 dev_priv
->rps
.client_boost
= false;
1147 spin_unlock_irq(&dev_priv
->irq_lock
);
1149 /* Make sure we didn't queue anything we're not going to process. */
1150 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1152 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1155 mutex_lock(&dev_priv
->rps
.hw_lock
);
1157 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1159 adj
= dev_priv
->rps
.last_adj
;
1160 new_delay
= dev_priv
->rps
.cur_freq
;
1161 min
= dev_priv
->rps
.min_freq_softlimit
;
1162 max
= dev_priv
->rps
.max_freq_softlimit
;
1163 if (client_boost
|| any_waiters(dev_priv
))
1164 max
= dev_priv
->rps
.max_freq
;
1165 if (client_boost
&& new_delay
< dev_priv
->rps
.boost_freq
) {
1166 new_delay
= dev_priv
->rps
.boost_freq
;
1168 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1171 else /* CHV needs even encode values */
1172 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1174 * For better performance, jump directly
1175 * to RPe if we're below it.
1177 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1178 new_delay
= dev_priv
->rps
.efficient_freq
;
1181 } else if (client_boost
|| any_waiters(dev_priv
)) {
1183 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1184 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1185 new_delay
= dev_priv
->rps
.efficient_freq
;
1187 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1189 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1192 else /* CHV needs even encode values */
1193 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1194 } else { /* unknown event */
1198 dev_priv
->rps
.last_adj
= adj
;
1200 /* sysfs frequency interfaces may have snuck in while servicing the
1204 new_delay
= clamp_t(int, new_delay
, min
, max
);
1206 intel_set_rps(dev_priv
, new_delay
);
1208 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1213 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1215 * @work: workqueue struct
1217 * Doesn't actually do anything except notify userspace. As a consequence of
1218 * this event, userspace should try to remap the bad rows since statistically
1219 * it is likely the same row is more likely to go bad again.
1221 static void ivybridge_parity_work(struct work_struct
*work
)
1223 struct drm_i915_private
*dev_priv
=
1224 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1225 u32 error_status
, row
, bank
, subbank
;
1226 char *parity_event
[6];
1230 /* We must turn off DOP level clock gating to access the L3 registers.
1231 * In order to prevent a get/put style interface, acquire struct mutex
1232 * any time we access those registers.
1234 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1236 /* If we've screwed up tracking, just let the interrupt fire again */
1237 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1240 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1241 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1242 POSTING_READ(GEN7_MISCCPCTL
);
1244 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1248 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1251 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1253 reg
= GEN7_L3CDERRST1(slice
);
1255 error_status
= I915_READ(reg
);
1256 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1257 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1258 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1260 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1263 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1264 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1265 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1266 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1267 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1268 parity_event
[5] = NULL
;
1270 kobject_uevent_env(&dev_priv
->drm
.primary
->kdev
->kobj
,
1271 KOBJ_CHANGE
, parity_event
);
1273 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1274 slice
, row
, bank
, subbank
);
1276 kfree(parity_event
[4]);
1277 kfree(parity_event
[3]);
1278 kfree(parity_event
[2]);
1279 kfree(parity_event
[1]);
1282 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1285 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1286 spin_lock_irq(&dev_priv
->irq_lock
);
1287 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1288 spin_unlock_irq(&dev_priv
->irq_lock
);
1290 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1293 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1296 if (!HAS_L3_DPF(dev_priv
))
1299 spin_lock(&dev_priv
->irq_lock
);
1300 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1301 spin_unlock(&dev_priv
->irq_lock
);
1303 iir
&= GT_PARITY_ERROR(dev_priv
);
1304 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1305 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1307 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1308 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1310 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1313 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1316 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1317 notify_ring(dev_priv
->engine
[RCS
]);
1318 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1319 notify_ring(dev_priv
->engine
[VCS
]);
1322 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1325 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1326 notify_ring(dev_priv
->engine
[RCS
]);
1327 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1328 notify_ring(dev_priv
->engine
[VCS
]);
1329 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1330 notify_ring(dev_priv
->engine
[BCS
]);
1332 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1333 GT_BSD_CS_ERROR_INTERRUPT
|
1334 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1335 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1337 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1338 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1341 static __always_inline
void
1342 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1344 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1345 notify_ring(engine
);
1346 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1347 tasklet_schedule(&engine
->irq_tasklet
);
1350 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1354 irqreturn_t ret
= IRQ_NONE
;
1356 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1357 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1359 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1362 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1365 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1366 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1368 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1371 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1374 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1375 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1377 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1380 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1383 if (master_ctl
& (GEN8_GT_PM_IRQ
| GEN8_GT_GUC_IRQ
)) {
1384 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1385 if (gt_iir
[2] & (dev_priv
->pm_rps_events
|
1386 dev_priv
->pm_guc_events
)) {
1387 I915_WRITE_FW(GEN8_GT_IIR(2),
1388 gt_iir
[2] & (dev_priv
->pm_rps_events
|
1389 dev_priv
->pm_guc_events
));
1392 DRM_ERROR("The master control interrupt lied (PM)!\n");
1398 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1402 gen8_cs_irq_handler(dev_priv
->engine
[RCS
],
1403 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1404 gen8_cs_irq_handler(dev_priv
->engine
[BCS
],
1405 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1409 gen8_cs_irq_handler(dev_priv
->engine
[VCS
],
1410 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1411 gen8_cs_irq_handler(dev_priv
->engine
[VCS2
],
1412 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1416 gen8_cs_irq_handler(dev_priv
->engine
[VECS
],
1417 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1419 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1420 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1422 if (gt_iir
[2] & dev_priv
->pm_guc_events
)
1423 gen9_guc_irq_handler(dev_priv
, gt_iir
[2]);
1426 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1430 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1432 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1434 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1440 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1444 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1450 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1454 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1456 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1458 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1460 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1466 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1470 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1476 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1480 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1482 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1484 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1490 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1494 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1496 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1498 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1505 * Get a bit mask of pins that have triggered, and which ones may be long.
1506 * This can be called multiple times with the same masks to accumulate
1507 * hotplug detection results from several registers.
1509 * Note that the caller is expected to zero out the masks initially.
1511 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1512 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1513 const u32 hpd
[HPD_NUM_PINS
],
1514 bool long_pulse_detect(enum port port
, u32 val
))
1519 for_each_hpd_pin(i
) {
1520 if ((hpd
[i
] & hotplug_trigger
) == 0)
1523 *pin_mask
|= BIT(i
);
1525 if (!intel_hpd_pin_to_port(i
, &port
))
1528 if (long_pulse_detect(port
, dig_hotplug_reg
))
1529 *long_mask
|= BIT(i
);
1532 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1533 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1537 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1539 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1542 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1544 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1547 #if defined(CONFIG_DEBUG_FS)
1548 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1550 uint32_t crc0
, uint32_t crc1
,
1551 uint32_t crc2
, uint32_t crc3
,
1554 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1555 struct intel_pipe_crc_entry
*entry
;
1558 spin_lock(&pipe_crc
->lock
);
1560 if (!pipe_crc
->entries
) {
1561 spin_unlock(&pipe_crc
->lock
);
1562 DRM_DEBUG_KMS("spurious interrupt\n");
1566 head
= pipe_crc
->head
;
1567 tail
= pipe_crc
->tail
;
1569 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1570 spin_unlock(&pipe_crc
->lock
);
1571 DRM_ERROR("CRC buffer overflowing\n");
1575 entry
= &pipe_crc
->entries
[head
];
1577 entry
->frame
= dev_priv
->drm
.driver
->get_vblank_counter(&dev_priv
->drm
,
1579 entry
->crc
[0] = crc0
;
1580 entry
->crc
[1] = crc1
;
1581 entry
->crc
[2] = crc2
;
1582 entry
->crc
[3] = crc3
;
1583 entry
->crc
[4] = crc4
;
1585 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1586 pipe_crc
->head
= head
;
1588 spin_unlock(&pipe_crc
->lock
);
1590 wake_up_interruptible(&pipe_crc
->wq
);
1594 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1596 uint32_t crc0
, uint32_t crc1
,
1597 uint32_t crc2
, uint32_t crc3
,
1602 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1605 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1606 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1610 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1613 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1614 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1615 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1616 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1617 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1618 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1621 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1624 uint32_t res1
, res2
;
1626 if (INTEL_GEN(dev_priv
) >= 3)
1627 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1631 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1632 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1636 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1637 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1638 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1639 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1643 /* The RPS events need forcewake, so we add them to a work queue and mask their
1644 * IMR bits until the work is done. Other interrupts can be processed without
1645 * the work queue. */
1646 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1648 if (pm_iir
& dev_priv
->pm_rps_events
) {
1649 spin_lock(&dev_priv
->irq_lock
);
1650 gen6_mask_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1651 if (dev_priv
->rps
.interrupts_enabled
) {
1652 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1653 schedule_work(&dev_priv
->rps
.work
);
1655 spin_unlock(&dev_priv
->irq_lock
);
1658 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1661 if (HAS_VEBOX(dev_priv
)) {
1662 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1663 notify_ring(dev_priv
->engine
[VECS
]);
1665 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1666 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1670 static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv
, u32 gt_iir
)
1672 if (gt_iir
& GEN9_GUC_TO_HOST_INT_EVENT
) {
1673 /* Sample the log buffer flush related bits & clear them out now
1674 * itself from the message identity register to minimize the
1675 * probability of losing a flush interrupt, when there are back
1676 * to back flush interrupts.
1677 * There can be a new flush interrupt, for different log buffer
1678 * type (like for ISR), whilst Host is handling one (for DPC).
1679 * Since same bit is used in message register for ISR & DPC, it
1680 * could happen that GuC sets the bit for 2nd interrupt but Host
1681 * clears out the bit on handling the 1st interrupt.
1685 msg
= I915_READ(SOFT_SCRATCH(15));
1686 flush
= msg
& (GUC2HOST_MSG_CRASH_DUMP_POSTED
|
1687 GUC2HOST_MSG_FLUSH_LOG_BUFFER
);
1689 /* Clear the message bits that are handled */
1690 I915_WRITE(SOFT_SCRATCH(15), msg
& ~flush
);
1692 /* Handle flush interrupt in bottom half */
1693 queue_work(dev_priv
->guc
.log
.flush_wq
,
1694 &dev_priv
->guc
.log
.flush_work
);
1696 dev_priv
->guc
.log
.flush_interrupt_count
++;
1698 /* Not clearing of unhandled event bits won't result in
1699 * re-triggering of the interrupt.
1705 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1710 ret
= drm_handle_vblank(&dev_priv
->drm
, pipe
);
1712 intel_finish_page_flip_mmio(dev_priv
, pipe
);
1717 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1718 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1722 spin_lock(&dev_priv
->irq_lock
);
1724 if (!dev_priv
->display_irqs_enabled
) {
1725 spin_unlock(&dev_priv
->irq_lock
);
1729 for_each_pipe(dev_priv
, pipe
) {
1731 u32 mask
, iir_bit
= 0;
1734 * PIPESTAT bits get signalled even when the interrupt is
1735 * disabled with the mask bits, and some of the status bits do
1736 * not generate interrupts at all (like the underrun bit). Hence
1737 * we need to be careful that we only handle what we want to
1741 /* fifo underruns are filterered in the underrun handler. */
1742 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1746 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1749 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1752 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1756 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1761 reg
= PIPESTAT(pipe
);
1762 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1763 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1766 * Clear the PIPE*STAT regs before the IIR
1768 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1769 PIPESTAT_INT_STATUS_MASK
))
1770 I915_WRITE(reg
, pipe_stats
[pipe
]);
1772 spin_unlock(&dev_priv
->irq_lock
);
1775 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1776 u32 pipe_stats
[I915_MAX_PIPES
])
1780 for_each_pipe(dev_priv
, pipe
) {
1781 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1782 intel_pipe_handle_vblank(dev_priv
, pipe
))
1783 intel_check_page_flip(dev_priv
, pipe
);
1785 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
)
1786 intel_finish_page_flip_cs(dev_priv
, pipe
);
1788 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1789 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1791 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1792 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1795 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1796 gmbus_irq_handler(dev_priv
);
1799 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1801 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1804 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1806 return hotplug_status
;
1809 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1812 u32 pin_mask
= 0, long_mask
= 0;
1814 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1815 IS_CHERRYVIEW(dev_priv
)) {
1816 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1818 if (hotplug_trigger
) {
1819 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1820 hotplug_trigger
, hpd_status_g4x
,
1821 i9xx_port_hotplug_long_detect
);
1823 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1826 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1827 dp_aux_irq_handler(dev_priv
);
1829 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1831 if (hotplug_trigger
) {
1832 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1833 hotplug_trigger
, hpd_status_i915
,
1834 i9xx_port_hotplug_long_detect
);
1835 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1840 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1842 struct drm_device
*dev
= arg
;
1843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1844 irqreturn_t ret
= IRQ_NONE
;
1846 if (!intel_irqs_enabled(dev_priv
))
1849 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1850 disable_rpm_wakeref_asserts(dev_priv
);
1853 u32 iir
, gt_iir
, pm_iir
;
1854 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1855 u32 hotplug_status
= 0;
1858 gt_iir
= I915_READ(GTIIR
);
1859 pm_iir
= I915_READ(GEN6_PMIIR
);
1860 iir
= I915_READ(VLV_IIR
);
1862 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1868 * Theory on interrupt generation, based on empirical evidence:
1870 * x = ((VLV_IIR & VLV_IER) ||
1871 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1872 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1874 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1875 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1876 * guarantee the CPU interrupt will be raised again even if we
1877 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1878 * bits this time around.
1880 I915_WRITE(VLV_MASTER_IER
, 0);
1881 ier
= I915_READ(VLV_IER
);
1882 I915_WRITE(VLV_IER
, 0);
1885 I915_WRITE(GTIIR
, gt_iir
);
1887 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1889 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1890 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1892 /* Call regardless, as some status bits might not be
1893 * signalled in iir */
1894 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1897 * VLV_IIR is single buffered, and reflects the level
1898 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1901 I915_WRITE(VLV_IIR
, iir
);
1903 I915_WRITE(VLV_IER
, ier
);
1904 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1905 POSTING_READ(VLV_MASTER_IER
);
1908 snb_gt_irq_handler(dev_priv
, gt_iir
);
1910 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1913 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1915 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1918 enable_rpm_wakeref_asserts(dev_priv
);
1923 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1925 struct drm_device
*dev
= arg
;
1926 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1927 irqreturn_t ret
= IRQ_NONE
;
1929 if (!intel_irqs_enabled(dev_priv
))
1932 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1933 disable_rpm_wakeref_asserts(dev_priv
);
1936 u32 master_ctl
, iir
;
1938 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1939 u32 hotplug_status
= 0;
1942 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1943 iir
= I915_READ(VLV_IIR
);
1945 if (master_ctl
== 0 && iir
== 0)
1951 * Theory on interrupt generation, based on empirical evidence:
1953 * x = ((VLV_IIR & VLV_IER) ||
1954 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1955 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1957 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1958 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1959 * guarantee the CPU interrupt will be raised again even if we
1960 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1961 * bits this time around.
1963 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1964 ier
= I915_READ(VLV_IER
);
1965 I915_WRITE(VLV_IER
, 0);
1967 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1969 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1970 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1972 /* Call regardless, as some status bits might not be
1973 * signalled in iir */
1974 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1977 * VLV_IIR is single buffered, and reflects the level
1978 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1981 I915_WRITE(VLV_IIR
, iir
);
1983 I915_WRITE(VLV_IER
, ier
);
1984 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1985 POSTING_READ(GEN8_MASTER_IRQ
);
1987 gen8_gt_irq_handler(dev_priv
, gt_iir
);
1990 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1992 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1995 enable_rpm_wakeref_asserts(dev_priv
);
2000 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2001 u32 hotplug_trigger
,
2002 const u32 hpd
[HPD_NUM_PINS
])
2004 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2007 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2008 * unless we touch the hotplug register, even if hotplug_trigger is
2009 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2012 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2013 if (!hotplug_trigger
) {
2014 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
2015 PORTD_HOTPLUG_STATUS_MASK
|
2016 PORTC_HOTPLUG_STATUS_MASK
|
2017 PORTB_HOTPLUG_STATUS_MASK
;
2018 dig_hotplug_reg
&= ~mask
;
2021 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2022 if (!hotplug_trigger
)
2025 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2026 dig_hotplug_reg
, hpd
,
2027 pch_port_hotplug_long_detect
);
2029 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2032 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2035 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
2037 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
2039 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
2040 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
2041 SDE_AUDIO_POWER_SHIFT
);
2042 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2046 if (pch_iir
& SDE_AUX_MASK
)
2047 dp_aux_irq_handler(dev_priv
);
2049 if (pch_iir
& SDE_GMBUS
)
2050 gmbus_irq_handler(dev_priv
);
2052 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
2053 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2055 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
2056 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2058 if (pch_iir
& SDE_POISON
)
2059 DRM_ERROR("PCH poison interrupt\n");
2061 if (pch_iir
& SDE_FDI_MASK
)
2062 for_each_pipe(dev_priv
, pipe
)
2063 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2065 I915_READ(FDI_RX_IIR(pipe
)));
2067 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
2068 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2070 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
2071 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2073 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
2074 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2076 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
2077 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2080 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
2082 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2085 if (err_int
& ERR_INT_POISON
)
2086 DRM_ERROR("Poison interrupt\n");
2088 for_each_pipe(dev_priv
, pipe
) {
2089 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2090 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2092 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2093 if (IS_IVYBRIDGE(dev_priv
))
2094 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
2096 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2100 I915_WRITE(GEN7_ERR_INT
, err_int
);
2103 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2105 u32 serr_int
= I915_READ(SERR_INT
);
2107 if (serr_int
& SERR_INT_POISON
)
2108 DRM_ERROR("PCH poison interrupt\n");
2110 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2111 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2113 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2114 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2116 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2117 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2119 I915_WRITE(SERR_INT
, serr_int
);
2122 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2125 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2127 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2129 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2130 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2131 SDE_AUDIO_POWER_SHIFT_CPT
);
2132 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2136 if (pch_iir
& SDE_AUX_MASK_CPT
)
2137 dp_aux_irq_handler(dev_priv
);
2139 if (pch_iir
& SDE_GMBUS_CPT
)
2140 gmbus_irq_handler(dev_priv
);
2142 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2143 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2145 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2146 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2148 if (pch_iir
& SDE_FDI_MASK_CPT
)
2149 for_each_pipe(dev_priv
, pipe
)
2150 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2152 I915_READ(FDI_RX_IIR(pipe
)));
2154 if (pch_iir
& SDE_ERROR_CPT
)
2155 cpt_serr_int_handler(dev_priv
);
2158 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2160 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2161 ~SDE_PORTE_HOTPLUG_SPT
;
2162 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2163 u32 pin_mask
= 0, long_mask
= 0;
2165 if (hotplug_trigger
) {
2166 u32 dig_hotplug_reg
;
2168 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2169 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2171 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2172 dig_hotplug_reg
, hpd_spt
,
2173 spt_port_hotplug_long_detect
);
2176 if (hotplug2_trigger
) {
2177 u32 dig_hotplug_reg
;
2179 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2180 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2182 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2183 dig_hotplug_reg
, hpd_spt
,
2184 spt_port_hotplug2_long_detect
);
2188 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2190 if (pch_iir
& SDE_GMBUS_CPT
)
2191 gmbus_irq_handler(dev_priv
);
2194 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2195 u32 hotplug_trigger
,
2196 const u32 hpd
[HPD_NUM_PINS
])
2198 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2200 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2201 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2203 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2204 dig_hotplug_reg
, hpd
,
2205 ilk_port_hotplug_long_detect
);
2207 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2210 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2214 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2216 if (hotplug_trigger
)
2217 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2219 if (de_iir
& DE_AUX_CHANNEL_A
)
2220 dp_aux_irq_handler(dev_priv
);
2222 if (de_iir
& DE_GSE
)
2223 intel_opregion_asle_intr(dev_priv
);
2225 if (de_iir
& DE_POISON
)
2226 DRM_ERROR("Poison interrupt\n");
2228 for_each_pipe(dev_priv
, pipe
) {
2229 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2230 intel_pipe_handle_vblank(dev_priv
, pipe
))
2231 intel_check_page_flip(dev_priv
, pipe
);
2233 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2234 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2236 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2237 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2239 /* plane/pipes map 1:1 on ilk+ */
2240 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
))
2241 intel_finish_page_flip_cs(dev_priv
, pipe
);
2244 /* check event from PCH */
2245 if (de_iir
& DE_PCH_EVENT
) {
2246 u32 pch_iir
= I915_READ(SDEIIR
);
2248 if (HAS_PCH_CPT(dev_priv
))
2249 cpt_irq_handler(dev_priv
, pch_iir
);
2251 ibx_irq_handler(dev_priv
, pch_iir
);
2253 /* should clear PCH hotplug event before clear CPU irq */
2254 I915_WRITE(SDEIIR
, pch_iir
);
2257 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2258 ironlake_rps_change_irq_handler(dev_priv
);
2261 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2265 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2267 if (hotplug_trigger
)
2268 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2270 if (de_iir
& DE_ERR_INT_IVB
)
2271 ivb_err_int_handler(dev_priv
);
2273 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2274 dp_aux_irq_handler(dev_priv
);
2276 if (de_iir
& DE_GSE_IVB
)
2277 intel_opregion_asle_intr(dev_priv
);
2279 for_each_pipe(dev_priv
, pipe
) {
2280 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2281 intel_pipe_handle_vblank(dev_priv
, pipe
))
2282 intel_check_page_flip(dev_priv
, pipe
);
2284 /* plane/pipes map 1:1 on ilk+ */
2285 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
))
2286 intel_finish_page_flip_cs(dev_priv
, pipe
);
2289 /* check event from PCH */
2290 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2291 u32 pch_iir
= I915_READ(SDEIIR
);
2293 cpt_irq_handler(dev_priv
, pch_iir
);
2295 /* clear PCH hotplug event before clear CPU irq */
2296 I915_WRITE(SDEIIR
, pch_iir
);
2301 * To handle irqs with the minimum potential races with fresh interrupts, we:
2302 * 1 - Disable Master Interrupt Control.
2303 * 2 - Find the source(s) of the interrupt.
2304 * 3 - Clear the Interrupt Identity bits (IIR).
2305 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2306 * 5 - Re-enable Master Interrupt Control.
2308 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2310 struct drm_device
*dev
= arg
;
2311 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2312 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2313 irqreturn_t ret
= IRQ_NONE
;
2315 if (!intel_irqs_enabled(dev_priv
))
2318 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2319 disable_rpm_wakeref_asserts(dev_priv
);
2321 /* disable master interrupt before clearing iir */
2322 de_ier
= I915_READ(DEIER
);
2323 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2324 POSTING_READ(DEIER
);
2326 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2327 * interrupts will will be stored on its back queue, and then we'll be
2328 * able to process them after we restore SDEIER (as soon as we restore
2329 * it, we'll get an interrupt if SDEIIR still has something to process
2330 * due to its back queue). */
2331 if (!HAS_PCH_NOP(dev_priv
)) {
2332 sde_ier
= I915_READ(SDEIER
);
2333 I915_WRITE(SDEIER
, 0);
2334 POSTING_READ(SDEIER
);
2337 /* Find, clear, then process each source of interrupt */
2339 gt_iir
= I915_READ(GTIIR
);
2341 I915_WRITE(GTIIR
, gt_iir
);
2343 if (INTEL_GEN(dev_priv
) >= 6)
2344 snb_gt_irq_handler(dev_priv
, gt_iir
);
2346 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2349 de_iir
= I915_READ(DEIIR
);
2351 I915_WRITE(DEIIR
, de_iir
);
2353 if (INTEL_GEN(dev_priv
) >= 7)
2354 ivb_display_irq_handler(dev_priv
, de_iir
);
2356 ilk_display_irq_handler(dev_priv
, de_iir
);
2359 if (INTEL_GEN(dev_priv
) >= 6) {
2360 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2362 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2364 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2368 I915_WRITE(DEIER
, de_ier
);
2369 POSTING_READ(DEIER
);
2370 if (!HAS_PCH_NOP(dev_priv
)) {
2371 I915_WRITE(SDEIER
, sde_ier
);
2372 POSTING_READ(SDEIER
);
2375 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2376 enable_rpm_wakeref_asserts(dev_priv
);
2381 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2382 u32 hotplug_trigger
,
2383 const u32 hpd
[HPD_NUM_PINS
])
2385 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2387 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2388 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2390 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2391 dig_hotplug_reg
, hpd
,
2392 bxt_port_hotplug_long_detect
);
2394 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2398 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2400 irqreturn_t ret
= IRQ_NONE
;
2404 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2405 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2407 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2409 if (iir
& GEN8_DE_MISC_GSE
)
2410 intel_opregion_asle_intr(dev_priv
);
2412 DRM_ERROR("Unexpected DE Misc interrupt\n");
2415 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2418 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2419 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2424 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2427 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2428 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2429 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2430 GEN9_AUX_CHANNEL_C
|
2433 if (iir
& tmp_mask
) {
2434 dp_aux_irq_handler(dev_priv
);
2438 if (IS_BROXTON(dev_priv
)) {
2439 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2441 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2445 } else if (IS_BROADWELL(dev_priv
)) {
2446 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2448 ilk_hpd_irq_handler(dev_priv
,
2454 if (IS_BROXTON(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2455 gmbus_irq_handler(dev_priv
);
2460 DRM_ERROR("Unexpected DE Port interrupt\n");
2463 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2466 for_each_pipe(dev_priv
, pipe
) {
2467 u32 flip_done
, fault_errors
;
2469 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2472 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2474 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2479 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2481 if (iir
& GEN8_PIPE_VBLANK
&&
2482 intel_pipe_handle_vblank(dev_priv
, pipe
))
2483 intel_check_page_flip(dev_priv
, pipe
);
2486 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2487 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2489 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2492 intel_finish_page_flip_cs(dev_priv
, pipe
);
2494 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2495 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2497 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2498 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2501 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2502 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2504 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2507 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2512 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2513 master_ctl
& GEN8_DE_PCH_IRQ
) {
2515 * FIXME(BDW): Assume for now that the new interrupt handling
2516 * scheme also closed the SDE interrupt handling race we've seen
2517 * on older pch-split platforms. But this needs testing.
2519 iir
= I915_READ(SDEIIR
);
2521 I915_WRITE(SDEIIR
, iir
);
2524 if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
))
2525 spt_irq_handler(dev_priv
, iir
);
2527 cpt_irq_handler(dev_priv
, iir
);
2530 * Like on previous PCH there seems to be something
2531 * fishy going on with forwarding PCH interrupts.
2533 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2540 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2542 struct drm_device
*dev
= arg
;
2543 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2548 if (!intel_irqs_enabled(dev_priv
))
2551 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2552 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2556 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2558 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2559 disable_rpm_wakeref_asserts(dev_priv
);
2561 /* Find, clear, then process each source of interrupt */
2562 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2563 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2564 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2566 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2567 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2569 enable_rpm_wakeref_asserts(dev_priv
);
2574 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
)
2577 * Notify all waiters for GPU completion events that reset state has
2578 * been changed, and that they need to restart their wait after
2579 * checking for potential errors (and bail out to drop locks if there is
2580 * a gpu reset pending so that i915_error_work_func can acquire them).
2583 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2584 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
2586 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2587 wake_up_all(&dev_priv
->pending_flip_queue
);
2591 * i915_reset_and_wakeup - do process context error handling work
2592 * @dev_priv: i915 device private
2594 * Fire an error uevent so userspace can see that a hang or error
2597 static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv
)
2599 struct kobject
*kobj
= &dev_priv
->drm
.primary
->kdev
->kobj
;
2600 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2601 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2602 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2604 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2606 DRM_DEBUG_DRIVER("resetting chip\n");
2607 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2610 * In most cases it's guaranteed that we get here with an RPM
2611 * reference held, for example because there is a pending GPU
2612 * request that won't finish until the reset is done. This
2613 * isn't the case at least when we get here by doing a
2614 * simulated reset via debugs, so get an RPM reference.
2616 intel_runtime_pm_get(dev_priv
);
2617 intel_prepare_reset(dev_priv
);
2621 * All state reset _must_ be completed before we update the
2622 * reset counter, for otherwise waiters might miss the reset
2623 * pending state and not properly drop locks, resulting in
2624 * deadlocks with the reset work.
2626 if (mutex_trylock(&dev_priv
->drm
.struct_mutex
)) {
2627 i915_reset(dev_priv
);
2628 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2631 /* We need to wait for anyone holding the lock to wakeup */
2632 } while (wait_on_bit_timeout(&dev_priv
->gpu_error
.flags
,
2633 I915_RESET_IN_PROGRESS
,
2634 TASK_UNINTERRUPTIBLE
,
2637 intel_finish_reset(dev_priv
);
2638 intel_runtime_pm_put(dev_priv
);
2640 if (!test_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
))
2641 kobject_uevent_env(kobj
,
2642 KOBJ_CHANGE
, reset_done_event
);
2645 * Note: The wake_up also serves as a memory barrier so that
2646 * waiters see the updated value of the dev_priv->gpu_error.
2648 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2652 i915_err_print_instdone(struct drm_i915_private
*dev_priv
,
2653 struct intel_instdone
*instdone
)
2658 pr_err(" INSTDONE: 0x%08x\n", instdone
->instdone
);
2660 if (INTEL_GEN(dev_priv
) <= 3)
2663 pr_err(" SC_INSTDONE: 0x%08x\n", instdone
->slice_common
);
2665 if (INTEL_GEN(dev_priv
) <= 6)
2668 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
2669 pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2670 slice
, subslice
, instdone
->sampler
[slice
][subslice
]);
2672 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
2673 pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n",
2674 slice
, subslice
, instdone
->row
[slice
][subslice
]);
2677 static void i915_clear_error_registers(struct drm_i915_private
*dev_priv
)
2681 if (!IS_GEN2(dev_priv
))
2682 I915_WRITE(PGTBL_ER
, I915_READ(PGTBL_ER
));
2684 if (INTEL_GEN(dev_priv
) < 4)
2685 I915_WRITE(IPEIR
, I915_READ(IPEIR
));
2687 I915_WRITE(IPEIR_I965
, I915_READ(IPEIR_I965
));
2689 I915_WRITE(EIR
, I915_READ(EIR
));
2690 eir
= I915_READ(EIR
);
2693 * some errors might have become stuck,
2696 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir
);
2697 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2698 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2703 * i915_handle_error - handle a gpu error
2704 * @dev_priv: i915 device private
2705 * @engine_mask: mask representing engines that are hung
2706 * Do some basic checking of register state at error time and
2707 * dump it to the syslog. Also call i915_capture_error_state() to make
2708 * sure we get a record and make it available in debugfs. Fire a uevent
2709 * so userspace knows something bad happened (should trigger collection
2710 * of a ring dump etc.).
2711 * @fmt: Error message format string
2713 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2715 const char *fmt
, ...)
2720 va_start(args
, fmt
);
2721 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2724 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2725 i915_clear_error_registers(dev_priv
);
2730 if (test_and_set_bit(I915_RESET_IN_PROGRESS
,
2731 &dev_priv
->gpu_error
.flags
))
2735 * Wakeup waiting processes so that the reset function
2736 * i915_reset_and_wakeup doesn't deadlock trying to grab
2737 * various locks. By bumping the reset counter first, the woken
2738 * processes will see a reset in progress and back off,
2739 * releasing their locks and then wait for the reset completion.
2740 * We must do this for _all_ gpu waiters that might hold locks
2741 * that the reset work needs to acquire.
2743 * Note: The wake_up also provides a memory barrier to ensure that the
2744 * waiters see the updated value of the reset flags.
2746 i915_error_wake_up(dev_priv
);
2748 i915_reset_and_wakeup(dev_priv
);
2751 /* Called from drm generic code, passed 'crtc' which
2752 * we use as a pipe index
2754 static int i8xx_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2757 unsigned long irqflags
;
2759 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2760 i915_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2761 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2766 static int i965_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2769 unsigned long irqflags
;
2771 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2772 i915_enable_pipestat(dev_priv
, pipe
,
2773 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2774 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2779 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2781 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2782 unsigned long irqflags
;
2783 uint32_t bit
= INTEL_GEN(dev_priv
) >= 7 ?
2784 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2786 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2787 ilk_enable_display_irq(dev_priv
, bit
);
2788 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2793 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2795 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2796 unsigned long irqflags
;
2798 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2799 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2800 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2805 /* Called from drm generic code, passed 'crtc' which
2806 * we use as a pipe index
2808 static void i8xx_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2810 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2811 unsigned long irqflags
;
2813 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2814 i915_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2815 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2818 static void i965_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2820 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2821 unsigned long irqflags
;
2823 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2824 i915_disable_pipestat(dev_priv
, pipe
,
2825 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2826 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2829 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2831 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2832 unsigned long irqflags
;
2833 uint32_t bit
= INTEL_GEN(dev_priv
) >= 7 ?
2834 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2836 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2837 ilk_disable_display_irq(dev_priv
, bit
);
2838 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2841 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2844 unsigned long irqflags
;
2846 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2847 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2848 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2851 static void ibx_irq_reset(struct drm_i915_private
*dev_priv
)
2853 if (HAS_PCH_NOP(dev_priv
))
2856 GEN5_IRQ_RESET(SDE
);
2858 if (HAS_PCH_CPT(dev_priv
) || HAS_PCH_LPT(dev_priv
))
2859 I915_WRITE(SERR_INT
, 0xffffffff);
2863 * SDEIER is also touched by the interrupt handler to work around missed PCH
2864 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2865 * instead we unconditionally enable all PCH interrupt sources here, but then
2866 * only unmask them as needed with SDEIMR.
2868 * This function needs to be called before interrupts are enabled.
2870 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
2872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2874 if (HAS_PCH_NOP(dev_priv
))
2877 WARN_ON(I915_READ(SDEIER
) != 0);
2878 I915_WRITE(SDEIER
, 0xffffffff);
2879 POSTING_READ(SDEIER
);
2882 static void gen5_gt_irq_reset(struct drm_i915_private
*dev_priv
)
2885 if (INTEL_GEN(dev_priv
) >= 6)
2886 GEN5_IRQ_RESET(GEN6_PM
);
2889 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
2893 if (IS_CHERRYVIEW(dev_priv
))
2894 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
2896 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2898 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
2899 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2901 for_each_pipe(dev_priv
, pipe
) {
2902 I915_WRITE(PIPESTAT(pipe
),
2903 PIPE_FIFO_UNDERRUN_STATUS
|
2904 PIPESTAT_INT_STATUS_MASK
);
2905 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
2908 GEN5_IRQ_RESET(VLV_
);
2909 dev_priv
->irq_mask
= ~0;
2912 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
2918 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
2919 PIPE_CRC_DONE_INTERRUPT_STATUS
;
2921 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
2922 for_each_pipe(dev_priv
, pipe
)
2923 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
2925 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
2926 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2927 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
2928 if (IS_CHERRYVIEW(dev_priv
))
2929 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
2931 WARN_ON(dev_priv
->irq_mask
!= ~0);
2933 dev_priv
->irq_mask
= ~enable_mask
;
2935 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
2940 static void ironlake_irq_reset(struct drm_device
*dev
)
2942 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2944 I915_WRITE(HWSTAM
, 0xffffffff);
2947 if (IS_GEN7(dev_priv
))
2948 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
2950 gen5_gt_irq_reset(dev_priv
);
2952 ibx_irq_reset(dev_priv
);
2955 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2957 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2959 I915_WRITE(VLV_MASTER_IER
, 0);
2960 POSTING_READ(VLV_MASTER_IER
);
2962 gen5_gt_irq_reset(dev_priv
);
2964 spin_lock_irq(&dev_priv
->irq_lock
);
2965 if (dev_priv
->display_irqs_enabled
)
2966 vlv_display_irq_reset(dev_priv
);
2967 spin_unlock_irq(&dev_priv
->irq_lock
);
2970 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
2972 GEN8_IRQ_RESET_NDX(GT
, 0);
2973 GEN8_IRQ_RESET_NDX(GT
, 1);
2974 GEN8_IRQ_RESET_NDX(GT
, 2);
2975 GEN8_IRQ_RESET_NDX(GT
, 3);
2978 static void gen8_irq_reset(struct drm_device
*dev
)
2980 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2983 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2984 POSTING_READ(GEN8_MASTER_IRQ
);
2986 gen8_gt_irq_reset(dev_priv
);
2988 for_each_pipe(dev_priv
, pipe
)
2989 if (intel_display_power_is_enabled(dev_priv
,
2990 POWER_DOMAIN_PIPE(pipe
)))
2991 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
2993 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
2994 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
2995 GEN5_IRQ_RESET(GEN8_PCU_
);
2997 if (HAS_PCH_SPLIT(dev_priv
))
2998 ibx_irq_reset(dev_priv
);
3001 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3002 unsigned int pipe_mask
)
3004 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3007 spin_lock_irq(&dev_priv
->irq_lock
);
3008 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3009 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3010 dev_priv
->de_irq_mask
[pipe
],
3011 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3012 spin_unlock_irq(&dev_priv
->irq_lock
);
3015 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3016 unsigned int pipe_mask
)
3020 spin_lock_irq(&dev_priv
->irq_lock
);
3021 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3022 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3023 spin_unlock_irq(&dev_priv
->irq_lock
);
3025 /* make sure we're done processing display irqs */
3026 synchronize_irq(dev_priv
->drm
.irq
);
3029 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3031 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3033 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3034 POSTING_READ(GEN8_MASTER_IRQ
);
3036 gen8_gt_irq_reset(dev_priv
);
3038 GEN5_IRQ_RESET(GEN8_PCU_
);
3040 spin_lock_irq(&dev_priv
->irq_lock
);
3041 if (dev_priv
->display_irqs_enabled
)
3042 vlv_display_irq_reset(dev_priv
);
3043 spin_unlock_irq(&dev_priv
->irq_lock
);
3046 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3047 const u32 hpd
[HPD_NUM_PINS
])
3049 struct intel_encoder
*encoder
;
3050 u32 enabled_irqs
= 0;
3052 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
3053 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3054 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3056 return enabled_irqs
;
3059 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3061 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3063 if (HAS_PCH_IBX(dev_priv
)) {
3064 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3065 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3067 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3068 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3071 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3074 * Enable digital hotplug on the PCH, and configure the DP short pulse
3075 * duration to 2ms (which is the minimum in the Display Port spec).
3076 * The pulse duration bits are reserved on LPT+.
3078 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3079 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3080 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3081 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3082 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3084 * When CPU and PCH are on the same package, port A
3085 * HPD must be enabled in both north and south.
3087 if (HAS_PCH_LPT_LP(dev_priv
))
3088 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3089 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3092 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3094 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3096 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3097 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3099 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3101 /* Enable digital hotplug on the PCH */
3102 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3103 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3104 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3105 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3107 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3108 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3109 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3112 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3114 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3116 if (INTEL_GEN(dev_priv
) >= 8) {
3117 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3118 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3120 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3121 } else if (INTEL_GEN(dev_priv
) >= 7) {
3122 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3123 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3125 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3127 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3128 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3130 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3134 * Enable digital hotplug on the CPU, and configure the DP short pulse
3135 * duration to 2ms (which is the minimum in the Display Port spec)
3136 * The pulse duration bits are reserved on HSW+.
3138 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3139 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3140 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3141 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3143 ibx_hpd_irq_setup(dev_priv
);
3146 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3148 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3150 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3151 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3153 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3155 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3156 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3157 PORTA_HOTPLUG_ENABLE
;
3159 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3160 hotplug
, enabled_irqs
);
3161 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3164 * For BXT invert bit has to be set based on AOB design
3165 * for HPD detection logic, update it based on VBT fields.
3168 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3169 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3170 hotplug
|= BXT_DDIA_HPD_INVERT
;
3171 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3172 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3173 hotplug
|= BXT_DDIB_HPD_INVERT
;
3174 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3175 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3176 hotplug
|= BXT_DDIC_HPD_INVERT
;
3178 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3181 static void ibx_irq_postinstall(struct drm_device
*dev
)
3183 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3186 if (HAS_PCH_NOP(dev_priv
))
3189 if (HAS_PCH_IBX(dev_priv
))
3190 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3192 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3194 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3195 I915_WRITE(SDEIMR
, ~mask
);
3198 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3200 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3201 u32 pm_irqs
, gt_irqs
;
3203 pm_irqs
= gt_irqs
= 0;
3205 dev_priv
->gt_irq_mask
= ~0;
3206 if (HAS_L3_DPF(dev_priv
)) {
3207 /* L3 parity interrupt is always unmasked. */
3208 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev_priv
);
3209 gt_irqs
|= GT_PARITY_ERROR(dev_priv
);
3212 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3213 if (IS_GEN5(dev_priv
)) {
3214 gt_irqs
|= ILK_BSD_USER_INTERRUPT
;
3216 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3219 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3221 if (INTEL_GEN(dev_priv
) >= 6) {
3223 * RPS interrupts will get enabled/disabled on demand when RPS
3224 * itself is enabled/disabled.
3226 if (HAS_VEBOX(dev_priv
)) {
3227 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3228 dev_priv
->pm_ier
|= PM_VEBOX_USER_INTERRUPT
;
3231 dev_priv
->pm_imr
= 0xffffffff;
3232 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_imr
, pm_irqs
);
3236 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3238 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3239 u32 display_mask
, extra_mask
;
3241 if (INTEL_GEN(dev_priv
) >= 7) {
3242 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3243 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3244 DE_PLANEB_FLIP_DONE_IVB
|
3245 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3246 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3247 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3248 DE_DP_A_HOTPLUG_IVB
);
3250 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3251 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3253 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3255 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3256 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3260 dev_priv
->irq_mask
= ~display_mask
;
3262 I915_WRITE(HWSTAM
, 0xeffe);
3264 ibx_irq_pre_postinstall(dev
);
3266 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3268 gen5_gt_irq_postinstall(dev
);
3270 ibx_irq_postinstall(dev
);
3272 if (IS_IRONLAKE_M(dev_priv
)) {
3273 /* Enable PCU event interrupts
3275 * spinlocking not required here for correctness since interrupt
3276 * setup is guaranteed to run in single-threaded context. But we
3277 * need it to make the assert_spin_locked happy. */
3278 spin_lock_irq(&dev_priv
->irq_lock
);
3279 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3280 spin_unlock_irq(&dev_priv
->irq_lock
);
3286 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3288 assert_spin_locked(&dev_priv
->irq_lock
);
3290 if (dev_priv
->display_irqs_enabled
)
3293 dev_priv
->display_irqs_enabled
= true;
3295 if (intel_irqs_enabled(dev_priv
)) {
3296 vlv_display_irq_reset(dev_priv
);
3297 vlv_display_irq_postinstall(dev_priv
);
3301 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3303 assert_spin_locked(&dev_priv
->irq_lock
);
3305 if (!dev_priv
->display_irqs_enabled
)
3308 dev_priv
->display_irqs_enabled
= false;
3310 if (intel_irqs_enabled(dev_priv
))
3311 vlv_display_irq_reset(dev_priv
);
3315 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3317 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3319 gen5_gt_irq_postinstall(dev
);
3321 spin_lock_irq(&dev_priv
->irq_lock
);
3322 if (dev_priv
->display_irqs_enabled
)
3323 vlv_display_irq_postinstall(dev_priv
);
3324 spin_unlock_irq(&dev_priv
->irq_lock
);
3326 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3327 POSTING_READ(VLV_MASTER_IER
);
3332 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3334 /* These are interrupts we'll toggle with the ring mask register */
3335 uint32_t gt_interrupts
[] = {
3336 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3337 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3338 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3339 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3340 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3341 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3342 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3343 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3345 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3346 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3349 if (HAS_L3_DPF(dev_priv
))
3350 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3352 dev_priv
->pm_ier
= 0x0;
3353 dev_priv
->pm_imr
= ~dev_priv
->pm_ier
;
3354 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3355 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3357 * RPS interrupts will get enabled/disabled on demand when RPS itself
3358 * is enabled/disabled. Same wil be the case for GuC interrupts.
3360 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_imr
, dev_priv
->pm_ier
);
3361 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3364 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3366 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3367 uint32_t de_pipe_enables
;
3368 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3369 u32 de_port_enables
;
3370 u32 de_misc_masked
= GEN8_DE_MISC_GSE
;
3373 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3374 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3375 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3376 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3378 if (IS_BROXTON(dev_priv
))
3379 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3381 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3382 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3385 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3386 GEN8_PIPE_FIFO_UNDERRUN
;
3388 de_port_enables
= de_port_masked
;
3389 if (IS_BROXTON(dev_priv
))
3390 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3391 else if (IS_BROADWELL(dev_priv
))
3392 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3394 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3395 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3396 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3398 for_each_pipe(dev_priv
, pipe
)
3399 if (intel_display_power_is_enabled(dev_priv
,
3400 POWER_DOMAIN_PIPE(pipe
)))
3401 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3402 dev_priv
->de_irq_mask
[pipe
],
3405 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3406 GEN5_IRQ_INIT(GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3409 static int gen8_irq_postinstall(struct drm_device
*dev
)
3411 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3413 if (HAS_PCH_SPLIT(dev_priv
))
3414 ibx_irq_pre_postinstall(dev
);
3416 gen8_gt_irq_postinstall(dev_priv
);
3417 gen8_de_irq_postinstall(dev_priv
);
3419 if (HAS_PCH_SPLIT(dev_priv
))
3420 ibx_irq_postinstall(dev
);
3422 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3423 POSTING_READ(GEN8_MASTER_IRQ
);
3428 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3430 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3432 gen8_gt_irq_postinstall(dev_priv
);
3434 spin_lock_irq(&dev_priv
->irq_lock
);
3435 if (dev_priv
->display_irqs_enabled
)
3436 vlv_display_irq_postinstall(dev_priv
);
3437 spin_unlock_irq(&dev_priv
->irq_lock
);
3439 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3440 POSTING_READ(GEN8_MASTER_IRQ
);
3445 static void gen8_irq_uninstall(struct drm_device
*dev
)
3447 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3452 gen8_irq_reset(dev
);
3455 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3457 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3462 I915_WRITE(VLV_MASTER_IER
, 0);
3463 POSTING_READ(VLV_MASTER_IER
);
3465 gen5_gt_irq_reset(dev_priv
);
3467 I915_WRITE(HWSTAM
, 0xffffffff);
3469 spin_lock_irq(&dev_priv
->irq_lock
);
3470 if (dev_priv
->display_irqs_enabled
)
3471 vlv_display_irq_reset(dev_priv
);
3472 spin_unlock_irq(&dev_priv
->irq_lock
);
3475 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3477 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3482 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3483 POSTING_READ(GEN8_MASTER_IRQ
);
3485 gen8_gt_irq_reset(dev_priv
);
3487 GEN5_IRQ_RESET(GEN8_PCU_
);
3489 spin_lock_irq(&dev_priv
->irq_lock
);
3490 if (dev_priv
->display_irqs_enabled
)
3491 vlv_display_irq_reset(dev_priv
);
3492 spin_unlock_irq(&dev_priv
->irq_lock
);
3495 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3497 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3502 ironlake_irq_reset(dev
);
3505 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3507 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3510 for_each_pipe(dev_priv
, pipe
)
3511 I915_WRITE(PIPESTAT(pipe
), 0);
3512 I915_WRITE16(IMR
, 0xffff);
3513 I915_WRITE16(IER
, 0x0);
3514 POSTING_READ16(IER
);
3517 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3522 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3524 /* Unmask the interrupts that we always want on. */
3525 dev_priv
->irq_mask
=
3526 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3527 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3528 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3529 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3530 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3533 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3534 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3535 I915_USER_INTERRUPT
);
3536 POSTING_READ16(IER
);
3538 /* Interrupt setup is already guaranteed to be single-threaded, this is
3539 * just to make the assert_spin_locked check happy. */
3540 spin_lock_irq(&dev_priv
->irq_lock
);
3541 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3542 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3543 spin_unlock_irq(&dev_priv
->irq_lock
);
3549 * Returns true when a page flip has completed.
3551 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3552 int plane
, int pipe
, u32 iir
)
3554 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3556 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3559 if ((iir
& flip_pending
) == 0)
3560 goto check_page_flip
;
3562 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3563 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3564 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3565 * the flip is completed (no longer pending). Since this doesn't raise
3566 * an interrupt per se, we watch for the change at vblank.
3568 if (I915_READ16(ISR
) & flip_pending
)
3569 goto check_page_flip
;
3571 intel_finish_page_flip_cs(dev_priv
, pipe
);
3575 intel_check_page_flip(dev_priv
, pipe
);
3579 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3581 struct drm_device
*dev
= arg
;
3582 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3587 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3588 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3591 if (!intel_irqs_enabled(dev_priv
))
3594 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3595 disable_rpm_wakeref_asserts(dev_priv
);
3598 iir
= I915_READ16(IIR
);
3602 while (iir
& ~flip_mask
) {
3603 /* Can't rely on pipestat interrupt bit in iir as it might
3604 * have been cleared after the pipestat interrupt was received.
3605 * It doesn't set the bit in iir again, but it still produces
3606 * interrupts (for non-MSI).
3608 spin_lock(&dev_priv
->irq_lock
);
3609 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3610 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3612 for_each_pipe(dev_priv
, pipe
) {
3613 i915_reg_t reg
= PIPESTAT(pipe
);
3614 pipe_stats
[pipe
] = I915_READ(reg
);
3617 * Clear the PIPE*STAT regs before the IIR
3619 if (pipe_stats
[pipe
] & 0x8000ffff)
3620 I915_WRITE(reg
, pipe_stats
[pipe
]);
3622 spin_unlock(&dev_priv
->irq_lock
);
3624 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3625 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3627 if (iir
& I915_USER_INTERRUPT
)
3628 notify_ring(dev_priv
->engine
[RCS
]);
3630 for_each_pipe(dev_priv
, pipe
) {
3632 if (HAS_FBC(dev_priv
))
3635 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3636 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
3637 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3639 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3640 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
3642 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3643 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3652 enable_rpm_wakeref_asserts(dev_priv
);
3657 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3659 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3662 for_each_pipe(dev_priv
, pipe
) {
3663 /* Clear enable bits; then clear status bits */
3664 I915_WRITE(PIPESTAT(pipe
), 0);
3665 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3667 I915_WRITE16(IMR
, 0xffff);
3668 I915_WRITE16(IER
, 0x0);
3669 I915_WRITE16(IIR
, I915_READ16(IIR
));
3672 static void i915_irq_preinstall(struct drm_device
* dev
)
3674 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3677 if (I915_HAS_HOTPLUG(dev_priv
)) {
3678 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3679 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3682 I915_WRITE16(HWSTAM
, 0xeffe);
3683 for_each_pipe(dev_priv
, pipe
)
3684 I915_WRITE(PIPESTAT(pipe
), 0);
3685 I915_WRITE(IMR
, 0xffffffff);
3686 I915_WRITE(IER
, 0x0);
3690 static int i915_irq_postinstall(struct drm_device
*dev
)
3692 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3695 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3697 /* Unmask the interrupts that we always want on. */
3698 dev_priv
->irq_mask
=
3699 ~(I915_ASLE_INTERRUPT
|
3700 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3701 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3702 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3703 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3706 I915_ASLE_INTERRUPT
|
3707 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3708 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3709 I915_USER_INTERRUPT
;
3711 if (I915_HAS_HOTPLUG(dev_priv
)) {
3712 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3713 POSTING_READ(PORT_HOTPLUG_EN
);
3715 /* Enable in IER... */
3716 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3717 /* and unmask in IMR */
3718 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3721 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3722 I915_WRITE(IER
, enable_mask
);
3725 i915_enable_asle_pipestat(dev_priv
);
3727 /* Interrupt setup is already guaranteed to be single-threaded, this is
3728 * just to make the assert_spin_locked check happy. */
3729 spin_lock_irq(&dev_priv
->irq_lock
);
3730 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3731 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3732 spin_unlock_irq(&dev_priv
->irq_lock
);
3738 * Returns true when a page flip has completed.
3740 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
3741 int plane
, int pipe
, u32 iir
)
3743 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3745 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3748 if ((iir
& flip_pending
) == 0)
3749 goto check_page_flip
;
3751 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3752 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3753 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3754 * the flip is completed (no longer pending). Since this doesn't raise
3755 * an interrupt per se, we watch for the change at vblank.
3757 if (I915_READ(ISR
) & flip_pending
)
3758 goto check_page_flip
;
3760 intel_finish_page_flip_cs(dev_priv
, pipe
);
3764 intel_check_page_flip(dev_priv
, pipe
);
3768 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3770 struct drm_device
*dev
= arg
;
3771 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3772 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3774 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3775 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3776 int pipe
, ret
= IRQ_NONE
;
3778 if (!intel_irqs_enabled(dev_priv
))
3781 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3782 disable_rpm_wakeref_asserts(dev_priv
);
3784 iir
= I915_READ(IIR
);
3786 bool irq_received
= (iir
& ~flip_mask
) != 0;
3787 bool blc_event
= false;
3789 /* Can't rely on pipestat interrupt bit in iir as it might
3790 * have been cleared after the pipestat interrupt was received.
3791 * It doesn't set the bit in iir again, but it still produces
3792 * interrupts (for non-MSI).
3794 spin_lock(&dev_priv
->irq_lock
);
3795 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3796 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3798 for_each_pipe(dev_priv
, pipe
) {
3799 i915_reg_t reg
= PIPESTAT(pipe
);
3800 pipe_stats
[pipe
] = I915_READ(reg
);
3802 /* Clear the PIPE*STAT regs before the IIR */
3803 if (pipe_stats
[pipe
] & 0x8000ffff) {
3804 I915_WRITE(reg
, pipe_stats
[pipe
]);
3805 irq_received
= true;
3808 spin_unlock(&dev_priv
->irq_lock
);
3813 /* Consume port. Then clear IIR or we'll miss events */
3814 if (I915_HAS_HOTPLUG(dev_priv
) &&
3815 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3816 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
3818 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
3821 I915_WRITE(IIR
, iir
& ~flip_mask
);
3822 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3824 if (iir
& I915_USER_INTERRUPT
)
3825 notify_ring(dev_priv
->engine
[RCS
]);
3827 for_each_pipe(dev_priv
, pipe
) {
3829 if (HAS_FBC(dev_priv
))
3832 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3833 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
3834 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3836 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3839 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3840 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
3842 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3843 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3847 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3848 intel_opregion_asle_intr(dev_priv
);
3850 /* With MSI, interrupts are only generated when iir
3851 * transitions from zero to nonzero. If another bit got
3852 * set while we were handling the existing iir bits, then
3853 * we would never get another interrupt.
3855 * This is fine on non-MSI as well, as if we hit this path
3856 * we avoid exiting the interrupt handler only to generate
3859 * Note that for MSI this could cause a stray interrupt report
3860 * if an interrupt landed in the time between writing IIR and
3861 * the posting read. This should be rare enough to never
3862 * trigger the 99% of 100,000 interrupts test for disabling
3867 } while (iir
& ~flip_mask
);
3869 enable_rpm_wakeref_asserts(dev_priv
);
3874 static void i915_irq_uninstall(struct drm_device
* dev
)
3876 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3879 if (I915_HAS_HOTPLUG(dev_priv
)) {
3880 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3881 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3884 I915_WRITE16(HWSTAM
, 0xffff);
3885 for_each_pipe(dev_priv
, pipe
) {
3886 /* Clear enable bits; then clear status bits */
3887 I915_WRITE(PIPESTAT(pipe
), 0);
3888 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3890 I915_WRITE(IMR
, 0xffffffff);
3891 I915_WRITE(IER
, 0x0);
3893 I915_WRITE(IIR
, I915_READ(IIR
));
3896 static void i965_irq_preinstall(struct drm_device
* dev
)
3898 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3901 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3902 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3904 I915_WRITE(HWSTAM
, 0xeffe);
3905 for_each_pipe(dev_priv
, pipe
)
3906 I915_WRITE(PIPESTAT(pipe
), 0);
3907 I915_WRITE(IMR
, 0xffffffff);
3908 I915_WRITE(IER
, 0x0);
3912 static int i965_irq_postinstall(struct drm_device
*dev
)
3914 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3918 /* Unmask the interrupts that we always want on. */
3919 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3920 I915_DISPLAY_PORT_INTERRUPT
|
3921 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3922 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3923 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3924 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3925 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3927 enable_mask
= ~dev_priv
->irq_mask
;
3928 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3929 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3930 enable_mask
|= I915_USER_INTERRUPT
;
3932 if (IS_G4X(dev_priv
))
3933 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3935 /* Interrupt setup is already guaranteed to be single-threaded, this is
3936 * just to make the assert_spin_locked check happy. */
3937 spin_lock_irq(&dev_priv
->irq_lock
);
3938 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3939 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3940 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3941 spin_unlock_irq(&dev_priv
->irq_lock
);
3944 * Enable some error detection, note the instruction error mask
3945 * bit is reserved, so we leave it masked.
3947 if (IS_G4X(dev_priv
)) {
3948 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3949 GM45_ERROR_MEM_PRIV
|
3950 GM45_ERROR_CP_PRIV
|
3951 I915_ERROR_MEMORY_REFRESH
);
3953 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3954 I915_ERROR_MEMORY_REFRESH
);
3956 I915_WRITE(EMR
, error_mask
);
3958 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3959 I915_WRITE(IER
, enable_mask
);
3962 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3963 POSTING_READ(PORT_HOTPLUG_EN
);
3965 i915_enable_asle_pipestat(dev_priv
);
3970 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3974 assert_spin_locked(&dev_priv
->irq_lock
);
3976 /* Note HDMI and DP share hotplug bits */
3977 /* enable bits are the same for all generations */
3978 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
3979 /* Programming the CRT detection parameters tends
3980 to generate a spurious hotplug event about three
3981 seconds later. So just do it once.
3983 if (IS_G4X(dev_priv
))
3984 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3985 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3987 /* Ignore TV since it's buggy */
3988 i915_hotplug_interrupt_update_locked(dev_priv
,
3989 HOTPLUG_INT_EN_MASK
|
3990 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
3991 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
3995 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3997 struct drm_device
*dev
= arg
;
3998 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4000 u32 pipe_stats
[I915_MAX_PIPES
];
4001 int ret
= IRQ_NONE
, pipe
;
4003 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4004 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4006 if (!intel_irqs_enabled(dev_priv
))
4009 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4010 disable_rpm_wakeref_asserts(dev_priv
);
4012 iir
= I915_READ(IIR
);
4015 bool irq_received
= (iir
& ~flip_mask
) != 0;
4016 bool blc_event
= false;
4018 /* Can't rely on pipestat interrupt bit in iir as it might
4019 * have been cleared after the pipestat interrupt was received.
4020 * It doesn't set the bit in iir again, but it still produces
4021 * interrupts (for non-MSI).
4023 spin_lock(&dev_priv
->irq_lock
);
4024 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4025 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4027 for_each_pipe(dev_priv
, pipe
) {
4028 i915_reg_t reg
= PIPESTAT(pipe
);
4029 pipe_stats
[pipe
] = I915_READ(reg
);
4032 * Clear the PIPE*STAT regs before the IIR
4034 if (pipe_stats
[pipe
] & 0x8000ffff) {
4035 I915_WRITE(reg
, pipe_stats
[pipe
]);
4036 irq_received
= true;
4039 spin_unlock(&dev_priv
->irq_lock
);
4046 /* Consume port. Then clear IIR or we'll miss events */
4047 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4048 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4050 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4053 I915_WRITE(IIR
, iir
& ~flip_mask
);
4054 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4056 if (iir
& I915_USER_INTERRUPT
)
4057 notify_ring(dev_priv
->engine
[RCS
]);
4058 if (iir
& I915_BSD_USER_INTERRUPT
)
4059 notify_ring(dev_priv
->engine
[VCS
]);
4061 for_each_pipe(dev_priv
, pipe
) {
4062 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4063 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4064 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4066 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4069 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4070 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4072 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4073 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4076 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4077 intel_opregion_asle_intr(dev_priv
);
4079 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4080 gmbus_irq_handler(dev_priv
);
4082 /* With MSI, interrupts are only generated when iir
4083 * transitions from zero to nonzero. If another bit got
4084 * set while we were handling the existing iir bits, then
4085 * we would never get another interrupt.
4087 * This is fine on non-MSI as well, as if we hit this path
4088 * we avoid exiting the interrupt handler only to generate
4091 * Note that for MSI this could cause a stray interrupt report
4092 * if an interrupt landed in the time between writing IIR and
4093 * the posting read. This should be rare enough to never
4094 * trigger the 99% of 100,000 interrupts test for disabling
4100 enable_rpm_wakeref_asserts(dev_priv
);
4105 static void i965_irq_uninstall(struct drm_device
* dev
)
4107 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4113 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4114 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4116 I915_WRITE(HWSTAM
, 0xffffffff);
4117 for_each_pipe(dev_priv
, pipe
)
4118 I915_WRITE(PIPESTAT(pipe
), 0);
4119 I915_WRITE(IMR
, 0xffffffff);
4120 I915_WRITE(IER
, 0x0);
4122 for_each_pipe(dev_priv
, pipe
)
4123 I915_WRITE(PIPESTAT(pipe
),
4124 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4125 I915_WRITE(IIR
, I915_READ(IIR
));
4129 * intel_irq_init - initializes irq support
4130 * @dev_priv: i915 device instance
4132 * This function initializes all the irq support including work items, timers
4133 * and all the vtables. It does not setup the interrupt itself though.
4135 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4137 struct drm_device
*dev
= &dev_priv
->drm
;
4139 intel_hpd_init_work(dev_priv
);
4141 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4142 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4144 if (HAS_GUC_SCHED(dev_priv
))
4145 dev_priv
->pm_guc_events
= GEN9_GUC_TO_HOST_INT_EVENT
;
4147 /* Let's track the enabled rps events */
4148 if (IS_VALLEYVIEW(dev_priv
))
4149 /* WaGsvRC0ResidencyMethod:vlv */
4150 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4152 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4154 dev_priv
->rps
.pm_intr_keep
= 0;
4157 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4158 * if GEN6_PM_UP_EI_EXPIRED is masked.
4160 * TODO: verify if this can be reproduced on VLV,CHV.
4162 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
4163 dev_priv
->rps
.pm_intr_keep
|= GEN6_PM_RP_UP_EI_EXPIRED
;
4165 if (INTEL_INFO(dev_priv
)->gen
>= 8)
4166 dev_priv
->rps
.pm_intr_keep
|= GEN8_PMINTR_REDIRECT_TO_GUC
;
4168 if (IS_GEN2(dev_priv
)) {
4169 /* Gen2 doesn't have a hardware frame counter */
4170 dev
->max_vblank_count
= 0;
4171 dev
->driver
->get_vblank_counter
= drm_vblank_no_hw_counter
;
4172 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4173 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4174 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4176 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4177 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4181 * Opt out of the vblank disable timer on everything except gen2.
4182 * Gen2 doesn't have a hardware frame counter and so depends on
4183 * vblank interrupts to produce sane vblank seuquence numbers.
4185 if (!IS_GEN2(dev_priv
))
4186 dev
->vblank_disable_immediate
= true;
4188 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4189 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4191 if (IS_CHERRYVIEW(dev_priv
)) {
4192 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4193 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4194 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4195 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4196 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4197 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4198 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4199 } else if (IS_VALLEYVIEW(dev_priv
)) {
4200 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4201 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4202 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4203 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4204 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4205 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4206 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4207 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4208 dev
->driver
->irq_handler
= gen8_irq_handler
;
4209 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4210 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4211 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4212 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4213 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4214 if (IS_BROXTON(dev_priv
))
4215 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4216 else if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
))
4217 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4219 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4220 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4221 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4222 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4223 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4224 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4225 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4226 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4227 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4229 if (IS_GEN2(dev_priv
)) {
4230 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4231 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4232 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4233 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4234 dev
->driver
->enable_vblank
= i8xx_enable_vblank
;
4235 dev
->driver
->disable_vblank
= i8xx_disable_vblank
;
4236 } else if (IS_GEN3(dev_priv
)) {
4237 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4238 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4239 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4240 dev
->driver
->irq_handler
= i915_irq_handler
;
4241 dev
->driver
->enable_vblank
= i8xx_enable_vblank
;
4242 dev
->driver
->disable_vblank
= i8xx_disable_vblank
;
4244 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4245 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4246 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4247 dev
->driver
->irq_handler
= i965_irq_handler
;
4248 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4249 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4251 if (I915_HAS_HOTPLUG(dev_priv
))
4252 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4257 * intel_irq_install - enables the hardware interrupt
4258 * @dev_priv: i915 device instance
4260 * This function enables the hardware interrupt handling, but leaves the hotplug
4261 * handling still disabled. It is called after intel_irq_init().
4263 * In the driver load and resume code we need working interrupts in a few places
4264 * but don't want to deal with the hassle of concurrent probe and hotplug
4265 * workers. Hence the split into this two-stage approach.
4267 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4270 * We enable some interrupt sources in our postinstall hooks, so mark
4271 * interrupts as enabled _before_ actually enabling them to avoid
4272 * special cases in our ordering checks.
4274 dev_priv
->pm
.irqs_enabled
= true;
4276 return drm_irq_install(&dev_priv
->drm
, dev_priv
->drm
.pdev
->irq
);
4280 * intel_irq_uninstall - finilizes all irq handling
4281 * @dev_priv: i915 device instance
4283 * This stops interrupt and hotplug handling and unregisters and frees all
4284 * resources acquired in the init functions.
4286 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4288 drm_irq_uninstall(&dev_priv
->drm
);
4289 intel_hpd_cancel_work(dev_priv
);
4290 dev_priv
->pm
.irqs_enabled
= false;
4294 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4295 * @dev_priv: i915 device instance
4297 * This function is used to disable interrupts at runtime, both in the runtime
4298 * pm and the system suspend/resume code.
4300 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4302 dev_priv
->drm
.driver
->irq_uninstall(&dev_priv
->drm
);
4303 dev_priv
->pm
.irqs_enabled
= false;
4304 synchronize_irq(dev_priv
->drm
.irq
);
4308 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4309 * @dev_priv: i915 device instance
4311 * This function is used to enable interrupts at runtime, both in the runtime
4312 * pm and the system suspend/resume code.
4314 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4316 dev_priv
->pm
.irqs_enabled
= true;
4317 dev_priv
->drm
.driver
->irq_preinstall(&dev_priv
->drm
);
4318 dev_priv
->drm
.driver
->irq_postinstall(&dev_priv
->drm
);