1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
173 static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
175 /* For display hotplug interrupt */
177 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
183 lockdep_assert_held(&dev_priv
->irq_lock
);
184 WARN_ON(bits
& ~mask
);
186 val
= I915_READ(PORT_HOTPLUG_EN
);
189 I915_WRITE(PORT_HOTPLUG_EN
, val
);
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
204 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
208 spin_lock_irq(&dev_priv
->irq_lock
);
209 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
210 spin_unlock_irq(&dev_priv
->irq_lock
);
214 * ilk_update_display_irq - update DEIMR
215 * @dev_priv: driver private
216 * @interrupt_mask: mask of interrupt bits to update
217 * @enabled_irq_mask: mask of interrupt bits to enable
219 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
220 uint32_t interrupt_mask
,
221 uint32_t enabled_irq_mask
)
225 lockdep_assert_held(&dev_priv
->irq_lock
);
227 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
229 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
232 new_val
= dev_priv
->irq_mask
;
233 new_val
&= ~interrupt_mask
;
234 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
236 if (new_val
!= dev_priv
->irq_mask
) {
237 dev_priv
->irq_mask
= new_val
;
238 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
244 * ilk_update_gt_irq - update GTIMR
245 * @dev_priv: driver private
246 * @interrupt_mask: mask of interrupt bits to update
247 * @enabled_irq_mask: mask of interrupt bits to enable
249 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
250 uint32_t interrupt_mask
,
251 uint32_t enabled_irq_mask
)
253 lockdep_assert_held(&dev_priv
->irq_lock
);
255 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
257 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
260 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
261 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
262 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
268 POSTING_READ_FW(GTIMR
);
271 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
273 ilk_update_gt_irq(dev_priv
, mask
, 0);
276 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
278 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
281 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
283 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
286 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
288 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
292 * snb_update_pm_irq - update GEN6_PMIMR
293 * @dev_priv: driver private
294 * @interrupt_mask: mask of interrupt bits to update
295 * @enabled_irq_mask: mask of interrupt bits to enable
297 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
298 uint32_t interrupt_mask
,
299 uint32_t enabled_irq_mask
)
303 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
305 lockdep_assert_held(&dev_priv
->irq_lock
);
307 new_val
= dev_priv
->pm_imr
;
308 new_val
&= ~interrupt_mask
;
309 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
311 if (new_val
!= dev_priv
->pm_imr
) {
312 dev_priv
->pm_imr
= new_val
;
313 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_imr
);
314 POSTING_READ(gen6_pm_imr(dev_priv
));
318 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
320 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
323 snb_update_pm_irq(dev_priv
, mask
, mask
);
326 static void __gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_mask_pm_irq(dev_priv
, mask
);
339 void gen6_reset_pm_iir(struct drm_i915_private
*dev_priv
, u32 reset_mask
)
341 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
343 lockdep_assert_held(&dev_priv
->irq_lock
);
345 I915_WRITE(reg
, reset_mask
);
346 I915_WRITE(reg
, reset_mask
);
350 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, u32 enable_mask
)
352 lockdep_assert_held(&dev_priv
->irq_lock
);
354 dev_priv
->pm_ier
|= enable_mask
;
355 I915_WRITE(gen6_pm_ier(dev_priv
), dev_priv
->pm_ier
);
356 gen6_unmask_pm_irq(dev_priv
, enable_mask
);
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
360 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, u32 disable_mask
)
362 lockdep_assert_held(&dev_priv
->irq_lock
);
364 dev_priv
->pm_ier
&= ~disable_mask
;
365 __gen6_mask_pm_irq(dev_priv
, disable_mask
);
366 I915_WRITE(gen6_pm_ier(dev_priv
), dev_priv
->pm_ier
);
367 /* though a barrier is missing here, but don't really need a one */
370 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
)
372 spin_lock_irq(&dev_priv
->irq_lock
);
373 gen6_reset_pm_iir(dev_priv
, dev_priv
->pm_rps_events
);
374 dev_priv
->rps
.pm_iir
= 0;
375 spin_unlock_irq(&dev_priv
->irq_lock
);
378 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
380 if (READ_ONCE(dev_priv
->rps
.interrupts_enabled
))
383 spin_lock_irq(&dev_priv
->irq_lock
);
384 WARN_ON_ONCE(dev_priv
->rps
.pm_iir
);
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
386 dev_priv
->rps
.interrupts_enabled
= true;
387 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
389 spin_unlock_irq(&dev_priv
->irq_lock
);
392 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
394 if (!READ_ONCE(dev_priv
->rps
.interrupts_enabled
))
397 spin_lock_irq(&dev_priv
->irq_lock
);
398 dev_priv
->rps
.interrupts_enabled
= false;
400 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0u));
402 gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
404 spin_unlock_irq(&dev_priv
->irq_lock
);
405 synchronize_irq(dev_priv
->drm
.irq
);
407 /* Now that we will not be generating any more work, flush any
408 * outsanding tasks. As we are called on the RPS idle path,
409 * we will reset the GPU to minimum frequencies, so the current
410 * state of the worker can be discarded.
412 cancel_work_sync(&dev_priv
->rps
.work
);
413 gen6_reset_rps_interrupts(dev_priv
);
416 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
)
418 spin_lock_irq(&dev_priv
->irq_lock
);
419 gen6_reset_pm_iir(dev_priv
, dev_priv
->pm_guc_events
);
420 spin_unlock_irq(&dev_priv
->irq_lock
);
423 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
)
425 spin_lock_irq(&dev_priv
->irq_lock
);
426 if (!dev_priv
->guc
.interrupts_enabled
) {
427 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) &
428 dev_priv
->pm_guc_events
);
429 dev_priv
->guc
.interrupts_enabled
= true;
430 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_guc_events
);
432 spin_unlock_irq(&dev_priv
->irq_lock
);
435 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
)
437 spin_lock_irq(&dev_priv
->irq_lock
);
438 dev_priv
->guc
.interrupts_enabled
= false;
440 gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_guc_events
);
442 spin_unlock_irq(&dev_priv
->irq_lock
);
443 synchronize_irq(dev_priv
->drm
.irq
);
445 gen9_reset_guc_interrupts(dev_priv
);
449 * bdw_update_port_irq - update DE port interrupt
450 * @dev_priv: driver private
451 * @interrupt_mask: mask of interrupt bits to update
452 * @enabled_irq_mask: mask of interrupt bits to enable
454 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
455 uint32_t interrupt_mask
,
456 uint32_t enabled_irq_mask
)
461 lockdep_assert_held(&dev_priv
->irq_lock
);
463 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
465 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
468 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
471 new_val
&= ~interrupt_mask
;
472 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
474 if (new_val
!= old_val
) {
475 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
476 POSTING_READ(GEN8_DE_PORT_IMR
);
481 * bdw_update_pipe_irq - update DE pipe interrupt
482 * @dev_priv: driver private
483 * @pipe: pipe whose interrupt to update
484 * @interrupt_mask: mask of interrupt bits to update
485 * @enabled_irq_mask: mask of interrupt bits to enable
487 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
489 uint32_t interrupt_mask
,
490 uint32_t enabled_irq_mask
)
494 lockdep_assert_held(&dev_priv
->irq_lock
);
496 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
498 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
501 new_val
= dev_priv
->de_irq_mask
[pipe
];
502 new_val
&= ~interrupt_mask
;
503 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
505 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
506 dev_priv
->de_irq_mask
[pipe
] = new_val
;
507 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
508 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
513 * ibx_display_interrupt_update - update SDEIMR
514 * @dev_priv: driver private
515 * @interrupt_mask: mask of interrupt bits to update
516 * @enabled_irq_mask: mask of interrupt bits to enable
518 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
519 uint32_t interrupt_mask
,
520 uint32_t enabled_irq_mask
)
522 uint32_t sdeimr
= I915_READ(SDEIMR
);
523 sdeimr
&= ~interrupt_mask
;
524 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
526 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
528 lockdep_assert_held(&dev_priv
->irq_lock
);
530 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
533 I915_WRITE(SDEIMR
, sdeimr
);
534 POSTING_READ(SDEIMR
);
538 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
539 u32 enable_mask
, u32 status_mask
)
541 i915_reg_t reg
= PIPESTAT(pipe
);
542 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
544 lockdep_assert_held(&dev_priv
->irq_lock
);
545 WARN_ON(!intel_irqs_enabled(dev_priv
));
547 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
548 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
549 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
550 pipe_name(pipe
), enable_mask
, status_mask
))
553 if ((pipestat
& enable_mask
) == enable_mask
)
556 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
558 /* Enable the interrupt, clear any pending status */
559 pipestat
|= enable_mask
| status_mask
;
560 I915_WRITE(reg
, pipestat
);
565 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
566 u32 enable_mask
, u32 status_mask
)
568 i915_reg_t reg
= PIPESTAT(pipe
);
569 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
571 lockdep_assert_held(&dev_priv
->irq_lock
);
572 WARN_ON(!intel_irqs_enabled(dev_priv
));
574 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
575 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
576 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
577 pipe_name(pipe
), enable_mask
, status_mask
))
580 if ((pipestat
& enable_mask
) == 0)
583 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
585 pipestat
&= ~enable_mask
;
586 I915_WRITE(reg
, pipestat
);
590 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
592 u32 enable_mask
= status_mask
<< 16;
595 * On pipe A we don't support the PSR interrupt yet,
596 * on pipe B and C the same bit MBZ.
598 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
601 * On pipe B and C we don't support the PSR interrupt yet, on pipe
602 * A the same bit is for perf counters which we don't use either.
604 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
607 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
608 SPRITE0_FLIP_DONE_INT_EN_VLV
|
609 SPRITE1_FLIP_DONE_INT_EN_VLV
);
610 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
611 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
612 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
613 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
619 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
624 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
625 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
628 enable_mask
= status_mask
<< 16;
629 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
633 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
638 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
639 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
642 enable_mask
= status_mask
<< 16;
643 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
647 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
648 * @dev_priv: i915 device private
650 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
652 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
655 spin_lock_irq(&dev_priv
->irq_lock
);
657 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
658 if (INTEL_GEN(dev_priv
) >= 4)
659 i915_enable_pipestat(dev_priv
, PIPE_A
,
660 PIPE_LEGACY_BLC_EVENT_STATUS
);
662 spin_unlock_irq(&dev_priv
->irq_lock
);
666 * This timing diagram depicts the video signal in and
667 * around the vertical blanking period.
669 * Assumptions about the fictitious mode used in this example:
671 * vsync_start = vblank_start + 1
672 * vsync_end = vblank_start + 2
673 * vtotal = vblank_start + 3
676 * latch double buffered registers
677 * increment frame counter (ctg+)
678 * generate start of vblank interrupt (gen4+)
681 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
682 * | may be shifted forward 1-3 extra lines via PIPECONF
684 * | | start of vsync:
685 * | | generate vsync interrupt
687 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
688 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
689 * ----va---> <-----------------vb--------------------> <--------va-------------
690 * | | <----vs-----> |
691 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
692 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
693 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
695 * last visible pixel first visible pixel
696 * | increment frame counter (gen3/4)
697 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
699 * x = horizontal active
700 * _ = horizontal blanking
701 * hs = horizontal sync
702 * va = vertical active
703 * vb = vertical blanking
705 * vbs = vblank_start (number)
708 * - most events happen at the start of horizontal sync
709 * - frame start happens at the start of horizontal blank, 1-4 lines
710 * (depending on PIPECONF settings) after the start of vblank
711 * - gen3/4 pixel and frame counter are synchronized with the start
712 * of horizontal active on the first line of vertical active
715 /* Called from drm generic code, passed a 'crtc', which
716 * we use as a pipe index
718 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
721 i915_reg_t high_frame
, low_frame
;
722 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
723 const struct drm_display_mode
*mode
= &dev
->vblank
[pipe
].hwmode
;
724 unsigned long irqflags
;
726 htotal
= mode
->crtc_htotal
;
727 hsync_start
= mode
->crtc_hsync_start
;
728 vbl_start
= mode
->crtc_vblank_start
;
729 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
730 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
732 /* Convert to pixel count */
735 /* Start of vblank event occurs at start of hsync */
736 vbl_start
-= htotal
- hsync_start
;
738 high_frame
= PIPEFRAME(pipe
);
739 low_frame
= PIPEFRAMEPIXEL(pipe
);
741 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
744 * High & low register fields aren't synchronized, so make sure
745 * we get a low value that's stable across two reads of the high
749 high1
= I915_READ_FW(high_frame
) & PIPE_FRAME_HIGH_MASK
;
750 low
= I915_READ_FW(low_frame
);
751 high2
= I915_READ_FW(high_frame
) & PIPE_FRAME_HIGH_MASK
;
752 } while (high1
!= high2
);
754 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
756 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
757 pixel
= low
& PIPE_PIXEL_MASK
;
758 low
>>= PIPE_FRAME_LOW_SHIFT
;
761 * The frame counter increments at beginning of active.
762 * Cook up a vblank counter by also checking the pixel
763 * counter against vblank start.
765 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
768 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
772 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
775 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
776 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
778 struct drm_device
*dev
= crtc
->base
.dev
;
779 struct drm_i915_private
*dev_priv
= to_i915(dev
);
780 const struct drm_display_mode
*mode
;
781 struct drm_vblank_crtc
*vblank
;
782 enum pipe pipe
= crtc
->pipe
;
783 int position
, vtotal
;
788 vblank
= &crtc
->base
.dev
->vblank
[drm_crtc_index(&crtc
->base
)];
789 mode
= &vblank
->hwmode
;
791 vtotal
= mode
->crtc_vtotal
;
792 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
795 if (IS_GEN2(dev_priv
))
796 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
798 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
801 * On HSW, the DSL reg (0x70000) appears to return 0 if we
802 * read it just before the start of vblank. So try it again
803 * so we don't accidentally end up spanning a vblank frame
804 * increment, causing the pipe_update_end() code to squak at us.
806 * The nature of this problem means we can't simply check the ISR
807 * bit and return the vblank start value; nor can we use the scanline
808 * debug register in the transcoder as it appears to have the same
809 * problem. We may need to extend this to include other platforms,
810 * but so far testing only shows the problem on HSW.
812 if (HAS_DDI(dev_priv
) && !position
) {
815 for (i
= 0; i
< 100; i
++) {
817 temp
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
818 if (temp
!= position
) {
826 * See update_scanline_offset() for the details on the
827 * scanline_offset adjustment.
829 return (position
+ crtc
->scanline_offset
) % vtotal
;
832 static bool i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
833 bool in_vblank_irq
, int *vpos
, int *hpos
,
834 ktime_t
*stime
, ktime_t
*etime
,
835 const struct drm_display_mode
*mode
)
837 struct drm_i915_private
*dev_priv
= to_i915(dev
);
838 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
841 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
843 unsigned long irqflags
;
845 if (WARN_ON(!mode
->crtc_clock
)) {
846 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
847 "pipe %c\n", pipe_name(pipe
));
851 htotal
= mode
->crtc_htotal
;
852 hsync_start
= mode
->crtc_hsync_start
;
853 vtotal
= mode
->crtc_vtotal
;
854 vbl_start
= mode
->crtc_vblank_start
;
855 vbl_end
= mode
->crtc_vblank_end
;
857 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
858 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
864 * Lock uncore.lock, as we will do multiple timing critical raw
865 * register reads, potentially with preemption disabled, so the
866 * following code must not block on uncore.lock.
868 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
870 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
872 /* Get optional system timestamp before query. */
874 *stime
= ktime_get();
876 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
877 /* No obvious pixelcount register. Only query vertical
878 * scanout position from Display scan line register.
880 position
= __intel_get_crtc_scanline(intel_crtc
);
882 /* Have access to pixelcount since start of frame.
883 * We can split this into vertical and horizontal
886 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
888 /* convert to pixel counts */
894 * In interlaced modes, the pixel counter counts all pixels,
895 * so one field will have htotal more pixels. In order to avoid
896 * the reported position from jumping backwards when the pixel
897 * counter is beyond the length of the shorter field, just
898 * clamp the position the length of the shorter field. This
899 * matches how the scanline counter based position works since
900 * the scanline counter doesn't count the two half lines.
902 if (position
>= vtotal
)
903 position
= vtotal
- 1;
906 * Start of vblank interrupt is triggered at start of hsync,
907 * just prior to the first active line of vblank. However we
908 * consider lines to start at the leading edge of horizontal
909 * active. So, should we get here before we've crossed into
910 * the horizontal active of the first line in vblank, we would
911 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
912 * always add htotal-hsync_start to the current pixel position.
914 position
= (position
+ htotal
- hsync_start
) % vtotal
;
917 /* Get optional system timestamp after query. */
919 *etime
= ktime_get();
921 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
923 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
925 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
928 * While in vblank, position will be negative
929 * counting up towards 0 at vbl_end. And outside
930 * vblank, position will be positive counting
933 if (position
>= vbl_start
)
936 position
+= vtotal
- vbl_end
;
938 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
942 *vpos
= position
/ htotal
;
943 *hpos
= position
- (*vpos
* htotal
);
949 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
951 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
952 unsigned long irqflags
;
955 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
956 position
= __intel_get_crtc_scanline(crtc
);
957 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
962 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
964 u32 busy_up
, busy_down
, max_avg
, min_avg
;
967 spin_lock(&mchdev_lock
);
969 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
971 new_delay
= dev_priv
->ips
.cur_delay
;
973 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
974 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
975 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
976 max_avg
= I915_READ(RCBMAXAVG
);
977 min_avg
= I915_READ(RCBMINAVG
);
979 /* Handle RCS change request from hw */
980 if (busy_up
> max_avg
) {
981 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
982 new_delay
= dev_priv
->ips
.cur_delay
- 1;
983 if (new_delay
< dev_priv
->ips
.max_delay
)
984 new_delay
= dev_priv
->ips
.max_delay
;
985 } else if (busy_down
< min_avg
) {
986 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
987 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
988 if (new_delay
> dev_priv
->ips
.min_delay
)
989 new_delay
= dev_priv
->ips
.min_delay
;
992 if (ironlake_set_drps(dev_priv
, new_delay
))
993 dev_priv
->ips
.cur_delay
= new_delay
;
995 spin_unlock(&mchdev_lock
);
1000 static void notify_ring(struct intel_engine_cs
*engine
)
1002 struct drm_i915_gem_request
*rq
= NULL
;
1003 struct intel_wait
*wait
;
1005 atomic_inc(&engine
->irq_count
);
1006 set_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
);
1008 spin_lock(&engine
->breadcrumbs
.irq_lock
);
1009 wait
= engine
->breadcrumbs
.irq_wait
;
1011 /* We use a callback from the dma-fence to submit
1012 * requests after waiting on our own requests. To
1013 * ensure minimum delay in queuing the next request to
1014 * hardware, signal the fence now rather than wait for
1015 * the signaler to be woken up. We still wake up the
1016 * waiter in order to handle the irq-seqno coherency
1017 * issues (we may receive the interrupt before the
1018 * seqno is written, see __i915_request_irq_complete())
1019 * and to handle coalescing of multiple seqno updates
1022 if (i915_seqno_passed(intel_engine_get_seqno(engine
),
1024 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
,
1025 &wait
->request
->fence
.flags
))
1026 rq
= i915_gem_request_get(wait
->request
);
1028 wake_up_process(wait
->tsk
);
1030 __intel_engine_disarm_breadcrumbs(engine
);
1032 spin_unlock(&engine
->breadcrumbs
.irq_lock
);
1035 dma_fence_signal(&rq
->fence
);
1036 i915_gem_request_put(rq
);
1039 trace_intel_engine_notify(engine
, wait
);
1042 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1043 struct intel_rps_ei
*ei
)
1045 ei
->ktime
= ktime_get_raw();
1046 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1047 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1050 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1052 memset(&dev_priv
->rps
.ei
, 0, sizeof(dev_priv
->rps
.ei
));
1055 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1057 const struct intel_rps_ei
*prev
= &dev_priv
->rps
.ei
;
1058 struct intel_rps_ei now
;
1061 if ((pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) == 0)
1064 vlv_c0_read(dev_priv
, &now
);
1070 time
= ktime_us_delta(now
.ktime
, prev
->ktime
);
1072 time
*= dev_priv
->czclk_freq
;
1074 /* Workload can be split between render + media,
1075 * e.g. SwapBuffers being blitted in X after being rendered in
1076 * mesa. To account for this we need to combine both engines
1077 * into our activity counter.
1079 render
= now
.render_c0
- prev
->render_c0
;
1080 media
= now
.media_c0
- prev
->media_c0
;
1081 c0
= max(render
, media
);
1082 c0
*= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1084 if (c0
> time
* dev_priv
->rps
.up_threshold
)
1085 events
= GEN6_PM_RP_UP_THRESHOLD
;
1086 else if (c0
< time
* dev_priv
->rps
.down_threshold
)
1087 events
= GEN6_PM_RP_DOWN_THRESHOLD
;
1090 dev_priv
->rps
.ei
= now
;
1094 static void gen6_pm_rps_work(struct work_struct
*work
)
1096 struct drm_i915_private
*dev_priv
=
1097 container_of(work
, struct drm_i915_private
, rps
.work
);
1098 bool client_boost
= false;
1099 int new_delay
, adj
, min
, max
;
1102 spin_lock_irq(&dev_priv
->irq_lock
);
1103 if (dev_priv
->rps
.interrupts_enabled
) {
1104 pm_iir
= fetch_and_zero(&dev_priv
->rps
.pm_iir
);
1105 client_boost
= atomic_read(&dev_priv
->rps
.num_waiters
);
1107 spin_unlock_irq(&dev_priv
->irq_lock
);
1109 /* Make sure we didn't queue anything we're not going to process. */
1110 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1111 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1114 mutex_lock(&dev_priv
->rps
.hw_lock
);
1116 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1118 adj
= dev_priv
->rps
.last_adj
;
1119 new_delay
= dev_priv
->rps
.cur_freq
;
1120 min
= dev_priv
->rps
.min_freq_softlimit
;
1121 max
= dev_priv
->rps
.max_freq_softlimit
;
1123 max
= dev_priv
->rps
.max_freq
;
1124 if (client_boost
&& new_delay
< dev_priv
->rps
.boost_freq
) {
1125 new_delay
= dev_priv
->rps
.boost_freq
;
1127 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1130 else /* CHV needs even encode values */
1131 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1133 if (new_delay
>= dev_priv
->rps
.max_freq_softlimit
)
1135 } else if (client_boost
) {
1137 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1138 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1139 new_delay
= dev_priv
->rps
.efficient_freq
;
1140 else if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.min_freq_softlimit
)
1141 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1143 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1146 else /* CHV needs even encode values */
1147 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1149 if (new_delay
<= dev_priv
->rps
.min_freq_softlimit
)
1151 } else { /* unknown event */
1155 dev_priv
->rps
.last_adj
= adj
;
1157 /* sysfs frequency interfaces may have snuck in while servicing the
1161 new_delay
= clamp_t(int, new_delay
, min
, max
);
1163 if (intel_set_rps(dev_priv
, new_delay
)) {
1164 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1165 dev_priv
->rps
.last_adj
= 0;
1168 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1171 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1172 spin_lock_irq(&dev_priv
->irq_lock
);
1173 if (dev_priv
->rps
.interrupts_enabled
)
1174 gen6_unmask_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1175 spin_unlock_irq(&dev_priv
->irq_lock
);
1180 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1182 * @work: workqueue struct
1184 * Doesn't actually do anything except notify userspace. As a consequence of
1185 * this event, userspace should try to remap the bad rows since statistically
1186 * it is likely the same row is more likely to go bad again.
1188 static void ivybridge_parity_work(struct work_struct
*work
)
1190 struct drm_i915_private
*dev_priv
=
1191 container_of(work
, typeof(*dev_priv
), l3_parity
.error_work
);
1192 u32 error_status
, row
, bank
, subbank
;
1193 char *parity_event
[6];
1197 /* We must turn off DOP level clock gating to access the L3 registers.
1198 * In order to prevent a get/put style interface, acquire struct mutex
1199 * any time we access those registers.
1201 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1203 /* If we've screwed up tracking, just let the interrupt fire again */
1204 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1207 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1208 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1209 POSTING_READ(GEN7_MISCCPCTL
);
1211 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1215 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1218 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1220 reg
= GEN7_L3CDERRST1(slice
);
1222 error_status
= I915_READ(reg
);
1223 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1224 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1225 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1227 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1230 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1231 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1232 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1233 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1234 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1235 parity_event
[5] = NULL
;
1237 kobject_uevent_env(&dev_priv
->drm
.primary
->kdev
->kobj
,
1238 KOBJ_CHANGE
, parity_event
);
1240 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1241 slice
, row
, bank
, subbank
);
1243 kfree(parity_event
[4]);
1244 kfree(parity_event
[3]);
1245 kfree(parity_event
[2]);
1246 kfree(parity_event
[1]);
1249 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1252 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1253 spin_lock_irq(&dev_priv
->irq_lock
);
1254 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1255 spin_unlock_irq(&dev_priv
->irq_lock
);
1257 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1260 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1263 if (!HAS_L3_DPF(dev_priv
))
1266 spin_lock(&dev_priv
->irq_lock
);
1267 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1268 spin_unlock(&dev_priv
->irq_lock
);
1270 iir
&= GT_PARITY_ERROR(dev_priv
);
1271 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1272 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1274 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1275 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1277 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1280 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1283 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1284 notify_ring(dev_priv
->engine
[RCS
]);
1285 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1286 notify_ring(dev_priv
->engine
[VCS
]);
1289 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1292 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1293 notify_ring(dev_priv
->engine
[RCS
]);
1294 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1295 notify_ring(dev_priv
->engine
[VCS
]);
1296 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1297 notify_ring(dev_priv
->engine
[BCS
]);
1299 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1300 GT_BSD_CS_ERROR_INTERRUPT
|
1301 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1302 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1304 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1305 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1309 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1311 bool tasklet
= false;
1313 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
)) {
1314 if (port_count(&engine
->execlist_port
[0])) {
1315 __set_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1320 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
)) {
1321 notify_ring(engine
);
1322 tasklet
|= i915
.enable_guc_submission
;
1326 tasklet_hi_schedule(&engine
->irq_tasklet
);
1329 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1333 irqreturn_t ret
= IRQ_NONE
;
1335 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1336 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1338 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1341 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1344 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1345 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1347 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1350 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1353 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1354 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1356 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1359 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1362 if (master_ctl
& (GEN8_GT_PM_IRQ
| GEN8_GT_GUC_IRQ
)) {
1363 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1364 if (gt_iir
[2] & (dev_priv
->pm_rps_events
|
1365 dev_priv
->pm_guc_events
)) {
1366 I915_WRITE_FW(GEN8_GT_IIR(2),
1367 gt_iir
[2] & (dev_priv
->pm_rps_events
|
1368 dev_priv
->pm_guc_events
));
1371 DRM_ERROR("The master control interrupt lied (PM)!\n");
1377 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1381 gen8_cs_irq_handler(dev_priv
->engine
[RCS
],
1382 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1383 gen8_cs_irq_handler(dev_priv
->engine
[BCS
],
1384 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1388 gen8_cs_irq_handler(dev_priv
->engine
[VCS
],
1389 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1390 gen8_cs_irq_handler(dev_priv
->engine
[VCS2
],
1391 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1395 gen8_cs_irq_handler(dev_priv
->engine
[VECS
],
1396 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1398 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1399 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1401 if (gt_iir
[2] & dev_priv
->pm_guc_events
)
1402 gen9_guc_irq_handler(dev_priv
, gt_iir
[2]);
1405 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1409 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1411 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1413 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1419 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1423 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1429 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1433 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1435 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1437 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1439 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1445 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1449 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1455 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1459 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1461 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1463 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1469 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1473 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1475 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1477 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1484 * Get a bit mask of pins that have triggered, and which ones may be long.
1485 * This can be called multiple times with the same masks to accumulate
1486 * hotplug detection results from several registers.
1488 * Note that the caller is expected to zero out the masks initially.
1490 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1491 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1492 const u32 hpd
[HPD_NUM_PINS
],
1493 bool long_pulse_detect(enum port port
, u32 val
))
1498 for_each_hpd_pin(i
) {
1499 if ((hpd
[i
] & hotplug_trigger
) == 0)
1502 *pin_mask
|= BIT(i
);
1504 if (!intel_hpd_pin_to_port(i
, &port
))
1507 if (long_pulse_detect(port
, dig_hotplug_reg
))
1508 *long_mask
|= BIT(i
);
1511 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1512 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1516 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1518 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1521 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1523 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1526 #if defined(CONFIG_DEBUG_FS)
1527 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1529 uint32_t crc0
, uint32_t crc1
,
1530 uint32_t crc2
, uint32_t crc3
,
1533 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1534 struct intel_pipe_crc_entry
*entry
;
1535 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1536 struct drm_driver
*driver
= dev_priv
->drm
.driver
;
1540 spin_lock(&pipe_crc
->lock
);
1541 if (pipe_crc
->source
) {
1542 if (!pipe_crc
->entries
) {
1543 spin_unlock(&pipe_crc
->lock
);
1544 DRM_DEBUG_KMS("spurious interrupt\n");
1548 head
= pipe_crc
->head
;
1549 tail
= pipe_crc
->tail
;
1551 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1552 spin_unlock(&pipe_crc
->lock
);
1553 DRM_ERROR("CRC buffer overflowing\n");
1557 entry
= &pipe_crc
->entries
[head
];
1559 entry
->frame
= driver
->get_vblank_counter(&dev_priv
->drm
, pipe
);
1560 entry
->crc
[0] = crc0
;
1561 entry
->crc
[1] = crc1
;
1562 entry
->crc
[2] = crc2
;
1563 entry
->crc
[3] = crc3
;
1564 entry
->crc
[4] = crc4
;
1566 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1567 pipe_crc
->head
= head
;
1569 spin_unlock(&pipe_crc
->lock
);
1571 wake_up_interruptible(&pipe_crc
->wq
);
1574 * For some not yet identified reason, the first CRC is
1575 * bonkers. So let's just wait for the next vblank and read
1576 * out the buggy result.
1578 * On CHV sometimes the second CRC is bonkers as well, so
1579 * don't trust that one either.
1581 if (pipe_crc
->skipped
== 0 ||
1582 (IS_CHERRYVIEW(dev_priv
) && pipe_crc
->skipped
== 1)) {
1583 pipe_crc
->skipped
++;
1584 spin_unlock(&pipe_crc
->lock
);
1587 spin_unlock(&pipe_crc
->lock
);
1593 drm_crtc_add_crc_entry(&crtc
->base
, true,
1594 drm_accurate_vblank_count(&crtc
->base
),
1600 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1602 uint32_t crc0
, uint32_t crc1
,
1603 uint32_t crc2
, uint32_t crc3
,
1608 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1611 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1612 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1616 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1619 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1620 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1621 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1622 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1623 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1624 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1627 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1630 uint32_t res1
, res2
;
1632 if (INTEL_GEN(dev_priv
) >= 3)
1633 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1637 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1638 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1642 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1643 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1644 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1645 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1649 /* The RPS events need forcewake, so we add them to a work queue and mask their
1650 * IMR bits until the work is done. Other interrupts can be processed without
1651 * the work queue. */
1652 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1654 if (pm_iir
& dev_priv
->pm_rps_events
) {
1655 spin_lock(&dev_priv
->irq_lock
);
1656 gen6_mask_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1657 if (dev_priv
->rps
.interrupts_enabled
) {
1658 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1659 schedule_work(&dev_priv
->rps
.work
);
1661 spin_unlock(&dev_priv
->irq_lock
);
1664 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1667 if (HAS_VEBOX(dev_priv
)) {
1668 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1669 notify_ring(dev_priv
->engine
[VECS
]);
1671 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1672 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1676 static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv
, u32 gt_iir
)
1678 if (gt_iir
& GEN9_GUC_TO_HOST_INT_EVENT
) {
1679 /* Sample the log buffer flush related bits & clear them out now
1680 * itself from the message identity register to minimize the
1681 * probability of losing a flush interrupt, when there are back
1682 * to back flush interrupts.
1683 * There can be a new flush interrupt, for different log buffer
1684 * type (like for ISR), whilst Host is handling one (for DPC).
1685 * Since same bit is used in message register for ISR & DPC, it
1686 * could happen that GuC sets the bit for 2nd interrupt but Host
1687 * clears out the bit on handling the 1st interrupt.
1691 msg
= I915_READ(SOFT_SCRATCH(15));
1692 flush
= msg
& (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED
|
1693 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER
);
1695 /* Clear the message bits that are handled */
1696 I915_WRITE(SOFT_SCRATCH(15), msg
& ~flush
);
1698 /* Handle flush interrupt in bottom half */
1699 queue_work(dev_priv
->guc
.log
.runtime
.flush_wq
,
1700 &dev_priv
->guc
.log
.runtime
.flush_work
);
1702 dev_priv
->guc
.log
.flush_interrupt_count
++;
1704 /* Not clearing of unhandled event bits won't result in
1705 * re-triggering of the interrupt.
1711 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1716 ret
= drm_handle_vblank(&dev_priv
->drm
, pipe
);
1718 intel_finish_page_flip_mmio(dev_priv
, pipe
);
1723 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1724 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1728 spin_lock(&dev_priv
->irq_lock
);
1730 if (!dev_priv
->display_irqs_enabled
) {
1731 spin_unlock(&dev_priv
->irq_lock
);
1735 for_each_pipe(dev_priv
, pipe
) {
1737 u32 mask
, iir_bit
= 0;
1740 * PIPESTAT bits get signalled even when the interrupt is
1741 * disabled with the mask bits, and some of the status bits do
1742 * not generate interrupts at all (like the underrun bit). Hence
1743 * we need to be careful that we only handle what we want to
1747 /* fifo underruns are filterered in the underrun handler. */
1748 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1752 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1755 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1758 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1762 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1767 reg
= PIPESTAT(pipe
);
1768 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1769 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1772 * Clear the PIPE*STAT regs before the IIR
1774 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1775 PIPESTAT_INT_STATUS_MASK
))
1776 I915_WRITE(reg
, pipe_stats
[pipe
]);
1778 spin_unlock(&dev_priv
->irq_lock
);
1781 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1782 u32 pipe_stats
[I915_MAX_PIPES
])
1786 for_each_pipe(dev_priv
, pipe
) {
1787 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1788 intel_pipe_handle_vblank(dev_priv
, pipe
))
1789 intel_check_page_flip(dev_priv
, pipe
);
1791 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
)
1792 intel_finish_page_flip_cs(dev_priv
, pipe
);
1794 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1795 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1797 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1798 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1801 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1802 gmbus_irq_handler(dev_priv
);
1805 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1807 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1810 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1812 return hotplug_status
;
1815 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1818 u32 pin_mask
= 0, long_mask
= 0;
1820 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1821 IS_CHERRYVIEW(dev_priv
)) {
1822 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1824 if (hotplug_trigger
) {
1825 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1826 hotplug_trigger
, hpd_status_g4x
,
1827 i9xx_port_hotplug_long_detect
);
1829 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1832 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1833 dp_aux_irq_handler(dev_priv
);
1835 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1837 if (hotplug_trigger
) {
1838 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1839 hotplug_trigger
, hpd_status_i915
,
1840 i9xx_port_hotplug_long_detect
);
1841 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1846 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1848 struct drm_device
*dev
= arg
;
1849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1850 irqreturn_t ret
= IRQ_NONE
;
1852 if (!intel_irqs_enabled(dev_priv
))
1855 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1856 disable_rpm_wakeref_asserts(dev_priv
);
1859 u32 iir
, gt_iir
, pm_iir
;
1860 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1861 u32 hotplug_status
= 0;
1864 gt_iir
= I915_READ(GTIIR
);
1865 pm_iir
= I915_READ(GEN6_PMIIR
);
1866 iir
= I915_READ(VLV_IIR
);
1868 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1874 * Theory on interrupt generation, based on empirical evidence:
1876 * x = ((VLV_IIR & VLV_IER) ||
1877 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1878 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1880 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1881 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1882 * guarantee the CPU interrupt will be raised again even if we
1883 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1884 * bits this time around.
1886 I915_WRITE(VLV_MASTER_IER
, 0);
1887 ier
= I915_READ(VLV_IER
);
1888 I915_WRITE(VLV_IER
, 0);
1891 I915_WRITE(GTIIR
, gt_iir
);
1893 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1895 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1896 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1898 /* Call regardless, as some status bits might not be
1899 * signalled in iir */
1900 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1902 if (iir
& (I915_LPE_PIPE_A_INTERRUPT
|
1903 I915_LPE_PIPE_B_INTERRUPT
))
1904 intel_lpe_audio_irq_handler(dev_priv
);
1907 * VLV_IIR is single buffered, and reflects the level
1908 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1911 I915_WRITE(VLV_IIR
, iir
);
1913 I915_WRITE(VLV_IER
, ier
);
1914 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1915 POSTING_READ(VLV_MASTER_IER
);
1918 snb_gt_irq_handler(dev_priv
, gt_iir
);
1920 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1923 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1925 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1928 enable_rpm_wakeref_asserts(dev_priv
);
1933 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1935 struct drm_device
*dev
= arg
;
1936 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1937 irqreturn_t ret
= IRQ_NONE
;
1939 if (!intel_irqs_enabled(dev_priv
))
1942 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1943 disable_rpm_wakeref_asserts(dev_priv
);
1946 u32 master_ctl
, iir
;
1948 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1949 u32 hotplug_status
= 0;
1952 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1953 iir
= I915_READ(VLV_IIR
);
1955 if (master_ctl
== 0 && iir
== 0)
1961 * Theory on interrupt generation, based on empirical evidence:
1963 * x = ((VLV_IIR & VLV_IER) ||
1964 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1965 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1967 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1968 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1969 * guarantee the CPU interrupt will be raised again even if we
1970 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1971 * bits this time around.
1973 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1974 ier
= I915_READ(VLV_IER
);
1975 I915_WRITE(VLV_IER
, 0);
1977 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1979 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1980 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1982 /* Call regardless, as some status bits might not be
1983 * signalled in iir */
1984 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1986 if (iir
& (I915_LPE_PIPE_A_INTERRUPT
|
1987 I915_LPE_PIPE_B_INTERRUPT
|
1988 I915_LPE_PIPE_C_INTERRUPT
))
1989 intel_lpe_audio_irq_handler(dev_priv
);
1992 * VLV_IIR is single buffered, and reflects the level
1993 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1996 I915_WRITE(VLV_IIR
, iir
);
1998 I915_WRITE(VLV_IER
, ier
);
1999 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2000 POSTING_READ(GEN8_MASTER_IRQ
);
2002 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2005 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
2007 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
2010 enable_rpm_wakeref_asserts(dev_priv
);
2015 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2016 u32 hotplug_trigger
,
2017 const u32 hpd
[HPD_NUM_PINS
])
2019 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2022 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2023 * unless we touch the hotplug register, even if hotplug_trigger is
2024 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2027 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2028 if (!hotplug_trigger
) {
2029 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
2030 PORTD_HOTPLUG_STATUS_MASK
|
2031 PORTC_HOTPLUG_STATUS_MASK
|
2032 PORTB_HOTPLUG_STATUS_MASK
;
2033 dig_hotplug_reg
&= ~mask
;
2036 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2037 if (!hotplug_trigger
)
2040 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2041 dig_hotplug_reg
, hpd
,
2042 pch_port_hotplug_long_detect
);
2044 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2047 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2050 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
2052 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
2054 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
2055 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
2056 SDE_AUDIO_POWER_SHIFT
);
2057 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2061 if (pch_iir
& SDE_AUX_MASK
)
2062 dp_aux_irq_handler(dev_priv
);
2064 if (pch_iir
& SDE_GMBUS
)
2065 gmbus_irq_handler(dev_priv
);
2067 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
2068 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2070 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
2071 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2073 if (pch_iir
& SDE_POISON
)
2074 DRM_ERROR("PCH poison interrupt\n");
2076 if (pch_iir
& SDE_FDI_MASK
)
2077 for_each_pipe(dev_priv
, pipe
)
2078 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2080 I915_READ(FDI_RX_IIR(pipe
)));
2082 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
2083 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2085 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
2086 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2088 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
2089 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2091 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
2092 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2095 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
2097 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2100 if (err_int
& ERR_INT_POISON
)
2101 DRM_ERROR("Poison interrupt\n");
2103 for_each_pipe(dev_priv
, pipe
) {
2104 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2105 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2107 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2108 if (IS_IVYBRIDGE(dev_priv
))
2109 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
2111 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2115 I915_WRITE(GEN7_ERR_INT
, err_int
);
2118 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2120 u32 serr_int
= I915_READ(SERR_INT
);
2122 if (serr_int
& SERR_INT_POISON
)
2123 DRM_ERROR("PCH poison interrupt\n");
2125 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2126 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2128 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2129 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2131 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2132 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2134 I915_WRITE(SERR_INT
, serr_int
);
2137 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2140 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2142 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2144 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2145 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2146 SDE_AUDIO_POWER_SHIFT_CPT
);
2147 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2151 if (pch_iir
& SDE_AUX_MASK_CPT
)
2152 dp_aux_irq_handler(dev_priv
);
2154 if (pch_iir
& SDE_GMBUS_CPT
)
2155 gmbus_irq_handler(dev_priv
);
2157 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2158 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2160 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2161 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2163 if (pch_iir
& SDE_FDI_MASK_CPT
)
2164 for_each_pipe(dev_priv
, pipe
)
2165 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2167 I915_READ(FDI_RX_IIR(pipe
)));
2169 if (pch_iir
& SDE_ERROR_CPT
)
2170 cpt_serr_int_handler(dev_priv
);
2173 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2175 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2176 ~SDE_PORTE_HOTPLUG_SPT
;
2177 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2178 u32 pin_mask
= 0, long_mask
= 0;
2180 if (hotplug_trigger
) {
2181 u32 dig_hotplug_reg
;
2183 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2184 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2186 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2187 dig_hotplug_reg
, hpd_spt
,
2188 spt_port_hotplug_long_detect
);
2191 if (hotplug2_trigger
) {
2192 u32 dig_hotplug_reg
;
2194 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2195 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2197 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2198 dig_hotplug_reg
, hpd_spt
,
2199 spt_port_hotplug2_long_detect
);
2203 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2205 if (pch_iir
& SDE_GMBUS_CPT
)
2206 gmbus_irq_handler(dev_priv
);
2209 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2210 u32 hotplug_trigger
,
2211 const u32 hpd
[HPD_NUM_PINS
])
2213 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2215 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2216 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2218 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2219 dig_hotplug_reg
, hpd
,
2220 ilk_port_hotplug_long_detect
);
2222 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2225 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2229 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2231 if (hotplug_trigger
)
2232 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2234 if (de_iir
& DE_AUX_CHANNEL_A
)
2235 dp_aux_irq_handler(dev_priv
);
2237 if (de_iir
& DE_GSE
)
2238 intel_opregion_asle_intr(dev_priv
);
2240 if (de_iir
& DE_POISON
)
2241 DRM_ERROR("Poison interrupt\n");
2243 for_each_pipe(dev_priv
, pipe
) {
2244 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2245 intel_pipe_handle_vblank(dev_priv
, pipe
))
2246 intel_check_page_flip(dev_priv
, pipe
);
2248 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2249 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2251 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2252 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2254 /* plane/pipes map 1:1 on ilk+ */
2255 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
))
2256 intel_finish_page_flip_cs(dev_priv
, pipe
);
2259 /* check event from PCH */
2260 if (de_iir
& DE_PCH_EVENT
) {
2261 u32 pch_iir
= I915_READ(SDEIIR
);
2263 if (HAS_PCH_CPT(dev_priv
))
2264 cpt_irq_handler(dev_priv
, pch_iir
);
2266 ibx_irq_handler(dev_priv
, pch_iir
);
2268 /* should clear PCH hotplug event before clear CPU irq */
2269 I915_WRITE(SDEIIR
, pch_iir
);
2272 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2273 ironlake_rps_change_irq_handler(dev_priv
);
2276 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2280 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2282 if (hotplug_trigger
)
2283 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2285 if (de_iir
& DE_ERR_INT_IVB
)
2286 ivb_err_int_handler(dev_priv
);
2288 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2289 dp_aux_irq_handler(dev_priv
);
2291 if (de_iir
& DE_GSE_IVB
)
2292 intel_opregion_asle_intr(dev_priv
);
2294 for_each_pipe(dev_priv
, pipe
) {
2295 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2296 intel_pipe_handle_vblank(dev_priv
, pipe
))
2297 intel_check_page_flip(dev_priv
, pipe
);
2299 /* plane/pipes map 1:1 on ilk+ */
2300 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
))
2301 intel_finish_page_flip_cs(dev_priv
, pipe
);
2304 /* check event from PCH */
2305 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2306 u32 pch_iir
= I915_READ(SDEIIR
);
2308 cpt_irq_handler(dev_priv
, pch_iir
);
2310 /* clear PCH hotplug event before clear CPU irq */
2311 I915_WRITE(SDEIIR
, pch_iir
);
2316 * To handle irqs with the minimum potential races with fresh interrupts, we:
2317 * 1 - Disable Master Interrupt Control.
2318 * 2 - Find the source(s) of the interrupt.
2319 * 3 - Clear the Interrupt Identity bits (IIR).
2320 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2321 * 5 - Re-enable Master Interrupt Control.
2323 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2325 struct drm_device
*dev
= arg
;
2326 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2327 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2328 irqreturn_t ret
= IRQ_NONE
;
2330 if (!intel_irqs_enabled(dev_priv
))
2333 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2334 disable_rpm_wakeref_asserts(dev_priv
);
2336 /* disable master interrupt before clearing iir */
2337 de_ier
= I915_READ(DEIER
);
2338 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2339 POSTING_READ(DEIER
);
2341 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2342 * interrupts will will be stored on its back queue, and then we'll be
2343 * able to process them after we restore SDEIER (as soon as we restore
2344 * it, we'll get an interrupt if SDEIIR still has something to process
2345 * due to its back queue). */
2346 if (!HAS_PCH_NOP(dev_priv
)) {
2347 sde_ier
= I915_READ(SDEIER
);
2348 I915_WRITE(SDEIER
, 0);
2349 POSTING_READ(SDEIER
);
2352 /* Find, clear, then process each source of interrupt */
2354 gt_iir
= I915_READ(GTIIR
);
2356 I915_WRITE(GTIIR
, gt_iir
);
2358 if (INTEL_GEN(dev_priv
) >= 6)
2359 snb_gt_irq_handler(dev_priv
, gt_iir
);
2361 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2364 de_iir
= I915_READ(DEIIR
);
2366 I915_WRITE(DEIIR
, de_iir
);
2368 if (INTEL_GEN(dev_priv
) >= 7)
2369 ivb_display_irq_handler(dev_priv
, de_iir
);
2371 ilk_display_irq_handler(dev_priv
, de_iir
);
2374 if (INTEL_GEN(dev_priv
) >= 6) {
2375 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2377 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2379 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2383 I915_WRITE(DEIER
, de_ier
);
2384 POSTING_READ(DEIER
);
2385 if (!HAS_PCH_NOP(dev_priv
)) {
2386 I915_WRITE(SDEIER
, sde_ier
);
2387 POSTING_READ(SDEIER
);
2390 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2391 enable_rpm_wakeref_asserts(dev_priv
);
2396 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2397 u32 hotplug_trigger
,
2398 const u32 hpd
[HPD_NUM_PINS
])
2400 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2402 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2403 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2405 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2406 dig_hotplug_reg
, hpd
,
2407 bxt_port_hotplug_long_detect
);
2409 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2413 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2415 irqreturn_t ret
= IRQ_NONE
;
2419 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2420 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2422 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2424 if (iir
& GEN8_DE_MISC_GSE
)
2425 intel_opregion_asle_intr(dev_priv
);
2427 DRM_ERROR("Unexpected DE Misc interrupt\n");
2430 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2433 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2434 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2439 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2442 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2443 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2444 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2445 GEN9_AUX_CHANNEL_C
|
2448 if (iir
& tmp_mask
) {
2449 dp_aux_irq_handler(dev_priv
);
2453 if (IS_GEN9_LP(dev_priv
)) {
2454 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2456 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2460 } else if (IS_BROADWELL(dev_priv
)) {
2461 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2463 ilk_hpd_irq_handler(dev_priv
,
2469 if (IS_GEN9_LP(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2470 gmbus_irq_handler(dev_priv
);
2475 DRM_ERROR("Unexpected DE Port interrupt\n");
2478 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2481 for_each_pipe(dev_priv
, pipe
) {
2482 u32 flip_done
, fault_errors
;
2484 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2487 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2489 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2494 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2496 if (iir
& GEN8_PIPE_VBLANK
&&
2497 intel_pipe_handle_vblank(dev_priv
, pipe
))
2498 intel_check_page_flip(dev_priv
, pipe
);
2501 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2502 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2504 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2507 intel_finish_page_flip_cs(dev_priv
, pipe
);
2509 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2510 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2512 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2513 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2516 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2517 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2519 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2522 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2527 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2528 master_ctl
& GEN8_DE_PCH_IRQ
) {
2530 * FIXME(BDW): Assume for now that the new interrupt handling
2531 * scheme also closed the SDE interrupt handling race we've seen
2532 * on older pch-split platforms. But this needs testing.
2534 iir
= I915_READ(SDEIIR
);
2536 I915_WRITE(SDEIIR
, iir
);
2539 if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
) ||
2540 HAS_PCH_CNP(dev_priv
))
2541 spt_irq_handler(dev_priv
, iir
);
2543 cpt_irq_handler(dev_priv
, iir
);
2546 * Like on previous PCH there seems to be something
2547 * fishy going on with forwarding PCH interrupts.
2549 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2556 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2558 struct drm_device
*dev
= arg
;
2559 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2564 if (!intel_irqs_enabled(dev_priv
))
2567 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2568 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2572 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2574 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2575 disable_rpm_wakeref_asserts(dev_priv
);
2577 /* Find, clear, then process each source of interrupt */
2578 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2579 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2580 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2582 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2583 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2585 enable_rpm_wakeref_asserts(dev_priv
);
2591 struct delayed_work work
;
2592 struct drm_i915_private
*i915
;
2596 static void wedge_me(struct work_struct
*work
)
2598 struct wedge_me
*w
= container_of(work
, typeof(*w
), work
.work
);
2600 dev_err(w
->i915
->drm
.dev
,
2601 "%s timed out, cancelling all in-flight rendering.\n",
2603 i915_gem_set_wedged(w
->i915
);
2606 static void __init_wedge(struct wedge_me
*w
,
2607 struct drm_i915_private
*i915
,
2614 INIT_DELAYED_WORK_ONSTACK(&w
->work
, wedge_me
);
2615 schedule_delayed_work(&w
->work
, timeout
);
2618 static void __fini_wedge(struct wedge_me
*w
)
2620 cancel_delayed_work_sync(&w
->work
);
2621 destroy_delayed_work_on_stack(&w
->work
);
2625 #define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
2626 for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \
2631 * i915_reset_device - do process context error handling work
2632 * @dev_priv: i915 device private
2634 * Fire an error uevent so userspace can see that a hang or error
2637 static void i915_reset_device(struct drm_i915_private
*dev_priv
)
2639 struct kobject
*kobj
= &dev_priv
->drm
.primary
->kdev
->kobj
;
2640 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2641 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2642 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2645 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2647 DRM_DEBUG_DRIVER("resetting chip\n");
2648 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2650 /* Use a watchdog to ensure that our reset completes */
2651 i915_wedge_on_timeout(&w
, dev_priv
, 5*HZ
) {
2652 intel_prepare_reset(dev_priv
);
2654 /* Signal that locked waiters should reset the GPU */
2655 set_bit(I915_RESET_HANDOFF
, &dev_priv
->gpu_error
.flags
);
2656 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
2658 /* Wait for anyone holding the lock to wakeup, without
2659 * blocking indefinitely on struct_mutex.
2662 if (mutex_trylock(&dev_priv
->drm
.struct_mutex
)) {
2663 i915_reset(dev_priv
);
2664 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2666 } while (wait_on_bit_timeout(&dev_priv
->gpu_error
.flags
,
2668 TASK_UNINTERRUPTIBLE
,
2671 intel_finish_reset(dev_priv
);
2674 if (!test_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
))
2675 kobject_uevent_env(kobj
,
2676 KOBJ_CHANGE
, reset_done_event
);
2680 i915_err_print_instdone(struct drm_i915_private
*dev_priv
,
2681 struct intel_instdone
*instdone
)
2686 pr_err(" INSTDONE: 0x%08x\n", instdone
->instdone
);
2688 if (INTEL_GEN(dev_priv
) <= 3)
2691 pr_err(" SC_INSTDONE: 0x%08x\n", instdone
->slice_common
);
2693 if (INTEL_GEN(dev_priv
) <= 6)
2696 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
2697 pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2698 slice
, subslice
, instdone
->sampler
[slice
][subslice
]);
2700 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
2701 pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n",
2702 slice
, subslice
, instdone
->row
[slice
][subslice
]);
2705 static void i915_clear_error_registers(struct drm_i915_private
*dev_priv
)
2709 if (!IS_GEN2(dev_priv
))
2710 I915_WRITE(PGTBL_ER
, I915_READ(PGTBL_ER
));
2712 if (INTEL_GEN(dev_priv
) < 4)
2713 I915_WRITE(IPEIR
, I915_READ(IPEIR
));
2715 I915_WRITE(IPEIR_I965
, I915_READ(IPEIR_I965
));
2717 I915_WRITE(EIR
, I915_READ(EIR
));
2718 eir
= I915_READ(EIR
);
2721 * some errors might have become stuck,
2724 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir
);
2725 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2726 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2731 * i915_handle_error - handle a gpu error
2732 * @dev_priv: i915 device private
2733 * @engine_mask: mask representing engines that are hung
2734 * @fmt: Error message format string
2736 * Do some basic checking of register state at error time and
2737 * dump it to the syslog. Also call i915_capture_error_state() to make
2738 * sure we get a record and make it available in debugfs. Fire a uevent
2739 * so userspace knows something bad happened (should trigger collection
2740 * of a ring dump etc.).
2742 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2744 const char *fmt
, ...)
2746 struct intel_engine_cs
*engine
;
2751 va_start(args
, fmt
);
2752 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2756 * In most cases it's guaranteed that we get here with an RPM
2757 * reference held, for example because there is a pending GPU
2758 * request that won't finish until the reset is done. This
2759 * isn't the case at least when we get here by doing a
2760 * simulated reset via debugfs, so get an RPM reference.
2762 intel_runtime_pm_get(dev_priv
);
2764 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2765 i915_clear_error_registers(dev_priv
);
2768 * Try engine reset when available. We fall back to full reset if
2769 * single reset fails.
2771 if (intel_has_reset_engine(dev_priv
)) {
2772 for_each_engine_masked(engine
, dev_priv
, engine_mask
, tmp
) {
2773 BUILD_BUG_ON(I915_RESET_HANDOFF
>= I915_RESET_ENGINE
);
2774 if (test_and_set_bit(I915_RESET_ENGINE
+ engine
->id
,
2775 &dev_priv
->gpu_error
.flags
))
2778 if (i915_reset_engine(engine
) == 0)
2779 engine_mask
&= ~intel_engine_flag(engine
);
2781 clear_bit(I915_RESET_ENGINE
+ engine
->id
,
2782 &dev_priv
->gpu_error
.flags
);
2783 wake_up_bit(&dev_priv
->gpu_error
.flags
,
2784 I915_RESET_ENGINE
+ engine
->id
);
2791 /* Full reset needs the mutex, stop any other user trying to do so. */
2792 if (test_and_set_bit(I915_RESET_BACKOFF
, &dev_priv
->gpu_error
.flags
)) {
2793 wait_event(dev_priv
->gpu_error
.reset_queue
,
2794 !test_bit(I915_RESET_BACKOFF
,
2795 &dev_priv
->gpu_error
.flags
));
2799 /* Prevent any other reset-engine attempt. */
2800 for_each_engine(engine
, dev_priv
, tmp
) {
2801 while (test_and_set_bit(I915_RESET_ENGINE
+ engine
->id
,
2802 &dev_priv
->gpu_error
.flags
))
2803 wait_on_bit(&dev_priv
->gpu_error
.flags
,
2804 I915_RESET_ENGINE
+ engine
->id
,
2805 TASK_UNINTERRUPTIBLE
);
2808 i915_reset_device(dev_priv
);
2810 for_each_engine(engine
, dev_priv
, tmp
) {
2811 clear_bit(I915_RESET_ENGINE
+ engine
->id
,
2812 &dev_priv
->gpu_error
.flags
);
2815 clear_bit(I915_RESET_BACKOFF
, &dev_priv
->gpu_error
.flags
);
2816 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2819 intel_runtime_pm_put(dev_priv
);
2822 /* Called from drm generic code, passed 'crtc' which
2823 * we use as a pipe index
2825 static int i8xx_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2827 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2828 unsigned long irqflags
;
2830 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2831 i915_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2832 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2837 static int i965_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2839 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2840 unsigned long irqflags
;
2842 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2843 i915_enable_pipestat(dev_priv
, pipe
,
2844 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2845 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2850 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2852 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2853 unsigned long irqflags
;
2854 uint32_t bit
= INTEL_GEN(dev_priv
) >= 7 ?
2855 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2857 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2858 ilk_enable_display_irq(dev_priv
, bit
);
2859 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2864 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2867 unsigned long irqflags
;
2869 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2870 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2871 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2876 /* Called from drm generic code, passed 'crtc' which
2877 * we use as a pipe index
2879 static void i8xx_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2882 unsigned long irqflags
;
2884 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2885 i915_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_STATUS
);
2886 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2889 static void i965_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2891 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2892 unsigned long irqflags
;
2894 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2895 i915_disable_pipestat(dev_priv
, pipe
,
2896 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2897 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2900 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2902 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2903 unsigned long irqflags
;
2904 uint32_t bit
= INTEL_GEN(dev_priv
) >= 7 ?
2905 DE_PIPE_VBLANK_IVB(pipe
) : DE_PIPE_VBLANK(pipe
);
2907 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2908 ilk_disable_display_irq(dev_priv
, bit
);
2909 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2912 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2914 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2915 unsigned long irqflags
;
2917 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2918 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2919 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2922 static void ibx_irq_reset(struct drm_i915_private
*dev_priv
)
2924 if (HAS_PCH_NOP(dev_priv
))
2927 GEN5_IRQ_RESET(SDE
);
2929 if (HAS_PCH_CPT(dev_priv
) || HAS_PCH_LPT(dev_priv
))
2930 I915_WRITE(SERR_INT
, 0xffffffff);
2934 * SDEIER is also touched by the interrupt handler to work around missed PCH
2935 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2936 * instead we unconditionally enable all PCH interrupt sources here, but then
2937 * only unmask them as needed with SDEIMR.
2939 * This function needs to be called before interrupts are enabled.
2941 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
2943 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2945 if (HAS_PCH_NOP(dev_priv
))
2948 WARN_ON(I915_READ(SDEIER
) != 0);
2949 I915_WRITE(SDEIER
, 0xffffffff);
2950 POSTING_READ(SDEIER
);
2953 static void gen5_gt_irq_reset(struct drm_i915_private
*dev_priv
)
2956 if (INTEL_GEN(dev_priv
) >= 6)
2957 GEN5_IRQ_RESET(GEN6_PM
);
2960 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
2964 if (IS_CHERRYVIEW(dev_priv
))
2965 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
2967 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2969 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
2970 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2972 for_each_pipe(dev_priv
, pipe
) {
2973 I915_WRITE(PIPESTAT(pipe
),
2974 PIPE_FIFO_UNDERRUN_STATUS
|
2975 PIPESTAT_INT_STATUS_MASK
);
2976 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
2979 GEN5_IRQ_RESET(VLV_
);
2980 dev_priv
->irq_mask
= ~0;
2983 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
2989 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
2990 PIPE_CRC_DONE_INTERRUPT_STATUS
;
2992 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
2993 for_each_pipe(dev_priv
, pipe
)
2994 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
2996 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
2997 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2998 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2999 I915_LPE_PIPE_A_INTERRUPT
|
3000 I915_LPE_PIPE_B_INTERRUPT
;
3002 if (IS_CHERRYVIEW(dev_priv
))
3003 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
|
3004 I915_LPE_PIPE_C_INTERRUPT
;
3006 WARN_ON(dev_priv
->irq_mask
!= ~0);
3008 dev_priv
->irq_mask
= ~enable_mask
;
3010 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3015 static void ironlake_irq_reset(struct drm_device
*dev
)
3017 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3019 I915_WRITE(HWSTAM
, 0xffffffff);
3022 if (IS_GEN7(dev_priv
))
3023 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3025 gen5_gt_irq_reset(dev_priv
);
3027 ibx_irq_reset(dev_priv
);
3030 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3032 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3034 I915_WRITE(VLV_MASTER_IER
, 0);
3035 POSTING_READ(VLV_MASTER_IER
);
3037 gen5_gt_irq_reset(dev_priv
);
3039 spin_lock_irq(&dev_priv
->irq_lock
);
3040 if (dev_priv
->display_irqs_enabled
)
3041 vlv_display_irq_reset(dev_priv
);
3042 spin_unlock_irq(&dev_priv
->irq_lock
);
3045 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3047 GEN8_IRQ_RESET_NDX(GT
, 0);
3048 GEN8_IRQ_RESET_NDX(GT
, 1);
3049 GEN8_IRQ_RESET_NDX(GT
, 2);
3050 GEN8_IRQ_RESET_NDX(GT
, 3);
3053 static void gen8_irq_reset(struct drm_device
*dev
)
3055 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3058 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3059 POSTING_READ(GEN8_MASTER_IRQ
);
3061 gen8_gt_irq_reset(dev_priv
);
3063 for_each_pipe(dev_priv
, pipe
)
3064 if (intel_display_power_is_enabled(dev_priv
,
3065 POWER_DOMAIN_PIPE(pipe
)))
3066 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3068 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3069 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3070 GEN5_IRQ_RESET(GEN8_PCU_
);
3072 if (HAS_PCH_SPLIT(dev_priv
))
3073 ibx_irq_reset(dev_priv
);
3076 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3077 unsigned int pipe_mask
)
3079 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3082 spin_lock_irq(&dev_priv
->irq_lock
);
3083 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3084 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3085 dev_priv
->de_irq_mask
[pipe
],
3086 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3087 spin_unlock_irq(&dev_priv
->irq_lock
);
3090 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3091 unsigned int pipe_mask
)
3095 spin_lock_irq(&dev_priv
->irq_lock
);
3096 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3097 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3098 spin_unlock_irq(&dev_priv
->irq_lock
);
3100 /* make sure we're done processing display irqs */
3101 synchronize_irq(dev_priv
->drm
.irq
);
3104 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3106 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3108 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3109 POSTING_READ(GEN8_MASTER_IRQ
);
3111 gen8_gt_irq_reset(dev_priv
);
3113 GEN5_IRQ_RESET(GEN8_PCU_
);
3115 spin_lock_irq(&dev_priv
->irq_lock
);
3116 if (dev_priv
->display_irqs_enabled
)
3117 vlv_display_irq_reset(dev_priv
);
3118 spin_unlock_irq(&dev_priv
->irq_lock
);
3121 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3122 const u32 hpd
[HPD_NUM_PINS
])
3124 struct intel_encoder
*encoder
;
3125 u32 enabled_irqs
= 0;
3127 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
3128 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3129 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3131 return enabled_irqs
;
3134 static void ibx_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3139 * Enable digital hotplug on the PCH, and configure the DP short pulse
3140 * duration to 2ms (which is the minimum in the Display Port spec).
3141 * The pulse duration bits are reserved on LPT+.
3143 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3144 hotplug
&= ~(PORTB_PULSE_DURATION_MASK
|
3145 PORTC_PULSE_DURATION_MASK
|
3146 PORTD_PULSE_DURATION_MASK
);
3147 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3148 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3149 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3151 * When CPU and PCH are on the same package, port A
3152 * HPD must be enabled in both north and south.
3154 if (HAS_PCH_LPT_LP(dev_priv
))
3155 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3156 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3159 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3161 u32 hotplug_irqs
, enabled_irqs
;
3163 if (HAS_PCH_IBX(dev_priv
)) {
3164 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3165 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3167 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3168 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3171 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3173 ibx_hpd_detection_setup(dev_priv
);
3176 static void spt_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3180 /* Enable digital hotplug on the PCH */
3181 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3182 hotplug
|= PORTA_HOTPLUG_ENABLE
|
3183 PORTB_HOTPLUG_ENABLE
|
3184 PORTC_HOTPLUG_ENABLE
|
3185 PORTD_HOTPLUG_ENABLE
;
3186 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3188 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3189 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3190 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3193 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3195 u32 hotplug_irqs
, enabled_irqs
;
3197 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3198 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3200 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3202 spt_hpd_detection_setup(dev_priv
);
3205 static void ilk_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3210 * Enable digital hotplug on the CPU, and configure the DP short pulse
3211 * duration to 2ms (which is the minimum in the Display Port spec)
3212 * The pulse duration bits are reserved on HSW+.
3214 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3215 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3216 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
|
3217 DIGITAL_PORTA_PULSE_DURATION_2ms
;
3218 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3221 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3223 u32 hotplug_irqs
, enabled_irqs
;
3225 if (INTEL_GEN(dev_priv
) >= 8) {
3226 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3227 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3229 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3230 } else if (INTEL_GEN(dev_priv
) >= 7) {
3231 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3232 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3234 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3236 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3237 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3239 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3242 ilk_hpd_detection_setup(dev_priv
);
3244 ibx_hpd_irq_setup(dev_priv
);
3247 static void __bxt_hpd_detection_setup(struct drm_i915_private
*dev_priv
,
3252 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3253 hotplug
|= PORTA_HOTPLUG_ENABLE
|
3254 PORTB_HOTPLUG_ENABLE
|
3255 PORTC_HOTPLUG_ENABLE
;
3257 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3258 hotplug
, enabled_irqs
);
3259 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3262 * For BXT invert bit has to be set based on AOB design
3263 * for HPD detection logic, update it based on VBT fields.
3265 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3266 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3267 hotplug
|= BXT_DDIA_HPD_INVERT
;
3268 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3269 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3270 hotplug
|= BXT_DDIB_HPD_INVERT
;
3271 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3272 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3273 hotplug
|= BXT_DDIC_HPD_INVERT
;
3275 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3278 static void bxt_hpd_detection_setup(struct drm_i915_private
*dev_priv
)
3280 __bxt_hpd_detection_setup(dev_priv
, BXT_DE_PORT_HOTPLUG_MASK
);
3283 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3285 u32 hotplug_irqs
, enabled_irqs
;
3287 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3288 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3290 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3292 __bxt_hpd_detection_setup(dev_priv
, enabled_irqs
);
3295 static void ibx_irq_postinstall(struct drm_device
*dev
)
3297 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3300 if (HAS_PCH_NOP(dev_priv
))
3303 if (HAS_PCH_IBX(dev_priv
))
3304 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3306 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3308 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3309 I915_WRITE(SDEIMR
, ~mask
);
3311 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
3312 HAS_PCH_LPT(dev_priv
))
3313 ibx_hpd_detection_setup(dev_priv
);
3315 spt_hpd_detection_setup(dev_priv
);
3318 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3320 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3321 u32 pm_irqs
, gt_irqs
;
3323 pm_irqs
= gt_irqs
= 0;
3325 dev_priv
->gt_irq_mask
= ~0;
3326 if (HAS_L3_DPF(dev_priv
)) {
3327 /* L3 parity interrupt is always unmasked. */
3328 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev_priv
);
3329 gt_irqs
|= GT_PARITY_ERROR(dev_priv
);
3332 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3333 if (IS_GEN5(dev_priv
)) {
3334 gt_irqs
|= ILK_BSD_USER_INTERRUPT
;
3336 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3339 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3341 if (INTEL_GEN(dev_priv
) >= 6) {
3343 * RPS interrupts will get enabled/disabled on demand when RPS
3344 * itself is enabled/disabled.
3346 if (HAS_VEBOX(dev_priv
)) {
3347 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3348 dev_priv
->pm_ier
|= PM_VEBOX_USER_INTERRUPT
;
3351 dev_priv
->pm_imr
= 0xffffffff;
3352 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_imr
, pm_irqs
);
3356 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3359 u32 display_mask
, extra_mask
;
3361 if (INTEL_GEN(dev_priv
) >= 7) {
3362 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3363 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3364 DE_PLANEB_FLIP_DONE_IVB
|
3365 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3366 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3367 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3368 DE_DP_A_HOTPLUG_IVB
);
3370 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3371 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3373 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3375 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3376 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3380 dev_priv
->irq_mask
= ~display_mask
;
3382 I915_WRITE(HWSTAM
, 0xeffe);
3384 ibx_irq_pre_postinstall(dev
);
3386 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3388 gen5_gt_irq_postinstall(dev
);
3390 ilk_hpd_detection_setup(dev_priv
);
3392 ibx_irq_postinstall(dev
);
3394 if (IS_IRONLAKE_M(dev_priv
)) {
3395 /* Enable PCU event interrupts
3397 * spinlocking not required here for correctness since interrupt
3398 * setup is guaranteed to run in single-threaded context. But we
3399 * need it to make the assert_spin_locked happy. */
3400 spin_lock_irq(&dev_priv
->irq_lock
);
3401 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3402 spin_unlock_irq(&dev_priv
->irq_lock
);
3408 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3410 lockdep_assert_held(&dev_priv
->irq_lock
);
3412 if (dev_priv
->display_irqs_enabled
)
3415 dev_priv
->display_irqs_enabled
= true;
3417 if (intel_irqs_enabled(dev_priv
)) {
3418 vlv_display_irq_reset(dev_priv
);
3419 vlv_display_irq_postinstall(dev_priv
);
3423 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3425 lockdep_assert_held(&dev_priv
->irq_lock
);
3427 if (!dev_priv
->display_irqs_enabled
)
3430 dev_priv
->display_irqs_enabled
= false;
3432 if (intel_irqs_enabled(dev_priv
))
3433 vlv_display_irq_reset(dev_priv
);
3437 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3439 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3441 gen5_gt_irq_postinstall(dev
);
3443 spin_lock_irq(&dev_priv
->irq_lock
);
3444 if (dev_priv
->display_irqs_enabled
)
3445 vlv_display_irq_postinstall(dev_priv
);
3446 spin_unlock_irq(&dev_priv
->irq_lock
);
3448 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3449 POSTING_READ(VLV_MASTER_IER
);
3454 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3456 /* These are interrupts we'll toggle with the ring mask register */
3457 uint32_t gt_interrupts
[] = {
3458 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3459 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3460 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3461 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3462 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3463 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3464 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3465 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3467 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3468 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3471 if (HAS_L3_DPF(dev_priv
))
3472 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3474 dev_priv
->pm_ier
= 0x0;
3475 dev_priv
->pm_imr
= ~dev_priv
->pm_ier
;
3476 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3477 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3479 * RPS interrupts will get enabled/disabled on demand when RPS itself
3480 * is enabled/disabled. Same wil be the case for GuC interrupts.
3482 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_imr
, dev_priv
->pm_ier
);
3483 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3486 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3488 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3489 uint32_t de_pipe_enables
;
3490 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3491 u32 de_port_enables
;
3492 u32 de_misc_masked
= GEN8_DE_MISC_GSE
;
3495 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3496 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3497 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3498 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3500 if (IS_GEN9_LP(dev_priv
))
3501 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3503 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3504 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3507 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3508 GEN8_PIPE_FIFO_UNDERRUN
;
3510 de_port_enables
= de_port_masked
;
3511 if (IS_GEN9_LP(dev_priv
))
3512 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3513 else if (IS_BROADWELL(dev_priv
))
3514 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3516 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3517 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3518 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3520 for_each_pipe(dev_priv
, pipe
)
3521 if (intel_display_power_is_enabled(dev_priv
,
3522 POWER_DOMAIN_PIPE(pipe
)))
3523 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3524 dev_priv
->de_irq_mask
[pipe
],
3527 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3528 GEN5_IRQ_INIT(GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3530 if (IS_GEN9_LP(dev_priv
))
3531 bxt_hpd_detection_setup(dev_priv
);
3532 else if (IS_BROADWELL(dev_priv
))
3533 ilk_hpd_detection_setup(dev_priv
);
3536 static int gen8_irq_postinstall(struct drm_device
*dev
)
3538 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3540 if (HAS_PCH_SPLIT(dev_priv
))
3541 ibx_irq_pre_postinstall(dev
);
3543 gen8_gt_irq_postinstall(dev_priv
);
3544 gen8_de_irq_postinstall(dev_priv
);
3546 if (HAS_PCH_SPLIT(dev_priv
))
3547 ibx_irq_postinstall(dev
);
3549 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3550 POSTING_READ(GEN8_MASTER_IRQ
);
3555 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3557 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3559 gen8_gt_irq_postinstall(dev_priv
);
3561 spin_lock_irq(&dev_priv
->irq_lock
);
3562 if (dev_priv
->display_irqs_enabled
)
3563 vlv_display_irq_postinstall(dev_priv
);
3564 spin_unlock_irq(&dev_priv
->irq_lock
);
3566 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3567 POSTING_READ(GEN8_MASTER_IRQ
);
3572 static void gen8_irq_uninstall(struct drm_device
*dev
)
3574 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3579 gen8_irq_reset(dev
);
3582 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3584 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3589 I915_WRITE(VLV_MASTER_IER
, 0);
3590 POSTING_READ(VLV_MASTER_IER
);
3592 gen5_gt_irq_reset(dev_priv
);
3594 I915_WRITE(HWSTAM
, 0xffffffff);
3596 spin_lock_irq(&dev_priv
->irq_lock
);
3597 if (dev_priv
->display_irqs_enabled
)
3598 vlv_display_irq_reset(dev_priv
);
3599 spin_unlock_irq(&dev_priv
->irq_lock
);
3602 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3604 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3609 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3610 POSTING_READ(GEN8_MASTER_IRQ
);
3612 gen8_gt_irq_reset(dev_priv
);
3614 GEN5_IRQ_RESET(GEN8_PCU_
);
3616 spin_lock_irq(&dev_priv
->irq_lock
);
3617 if (dev_priv
->display_irqs_enabled
)
3618 vlv_display_irq_reset(dev_priv
);
3619 spin_unlock_irq(&dev_priv
->irq_lock
);
3622 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3624 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3629 ironlake_irq_reset(dev
);
3632 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3634 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3637 for_each_pipe(dev_priv
, pipe
)
3638 I915_WRITE(PIPESTAT(pipe
), 0);
3639 I915_WRITE16(IMR
, 0xffff);
3640 I915_WRITE16(IER
, 0x0);
3641 POSTING_READ16(IER
);
3644 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3646 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3649 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3651 /* Unmask the interrupts that we always want on. */
3652 dev_priv
->irq_mask
=
3653 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3654 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3655 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3656 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3657 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3660 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3661 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3662 I915_USER_INTERRUPT
);
3663 POSTING_READ16(IER
);
3665 /* Interrupt setup is already guaranteed to be single-threaded, this is
3666 * just to make the assert_spin_locked check happy. */
3667 spin_lock_irq(&dev_priv
->irq_lock
);
3668 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3669 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3670 spin_unlock_irq(&dev_priv
->irq_lock
);
3676 * Returns true when a page flip has completed.
3678 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3679 int plane
, int pipe
, u32 iir
)
3681 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3683 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3686 if ((iir
& flip_pending
) == 0)
3687 goto check_page_flip
;
3689 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3690 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3691 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3692 * the flip is completed (no longer pending). Since this doesn't raise
3693 * an interrupt per se, we watch for the change at vblank.
3695 if (I915_READ16(ISR
) & flip_pending
)
3696 goto check_page_flip
;
3698 intel_finish_page_flip_cs(dev_priv
, pipe
);
3702 intel_check_page_flip(dev_priv
, pipe
);
3706 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3708 struct drm_device
*dev
= arg
;
3709 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3714 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3715 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3718 if (!intel_irqs_enabled(dev_priv
))
3721 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3722 disable_rpm_wakeref_asserts(dev_priv
);
3725 iir
= I915_READ16(IIR
);
3729 while (iir
& ~flip_mask
) {
3730 /* Can't rely on pipestat interrupt bit in iir as it might
3731 * have been cleared after the pipestat interrupt was received.
3732 * It doesn't set the bit in iir again, but it still produces
3733 * interrupts (for non-MSI).
3735 spin_lock(&dev_priv
->irq_lock
);
3736 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3737 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3739 for_each_pipe(dev_priv
, pipe
) {
3740 i915_reg_t reg
= PIPESTAT(pipe
);
3741 pipe_stats
[pipe
] = I915_READ(reg
);
3744 * Clear the PIPE*STAT regs before the IIR
3746 if (pipe_stats
[pipe
] & 0x8000ffff)
3747 I915_WRITE(reg
, pipe_stats
[pipe
]);
3749 spin_unlock(&dev_priv
->irq_lock
);
3751 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3752 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3754 if (iir
& I915_USER_INTERRUPT
)
3755 notify_ring(dev_priv
->engine
[RCS
]);
3757 for_each_pipe(dev_priv
, pipe
) {
3759 if (HAS_FBC(dev_priv
))
3762 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3763 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
3764 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3766 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3767 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
3769 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3770 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3779 enable_rpm_wakeref_asserts(dev_priv
);
3784 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3786 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3789 for_each_pipe(dev_priv
, pipe
) {
3790 /* Clear enable bits; then clear status bits */
3791 I915_WRITE(PIPESTAT(pipe
), 0);
3792 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3794 I915_WRITE16(IMR
, 0xffff);
3795 I915_WRITE16(IER
, 0x0);
3796 I915_WRITE16(IIR
, I915_READ16(IIR
));
3799 static void i915_irq_preinstall(struct drm_device
* dev
)
3801 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3804 if (I915_HAS_HOTPLUG(dev_priv
)) {
3805 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3806 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3809 I915_WRITE16(HWSTAM
, 0xeffe);
3810 for_each_pipe(dev_priv
, pipe
)
3811 I915_WRITE(PIPESTAT(pipe
), 0);
3812 I915_WRITE(IMR
, 0xffffffff);
3813 I915_WRITE(IER
, 0x0);
3817 static int i915_irq_postinstall(struct drm_device
*dev
)
3819 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3822 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3824 /* Unmask the interrupts that we always want on. */
3825 dev_priv
->irq_mask
=
3826 ~(I915_ASLE_INTERRUPT
|
3827 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3828 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3829 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3830 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3833 I915_ASLE_INTERRUPT
|
3834 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3835 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3836 I915_USER_INTERRUPT
;
3838 if (I915_HAS_HOTPLUG(dev_priv
)) {
3839 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
3840 POSTING_READ(PORT_HOTPLUG_EN
);
3842 /* Enable in IER... */
3843 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3844 /* and unmask in IMR */
3845 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3848 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3849 I915_WRITE(IER
, enable_mask
);
3852 i915_enable_asle_pipestat(dev_priv
);
3854 /* Interrupt setup is already guaranteed to be single-threaded, this is
3855 * just to make the assert_spin_locked check happy. */
3856 spin_lock_irq(&dev_priv
->irq_lock
);
3857 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3858 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3859 spin_unlock_irq(&dev_priv
->irq_lock
);
3865 * Returns true when a page flip has completed.
3867 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
3868 int plane
, int pipe
, u32 iir
)
3870 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3872 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3875 if ((iir
& flip_pending
) == 0)
3876 goto check_page_flip
;
3878 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3879 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3880 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3881 * the flip is completed (no longer pending). Since this doesn't raise
3882 * an interrupt per se, we watch for the change at vblank.
3884 if (I915_READ(ISR
) & flip_pending
)
3885 goto check_page_flip
;
3887 intel_finish_page_flip_cs(dev_priv
, pipe
);
3891 intel_check_page_flip(dev_priv
, pipe
);
3895 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3897 struct drm_device
*dev
= arg
;
3898 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3899 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3901 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3902 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3903 int pipe
, ret
= IRQ_NONE
;
3905 if (!intel_irqs_enabled(dev_priv
))
3908 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3909 disable_rpm_wakeref_asserts(dev_priv
);
3911 iir
= I915_READ(IIR
);
3913 bool irq_received
= (iir
& ~flip_mask
) != 0;
3914 bool blc_event
= false;
3916 /* Can't rely on pipestat interrupt bit in iir as it might
3917 * have been cleared after the pipestat interrupt was received.
3918 * It doesn't set the bit in iir again, but it still produces
3919 * interrupts (for non-MSI).
3921 spin_lock(&dev_priv
->irq_lock
);
3922 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3923 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3925 for_each_pipe(dev_priv
, pipe
) {
3926 i915_reg_t reg
= PIPESTAT(pipe
);
3927 pipe_stats
[pipe
] = I915_READ(reg
);
3929 /* Clear the PIPE*STAT regs before the IIR */
3930 if (pipe_stats
[pipe
] & 0x8000ffff) {
3931 I915_WRITE(reg
, pipe_stats
[pipe
]);
3932 irq_received
= true;
3935 spin_unlock(&dev_priv
->irq_lock
);
3940 /* Consume port. Then clear IIR or we'll miss events */
3941 if (I915_HAS_HOTPLUG(dev_priv
) &&
3942 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3943 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
3945 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
3948 I915_WRITE(IIR
, iir
& ~flip_mask
);
3949 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3951 if (iir
& I915_USER_INTERRUPT
)
3952 notify_ring(dev_priv
->engine
[RCS
]);
3954 for_each_pipe(dev_priv
, pipe
) {
3956 if (HAS_FBC(dev_priv
))
3959 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3960 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
3961 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3963 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3966 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3967 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
3969 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3970 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3974 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3975 intel_opregion_asle_intr(dev_priv
);
3977 /* With MSI, interrupts are only generated when iir
3978 * transitions from zero to nonzero. If another bit got
3979 * set while we were handling the existing iir bits, then
3980 * we would never get another interrupt.
3982 * This is fine on non-MSI as well, as if we hit this path
3983 * we avoid exiting the interrupt handler only to generate
3986 * Note that for MSI this could cause a stray interrupt report
3987 * if an interrupt landed in the time between writing IIR and
3988 * the posting read. This should be rare enough to never
3989 * trigger the 99% of 100,000 interrupts test for disabling
3994 } while (iir
& ~flip_mask
);
3996 enable_rpm_wakeref_asserts(dev_priv
);
4001 static void i915_irq_uninstall(struct drm_device
* dev
)
4003 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4006 if (I915_HAS_HOTPLUG(dev_priv
)) {
4007 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4008 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4011 I915_WRITE16(HWSTAM
, 0xffff);
4012 for_each_pipe(dev_priv
, pipe
) {
4013 /* Clear enable bits; then clear status bits */
4014 I915_WRITE(PIPESTAT(pipe
), 0);
4015 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4017 I915_WRITE(IMR
, 0xffffffff);
4018 I915_WRITE(IER
, 0x0);
4020 I915_WRITE(IIR
, I915_READ(IIR
));
4023 static void i965_irq_preinstall(struct drm_device
* dev
)
4025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4028 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4029 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4031 I915_WRITE(HWSTAM
, 0xeffe);
4032 for_each_pipe(dev_priv
, pipe
)
4033 I915_WRITE(PIPESTAT(pipe
), 0);
4034 I915_WRITE(IMR
, 0xffffffff);
4035 I915_WRITE(IER
, 0x0);
4039 static int i965_irq_postinstall(struct drm_device
*dev
)
4041 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4045 /* Unmask the interrupts that we always want on. */
4046 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4047 I915_DISPLAY_PORT_INTERRUPT
|
4048 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4049 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4050 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4051 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4052 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4054 enable_mask
= ~dev_priv
->irq_mask
;
4055 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4056 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4057 enable_mask
|= I915_USER_INTERRUPT
;
4059 if (IS_G4X(dev_priv
))
4060 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4062 /* Interrupt setup is already guaranteed to be single-threaded, this is
4063 * just to make the assert_spin_locked check happy. */
4064 spin_lock_irq(&dev_priv
->irq_lock
);
4065 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4066 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4067 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4068 spin_unlock_irq(&dev_priv
->irq_lock
);
4071 * Enable some error detection, note the instruction error mask
4072 * bit is reserved, so we leave it masked.
4074 if (IS_G4X(dev_priv
)) {
4075 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4076 GM45_ERROR_MEM_PRIV
|
4077 GM45_ERROR_CP_PRIV
|
4078 I915_ERROR_MEMORY_REFRESH
);
4080 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4081 I915_ERROR_MEMORY_REFRESH
);
4083 I915_WRITE(EMR
, error_mask
);
4085 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4086 I915_WRITE(IER
, enable_mask
);
4089 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4090 POSTING_READ(PORT_HOTPLUG_EN
);
4092 i915_enable_asle_pipestat(dev_priv
);
4097 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
4101 lockdep_assert_held(&dev_priv
->irq_lock
);
4103 /* Note HDMI and DP share hotplug bits */
4104 /* enable bits are the same for all generations */
4105 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
4106 /* Programming the CRT detection parameters tends
4107 to generate a spurious hotplug event about three
4108 seconds later. So just do it once.
4110 if (IS_G4X(dev_priv
))
4111 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4112 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4114 /* Ignore TV since it's buggy */
4115 i915_hotplug_interrupt_update_locked(dev_priv
,
4116 HOTPLUG_INT_EN_MASK
|
4117 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4118 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4122 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4124 struct drm_device
*dev
= arg
;
4125 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4127 u32 pipe_stats
[I915_MAX_PIPES
];
4128 int ret
= IRQ_NONE
, pipe
;
4130 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4131 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4133 if (!intel_irqs_enabled(dev_priv
))
4136 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4137 disable_rpm_wakeref_asserts(dev_priv
);
4139 iir
= I915_READ(IIR
);
4142 bool irq_received
= (iir
& ~flip_mask
) != 0;
4143 bool blc_event
= false;
4145 /* Can't rely on pipestat interrupt bit in iir as it might
4146 * have been cleared after the pipestat interrupt was received.
4147 * It doesn't set the bit in iir again, but it still produces
4148 * interrupts (for non-MSI).
4150 spin_lock(&dev_priv
->irq_lock
);
4151 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4152 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4154 for_each_pipe(dev_priv
, pipe
) {
4155 i915_reg_t reg
= PIPESTAT(pipe
);
4156 pipe_stats
[pipe
] = I915_READ(reg
);
4159 * Clear the PIPE*STAT regs before the IIR
4161 if (pipe_stats
[pipe
] & 0x8000ffff) {
4162 I915_WRITE(reg
, pipe_stats
[pipe
]);
4163 irq_received
= true;
4166 spin_unlock(&dev_priv
->irq_lock
);
4173 /* Consume port. Then clear IIR or we'll miss events */
4174 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4175 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4177 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4180 I915_WRITE(IIR
, iir
& ~flip_mask
);
4181 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4183 if (iir
& I915_USER_INTERRUPT
)
4184 notify_ring(dev_priv
->engine
[RCS
]);
4185 if (iir
& I915_BSD_USER_INTERRUPT
)
4186 notify_ring(dev_priv
->engine
[VCS
]);
4188 for_each_pipe(dev_priv
, pipe
) {
4189 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4190 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4191 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4193 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4196 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4197 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4199 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4200 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4203 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4204 intel_opregion_asle_intr(dev_priv
);
4206 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4207 gmbus_irq_handler(dev_priv
);
4209 /* With MSI, interrupts are only generated when iir
4210 * transitions from zero to nonzero. If another bit got
4211 * set while we were handling the existing iir bits, then
4212 * we would never get another interrupt.
4214 * This is fine on non-MSI as well, as if we hit this path
4215 * we avoid exiting the interrupt handler only to generate
4218 * Note that for MSI this could cause a stray interrupt report
4219 * if an interrupt landed in the time between writing IIR and
4220 * the posting read. This should be rare enough to never
4221 * trigger the 99% of 100,000 interrupts test for disabling
4227 enable_rpm_wakeref_asserts(dev_priv
);
4232 static void i965_irq_uninstall(struct drm_device
* dev
)
4234 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4240 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4241 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4243 I915_WRITE(HWSTAM
, 0xffffffff);
4244 for_each_pipe(dev_priv
, pipe
)
4245 I915_WRITE(PIPESTAT(pipe
), 0);
4246 I915_WRITE(IMR
, 0xffffffff);
4247 I915_WRITE(IER
, 0x0);
4249 for_each_pipe(dev_priv
, pipe
)
4250 I915_WRITE(PIPESTAT(pipe
),
4251 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4252 I915_WRITE(IIR
, I915_READ(IIR
));
4256 * intel_irq_init - initializes irq support
4257 * @dev_priv: i915 device instance
4259 * This function initializes all the irq support including work items, timers
4260 * and all the vtables. It does not setup the interrupt itself though.
4262 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4264 struct drm_device
*dev
= &dev_priv
->drm
;
4267 intel_hpd_init_work(dev_priv
);
4269 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4271 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4272 for (i
= 0; i
< MAX_L3_SLICES
; ++i
)
4273 dev_priv
->l3_parity
.remap_info
[i
] = NULL
;
4275 if (HAS_GUC_SCHED(dev_priv
))
4276 dev_priv
->pm_guc_events
= GEN9_GUC_TO_HOST_INT_EVENT
;
4278 /* Let's track the enabled rps events */
4279 if (IS_VALLEYVIEW(dev_priv
))
4280 /* WaGsvRC0ResidencyMethod:vlv */
4281 dev_priv
->pm_rps_events
= GEN6_PM_RP_UP_EI_EXPIRED
;
4283 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4285 dev_priv
->rps
.pm_intrmsk_mbz
= 0;
4288 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4289 * if GEN6_PM_UP_EI_EXPIRED is masked.
4291 * TODO: verify if this can be reproduced on VLV,CHV.
4293 if (INTEL_INFO(dev_priv
)->gen
<= 7)
4294 dev_priv
->rps
.pm_intrmsk_mbz
|= GEN6_PM_RP_UP_EI_EXPIRED
;
4296 if (INTEL_INFO(dev_priv
)->gen
>= 8)
4297 dev_priv
->rps
.pm_intrmsk_mbz
|= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
;
4299 if (IS_GEN2(dev_priv
)) {
4300 /* Gen2 doesn't have a hardware frame counter */
4301 dev
->max_vblank_count
= 0;
4302 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4303 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4304 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4306 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4307 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4311 * Opt out of the vblank disable timer on everything except gen2.
4312 * Gen2 doesn't have a hardware frame counter and so depends on
4313 * vblank interrupts to produce sane vblank seuquence numbers.
4315 if (!IS_GEN2(dev_priv
))
4316 dev
->vblank_disable_immediate
= true;
4318 /* Most platforms treat the display irq block as an always-on
4319 * power domain. vlv/chv can disable it at runtime and need
4320 * special care to avoid writing any of the display block registers
4321 * outside of the power domain. We defer setting up the display irqs
4322 * in this case to the runtime pm.
4324 dev_priv
->display_irqs_enabled
= true;
4325 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4326 dev_priv
->display_irqs_enabled
= false;
4328 dev_priv
->hotplug
.hpd_storm_threshold
= HPD_STORM_DEFAULT_THRESHOLD
;
4330 dev
->driver
->get_vblank_timestamp
= drm_calc_vbltimestamp_from_scanoutpos
;
4331 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4333 if (IS_CHERRYVIEW(dev_priv
)) {
4334 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4335 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4336 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4337 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4338 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4339 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4340 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4341 } else if (IS_VALLEYVIEW(dev_priv
)) {
4342 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4343 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4344 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4345 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4346 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4347 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4348 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4349 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4350 dev
->driver
->irq_handler
= gen8_irq_handler
;
4351 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4352 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4353 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4354 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4355 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4356 if (IS_GEN9_LP(dev_priv
))
4357 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4358 else if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
) ||
4359 HAS_PCH_CNP(dev_priv
))
4360 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4362 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4363 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4364 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4365 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4366 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4367 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4368 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4369 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4370 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4372 if (IS_GEN2(dev_priv
)) {
4373 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4374 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4375 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4376 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4377 dev
->driver
->enable_vblank
= i8xx_enable_vblank
;
4378 dev
->driver
->disable_vblank
= i8xx_disable_vblank
;
4379 } else if (IS_GEN3(dev_priv
)) {
4380 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4381 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4382 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4383 dev
->driver
->irq_handler
= i915_irq_handler
;
4384 dev
->driver
->enable_vblank
= i8xx_enable_vblank
;
4385 dev
->driver
->disable_vblank
= i8xx_disable_vblank
;
4387 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4388 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4389 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4390 dev
->driver
->irq_handler
= i965_irq_handler
;
4391 dev
->driver
->enable_vblank
= i965_enable_vblank
;
4392 dev
->driver
->disable_vblank
= i965_disable_vblank
;
4394 if (I915_HAS_HOTPLUG(dev_priv
))
4395 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4400 * intel_irq_fini - deinitializes IRQ support
4401 * @i915: i915 device instance
4403 * This function deinitializes all the IRQ support.
4405 void intel_irq_fini(struct drm_i915_private
*i915
)
4409 for (i
= 0; i
< MAX_L3_SLICES
; ++i
)
4410 kfree(i915
->l3_parity
.remap_info
[i
]);
4414 * intel_irq_install - enables the hardware interrupt
4415 * @dev_priv: i915 device instance
4417 * This function enables the hardware interrupt handling, but leaves the hotplug
4418 * handling still disabled. It is called after intel_irq_init().
4420 * In the driver load and resume code we need working interrupts in a few places
4421 * but don't want to deal with the hassle of concurrent probe and hotplug
4422 * workers. Hence the split into this two-stage approach.
4424 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4427 * We enable some interrupt sources in our postinstall hooks, so mark
4428 * interrupts as enabled _before_ actually enabling them to avoid
4429 * special cases in our ordering checks.
4431 dev_priv
->pm
.irqs_enabled
= true;
4433 return drm_irq_install(&dev_priv
->drm
, dev_priv
->drm
.pdev
->irq
);
4437 * intel_irq_uninstall - finilizes all irq handling
4438 * @dev_priv: i915 device instance
4440 * This stops interrupt and hotplug handling and unregisters and frees all
4441 * resources acquired in the init functions.
4443 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4445 drm_irq_uninstall(&dev_priv
->drm
);
4446 intel_hpd_cancel_work(dev_priv
);
4447 dev_priv
->pm
.irqs_enabled
= false;
4451 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4452 * @dev_priv: i915 device instance
4454 * This function is used to disable interrupts at runtime, both in the runtime
4455 * pm and the system suspend/resume code.
4457 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4459 dev_priv
->drm
.driver
->irq_uninstall(&dev_priv
->drm
);
4460 dev_priv
->pm
.irqs_enabled
= false;
4461 synchronize_irq(dev_priv
->drm
.irq
);
4465 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4466 * @dev_priv: i915 device instance
4468 * This function is used to enable interrupts at runtime, both in the runtime
4469 * pm and the system suspend/resume code.
4471 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4473 dev_priv
->pm
.irqs_enabled
= true;
4474 dev_priv
->drm
.driver
->irq_preinstall(&dev_priv
->drm
);
4475 dev_priv
->drm
.driver
->irq_postinstall(&dev_priv
->drm
);