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drm/i915: Remove the list of pinned inactive objects
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 #define MAX_NOPID ((u32)~0)
41
42 /**
43 * Interrupts that are always left unmasked.
44 *
45 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
46 * we leave them always unmasked in IMR and then control enabling them through
47 * PIPESTAT alone.
48 */
49 #define I915_INTERRUPT_ENABLE_FIX \
50 (I915_ASLE_INTERRUPT | \
51 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
52 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
53 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
54 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
55 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
56
57 /** Interrupts that we mask and unmask at runtime. */
58 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
59
60 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
61 PIPE_VBLANK_INTERRUPT_STATUS)
62
63 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
64 PIPE_VBLANK_INTERRUPT_ENABLE)
65
66 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
67 DRM_I915_VBLANK_PIPE_B)
68
69 /* For display hotplug interrupt */
70 static void
71 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
72 {
73 if ((dev_priv->irq_mask & mask) != 0) {
74 dev_priv->irq_mask &= ~mask;
75 I915_WRITE(DEIMR, dev_priv->irq_mask);
76 POSTING_READ(DEIMR);
77 }
78 }
79
80 static inline void
81 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
82 {
83 if ((dev_priv->irq_mask & mask) != mask) {
84 dev_priv->irq_mask |= mask;
85 I915_WRITE(DEIMR, dev_priv->irq_mask);
86 POSTING_READ(DEIMR);
87 }
88 }
89
90 void
91 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
92 {
93 if ((dev_priv->pipestat[pipe] & mask) != mask) {
94 u32 reg = PIPESTAT(pipe);
95
96 dev_priv->pipestat[pipe] |= mask;
97 /* Enable the interrupt, clear any pending status */
98 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
99 POSTING_READ(reg);
100 }
101 }
102
103 void
104 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
105 {
106 if ((dev_priv->pipestat[pipe] & mask) != 0) {
107 u32 reg = PIPESTAT(pipe);
108
109 dev_priv->pipestat[pipe] &= ~mask;
110 I915_WRITE(reg, dev_priv->pipestat[pipe]);
111 POSTING_READ(reg);
112 }
113 }
114
115 /**
116 * intel_enable_asle - enable ASLE interrupt for OpRegion
117 */
118 void intel_enable_asle(struct drm_device *dev)
119 {
120 drm_i915_private_t *dev_priv = dev->dev_private;
121 unsigned long irqflags;
122
123 /* FIXME: opregion/asle for VLV */
124 if (IS_VALLEYVIEW(dev))
125 return;
126
127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
128
129 if (HAS_PCH_SPLIT(dev))
130 ironlake_enable_display_irq(dev_priv, DE_GSE);
131 else {
132 i915_enable_pipestat(dev_priv, 1,
133 PIPE_LEGACY_BLC_EVENT_ENABLE);
134 if (INTEL_INFO(dev)->gen >= 4)
135 i915_enable_pipestat(dev_priv, 0,
136 PIPE_LEGACY_BLC_EVENT_ENABLE);
137 }
138
139 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
140 }
141
142 /**
143 * i915_pipe_enabled - check if a pipe is enabled
144 * @dev: DRM device
145 * @pipe: pipe to check
146 *
147 * Reading certain registers when the pipe is disabled can hang the chip.
148 * Use this routine to make sure the PLL is running and the pipe is active
149 * before reading such registers if unsure.
150 */
151 static int
152 i915_pipe_enabled(struct drm_device *dev, int pipe)
153 {
154 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
155 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
156 }
157
158 /* Called from drm generic code, passed a 'crtc', which
159 * we use as a pipe index
160 */
161 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
162 {
163 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
164 unsigned long high_frame;
165 unsigned long low_frame;
166 u32 high1, high2, low;
167
168 if (!i915_pipe_enabled(dev, pipe)) {
169 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
170 "pipe %c\n", pipe_name(pipe));
171 return 0;
172 }
173
174 high_frame = PIPEFRAME(pipe);
175 low_frame = PIPEFRAMEPIXEL(pipe);
176
177 /*
178 * High & low register fields aren't synchronized, so make sure
179 * we get a low value that's stable across two reads of the high
180 * register.
181 */
182 do {
183 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
184 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
185 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
186 } while (high1 != high2);
187
188 high1 >>= PIPE_FRAME_HIGH_SHIFT;
189 low >>= PIPE_FRAME_LOW_SHIFT;
190 return (high1 << 8) | low;
191 }
192
193 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
194 {
195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
196 int reg = PIPE_FRMCOUNT_GM45(pipe);
197
198 if (!i915_pipe_enabled(dev, pipe)) {
199 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
200 "pipe %c\n", pipe_name(pipe));
201 return 0;
202 }
203
204 return I915_READ(reg);
205 }
206
207 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
208 int *vpos, int *hpos)
209 {
210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
211 u32 vbl = 0, position = 0;
212 int vbl_start, vbl_end, htotal, vtotal;
213 bool in_vbl = true;
214 int ret = 0;
215
216 if (!i915_pipe_enabled(dev, pipe)) {
217 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
218 "pipe %c\n", pipe_name(pipe));
219 return 0;
220 }
221
222 /* Get vtotal. */
223 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
224
225 if (INTEL_INFO(dev)->gen >= 4) {
226 /* No obvious pixelcount register. Only query vertical
227 * scanout position from Display scan line register.
228 */
229 position = I915_READ(PIPEDSL(pipe));
230
231 /* Decode into vertical scanout position. Don't have
232 * horizontal scanout position.
233 */
234 *vpos = position & 0x1fff;
235 *hpos = 0;
236 } else {
237 /* Have access to pixelcount since start of frame.
238 * We can split this into vertical and horizontal
239 * scanout position.
240 */
241 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
242
243 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
244 *vpos = position / htotal;
245 *hpos = position - (*vpos * htotal);
246 }
247
248 /* Query vblank area. */
249 vbl = I915_READ(VBLANK(pipe));
250
251 /* Test position against vblank region. */
252 vbl_start = vbl & 0x1fff;
253 vbl_end = (vbl >> 16) & 0x1fff;
254
255 if ((*vpos < vbl_start) || (*vpos > vbl_end))
256 in_vbl = false;
257
258 /* Inside "upper part" of vblank area? Apply corrective offset: */
259 if (in_vbl && (*vpos >= vbl_start))
260 *vpos = *vpos - vtotal;
261
262 /* Readouts valid? */
263 if (vbl > 0)
264 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
265
266 /* In vblank? */
267 if (in_vbl)
268 ret |= DRM_SCANOUTPOS_INVBL;
269
270 return ret;
271 }
272
273 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
274 int *max_error,
275 struct timeval *vblank_time,
276 unsigned flags)
277 {
278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct drm_crtc *crtc;
280
281 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
282 DRM_ERROR("Invalid crtc %d\n", pipe);
283 return -EINVAL;
284 }
285
286 /* Get drm_crtc to timestamp: */
287 crtc = intel_get_crtc_for_pipe(dev, pipe);
288 if (crtc == NULL) {
289 DRM_ERROR("Invalid crtc %d\n", pipe);
290 return -EINVAL;
291 }
292
293 if (!crtc->enabled) {
294 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
295 return -EBUSY;
296 }
297
298 /* Helper routine in DRM core does all the work: */
299 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
300 vblank_time, flags,
301 crtc);
302 }
303
304 /*
305 * Handle hotplug events outside the interrupt handler proper.
306 */
307 static void i915_hotplug_work_func(struct work_struct *work)
308 {
309 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
310 hotplug_work);
311 struct drm_device *dev = dev_priv->dev;
312 struct drm_mode_config *mode_config = &dev->mode_config;
313 struct intel_encoder *encoder;
314
315 mutex_lock(&mode_config->mutex);
316 DRM_DEBUG_KMS("running encoder hotplug functions\n");
317
318 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
319 if (encoder->hot_plug)
320 encoder->hot_plug(encoder);
321
322 mutex_unlock(&mode_config->mutex);
323
324 /* Just fire off a uevent and let userspace tell us what to do */
325 drm_helper_hpd_irq_event(dev);
326 }
327
328 static void i915_handle_rps_change(struct drm_device *dev)
329 {
330 drm_i915_private_t *dev_priv = dev->dev_private;
331 u32 busy_up, busy_down, max_avg, min_avg;
332 u8 new_delay = dev_priv->cur_delay;
333
334 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
335 busy_up = I915_READ(RCPREVBSYTUPAVG);
336 busy_down = I915_READ(RCPREVBSYTDNAVG);
337 max_avg = I915_READ(RCBMAXAVG);
338 min_avg = I915_READ(RCBMINAVG);
339
340 /* Handle RCS change request from hw */
341 if (busy_up > max_avg) {
342 if (dev_priv->cur_delay != dev_priv->max_delay)
343 new_delay = dev_priv->cur_delay - 1;
344 if (new_delay < dev_priv->max_delay)
345 new_delay = dev_priv->max_delay;
346 } else if (busy_down < min_avg) {
347 if (dev_priv->cur_delay != dev_priv->min_delay)
348 new_delay = dev_priv->cur_delay + 1;
349 if (new_delay > dev_priv->min_delay)
350 new_delay = dev_priv->min_delay;
351 }
352
353 if (ironlake_set_drps(dev, new_delay))
354 dev_priv->cur_delay = new_delay;
355
356 return;
357 }
358
359 static void notify_ring(struct drm_device *dev,
360 struct intel_ring_buffer *ring)
361 {
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 u32 seqno;
364
365 if (ring->obj == NULL)
366 return;
367
368 seqno = ring->get_seqno(ring);
369 trace_i915_gem_request_complete(ring, seqno);
370
371 ring->irq_seqno = seqno;
372 wake_up_all(&ring->irq_queue);
373 if (i915_enable_hangcheck) {
374 dev_priv->hangcheck_count = 0;
375 mod_timer(&dev_priv->hangcheck_timer,
376 jiffies +
377 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
378 }
379 }
380
381 static void gen6_pm_rps_work(struct work_struct *work)
382 {
383 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
384 rps_work);
385 u8 new_delay = dev_priv->cur_delay;
386 u32 pm_iir, pm_imr;
387
388 spin_lock_irq(&dev_priv->rps_lock);
389 pm_iir = dev_priv->pm_iir;
390 dev_priv->pm_iir = 0;
391 pm_imr = I915_READ(GEN6_PMIMR);
392 I915_WRITE(GEN6_PMIMR, 0);
393 spin_unlock_irq(&dev_priv->rps_lock);
394
395 if (!pm_iir)
396 return;
397
398 mutex_lock(&dev_priv->dev->struct_mutex);
399 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
400 if (dev_priv->cur_delay != dev_priv->max_delay)
401 new_delay = dev_priv->cur_delay + 1;
402 if (new_delay > dev_priv->max_delay)
403 new_delay = dev_priv->max_delay;
404 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
405 gen6_gt_force_wake_get(dev_priv);
406 if (dev_priv->cur_delay != dev_priv->min_delay)
407 new_delay = dev_priv->cur_delay - 1;
408 if (new_delay < dev_priv->min_delay) {
409 new_delay = dev_priv->min_delay;
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
412 ((new_delay << 16) & 0x3f0000));
413 } else {
414 /* Make sure we continue to get down interrupts
415 * until we hit the minimum frequency */
416 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
417 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
418 }
419 gen6_gt_force_wake_put(dev_priv);
420 }
421
422 gen6_set_rps(dev_priv->dev, new_delay);
423 dev_priv->cur_delay = new_delay;
424
425 /*
426 * rps_lock not held here because clearing is non-destructive. There is
427 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
428 * by holding struct_mutex for the duration of the write.
429 */
430 mutex_unlock(&dev_priv->dev->struct_mutex);
431 }
432
433 static void snb_gt_irq_handler(struct drm_device *dev,
434 struct drm_i915_private *dev_priv,
435 u32 gt_iir)
436 {
437
438 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
439 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
440 notify_ring(dev, &dev_priv->ring[RCS]);
441 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
442 notify_ring(dev, &dev_priv->ring[VCS]);
443 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
444 notify_ring(dev, &dev_priv->ring[BCS]);
445
446 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
447 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
448 GT_RENDER_CS_ERROR_INTERRUPT)) {
449 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
450 i915_handle_error(dev, false);
451 }
452 }
453
454 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
455 u32 pm_iir)
456 {
457 unsigned long flags;
458
459 /*
460 * IIR bits should never already be set because IMR should
461 * prevent an interrupt from being shown in IIR. The warning
462 * displays a case where we've unsafely cleared
463 * dev_priv->pm_iir. Although missing an interrupt of the same
464 * type is not a problem, it displays a problem in the logic.
465 *
466 * The mask bit in IMR is cleared by rps_work.
467 */
468
469 spin_lock_irqsave(&dev_priv->rps_lock, flags);
470 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
471 dev_priv->pm_iir |= pm_iir;
472 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
473 POSTING_READ(GEN6_PMIMR);
474 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
475
476 queue_work(dev_priv->wq, &dev_priv->rps_work);
477 }
478
479 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
480 {
481 struct drm_device *dev = (struct drm_device *) arg;
482 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
483 u32 iir, gt_iir, pm_iir;
484 irqreturn_t ret = IRQ_NONE;
485 unsigned long irqflags;
486 int pipe;
487 u32 pipe_stats[I915_MAX_PIPES];
488 u32 vblank_status;
489 int vblank = 0;
490 bool blc_event;
491
492 atomic_inc(&dev_priv->irq_received);
493
494 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
495 PIPE_VBLANK_INTERRUPT_STATUS;
496
497 while (true) {
498 iir = I915_READ(VLV_IIR);
499 gt_iir = I915_READ(GTIIR);
500 pm_iir = I915_READ(GEN6_PMIIR);
501
502 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
503 goto out;
504
505 ret = IRQ_HANDLED;
506
507 snb_gt_irq_handler(dev, dev_priv, gt_iir);
508
509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
510 for_each_pipe(pipe) {
511 int reg = PIPESTAT(pipe);
512 pipe_stats[pipe] = I915_READ(reg);
513
514 /*
515 * Clear the PIPE*STAT regs before the IIR
516 */
517 if (pipe_stats[pipe] & 0x8000ffff) {
518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
519 DRM_DEBUG_DRIVER("pipe %c underrun\n",
520 pipe_name(pipe));
521 I915_WRITE(reg, pipe_stats[pipe]);
522 }
523 }
524 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
525
526 /* Consume port. Then clear IIR or we'll miss events */
527 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
528 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
529
530 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
531 hotplug_status);
532 if (hotplug_status & dev_priv->hotplug_supported_mask)
533 queue_work(dev_priv->wq,
534 &dev_priv->hotplug_work);
535
536 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
537 I915_READ(PORT_HOTPLUG_STAT);
538 }
539
540
541 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
542 drm_handle_vblank(dev, 0);
543 vblank++;
544 if (!dev_priv->flip_pending_is_done) {
545 intel_finish_page_flip(dev, 0);
546 }
547 }
548
549 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
550 drm_handle_vblank(dev, 1);
551 vblank++;
552 if (!dev_priv->flip_pending_is_done) {
553 intel_finish_page_flip(dev, 0);
554 }
555 }
556
557 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
558 blc_event = true;
559
560 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
561 gen6_queue_rps_work(dev_priv, pm_iir);
562
563 I915_WRITE(GTIIR, gt_iir);
564 I915_WRITE(GEN6_PMIIR, pm_iir);
565 I915_WRITE(VLV_IIR, iir);
566 }
567
568 out:
569 return ret;
570 }
571
572 static void pch_irq_handler(struct drm_device *dev)
573 {
574 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
575 u32 pch_iir;
576 int pipe;
577
578 pch_iir = I915_READ(SDEIIR);
579
580 if (pch_iir & SDE_AUDIO_POWER_MASK)
581 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
582 (pch_iir & SDE_AUDIO_POWER_MASK) >>
583 SDE_AUDIO_POWER_SHIFT);
584
585 if (pch_iir & SDE_GMBUS)
586 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
587
588 if (pch_iir & SDE_AUDIO_HDCP_MASK)
589 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
590
591 if (pch_iir & SDE_AUDIO_TRANS_MASK)
592 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
593
594 if (pch_iir & SDE_POISON)
595 DRM_ERROR("PCH poison interrupt\n");
596
597 if (pch_iir & SDE_FDI_MASK)
598 for_each_pipe(pipe)
599 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
600 pipe_name(pipe),
601 I915_READ(FDI_RX_IIR(pipe)));
602
603 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
604 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
605
606 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
607 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
608
609 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
610 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
611 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
612 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
613 }
614
615 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
616 {
617 struct drm_device *dev = (struct drm_device *) arg;
618 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
619 int ret = IRQ_NONE;
620 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
621 struct drm_i915_master_private *master_priv;
622
623 atomic_inc(&dev_priv->irq_received);
624
625 /* disable master interrupt before clearing iir */
626 de_ier = I915_READ(DEIER);
627 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
628 POSTING_READ(DEIER);
629
630 de_iir = I915_READ(DEIIR);
631 gt_iir = I915_READ(GTIIR);
632 pch_iir = I915_READ(SDEIIR);
633 pm_iir = I915_READ(GEN6_PMIIR);
634
635 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
636 goto done;
637
638 ret = IRQ_HANDLED;
639
640 if (dev->primary->master) {
641 master_priv = dev->primary->master->driver_priv;
642 if (master_priv->sarea_priv)
643 master_priv->sarea_priv->last_dispatch =
644 READ_BREADCRUMB(dev_priv);
645 }
646
647 snb_gt_irq_handler(dev, dev_priv, gt_iir);
648
649 if (de_iir & DE_GSE_IVB)
650 intel_opregion_gse_intr(dev);
651
652 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
653 intel_prepare_page_flip(dev, 0);
654 intel_finish_page_flip_plane(dev, 0);
655 }
656
657 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
658 intel_prepare_page_flip(dev, 1);
659 intel_finish_page_flip_plane(dev, 1);
660 }
661
662 if (de_iir & DE_PIPEA_VBLANK_IVB)
663 drm_handle_vblank(dev, 0);
664
665 if (de_iir & DE_PIPEB_VBLANK_IVB)
666 drm_handle_vblank(dev, 1);
667
668 /* check event from PCH */
669 if (de_iir & DE_PCH_EVENT_IVB) {
670 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
671 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
672 pch_irq_handler(dev);
673 }
674
675 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
676 gen6_queue_rps_work(dev_priv, pm_iir);
677
678 /* should clear PCH hotplug event before clear CPU irq */
679 I915_WRITE(SDEIIR, pch_iir);
680 I915_WRITE(GTIIR, gt_iir);
681 I915_WRITE(DEIIR, de_iir);
682 I915_WRITE(GEN6_PMIIR, pm_iir);
683
684 done:
685 I915_WRITE(DEIER, de_ier);
686 POSTING_READ(DEIER);
687
688 return ret;
689 }
690
691 static void ilk_gt_irq_handler(struct drm_device *dev,
692 struct drm_i915_private *dev_priv,
693 u32 gt_iir)
694 {
695 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
696 notify_ring(dev, &dev_priv->ring[RCS]);
697 if (gt_iir & GT_BSD_USER_INTERRUPT)
698 notify_ring(dev, &dev_priv->ring[VCS]);
699 }
700
701 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
702 {
703 struct drm_device *dev = (struct drm_device *) arg;
704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
705 int ret = IRQ_NONE;
706 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
707 u32 hotplug_mask;
708 struct drm_i915_master_private *master_priv;
709
710 atomic_inc(&dev_priv->irq_received);
711
712 /* disable master interrupt before clearing iir */
713 de_ier = I915_READ(DEIER);
714 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
715 POSTING_READ(DEIER);
716
717 de_iir = I915_READ(DEIIR);
718 gt_iir = I915_READ(GTIIR);
719 pch_iir = I915_READ(SDEIIR);
720 pm_iir = I915_READ(GEN6_PMIIR);
721
722 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
723 (!IS_GEN6(dev) || pm_iir == 0))
724 goto done;
725
726 if (HAS_PCH_CPT(dev))
727 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
728 else
729 hotplug_mask = SDE_HOTPLUG_MASK;
730
731 ret = IRQ_HANDLED;
732
733 if (dev->primary->master) {
734 master_priv = dev->primary->master->driver_priv;
735 if (master_priv->sarea_priv)
736 master_priv->sarea_priv->last_dispatch =
737 READ_BREADCRUMB(dev_priv);
738 }
739
740 if (IS_GEN5(dev))
741 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
742 else
743 snb_gt_irq_handler(dev, dev_priv, gt_iir);
744
745 if (de_iir & DE_GSE)
746 intel_opregion_gse_intr(dev);
747
748 if (de_iir & DE_PLANEA_FLIP_DONE) {
749 intel_prepare_page_flip(dev, 0);
750 intel_finish_page_flip_plane(dev, 0);
751 }
752
753 if (de_iir & DE_PLANEB_FLIP_DONE) {
754 intel_prepare_page_flip(dev, 1);
755 intel_finish_page_flip_plane(dev, 1);
756 }
757
758 if (de_iir & DE_PIPEA_VBLANK)
759 drm_handle_vblank(dev, 0);
760
761 if (de_iir & DE_PIPEB_VBLANK)
762 drm_handle_vblank(dev, 1);
763
764 /* check event from PCH */
765 if (de_iir & DE_PCH_EVENT) {
766 if (pch_iir & hotplug_mask)
767 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
768 pch_irq_handler(dev);
769 }
770
771 if (de_iir & DE_PCU_EVENT) {
772 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
773 i915_handle_rps_change(dev);
774 }
775
776 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
777 gen6_queue_rps_work(dev_priv, pm_iir);
778
779 /* should clear PCH hotplug event before clear CPU irq */
780 I915_WRITE(SDEIIR, pch_iir);
781 I915_WRITE(GTIIR, gt_iir);
782 I915_WRITE(DEIIR, de_iir);
783 I915_WRITE(GEN6_PMIIR, pm_iir);
784
785 done:
786 I915_WRITE(DEIER, de_ier);
787 POSTING_READ(DEIER);
788
789 return ret;
790 }
791
792 /**
793 * i915_error_work_func - do process context error handling work
794 * @work: work struct
795 *
796 * Fire an error uevent so userspace can see that a hang or error
797 * was detected.
798 */
799 static void i915_error_work_func(struct work_struct *work)
800 {
801 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
802 error_work);
803 struct drm_device *dev = dev_priv->dev;
804 char *error_event[] = { "ERROR=1", NULL };
805 char *reset_event[] = { "RESET=1", NULL };
806 char *reset_done_event[] = { "ERROR=0", NULL };
807
808 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
809
810 if (atomic_read(&dev_priv->mm.wedged)) {
811 DRM_DEBUG_DRIVER("resetting chip\n");
812 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
813 if (!i915_reset(dev, GRDOM_RENDER)) {
814 atomic_set(&dev_priv->mm.wedged, 0);
815 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
816 }
817 complete_all(&dev_priv->error_completion);
818 }
819 }
820
821 #ifdef CONFIG_DEBUG_FS
822 static struct drm_i915_error_object *
823 i915_error_object_create(struct drm_i915_private *dev_priv,
824 struct drm_i915_gem_object *src)
825 {
826 struct drm_i915_error_object *dst;
827 int page, page_count;
828 u32 reloc_offset;
829
830 if (src == NULL || src->pages == NULL)
831 return NULL;
832
833 page_count = src->base.size / PAGE_SIZE;
834
835 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
836 if (dst == NULL)
837 return NULL;
838
839 reloc_offset = src->gtt_offset;
840 for (page = 0; page < page_count; page++) {
841 unsigned long flags;
842 void *d;
843
844 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
845 if (d == NULL)
846 goto unwind;
847
848 local_irq_save(flags);
849 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
850 src->has_global_gtt_mapping) {
851 void __iomem *s;
852
853 /* Simply ignore tiling or any overlapping fence.
854 * It's part of the error state, and this hopefully
855 * captures what the GPU read.
856 */
857
858 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
859 reloc_offset);
860 memcpy_fromio(d, s, PAGE_SIZE);
861 io_mapping_unmap_atomic(s);
862 } else {
863 void *s;
864
865 drm_clflush_pages(&src->pages[page], 1);
866
867 s = kmap_atomic(src->pages[page]);
868 memcpy(d, s, PAGE_SIZE);
869 kunmap_atomic(s);
870
871 drm_clflush_pages(&src->pages[page], 1);
872 }
873 local_irq_restore(flags);
874
875 dst->pages[page] = d;
876
877 reloc_offset += PAGE_SIZE;
878 }
879 dst->page_count = page_count;
880 dst->gtt_offset = src->gtt_offset;
881
882 return dst;
883
884 unwind:
885 while (page--)
886 kfree(dst->pages[page]);
887 kfree(dst);
888 return NULL;
889 }
890
891 static void
892 i915_error_object_free(struct drm_i915_error_object *obj)
893 {
894 int page;
895
896 if (obj == NULL)
897 return;
898
899 for (page = 0; page < obj->page_count; page++)
900 kfree(obj->pages[page]);
901
902 kfree(obj);
903 }
904
905 static void
906 i915_error_state_free(struct drm_device *dev,
907 struct drm_i915_error_state *error)
908 {
909 int i;
910
911 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
912 i915_error_object_free(error->ring[i].batchbuffer);
913 i915_error_object_free(error->ring[i].ringbuffer);
914 kfree(error->ring[i].requests);
915 }
916
917 kfree(error->active_bo);
918 kfree(error->overlay);
919 kfree(error);
920 }
921 static void capture_bo(struct drm_i915_error_buffer *err,
922 struct drm_i915_gem_object *obj)
923 {
924 err->size = obj->base.size;
925 err->name = obj->base.name;
926 err->seqno = obj->last_rendering_seqno;
927 err->gtt_offset = obj->gtt_offset;
928 err->read_domains = obj->base.read_domains;
929 err->write_domain = obj->base.write_domain;
930 err->fence_reg = obj->fence_reg;
931 err->pinned = 0;
932 if (obj->pin_count > 0)
933 err->pinned = 1;
934 if (obj->user_pin_count > 0)
935 err->pinned = -1;
936 err->tiling = obj->tiling_mode;
937 err->dirty = obj->dirty;
938 err->purgeable = obj->madv != I915_MADV_WILLNEED;
939 err->ring = obj->ring ? obj->ring->id : -1;
940 err->cache_level = obj->cache_level;
941 }
942
943 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
944 int count, struct list_head *head)
945 {
946 struct drm_i915_gem_object *obj;
947 int i = 0;
948
949 list_for_each_entry(obj, head, mm_list) {
950 capture_bo(err++, obj);
951 if (++i == count)
952 break;
953 }
954
955 return i;
956 }
957
958 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
959 int count, struct list_head *head)
960 {
961 struct drm_i915_gem_object *obj;
962 int i = 0;
963
964 list_for_each_entry(obj, head, gtt_list) {
965 if (obj->pin_count == 0)
966 continue;
967
968 capture_bo(err++, obj);
969 if (++i == count)
970 break;
971 }
972
973 return i;
974 }
975
976 static void i915_gem_record_fences(struct drm_device *dev,
977 struct drm_i915_error_state *error)
978 {
979 struct drm_i915_private *dev_priv = dev->dev_private;
980 int i;
981
982 /* Fences */
983 switch (INTEL_INFO(dev)->gen) {
984 case 7:
985 case 6:
986 for (i = 0; i < 16; i++)
987 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
988 break;
989 case 5:
990 case 4:
991 for (i = 0; i < 16; i++)
992 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
993 break;
994 case 3:
995 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
996 for (i = 0; i < 8; i++)
997 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
998 case 2:
999 for (i = 0; i < 8; i++)
1000 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1001 break;
1002
1003 }
1004 }
1005
1006 static struct drm_i915_error_object *
1007 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1008 struct intel_ring_buffer *ring)
1009 {
1010 struct drm_i915_gem_object *obj;
1011 u32 seqno;
1012
1013 if (!ring->get_seqno)
1014 return NULL;
1015
1016 seqno = ring->get_seqno(ring);
1017 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1018 if (obj->ring != ring)
1019 continue;
1020
1021 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
1022 continue;
1023
1024 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1025 continue;
1026
1027 /* We need to copy these to an anonymous buffer as the simplest
1028 * method to avoid being overwritten by userspace.
1029 */
1030 return i915_error_object_create(dev_priv, obj);
1031 }
1032
1033 return NULL;
1034 }
1035
1036 static void i915_record_ring_state(struct drm_device *dev,
1037 struct drm_i915_error_state *error,
1038 struct intel_ring_buffer *ring)
1039 {
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041
1042 if (INTEL_INFO(dev)->gen >= 6) {
1043 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1044 error->semaphore_mboxes[ring->id][0]
1045 = I915_READ(RING_SYNC_0(ring->mmio_base));
1046 error->semaphore_mboxes[ring->id][1]
1047 = I915_READ(RING_SYNC_1(ring->mmio_base));
1048 }
1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1052 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1053 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1054 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1055 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1056 if (ring->id == RCS) {
1057 error->instdone1 = I915_READ(INSTDONE1);
1058 error->bbaddr = I915_READ64(BB_ADDR);
1059 }
1060 } else {
1061 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1062 error->ipeir[ring->id] = I915_READ(IPEIR);
1063 error->ipehr[ring->id] = I915_READ(IPEHR);
1064 error->instdone[ring->id] = I915_READ(INSTDONE);
1065 }
1066
1067 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1068 error->seqno[ring->id] = ring->get_seqno(ring);
1069 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1070 error->head[ring->id] = I915_READ_HEAD(ring);
1071 error->tail[ring->id] = I915_READ_TAIL(ring);
1072
1073 error->cpu_ring_head[ring->id] = ring->head;
1074 error->cpu_ring_tail[ring->id] = ring->tail;
1075 }
1076
1077 static void i915_gem_record_rings(struct drm_device *dev,
1078 struct drm_i915_error_state *error)
1079 {
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct drm_i915_gem_request *request;
1082 int i, count;
1083
1084 for (i = 0; i < I915_NUM_RINGS; i++) {
1085 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1086
1087 if (ring->obj == NULL)
1088 continue;
1089
1090 i915_record_ring_state(dev, error, ring);
1091
1092 error->ring[i].batchbuffer =
1093 i915_error_first_batchbuffer(dev_priv, ring);
1094
1095 error->ring[i].ringbuffer =
1096 i915_error_object_create(dev_priv, ring->obj);
1097
1098 count = 0;
1099 list_for_each_entry(request, &ring->request_list, list)
1100 count++;
1101
1102 error->ring[i].num_requests = count;
1103 error->ring[i].requests =
1104 kmalloc(count*sizeof(struct drm_i915_error_request),
1105 GFP_ATOMIC);
1106 if (error->ring[i].requests == NULL) {
1107 error->ring[i].num_requests = 0;
1108 continue;
1109 }
1110
1111 count = 0;
1112 list_for_each_entry(request, &ring->request_list, list) {
1113 struct drm_i915_error_request *erq;
1114
1115 erq = &error->ring[i].requests[count++];
1116 erq->seqno = request->seqno;
1117 erq->jiffies = request->emitted_jiffies;
1118 erq->tail = request->tail;
1119 }
1120 }
1121 }
1122
1123 /**
1124 * i915_capture_error_state - capture an error record for later analysis
1125 * @dev: drm device
1126 *
1127 * Should be called when an error is detected (either a hang or an error
1128 * interrupt) to capture error state from the time of the error. Fills
1129 * out a structure which becomes available in debugfs for user level tools
1130 * to pick up.
1131 */
1132 static void i915_capture_error_state(struct drm_device *dev)
1133 {
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 struct drm_i915_gem_object *obj;
1136 struct drm_i915_error_state *error;
1137 unsigned long flags;
1138 int i, pipe;
1139
1140 spin_lock_irqsave(&dev_priv->error_lock, flags);
1141 error = dev_priv->first_error;
1142 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1143 if (error)
1144 return;
1145
1146 /* Account for pipe specific data like PIPE*STAT */
1147 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1148 if (!error) {
1149 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1150 return;
1151 }
1152
1153 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1154 dev->primary->index);
1155
1156 error->eir = I915_READ(EIR);
1157 error->pgtbl_er = I915_READ(PGTBL_ER);
1158 for_each_pipe(pipe)
1159 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1160
1161 if (INTEL_INFO(dev)->gen >= 6) {
1162 error->error = I915_READ(ERROR_GEN6);
1163 error->done_reg = I915_READ(DONE_REG);
1164 }
1165
1166 i915_gem_record_fences(dev, error);
1167 i915_gem_record_rings(dev, error);
1168
1169 /* Record buffers on the active and pinned lists. */
1170 error->active_bo = NULL;
1171 error->pinned_bo = NULL;
1172
1173 i = 0;
1174 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1175 i++;
1176 error->active_bo_count = i;
1177 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1178 if (obj->pin_count)
1179 i++;
1180 error->pinned_bo_count = i - error->active_bo_count;
1181
1182 error->active_bo = NULL;
1183 error->pinned_bo = NULL;
1184 if (i) {
1185 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1186 GFP_ATOMIC);
1187 if (error->active_bo)
1188 error->pinned_bo =
1189 error->active_bo + error->active_bo_count;
1190 }
1191
1192 if (error->active_bo)
1193 error->active_bo_count =
1194 capture_active_bo(error->active_bo,
1195 error->active_bo_count,
1196 &dev_priv->mm.active_list);
1197
1198 if (error->pinned_bo)
1199 error->pinned_bo_count =
1200 capture_pinned_bo(error->pinned_bo,
1201 error->pinned_bo_count,
1202 &dev_priv->mm.gtt_list);
1203
1204 do_gettimeofday(&error->time);
1205
1206 error->overlay = intel_overlay_capture_error_state(dev);
1207 error->display = intel_display_capture_error_state(dev);
1208
1209 spin_lock_irqsave(&dev_priv->error_lock, flags);
1210 if (dev_priv->first_error == NULL) {
1211 dev_priv->first_error = error;
1212 error = NULL;
1213 }
1214 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1215
1216 if (error)
1217 i915_error_state_free(dev, error);
1218 }
1219
1220 void i915_destroy_error_state(struct drm_device *dev)
1221 {
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct drm_i915_error_state *error;
1224 unsigned long flags;
1225
1226 spin_lock_irqsave(&dev_priv->error_lock, flags);
1227 error = dev_priv->first_error;
1228 dev_priv->first_error = NULL;
1229 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1230
1231 if (error)
1232 i915_error_state_free(dev, error);
1233 }
1234 #else
1235 #define i915_capture_error_state(x)
1236 #endif
1237
1238 static void i915_report_and_clear_eir(struct drm_device *dev)
1239 {
1240 struct drm_i915_private *dev_priv = dev->dev_private;
1241 u32 eir = I915_READ(EIR);
1242 int pipe;
1243
1244 if (!eir)
1245 return;
1246
1247 pr_err("render error detected, EIR: 0x%08x\n", eir);
1248
1249 if (IS_G4X(dev)) {
1250 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1251 u32 ipeir = I915_READ(IPEIR_I965);
1252
1253 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1254 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1255 pr_err(" INSTDONE: 0x%08x\n",
1256 I915_READ(INSTDONE_I965));
1257 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1258 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1259 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1260 I915_WRITE(IPEIR_I965, ipeir);
1261 POSTING_READ(IPEIR_I965);
1262 }
1263 if (eir & GM45_ERROR_PAGE_TABLE) {
1264 u32 pgtbl_err = I915_READ(PGTBL_ER);
1265 pr_err("page table error\n");
1266 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1267 I915_WRITE(PGTBL_ER, pgtbl_err);
1268 POSTING_READ(PGTBL_ER);
1269 }
1270 }
1271
1272 if (!IS_GEN2(dev)) {
1273 if (eir & I915_ERROR_PAGE_TABLE) {
1274 u32 pgtbl_err = I915_READ(PGTBL_ER);
1275 pr_err("page table error\n");
1276 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1277 I915_WRITE(PGTBL_ER, pgtbl_err);
1278 POSTING_READ(PGTBL_ER);
1279 }
1280 }
1281
1282 if (eir & I915_ERROR_MEMORY_REFRESH) {
1283 pr_err("memory refresh error:\n");
1284 for_each_pipe(pipe)
1285 pr_err("pipe %c stat: 0x%08x\n",
1286 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1287 /* pipestat has already been acked */
1288 }
1289 if (eir & I915_ERROR_INSTRUCTION) {
1290 pr_err("instruction error\n");
1291 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1292 if (INTEL_INFO(dev)->gen < 4) {
1293 u32 ipeir = I915_READ(IPEIR);
1294
1295 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1296 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1297 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1298 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1299 I915_WRITE(IPEIR, ipeir);
1300 POSTING_READ(IPEIR);
1301 } else {
1302 u32 ipeir = I915_READ(IPEIR_I965);
1303
1304 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1305 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1306 pr_err(" INSTDONE: 0x%08x\n",
1307 I915_READ(INSTDONE_I965));
1308 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1309 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1310 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1311 I915_WRITE(IPEIR_I965, ipeir);
1312 POSTING_READ(IPEIR_I965);
1313 }
1314 }
1315
1316 I915_WRITE(EIR, eir);
1317 POSTING_READ(EIR);
1318 eir = I915_READ(EIR);
1319 if (eir) {
1320 /*
1321 * some errors might have become stuck,
1322 * mask them.
1323 */
1324 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1325 I915_WRITE(EMR, I915_READ(EMR) | eir);
1326 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1327 }
1328 }
1329
1330 /**
1331 * i915_handle_error - handle an error interrupt
1332 * @dev: drm device
1333 *
1334 * Do some basic checking of regsiter state at error interrupt time and
1335 * dump it to the syslog. Also call i915_capture_error_state() to make
1336 * sure we get a record and make it available in debugfs. Fire a uevent
1337 * so userspace knows something bad happened (should trigger collection
1338 * of a ring dump etc.).
1339 */
1340 void i915_handle_error(struct drm_device *dev, bool wedged)
1341 {
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343
1344 i915_capture_error_state(dev);
1345 i915_report_and_clear_eir(dev);
1346
1347 if (wedged) {
1348 INIT_COMPLETION(dev_priv->error_completion);
1349 atomic_set(&dev_priv->mm.wedged, 1);
1350
1351 /*
1352 * Wakeup waiting processes so they don't hang
1353 */
1354 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1355 if (HAS_BSD(dev))
1356 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1357 if (HAS_BLT(dev))
1358 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1359 }
1360
1361 queue_work(dev_priv->wq, &dev_priv->error_work);
1362 }
1363
1364 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1365 {
1366 drm_i915_private_t *dev_priv = dev->dev_private;
1367 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1369 struct drm_i915_gem_object *obj;
1370 struct intel_unpin_work *work;
1371 unsigned long flags;
1372 bool stall_detected;
1373
1374 /* Ignore early vblank irqs */
1375 if (intel_crtc == NULL)
1376 return;
1377
1378 spin_lock_irqsave(&dev->event_lock, flags);
1379 work = intel_crtc->unpin_work;
1380
1381 if (work == NULL || work->pending || !work->enable_stall_check) {
1382 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1383 spin_unlock_irqrestore(&dev->event_lock, flags);
1384 return;
1385 }
1386
1387 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1388 obj = work->pending_flip_obj;
1389 if (INTEL_INFO(dev)->gen >= 4) {
1390 int dspsurf = DSPSURF(intel_crtc->plane);
1391 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1392 obj->gtt_offset;
1393 } else {
1394 int dspaddr = DSPADDR(intel_crtc->plane);
1395 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1396 crtc->y * crtc->fb->pitches[0] +
1397 crtc->x * crtc->fb->bits_per_pixel/8);
1398 }
1399
1400 spin_unlock_irqrestore(&dev->event_lock, flags);
1401
1402 if (stall_detected) {
1403 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1404 intel_prepare_page_flip(dev, intel_crtc->plane);
1405 }
1406 }
1407
1408 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1409 {
1410 struct drm_device *dev = (struct drm_device *) arg;
1411 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1412 struct drm_i915_master_private *master_priv;
1413 u32 iir, new_iir;
1414 u32 pipe_stats[I915_MAX_PIPES];
1415 u32 vblank_status;
1416 int vblank = 0;
1417 unsigned long irqflags;
1418 int irq_received;
1419 int ret = IRQ_NONE, pipe;
1420 bool blc_event = false;
1421
1422 atomic_inc(&dev_priv->irq_received);
1423
1424 iir = I915_READ(IIR);
1425
1426 if (INTEL_INFO(dev)->gen >= 4)
1427 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1428 else
1429 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1430
1431 for (;;) {
1432 irq_received = iir != 0;
1433
1434 /* Can't rely on pipestat interrupt bit in iir as it might
1435 * have been cleared after the pipestat interrupt was received.
1436 * It doesn't set the bit in iir again, but it still produces
1437 * interrupts (for non-MSI).
1438 */
1439 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1440 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1441 i915_handle_error(dev, false);
1442
1443 for_each_pipe(pipe) {
1444 int reg = PIPESTAT(pipe);
1445 pipe_stats[pipe] = I915_READ(reg);
1446
1447 /*
1448 * Clear the PIPE*STAT regs before the IIR
1449 */
1450 if (pipe_stats[pipe] & 0x8000ffff) {
1451 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1452 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1453 pipe_name(pipe));
1454 I915_WRITE(reg, pipe_stats[pipe]);
1455 irq_received = 1;
1456 }
1457 }
1458 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1459
1460 if (!irq_received)
1461 break;
1462
1463 ret = IRQ_HANDLED;
1464
1465 /* Consume port. Then clear IIR or we'll miss events */
1466 if ((I915_HAS_HOTPLUG(dev)) &&
1467 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1468 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1469
1470 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1471 hotplug_status);
1472 if (hotplug_status & dev_priv->hotplug_supported_mask)
1473 queue_work(dev_priv->wq,
1474 &dev_priv->hotplug_work);
1475
1476 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1477 I915_READ(PORT_HOTPLUG_STAT);
1478 }
1479
1480 I915_WRITE(IIR, iir);
1481 new_iir = I915_READ(IIR); /* Flush posted writes */
1482
1483 if (dev->primary->master) {
1484 master_priv = dev->primary->master->driver_priv;
1485 if (master_priv->sarea_priv)
1486 master_priv->sarea_priv->last_dispatch =
1487 READ_BREADCRUMB(dev_priv);
1488 }
1489
1490 if (iir & I915_USER_INTERRUPT)
1491 notify_ring(dev, &dev_priv->ring[RCS]);
1492 if (iir & I915_BSD_USER_INTERRUPT)
1493 notify_ring(dev, &dev_priv->ring[VCS]);
1494
1495 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1496 intel_prepare_page_flip(dev, 0);
1497 if (dev_priv->flip_pending_is_done)
1498 intel_finish_page_flip_plane(dev, 0);
1499 }
1500
1501 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1502 intel_prepare_page_flip(dev, 1);
1503 if (dev_priv->flip_pending_is_done)
1504 intel_finish_page_flip_plane(dev, 1);
1505 }
1506
1507 for_each_pipe(pipe) {
1508 if (pipe_stats[pipe] & vblank_status &&
1509 drm_handle_vblank(dev, pipe)) {
1510 vblank++;
1511 if (!dev_priv->flip_pending_is_done) {
1512 i915_pageflip_stall_check(dev, pipe);
1513 intel_finish_page_flip(dev, pipe);
1514 }
1515 }
1516
1517 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1518 blc_event = true;
1519 }
1520
1521
1522 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1523 intel_opregion_asle_intr(dev);
1524
1525 /* With MSI, interrupts are only generated when iir
1526 * transitions from zero to nonzero. If another bit got
1527 * set while we were handling the existing iir bits, then
1528 * we would never get another interrupt.
1529 *
1530 * This is fine on non-MSI as well, as if we hit this path
1531 * we avoid exiting the interrupt handler only to generate
1532 * another one.
1533 *
1534 * Note that for MSI this could cause a stray interrupt report
1535 * if an interrupt landed in the time between writing IIR and
1536 * the posting read. This should be rare enough to never
1537 * trigger the 99% of 100,000 interrupts test for disabling
1538 * stray interrupts.
1539 */
1540 iir = new_iir;
1541 }
1542
1543 return ret;
1544 }
1545
1546 static int i915_emit_irq(struct drm_device * dev)
1547 {
1548 drm_i915_private_t *dev_priv = dev->dev_private;
1549 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1550
1551 i915_kernel_lost_context(dev);
1552
1553 DRM_DEBUG_DRIVER("\n");
1554
1555 dev_priv->counter++;
1556 if (dev_priv->counter > 0x7FFFFFFFUL)
1557 dev_priv->counter = 1;
1558 if (master_priv->sarea_priv)
1559 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1560
1561 if (BEGIN_LP_RING(4) == 0) {
1562 OUT_RING(MI_STORE_DWORD_INDEX);
1563 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1564 OUT_RING(dev_priv->counter);
1565 OUT_RING(MI_USER_INTERRUPT);
1566 ADVANCE_LP_RING();
1567 }
1568
1569 return dev_priv->counter;
1570 }
1571
1572 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1573 {
1574 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1575 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1576 int ret = 0;
1577 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1578
1579 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1580 READ_BREADCRUMB(dev_priv));
1581
1582 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1583 if (master_priv->sarea_priv)
1584 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1585 return 0;
1586 }
1587
1588 if (master_priv->sarea_priv)
1589 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1590
1591 if (ring->irq_get(ring)) {
1592 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1593 READ_BREADCRUMB(dev_priv) >= irq_nr);
1594 ring->irq_put(ring);
1595 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1596 ret = -EBUSY;
1597
1598 if (ret == -EBUSY) {
1599 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1600 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1601 }
1602
1603 return ret;
1604 }
1605
1606 /* Needs the lock as it touches the ring.
1607 */
1608 int i915_irq_emit(struct drm_device *dev, void *data,
1609 struct drm_file *file_priv)
1610 {
1611 drm_i915_private_t *dev_priv = dev->dev_private;
1612 drm_i915_irq_emit_t *emit = data;
1613 int result;
1614
1615 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1616 DRM_ERROR("called with no initialization\n");
1617 return -EINVAL;
1618 }
1619
1620 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1621
1622 mutex_lock(&dev->struct_mutex);
1623 result = i915_emit_irq(dev);
1624 mutex_unlock(&dev->struct_mutex);
1625
1626 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1627 DRM_ERROR("copy_to_user\n");
1628 return -EFAULT;
1629 }
1630
1631 return 0;
1632 }
1633
1634 /* Doesn't need the hardware lock.
1635 */
1636 int i915_irq_wait(struct drm_device *dev, void *data,
1637 struct drm_file *file_priv)
1638 {
1639 drm_i915_private_t *dev_priv = dev->dev_private;
1640 drm_i915_irq_wait_t *irqwait = data;
1641
1642 if (!dev_priv) {
1643 DRM_ERROR("called with no initialization\n");
1644 return -EINVAL;
1645 }
1646
1647 return i915_wait_irq(dev, irqwait->irq_seq);
1648 }
1649
1650 /* Called from drm generic code, passed 'crtc' which
1651 * we use as a pipe index
1652 */
1653 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1654 {
1655 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1656 unsigned long irqflags;
1657
1658 if (!i915_pipe_enabled(dev, pipe))
1659 return -EINVAL;
1660
1661 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1662 if (INTEL_INFO(dev)->gen >= 4)
1663 i915_enable_pipestat(dev_priv, pipe,
1664 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1665 else
1666 i915_enable_pipestat(dev_priv, pipe,
1667 PIPE_VBLANK_INTERRUPT_ENABLE);
1668
1669 /* maintain vblank delivery even in deep C-states */
1670 if (dev_priv->info->gen == 3)
1671 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1672 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1673
1674 return 0;
1675 }
1676
1677 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1678 {
1679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1680 unsigned long irqflags;
1681
1682 if (!i915_pipe_enabled(dev, pipe))
1683 return -EINVAL;
1684
1685 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1686 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1687 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1688 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1689
1690 return 0;
1691 }
1692
1693 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1694 {
1695 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1696 unsigned long irqflags;
1697
1698 if (!i915_pipe_enabled(dev, pipe))
1699 return -EINVAL;
1700
1701 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1702 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1703 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1704 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1705
1706 return 0;
1707 }
1708
1709 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1710 {
1711 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1712 unsigned long irqflags;
1713 u32 dpfl, imr;
1714
1715 if (!i915_pipe_enabled(dev, pipe))
1716 return -EINVAL;
1717
1718 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1719 dpfl = I915_READ(VLV_DPFLIPSTAT);
1720 imr = I915_READ(VLV_IMR);
1721 if (pipe == 0) {
1722 dpfl |= PIPEA_VBLANK_INT_EN;
1723 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1724 } else {
1725 dpfl |= PIPEA_VBLANK_INT_EN;
1726 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1727 }
1728 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1729 I915_WRITE(VLV_IMR, imr);
1730 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1731
1732 return 0;
1733 }
1734
1735 /* Called from drm generic code, passed 'crtc' which
1736 * we use as a pipe index
1737 */
1738 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1739 {
1740 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1741 unsigned long irqflags;
1742
1743 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1744 if (dev_priv->info->gen == 3)
1745 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1746
1747 i915_disable_pipestat(dev_priv, pipe,
1748 PIPE_VBLANK_INTERRUPT_ENABLE |
1749 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1750 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1751 }
1752
1753 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1754 {
1755 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1756 unsigned long irqflags;
1757
1758 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1759 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1760 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1761 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1762 }
1763
1764 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1765 {
1766 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1767 unsigned long irqflags;
1768
1769 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1770 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1771 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1772 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1773 }
1774
1775 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1776 {
1777 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1778 unsigned long irqflags;
1779 u32 dpfl, imr;
1780
1781 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1782 dpfl = I915_READ(VLV_DPFLIPSTAT);
1783 imr = I915_READ(VLV_IMR);
1784 if (pipe == 0) {
1785 dpfl &= ~PIPEA_VBLANK_INT_EN;
1786 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1787 } else {
1788 dpfl &= ~PIPEB_VBLANK_INT_EN;
1789 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1790 }
1791 I915_WRITE(VLV_IMR, imr);
1792 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1793 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1794 }
1795
1796
1797 /* Set the vblank monitor pipe
1798 */
1799 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1800 struct drm_file *file_priv)
1801 {
1802 drm_i915_private_t *dev_priv = dev->dev_private;
1803
1804 if (!dev_priv) {
1805 DRM_ERROR("called with no initialization\n");
1806 return -EINVAL;
1807 }
1808
1809 return 0;
1810 }
1811
1812 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1813 struct drm_file *file_priv)
1814 {
1815 drm_i915_private_t *dev_priv = dev->dev_private;
1816 drm_i915_vblank_pipe_t *pipe = data;
1817
1818 if (!dev_priv) {
1819 DRM_ERROR("called with no initialization\n");
1820 return -EINVAL;
1821 }
1822
1823 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1824
1825 return 0;
1826 }
1827
1828 /**
1829 * Schedule buffer swap at given vertical blank.
1830 */
1831 int i915_vblank_swap(struct drm_device *dev, void *data,
1832 struct drm_file *file_priv)
1833 {
1834 /* The delayed swap mechanism was fundamentally racy, and has been
1835 * removed. The model was that the client requested a delayed flip/swap
1836 * from the kernel, then waited for vblank before continuing to perform
1837 * rendering. The problem was that the kernel might wake the client
1838 * up before it dispatched the vblank swap (since the lock has to be
1839 * held while touching the ringbuffer), in which case the client would
1840 * clear and start the next frame before the swap occurred, and
1841 * flicker would occur in addition to likely missing the vblank.
1842 *
1843 * In the absence of this ioctl, userland falls back to a correct path
1844 * of waiting for a vblank, then dispatching the swap on its own.
1845 * Context switching to userland and back is plenty fast enough for
1846 * meeting the requirements of vblank swapping.
1847 */
1848 return -EINVAL;
1849 }
1850
1851 static u32
1852 ring_last_seqno(struct intel_ring_buffer *ring)
1853 {
1854 return list_entry(ring->request_list.prev,
1855 struct drm_i915_gem_request, list)->seqno;
1856 }
1857
1858 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1859 {
1860 if (list_empty(&ring->request_list) ||
1861 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1862 /* Issue a wake-up to catch stuck h/w. */
1863 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1864 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1865 ring->name,
1866 ring->waiting_seqno,
1867 ring->get_seqno(ring));
1868 wake_up_all(&ring->irq_queue);
1869 *err = true;
1870 }
1871 return true;
1872 }
1873 return false;
1874 }
1875
1876 static bool kick_ring(struct intel_ring_buffer *ring)
1877 {
1878 struct drm_device *dev = ring->dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 u32 tmp = I915_READ_CTL(ring);
1881 if (tmp & RING_WAIT) {
1882 DRM_ERROR("Kicking stuck wait on %s\n",
1883 ring->name);
1884 I915_WRITE_CTL(ring, tmp);
1885 return true;
1886 }
1887 return false;
1888 }
1889
1890 static bool i915_hangcheck_hung(struct drm_device *dev)
1891 {
1892 drm_i915_private_t *dev_priv = dev->dev_private;
1893
1894 if (dev_priv->hangcheck_count++ > 1) {
1895 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1896 i915_handle_error(dev, true);
1897
1898 if (!IS_GEN2(dev)) {
1899 /* Is the chip hanging on a WAIT_FOR_EVENT?
1900 * If so we can simply poke the RB_WAIT bit
1901 * and break the hang. This should work on
1902 * all but the second generation chipsets.
1903 */
1904 if (kick_ring(&dev_priv->ring[RCS]))
1905 return false;
1906
1907 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1908 return false;
1909
1910 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1911 return false;
1912 }
1913
1914 return true;
1915 }
1916
1917 return false;
1918 }
1919
1920 /**
1921 * This is called when the chip hasn't reported back with completed
1922 * batchbuffers in a long time. The first time this is called we simply record
1923 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1924 * again, we assume the chip is wedged and try to fix it.
1925 */
1926 void i915_hangcheck_elapsed(unsigned long data)
1927 {
1928 struct drm_device *dev = (struct drm_device *)data;
1929 drm_i915_private_t *dev_priv = dev->dev_private;
1930 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1931 bool err = false;
1932
1933 if (!i915_enable_hangcheck)
1934 return;
1935
1936 /* If all work is done then ACTHD clearly hasn't advanced. */
1937 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1938 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1939 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1940 if (err) {
1941 if (i915_hangcheck_hung(dev))
1942 return;
1943
1944 goto repeat;
1945 }
1946
1947 dev_priv->hangcheck_count = 0;
1948 return;
1949 }
1950
1951 if (INTEL_INFO(dev)->gen < 4) {
1952 instdone = I915_READ(INSTDONE);
1953 instdone1 = 0;
1954 } else {
1955 instdone = I915_READ(INSTDONE_I965);
1956 instdone1 = I915_READ(INSTDONE1);
1957 }
1958 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1959 acthd_bsd = HAS_BSD(dev) ?
1960 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1961 acthd_blt = HAS_BLT(dev) ?
1962 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1963
1964 if (dev_priv->last_acthd == acthd &&
1965 dev_priv->last_acthd_bsd == acthd_bsd &&
1966 dev_priv->last_acthd_blt == acthd_blt &&
1967 dev_priv->last_instdone == instdone &&
1968 dev_priv->last_instdone1 == instdone1) {
1969 if (i915_hangcheck_hung(dev))
1970 return;
1971 } else {
1972 dev_priv->hangcheck_count = 0;
1973
1974 dev_priv->last_acthd = acthd;
1975 dev_priv->last_acthd_bsd = acthd_bsd;
1976 dev_priv->last_acthd_blt = acthd_blt;
1977 dev_priv->last_instdone = instdone;
1978 dev_priv->last_instdone1 = instdone1;
1979 }
1980
1981 repeat:
1982 /* Reset timer case chip hangs without another request being added */
1983 mod_timer(&dev_priv->hangcheck_timer,
1984 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1985 }
1986
1987 /* drm_dma.h hooks
1988 */
1989 static void ironlake_irq_preinstall(struct drm_device *dev)
1990 {
1991 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1992
1993 atomic_set(&dev_priv->irq_received, 0);
1994
1995 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1996 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1997 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1998 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1999
2000 I915_WRITE(HWSTAM, 0xeffe);
2001
2002 /* XXX hotplug from PCH */
2003
2004 I915_WRITE(DEIMR, 0xffffffff);
2005 I915_WRITE(DEIER, 0x0);
2006 POSTING_READ(DEIER);
2007
2008 /* and GT */
2009 I915_WRITE(GTIMR, 0xffffffff);
2010 I915_WRITE(GTIER, 0x0);
2011 POSTING_READ(GTIER);
2012
2013 /* south display irq */
2014 I915_WRITE(SDEIMR, 0xffffffff);
2015 I915_WRITE(SDEIER, 0x0);
2016 POSTING_READ(SDEIER);
2017 }
2018
2019 static void valleyview_irq_preinstall(struct drm_device *dev)
2020 {
2021 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2022 int pipe;
2023
2024 atomic_set(&dev_priv->irq_received, 0);
2025
2026 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2027 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2028
2029 /* VLV magic */
2030 I915_WRITE(VLV_IMR, 0);
2031 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2032 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2033 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2034
2035 /* and GT */
2036 I915_WRITE(GTIIR, I915_READ(GTIIR));
2037 I915_WRITE(GTIIR, I915_READ(GTIIR));
2038 I915_WRITE(GTIMR, 0xffffffff);
2039 I915_WRITE(GTIER, 0x0);
2040 POSTING_READ(GTIER);
2041
2042 I915_WRITE(DPINVGTT, 0xff);
2043
2044 I915_WRITE(PORT_HOTPLUG_EN, 0);
2045 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2046 for_each_pipe(pipe)
2047 I915_WRITE(PIPESTAT(pipe), 0xffff);
2048 I915_WRITE(VLV_IIR, 0xffffffff);
2049 I915_WRITE(VLV_IMR, 0xffffffff);
2050 I915_WRITE(VLV_IER, 0x0);
2051 POSTING_READ(VLV_IER);
2052 }
2053
2054 /*
2055 * Enable digital hotplug on the PCH, and configure the DP short pulse
2056 * duration to 2ms (which is the minimum in the Display Port spec)
2057 *
2058 * This register is the same on all known PCH chips.
2059 */
2060
2061 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
2062 {
2063 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2064 u32 hotplug;
2065
2066 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2067 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2068 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2069 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2070 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2071 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2072 }
2073
2074 static int ironlake_irq_postinstall(struct drm_device *dev)
2075 {
2076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2077 /* enable kind of interrupts always enabled */
2078 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2079 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
2080 u32 render_irqs;
2081 u32 hotplug_mask;
2082
2083 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2084 if (HAS_BSD(dev))
2085 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2086 if (HAS_BLT(dev))
2087 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2088
2089 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2090 dev_priv->irq_mask = ~display_mask;
2091
2092 /* should always can generate irq */
2093 I915_WRITE(DEIIR, I915_READ(DEIIR));
2094 I915_WRITE(DEIMR, dev_priv->irq_mask);
2095 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2096 POSTING_READ(DEIER);
2097
2098 dev_priv->gt_irq_mask = ~0;
2099
2100 I915_WRITE(GTIIR, I915_READ(GTIIR));
2101 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2102
2103 if (IS_GEN6(dev))
2104 render_irqs =
2105 GT_USER_INTERRUPT |
2106 GEN6_BSD_USER_INTERRUPT |
2107 GEN6_BLITTER_USER_INTERRUPT;
2108 else
2109 render_irqs =
2110 GT_USER_INTERRUPT |
2111 GT_PIPE_NOTIFY |
2112 GT_BSD_USER_INTERRUPT;
2113 I915_WRITE(GTIER, render_irqs);
2114 POSTING_READ(GTIER);
2115
2116 if (HAS_PCH_CPT(dev)) {
2117 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2118 SDE_PORTB_HOTPLUG_CPT |
2119 SDE_PORTC_HOTPLUG_CPT |
2120 SDE_PORTD_HOTPLUG_CPT);
2121 } else {
2122 hotplug_mask = (SDE_CRT_HOTPLUG |
2123 SDE_PORTB_HOTPLUG |
2124 SDE_PORTC_HOTPLUG |
2125 SDE_PORTD_HOTPLUG |
2126 SDE_AUX_MASK);
2127 }
2128
2129 dev_priv->pch_irq_mask = ~hotplug_mask;
2130
2131 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2132 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2133 I915_WRITE(SDEIER, hotplug_mask);
2134 POSTING_READ(SDEIER);
2135
2136 ironlake_enable_pch_hotplug(dev);
2137
2138 if (IS_IRONLAKE_M(dev)) {
2139 /* Clear & enable PCU event interrupts */
2140 I915_WRITE(DEIIR, DE_PCU_EVENT);
2141 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2142 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2143 }
2144
2145 return 0;
2146 }
2147
2148 static int ivybridge_irq_postinstall(struct drm_device *dev)
2149 {
2150 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2151 /* enable kind of interrupts always enabled */
2152 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2153 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
2154 DE_PLANEB_FLIP_DONE_IVB;
2155 u32 render_irqs;
2156 u32 hotplug_mask;
2157
2158 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2159 if (HAS_BSD(dev))
2160 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2161 if (HAS_BLT(dev))
2162 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2163
2164 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2165 dev_priv->irq_mask = ~display_mask;
2166
2167 /* should always can generate irq */
2168 I915_WRITE(DEIIR, I915_READ(DEIIR));
2169 I915_WRITE(DEIMR, dev_priv->irq_mask);
2170 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
2171 DE_PIPEB_VBLANK_IVB);
2172 POSTING_READ(DEIER);
2173
2174 dev_priv->gt_irq_mask = ~0;
2175
2176 I915_WRITE(GTIIR, I915_READ(GTIIR));
2177 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2178
2179 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2180 GEN6_BLITTER_USER_INTERRUPT;
2181 I915_WRITE(GTIER, render_irqs);
2182 POSTING_READ(GTIER);
2183
2184 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2185 SDE_PORTB_HOTPLUG_CPT |
2186 SDE_PORTC_HOTPLUG_CPT |
2187 SDE_PORTD_HOTPLUG_CPT);
2188 dev_priv->pch_irq_mask = ~hotplug_mask;
2189
2190 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2191 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2192 I915_WRITE(SDEIER, hotplug_mask);
2193 POSTING_READ(SDEIER);
2194
2195 ironlake_enable_pch_hotplug(dev);
2196
2197 return 0;
2198 }
2199
2200 static int valleyview_irq_postinstall(struct drm_device *dev)
2201 {
2202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2203 u32 render_irqs;
2204 u32 enable_mask;
2205 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2206 u16 msid;
2207
2208 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2209 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2210 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2211
2212 dev_priv->irq_mask = ~enable_mask;
2213
2214
2215 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2216 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2217 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2218
2219 dev_priv->pipestat[0] = 0;
2220 dev_priv->pipestat[1] = 0;
2221
2222 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2223
2224 /* Hack for broken MSIs on VLV */
2225 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2226 pci_read_config_word(dev->pdev, 0x98, &msid);
2227 msid &= 0xff; /* mask out delivery bits */
2228 msid |= (1<<14);
2229 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2230
2231 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2232 I915_WRITE(VLV_IER, enable_mask);
2233 I915_WRITE(VLV_IIR, 0xffffffff);
2234 I915_WRITE(PIPESTAT(0), 0xffff);
2235 I915_WRITE(PIPESTAT(1), 0xffff);
2236 POSTING_READ(VLV_IER);
2237
2238 I915_WRITE(VLV_IIR, 0xffffffff);
2239 I915_WRITE(VLV_IIR, 0xffffffff);
2240
2241 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2242 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
2243 GT_GEN6_BLT_USER_INTERRUPT |
2244 GT_GEN6_BSD_USER_INTERRUPT |
2245 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2246 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2247 GT_PIPE_NOTIFY |
2248 GT_RENDER_CS_ERROR_INTERRUPT |
2249 GT_SYNC_STATUS |
2250 GT_USER_INTERRUPT;
2251
2252 dev_priv->gt_irq_mask = ~render_irqs;
2253
2254 I915_WRITE(GTIIR, I915_READ(GTIIR));
2255 I915_WRITE(GTIIR, I915_READ(GTIIR));
2256 I915_WRITE(GTIMR, 0);
2257 I915_WRITE(GTIER, render_irqs);
2258 POSTING_READ(GTIER);
2259
2260 /* ack & enable invalid PTE error interrupts */
2261 #if 0 /* FIXME: add support to irq handler for checking these bits */
2262 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2263 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2264 #endif
2265
2266 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2267 #if 0 /* FIXME: check register definitions; some have moved */
2268 /* Note HDMI and DP share bits */
2269 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2270 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2271 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2272 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2273 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2274 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2275 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2276 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2277 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2278 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2279 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2280 hotplug_en |= CRT_HOTPLUG_INT_EN;
2281 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2282 }
2283 #endif
2284
2285 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2286
2287 return 0;
2288 }
2289
2290 static void i915_driver_irq_preinstall(struct drm_device * dev)
2291 {
2292 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2293 int pipe;
2294
2295 atomic_set(&dev_priv->irq_received, 0);
2296
2297 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2298 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2299
2300 if (I915_HAS_HOTPLUG(dev)) {
2301 I915_WRITE(PORT_HOTPLUG_EN, 0);
2302 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2303 }
2304
2305 I915_WRITE(HWSTAM, 0xeffe);
2306 for_each_pipe(pipe)
2307 I915_WRITE(PIPESTAT(pipe), 0);
2308 I915_WRITE(IMR, 0xffffffff);
2309 I915_WRITE(IER, 0x0);
2310 POSTING_READ(IER);
2311 }
2312
2313 /*
2314 * Must be called after intel_modeset_init or hotplug interrupts won't be
2315 * enabled correctly.
2316 */
2317 static int i915_driver_irq_postinstall(struct drm_device *dev)
2318 {
2319 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2320 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
2321 u32 error_mask;
2322
2323 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2324
2325 /* Unmask the interrupts that we always want on. */
2326 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
2327
2328 dev_priv->pipestat[0] = 0;
2329 dev_priv->pipestat[1] = 0;
2330
2331 if (I915_HAS_HOTPLUG(dev)) {
2332 /* Enable in IER... */
2333 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2334 /* and unmask in IMR */
2335 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2336 }
2337
2338 /*
2339 * Enable some error detection, note the instruction error mask
2340 * bit is reserved, so we leave it masked.
2341 */
2342 if (IS_G4X(dev)) {
2343 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2344 GM45_ERROR_MEM_PRIV |
2345 GM45_ERROR_CP_PRIV |
2346 I915_ERROR_MEMORY_REFRESH);
2347 } else {
2348 error_mask = ~(I915_ERROR_PAGE_TABLE |
2349 I915_ERROR_MEMORY_REFRESH);
2350 }
2351 I915_WRITE(EMR, error_mask);
2352
2353 I915_WRITE(IMR, dev_priv->irq_mask);
2354 I915_WRITE(IER, enable_mask);
2355 POSTING_READ(IER);
2356
2357 if (I915_HAS_HOTPLUG(dev)) {
2358 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2359
2360 /* Note HDMI and DP share bits */
2361 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2362 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2363 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2364 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2365 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2366 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2367 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2368 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2369 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2370 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2371 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2372 hotplug_en |= CRT_HOTPLUG_INT_EN;
2373
2374 /* Programming the CRT detection parameters tends
2375 to generate a spurious hotplug event about three
2376 seconds later. So just do it once.
2377 */
2378 if (IS_G4X(dev))
2379 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2380 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2381 }
2382
2383 /* Ignore TV since it's buggy */
2384
2385 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2386 }
2387
2388 intel_opregion_enable_asle(dev);
2389
2390 return 0;
2391 }
2392
2393 static void valleyview_irq_uninstall(struct drm_device *dev)
2394 {
2395 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2396 int pipe;
2397
2398 if (!dev_priv)
2399 return;
2400
2401 dev_priv->vblank_pipe = 0;
2402
2403 for_each_pipe(pipe)
2404 I915_WRITE(PIPESTAT(pipe), 0xffff);
2405
2406 I915_WRITE(HWSTAM, 0xffffffff);
2407 I915_WRITE(PORT_HOTPLUG_EN, 0);
2408 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2409 for_each_pipe(pipe)
2410 I915_WRITE(PIPESTAT(pipe), 0xffff);
2411 I915_WRITE(VLV_IIR, 0xffffffff);
2412 I915_WRITE(VLV_IMR, 0xffffffff);
2413 I915_WRITE(VLV_IER, 0x0);
2414 POSTING_READ(VLV_IER);
2415 }
2416
2417 static void ironlake_irq_uninstall(struct drm_device *dev)
2418 {
2419 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2420
2421 if (!dev_priv)
2422 return;
2423
2424 dev_priv->vblank_pipe = 0;
2425
2426 I915_WRITE(HWSTAM, 0xffffffff);
2427
2428 I915_WRITE(DEIMR, 0xffffffff);
2429 I915_WRITE(DEIER, 0x0);
2430 I915_WRITE(DEIIR, I915_READ(DEIIR));
2431
2432 I915_WRITE(GTIMR, 0xffffffff);
2433 I915_WRITE(GTIER, 0x0);
2434 I915_WRITE(GTIIR, I915_READ(GTIIR));
2435
2436 I915_WRITE(SDEIMR, 0xffffffff);
2437 I915_WRITE(SDEIER, 0x0);
2438 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2439 }
2440
2441 static void i915_driver_irq_uninstall(struct drm_device * dev)
2442 {
2443 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2444 int pipe;
2445
2446 if (!dev_priv)
2447 return;
2448
2449 dev_priv->vblank_pipe = 0;
2450
2451 if (I915_HAS_HOTPLUG(dev)) {
2452 I915_WRITE(PORT_HOTPLUG_EN, 0);
2453 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2454 }
2455
2456 I915_WRITE(HWSTAM, 0xffffffff);
2457 for_each_pipe(pipe)
2458 I915_WRITE(PIPESTAT(pipe), 0);
2459 I915_WRITE(IMR, 0xffffffff);
2460 I915_WRITE(IER, 0x0);
2461
2462 for_each_pipe(pipe)
2463 I915_WRITE(PIPESTAT(pipe),
2464 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2465 I915_WRITE(IIR, I915_READ(IIR));
2466 }
2467
2468 static void i8xx_irq_preinstall(struct drm_device * dev)
2469 {
2470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2471 int pipe;
2472
2473 atomic_set(&dev_priv->irq_received, 0);
2474
2475 for_each_pipe(pipe)
2476 I915_WRITE(PIPESTAT(pipe), 0);
2477 I915_WRITE16(IMR, 0xffff);
2478 I915_WRITE16(IER, 0x0);
2479 POSTING_READ16(IER);
2480 }
2481
2482 static int i8xx_irq_postinstall(struct drm_device *dev)
2483 {
2484 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2485
2486 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2487
2488 dev_priv->pipestat[0] = 0;
2489 dev_priv->pipestat[1] = 0;
2490
2491 I915_WRITE16(EMR,
2492 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2493
2494 /* Unmask the interrupts that we always want on. */
2495 dev_priv->irq_mask =
2496 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2497 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2498 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2499 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2500 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2501 I915_WRITE16(IMR, dev_priv->irq_mask);
2502
2503 I915_WRITE16(IER,
2504 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2505 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2506 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2507 I915_USER_INTERRUPT);
2508 POSTING_READ16(IER);
2509
2510 return 0;
2511 }
2512
2513 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2514 {
2515 struct drm_device *dev = (struct drm_device *) arg;
2516 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2517 struct drm_i915_master_private *master_priv;
2518 u16 iir, new_iir;
2519 u32 pipe_stats[2];
2520 unsigned long irqflags;
2521 int irq_received;
2522 int pipe;
2523 u16 flip_mask =
2524 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2525 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2526
2527 atomic_inc(&dev_priv->irq_received);
2528
2529 iir = I915_READ16(IIR);
2530 if (iir == 0)
2531 return IRQ_NONE;
2532
2533 while (iir & ~flip_mask) {
2534 /* Can't rely on pipestat interrupt bit in iir as it might
2535 * have been cleared after the pipestat interrupt was received.
2536 * It doesn't set the bit in iir again, but it still produces
2537 * interrupts (for non-MSI).
2538 */
2539 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2540 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2541 i915_handle_error(dev, false);
2542
2543 for_each_pipe(pipe) {
2544 int reg = PIPESTAT(pipe);
2545 pipe_stats[pipe] = I915_READ(reg);
2546
2547 /*
2548 * Clear the PIPE*STAT regs before the IIR
2549 */
2550 if (pipe_stats[pipe] & 0x8000ffff) {
2551 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2552 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2553 pipe_name(pipe));
2554 I915_WRITE(reg, pipe_stats[pipe]);
2555 irq_received = 1;
2556 }
2557 }
2558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2559
2560 I915_WRITE16(IIR, iir & ~flip_mask);
2561 new_iir = I915_READ16(IIR); /* Flush posted writes */
2562
2563 if (dev->primary->master) {
2564 master_priv = dev->primary->master->driver_priv;
2565 if (master_priv->sarea_priv)
2566 master_priv->sarea_priv->last_dispatch =
2567 READ_BREADCRUMB(dev_priv);
2568 }
2569
2570 if (iir & I915_USER_INTERRUPT)
2571 notify_ring(dev, &dev_priv->ring[RCS]);
2572
2573 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2574 drm_handle_vblank(dev, 0)) {
2575 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2576 intel_prepare_page_flip(dev, 0);
2577 intel_finish_page_flip(dev, 0);
2578 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2579 }
2580 }
2581
2582 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2583 drm_handle_vblank(dev, 1)) {
2584 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2585 intel_prepare_page_flip(dev, 1);
2586 intel_finish_page_flip(dev, 1);
2587 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2588 }
2589 }
2590
2591 iir = new_iir;
2592 }
2593
2594 return IRQ_HANDLED;
2595 }
2596
2597 static void i8xx_irq_uninstall(struct drm_device * dev)
2598 {
2599 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2600 int pipe;
2601
2602 dev_priv->vblank_pipe = 0;
2603
2604 for_each_pipe(pipe) {
2605 /* Clear enable bits; then clear status bits */
2606 I915_WRITE(PIPESTAT(pipe), 0);
2607 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2608 }
2609 I915_WRITE16(IMR, 0xffff);
2610 I915_WRITE16(IER, 0x0);
2611 I915_WRITE16(IIR, I915_READ16(IIR));
2612 }
2613
2614 void intel_irq_init(struct drm_device *dev)
2615 {
2616 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2617 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2618 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2619 IS_VALLEYVIEW(dev)) {
2620 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2621 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2622 }
2623
2624 if (drm_core_check_feature(dev, DRIVER_MODESET))
2625 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2626 else
2627 dev->driver->get_vblank_timestamp = NULL;
2628 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2629
2630 if (IS_VALLEYVIEW(dev)) {
2631 dev->driver->irq_handler = valleyview_irq_handler;
2632 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2633 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2634 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2635 dev->driver->enable_vblank = valleyview_enable_vblank;
2636 dev->driver->disable_vblank = valleyview_disable_vblank;
2637 } else if (IS_IVYBRIDGE(dev)) {
2638 /* Share pre & uninstall handlers with ILK/SNB */
2639 dev->driver->irq_handler = ivybridge_irq_handler;
2640 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2641 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2642 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2643 dev->driver->enable_vblank = ivybridge_enable_vblank;
2644 dev->driver->disable_vblank = ivybridge_disable_vblank;
2645 } else if (HAS_PCH_SPLIT(dev)) {
2646 dev->driver->irq_handler = ironlake_irq_handler;
2647 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2648 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2649 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2650 dev->driver->enable_vblank = ironlake_enable_vblank;
2651 dev->driver->disable_vblank = ironlake_disable_vblank;
2652 } else {
2653 if (INTEL_INFO(dev)->gen == 2) {
2654 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2655 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2656 dev->driver->irq_handler = i8xx_irq_handler;
2657 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2658 } else {
2659 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2660 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2661 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2662 dev->driver->irq_handler = i915_driver_irq_handler;
2663 }
2664 dev->driver->enable_vblank = i915_enable_vblank;
2665 dev->driver->disable_vblank = i915_disable_vblank;
2666 }
2667 }
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