1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 /* For display hotplug interrupt */
42 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
44 if ((dev_priv
->irq_mask
& mask
) != 0) {
45 dev_priv
->irq_mask
&= ~mask
;
46 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
52 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
54 if ((dev_priv
->irq_mask
& mask
) != mask
) {
55 dev_priv
->irq_mask
|= mask
;
56 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
62 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
64 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
65 u32 reg
= PIPESTAT(pipe
);
67 dev_priv
->pipestat
[pipe
] |= mask
;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
75 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
77 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
78 u32 reg
= PIPESTAT(pipe
);
80 dev_priv
->pipestat
[pipe
] &= ~mask
;
81 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
89 void intel_enable_asle(struct drm_device
*dev
)
91 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
92 unsigned long irqflags
;
94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev
))
98 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
100 if (HAS_PCH_SPLIT(dev
))
101 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
103 i915_enable_pipestat(dev_priv
, 1,
104 PIPE_LEGACY_BLC_EVENT_ENABLE
);
105 if (INTEL_INFO(dev
)->gen
>= 4)
106 i915_enable_pipestat(dev_priv
, 0,
107 PIPE_LEGACY_BLC_EVENT_ENABLE
);
110 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
114 * i915_pipe_enabled - check if a pipe is enabled
116 * @pipe: pipe to check
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
123 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
125 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
126 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
129 /* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
132 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
134 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
135 unsigned long high_frame
;
136 unsigned long low_frame
;
137 u32 high1
, high2
, low
;
139 if (!i915_pipe_enabled(dev
, pipe
)) {
140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
141 "pipe %c\n", pipe_name(pipe
));
145 high_frame
= PIPEFRAME(pipe
);
146 low_frame
= PIPEFRAMEPIXEL(pipe
);
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
154 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
155 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
156 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
157 } while (high1
!= high2
);
159 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
160 low
>>= PIPE_FRAME_LOW_SHIFT
;
161 return (high1
<< 8) | low
;
164 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
166 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
167 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
169 if (!i915_pipe_enabled(dev
, pipe
)) {
170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
171 "pipe %c\n", pipe_name(pipe
));
175 return I915_READ(reg
);
178 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
179 int *vpos
, int *hpos
)
181 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
182 u32 vbl
= 0, position
= 0;
183 int vbl_start
, vbl_end
, htotal
, vtotal
;
187 if (!i915_pipe_enabled(dev
, pipe
)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
189 "pipe %c\n", pipe_name(pipe
));
194 vtotal
= 1 + ((I915_READ(VTOTAL(pipe
)) >> 16) & 0x1fff);
196 if (INTEL_INFO(dev
)->gen
>= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
200 position
= I915_READ(PIPEDSL(pipe
));
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
205 *vpos
= position
& 0x1fff;
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
212 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
214 htotal
= 1 + ((I915_READ(HTOTAL(pipe
)) >> 16) & 0x1fff);
215 *vpos
= position
/ htotal
;
216 *hpos
= position
- (*vpos
* htotal
);
219 /* Query vblank area. */
220 vbl
= I915_READ(VBLANK(pipe
));
222 /* Test position against vblank region. */
223 vbl_start
= vbl
& 0x1fff;
224 vbl_end
= (vbl
>> 16) & 0x1fff;
226 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl
&& (*vpos
>= vbl_start
))
231 *vpos
= *vpos
- vtotal
;
233 /* Readouts valid? */
235 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
239 ret
|= DRM_SCANOUTPOS_INVBL
;
244 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
246 struct timeval
*vblank_time
,
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 struct drm_crtc
*crtc
;
252 if (pipe
< 0 || pipe
>= dev_priv
->num_pipe
) {
253 DRM_ERROR("Invalid crtc %d\n", pipe
);
257 /* Get drm_crtc to timestamp: */
258 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
260 DRM_ERROR("Invalid crtc %d\n", pipe
);
264 if (!crtc
->enabled
) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
269 /* Helper routine in DRM core does all the work: */
270 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
276 * Handle hotplug events outside the interrupt handler proper.
278 static void i915_hotplug_work_func(struct work_struct
*work
)
280 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
282 struct drm_device
*dev
= dev_priv
->dev
;
283 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
284 struct intel_encoder
*encoder
;
286 mutex_lock(&mode_config
->mutex
);
287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
289 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
290 if (encoder
->hot_plug
)
291 encoder
->hot_plug(encoder
);
293 mutex_unlock(&mode_config
->mutex
);
295 /* Just fire off a uevent and let userspace tell us what to do */
296 drm_helper_hpd_irq_event(dev
);
299 static void i915_handle_rps_change(struct drm_device
*dev
)
301 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
302 u32 busy_up
, busy_down
, max_avg
, min_avg
;
303 u8 new_delay
= dev_priv
->cur_delay
;
305 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
306 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
307 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
308 max_avg
= I915_READ(RCBMAXAVG
);
309 min_avg
= I915_READ(RCBMINAVG
);
311 /* Handle RCS change request from hw */
312 if (busy_up
> max_avg
) {
313 if (dev_priv
->cur_delay
!= dev_priv
->max_delay
)
314 new_delay
= dev_priv
->cur_delay
- 1;
315 if (new_delay
< dev_priv
->max_delay
)
316 new_delay
= dev_priv
->max_delay
;
317 } else if (busy_down
< min_avg
) {
318 if (dev_priv
->cur_delay
!= dev_priv
->min_delay
)
319 new_delay
= dev_priv
->cur_delay
+ 1;
320 if (new_delay
> dev_priv
->min_delay
)
321 new_delay
= dev_priv
->min_delay
;
324 if (ironlake_set_drps(dev
, new_delay
))
325 dev_priv
->cur_delay
= new_delay
;
330 static void notify_ring(struct drm_device
*dev
,
331 struct intel_ring_buffer
*ring
)
333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
335 if (ring
->obj
== NULL
)
338 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
));
340 wake_up_all(&ring
->irq_queue
);
341 if (i915_enable_hangcheck
) {
342 dev_priv
->hangcheck_count
= 0;
343 mod_timer(&dev_priv
->hangcheck_timer
,
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
349 static void gen6_pm_rps_work(struct work_struct
*work
)
351 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
353 u8 new_delay
= dev_priv
->cur_delay
;
356 spin_lock_irq(&dev_priv
->rps_lock
);
357 pm_iir
= dev_priv
->pm_iir
;
358 dev_priv
->pm_iir
= 0;
359 pm_imr
= I915_READ(GEN6_PMIMR
);
360 I915_WRITE(GEN6_PMIMR
, 0);
361 spin_unlock_irq(&dev_priv
->rps_lock
);
366 mutex_lock(&dev_priv
->dev
->struct_mutex
);
367 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
368 if (dev_priv
->cur_delay
!= dev_priv
->max_delay
)
369 new_delay
= dev_priv
->cur_delay
+ 1;
370 if (new_delay
> dev_priv
->max_delay
)
371 new_delay
= dev_priv
->max_delay
;
372 } else if (pm_iir
& (GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
)) {
373 gen6_gt_force_wake_get(dev_priv
);
374 if (dev_priv
->cur_delay
!= dev_priv
->min_delay
)
375 new_delay
= dev_priv
->cur_delay
- 1;
376 if (new_delay
< dev_priv
->min_delay
) {
377 new_delay
= dev_priv
->min_delay
;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS
) |
380 ((new_delay
<< 16) & 0x3f0000));
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS
) & ~0x3f0000);
387 gen6_gt_force_wake_put(dev_priv
);
390 gen6_set_rps(dev_priv
->dev
, new_delay
);
391 dev_priv
->cur_delay
= new_delay
;
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
398 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
401 static void snb_gt_irq_handler(struct drm_device
*dev
,
402 struct drm_i915_private
*dev_priv
,
406 if (gt_iir
& (GEN6_RENDER_USER_INTERRUPT
|
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
))
408 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
409 if (gt_iir
& GEN6_BSD_USER_INTERRUPT
)
410 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
411 if (gt_iir
& GEN6_BLITTER_USER_INTERRUPT
)
412 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
414 if (gt_iir
& (GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
416 GT_RENDER_CS_ERROR_INTERRUPT
)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
418 i915_handle_error(dev
, false);
422 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
434 * The mask bit in IMR is cleared by rps_work.
437 spin_lock_irqsave(&dev_priv
->rps_lock
, flags
);
438 WARN(dev_priv
->pm_iir
& pm_iir
, "Missed a PM interrupt\n");
439 dev_priv
->pm_iir
|= pm_iir
;
440 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_iir
);
441 POSTING_READ(GEN6_PMIMR
);
442 spin_unlock_irqrestore(&dev_priv
->rps_lock
, flags
);
444 queue_work(dev_priv
->wq
, &dev_priv
->rps_work
);
447 static irqreturn_t
valleyview_irq_handler(DRM_IRQ_ARGS
)
449 struct drm_device
*dev
= (struct drm_device
*) arg
;
450 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
451 u32 iir
, gt_iir
, pm_iir
;
452 irqreturn_t ret
= IRQ_NONE
;
453 unsigned long irqflags
;
455 u32 pipe_stats
[I915_MAX_PIPES
];
460 atomic_inc(&dev_priv
->irq_received
);
462 vblank_status
= PIPE_START_VBLANK_INTERRUPT_STATUS
|
463 PIPE_VBLANK_INTERRUPT_STATUS
;
466 iir
= I915_READ(VLV_IIR
);
467 gt_iir
= I915_READ(GTIIR
);
468 pm_iir
= I915_READ(GEN6_PMIIR
);
470 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
475 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
477 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
478 for_each_pipe(pipe
) {
479 int reg
= PIPESTAT(pipe
);
480 pipe_stats
[pipe
] = I915_READ(reg
);
483 * Clear the PIPE*STAT regs before the IIR
485 if (pipe_stats
[pipe
] & 0x8000ffff) {
486 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
489 I915_WRITE(reg
, pipe_stats
[pipe
]);
492 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
496 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
500 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
501 queue_work(dev_priv
->wq
,
502 &dev_priv
->hotplug_work
);
504 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
505 I915_READ(PORT_HOTPLUG_STAT
);
509 if (iir
& I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
) {
510 drm_handle_vblank(dev
, 0);
512 intel_finish_page_flip(dev
, 0);
515 if (iir
& I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
) {
516 drm_handle_vblank(dev
, 1);
518 intel_finish_page_flip(dev
, 0);
521 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
524 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
525 gen6_queue_rps_work(dev_priv
, pm_iir
);
527 I915_WRITE(GTIIR
, gt_iir
);
528 I915_WRITE(GEN6_PMIIR
, pm_iir
);
529 I915_WRITE(VLV_IIR
, iir
);
536 static void pch_irq_handler(struct drm_device
*dev
)
538 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
542 pch_iir
= I915_READ(SDEIIR
);
544 if (pch_iir
& SDE_AUDIO_POWER_MASK
)
545 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
546 (pch_iir
& SDE_AUDIO_POWER_MASK
) >>
547 SDE_AUDIO_POWER_SHIFT
);
549 if (pch_iir
& SDE_GMBUS
)
550 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
552 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
553 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
555 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
556 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
558 if (pch_iir
& SDE_POISON
)
559 DRM_ERROR("PCH poison interrupt\n");
561 if (pch_iir
& SDE_FDI_MASK
)
563 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
565 I915_READ(FDI_RX_IIR(pipe
)));
567 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
570 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
573 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
574 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
575 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
576 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
579 static irqreturn_t
ivybridge_irq_handler(DRM_IRQ_ARGS
)
581 struct drm_device
*dev
= (struct drm_device
*) arg
;
582 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
584 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
586 atomic_inc(&dev_priv
->irq_received
);
588 /* disable master interrupt before clearing iir */
589 de_ier
= I915_READ(DEIER
);
590 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
593 de_iir
= I915_READ(DEIIR
);
594 gt_iir
= I915_READ(GTIIR
);
595 pch_iir
= I915_READ(SDEIIR
);
596 pm_iir
= I915_READ(GEN6_PMIIR
);
598 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 && pm_iir
== 0)
603 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
605 if (de_iir
& DE_GSE_IVB
)
606 intel_opregion_gse_intr(dev
);
608 if (de_iir
& DE_PLANEA_FLIP_DONE_IVB
) {
609 intel_prepare_page_flip(dev
, 0);
610 intel_finish_page_flip_plane(dev
, 0);
613 if (de_iir
& DE_PLANEB_FLIP_DONE_IVB
) {
614 intel_prepare_page_flip(dev
, 1);
615 intel_finish_page_flip_plane(dev
, 1);
618 if (de_iir
& DE_PIPEA_VBLANK_IVB
)
619 drm_handle_vblank(dev
, 0);
621 if (de_iir
& DE_PIPEB_VBLANK_IVB
)
622 drm_handle_vblank(dev
, 1);
624 /* check event from PCH */
625 if (de_iir
& DE_PCH_EVENT_IVB
) {
626 if (pch_iir
& SDE_HOTPLUG_MASK_CPT
)
627 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
628 pch_irq_handler(dev
);
631 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
632 gen6_queue_rps_work(dev_priv
, pm_iir
);
634 /* should clear PCH hotplug event before clear CPU irq */
635 I915_WRITE(SDEIIR
, pch_iir
);
636 I915_WRITE(GTIIR
, gt_iir
);
637 I915_WRITE(DEIIR
, de_iir
);
638 I915_WRITE(GEN6_PMIIR
, pm_iir
);
641 I915_WRITE(DEIER
, de_ier
);
647 static void ilk_gt_irq_handler(struct drm_device
*dev
,
648 struct drm_i915_private
*dev_priv
,
651 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
652 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
653 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
654 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
657 static irqreturn_t
ironlake_irq_handler(DRM_IRQ_ARGS
)
659 struct drm_device
*dev
= (struct drm_device
*) arg
;
660 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
662 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
665 atomic_inc(&dev_priv
->irq_received
);
667 /* disable master interrupt before clearing iir */
668 de_ier
= I915_READ(DEIER
);
669 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
672 de_iir
= I915_READ(DEIIR
);
673 gt_iir
= I915_READ(GTIIR
);
674 pch_iir
= I915_READ(SDEIIR
);
675 pm_iir
= I915_READ(GEN6_PMIIR
);
677 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 &&
678 (!IS_GEN6(dev
) || pm_iir
== 0))
681 if (HAS_PCH_CPT(dev
))
682 hotplug_mask
= SDE_HOTPLUG_MASK_CPT
;
684 hotplug_mask
= SDE_HOTPLUG_MASK
;
689 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
691 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
694 intel_opregion_gse_intr(dev
);
696 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
697 intel_prepare_page_flip(dev
, 0);
698 intel_finish_page_flip_plane(dev
, 0);
701 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
702 intel_prepare_page_flip(dev
, 1);
703 intel_finish_page_flip_plane(dev
, 1);
706 if (de_iir
& DE_PIPEA_VBLANK
)
707 drm_handle_vblank(dev
, 0);
709 if (de_iir
& DE_PIPEB_VBLANK
)
710 drm_handle_vblank(dev
, 1);
712 /* check event from PCH */
713 if (de_iir
& DE_PCH_EVENT
) {
714 if (pch_iir
& hotplug_mask
)
715 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
716 pch_irq_handler(dev
);
719 if (de_iir
& DE_PCU_EVENT
) {
720 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
721 i915_handle_rps_change(dev
);
724 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
725 gen6_queue_rps_work(dev_priv
, pm_iir
);
727 /* should clear PCH hotplug event before clear CPU irq */
728 I915_WRITE(SDEIIR
, pch_iir
);
729 I915_WRITE(GTIIR
, gt_iir
);
730 I915_WRITE(DEIIR
, de_iir
);
731 I915_WRITE(GEN6_PMIIR
, pm_iir
);
734 I915_WRITE(DEIER
, de_ier
);
741 * i915_error_work_func - do process context error handling work
744 * Fire an error uevent so userspace can see that a hang or error
747 static void i915_error_work_func(struct work_struct
*work
)
749 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
751 struct drm_device
*dev
= dev_priv
->dev
;
752 char *error_event
[] = { "ERROR=1", NULL
};
753 char *reset_event
[] = { "RESET=1", NULL
};
754 char *reset_done_event
[] = { "ERROR=0", NULL
};
756 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
758 if (atomic_read(&dev_priv
->mm
.wedged
)) {
759 DRM_DEBUG_DRIVER("resetting chip\n");
760 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_event
);
761 if (!i915_reset(dev
, GRDOM_RENDER
)) {
762 atomic_set(&dev_priv
->mm
.wedged
, 0);
763 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_done_event
);
765 complete_all(&dev_priv
->error_completion
);
769 #ifdef CONFIG_DEBUG_FS
770 static struct drm_i915_error_object
*
771 i915_error_object_create(struct drm_i915_private
*dev_priv
,
772 struct drm_i915_gem_object
*src
)
774 struct drm_i915_error_object
*dst
;
775 int page
, page_count
;
778 if (src
== NULL
|| src
->pages
== NULL
)
781 page_count
= src
->base
.size
/ PAGE_SIZE
;
783 dst
= kmalloc(sizeof(*dst
) + page_count
* sizeof(u32
*), GFP_ATOMIC
);
787 reloc_offset
= src
->gtt_offset
;
788 for (page
= 0; page
< page_count
; page
++) {
792 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
796 local_irq_save(flags
);
797 if (reloc_offset
< dev_priv
->mm
.gtt_mappable_end
&&
798 src
->has_global_gtt_mapping
) {
801 /* Simply ignore tiling or any overlapping fence.
802 * It's part of the error state, and this hopefully
803 * captures what the GPU read.
806 s
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
808 memcpy_fromio(d
, s
, PAGE_SIZE
);
809 io_mapping_unmap_atomic(s
);
813 drm_clflush_pages(&src
->pages
[page
], 1);
815 s
= kmap_atomic(src
->pages
[page
]);
816 memcpy(d
, s
, PAGE_SIZE
);
819 drm_clflush_pages(&src
->pages
[page
], 1);
821 local_irq_restore(flags
);
823 dst
->pages
[page
] = d
;
825 reloc_offset
+= PAGE_SIZE
;
827 dst
->page_count
= page_count
;
828 dst
->gtt_offset
= src
->gtt_offset
;
834 kfree(dst
->pages
[page
]);
840 i915_error_object_free(struct drm_i915_error_object
*obj
)
847 for (page
= 0; page
< obj
->page_count
; page
++)
848 kfree(obj
->pages
[page
]);
854 i915_error_state_free(struct drm_device
*dev
,
855 struct drm_i915_error_state
*error
)
859 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
860 i915_error_object_free(error
->ring
[i
].batchbuffer
);
861 i915_error_object_free(error
->ring
[i
].ringbuffer
);
862 kfree(error
->ring
[i
].requests
);
865 kfree(error
->active_bo
);
866 kfree(error
->overlay
);
869 static void capture_bo(struct drm_i915_error_buffer
*err
,
870 struct drm_i915_gem_object
*obj
)
872 err
->size
= obj
->base
.size
;
873 err
->name
= obj
->base
.name
;
874 err
->seqno
= obj
->last_rendering_seqno
;
875 err
->gtt_offset
= obj
->gtt_offset
;
876 err
->read_domains
= obj
->base
.read_domains
;
877 err
->write_domain
= obj
->base
.write_domain
;
878 err
->fence_reg
= obj
->fence_reg
;
880 if (obj
->pin_count
> 0)
882 if (obj
->user_pin_count
> 0)
884 err
->tiling
= obj
->tiling_mode
;
885 err
->dirty
= obj
->dirty
;
886 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
887 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
888 err
->cache_level
= obj
->cache_level
;
891 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
892 int count
, struct list_head
*head
)
894 struct drm_i915_gem_object
*obj
;
897 list_for_each_entry(obj
, head
, mm_list
) {
898 capture_bo(err
++, obj
);
906 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
907 int count
, struct list_head
*head
)
909 struct drm_i915_gem_object
*obj
;
912 list_for_each_entry(obj
, head
, gtt_list
) {
913 if (obj
->pin_count
== 0)
916 capture_bo(err
++, obj
);
924 static void i915_gem_record_fences(struct drm_device
*dev
,
925 struct drm_i915_error_state
*error
)
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
931 switch (INTEL_INFO(dev
)->gen
) {
934 for (i
= 0; i
< 16; i
++)
935 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
939 for (i
= 0; i
< 16; i
++)
940 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
943 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
944 for (i
= 0; i
< 8; i
++)
945 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
947 for (i
= 0; i
< 8; i
++)
948 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
954 static struct drm_i915_error_object
*
955 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
956 struct intel_ring_buffer
*ring
)
958 struct drm_i915_gem_object
*obj
;
961 if (!ring
->get_seqno
)
964 seqno
= ring
->get_seqno(ring
);
965 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
966 if (obj
->ring
!= ring
)
969 if (i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
972 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
975 /* We need to copy these to an anonymous buffer as the simplest
976 * method to avoid being overwritten by userspace.
978 return i915_error_object_create(dev_priv
, obj
);
984 static void i915_record_ring_state(struct drm_device
*dev
,
985 struct drm_i915_error_state
*error
,
986 struct intel_ring_buffer
*ring
)
988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
990 if (INTEL_INFO(dev
)->gen
>= 6) {
991 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
992 error
->semaphore_mboxes
[ring
->id
][0]
993 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
994 error
->semaphore_mboxes
[ring
->id
][1]
995 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
998 if (INTEL_INFO(dev
)->gen
>= 4) {
999 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1000 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1001 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1002 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1003 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1004 if (ring
->id
== RCS
) {
1005 error
->instdone1
= I915_READ(INSTDONE1
);
1006 error
->bbaddr
= I915_READ64(BB_ADDR
);
1009 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1010 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1011 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1012 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1015 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1016 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1017 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
);
1018 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1019 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1020 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1022 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1023 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1026 static void i915_gem_record_rings(struct drm_device
*dev
,
1027 struct drm_i915_error_state
*error
)
1029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1030 struct drm_i915_gem_request
*request
;
1033 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1034 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1036 if (ring
->obj
== NULL
)
1039 i915_record_ring_state(dev
, error
, ring
);
1041 error
->ring
[i
].batchbuffer
=
1042 i915_error_first_batchbuffer(dev_priv
, ring
);
1044 error
->ring
[i
].ringbuffer
=
1045 i915_error_object_create(dev_priv
, ring
->obj
);
1048 list_for_each_entry(request
, &ring
->request_list
, list
)
1051 error
->ring
[i
].num_requests
= count
;
1052 error
->ring
[i
].requests
=
1053 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1055 if (error
->ring
[i
].requests
== NULL
) {
1056 error
->ring
[i
].num_requests
= 0;
1061 list_for_each_entry(request
, &ring
->request_list
, list
) {
1062 struct drm_i915_error_request
*erq
;
1064 erq
= &error
->ring
[i
].requests
[count
++];
1065 erq
->seqno
= request
->seqno
;
1066 erq
->jiffies
= request
->emitted_jiffies
;
1067 erq
->tail
= request
->tail
;
1073 * i915_capture_error_state - capture an error record for later analysis
1076 * Should be called when an error is detected (either a hang or an error
1077 * interrupt) to capture error state from the time of the error. Fills
1078 * out a structure which becomes available in debugfs for user level tools
1081 static void i915_capture_error_state(struct drm_device
*dev
)
1083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1084 struct drm_i915_gem_object
*obj
;
1085 struct drm_i915_error_state
*error
;
1086 unsigned long flags
;
1089 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1090 error
= dev_priv
->first_error
;
1091 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1095 /* Account for pipe specific data like PIPE*STAT */
1096 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1098 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1102 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1103 dev
->primary
->index
);
1105 error
->eir
= I915_READ(EIR
);
1106 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1108 if (HAS_PCH_SPLIT(dev
))
1109 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1110 else if (IS_VALLEYVIEW(dev
))
1111 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1112 else if (IS_GEN2(dev
))
1113 error
->ier
= I915_READ16(IER
);
1115 error
->ier
= I915_READ(IER
);
1118 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1120 if (INTEL_INFO(dev
)->gen
>= 6) {
1121 error
->error
= I915_READ(ERROR_GEN6
);
1122 error
->done_reg
= I915_READ(DONE_REG
);
1125 i915_gem_record_fences(dev
, error
);
1126 i915_gem_record_rings(dev
, error
);
1128 /* Record buffers on the active and pinned lists. */
1129 error
->active_bo
= NULL
;
1130 error
->pinned_bo
= NULL
;
1133 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1135 error
->active_bo_count
= i
;
1136 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
)
1139 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1141 error
->active_bo
= NULL
;
1142 error
->pinned_bo
= NULL
;
1144 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1146 if (error
->active_bo
)
1148 error
->active_bo
+ error
->active_bo_count
;
1151 if (error
->active_bo
)
1152 error
->active_bo_count
=
1153 capture_active_bo(error
->active_bo
,
1154 error
->active_bo_count
,
1155 &dev_priv
->mm
.active_list
);
1157 if (error
->pinned_bo
)
1158 error
->pinned_bo_count
=
1159 capture_pinned_bo(error
->pinned_bo
,
1160 error
->pinned_bo_count
,
1161 &dev_priv
->mm
.gtt_list
);
1163 do_gettimeofday(&error
->time
);
1165 error
->overlay
= intel_overlay_capture_error_state(dev
);
1166 error
->display
= intel_display_capture_error_state(dev
);
1168 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1169 if (dev_priv
->first_error
== NULL
) {
1170 dev_priv
->first_error
= error
;
1173 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1176 i915_error_state_free(dev
, error
);
1179 void i915_destroy_error_state(struct drm_device
*dev
)
1181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1182 struct drm_i915_error_state
*error
;
1183 unsigned long flags
;
1185 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1186 error
= dev_priv
->first_error
;
1187 dev_priv
->first_error
= NULL
;
1188 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1191 i915_error_state_free(dev
, error
);
1194 #define i915_capture_error_state(x)
1197 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 u32 eir
= I915_READ(EIR
);
1206 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1209 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1210 u32 ipeir
= I915_READ(IPEIR_I965
);
1212 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1213 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1214 pr_err(" INSTDONE: 0x%08x\n",
1215 I915_READ(INSTDONE_I965
));
1216 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1217 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1
));
1218 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1219 I915_WRITE(IPEIR_I965
, ipeir
);
1220 POSTING_READ(IPEIR_I965
);
1222 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1223 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1224 pr_err("page table error\n");
1225 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1226 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1227 POSTING_READ(PGTBL_ER
);
1231 if (!IS_GEN2(dev
)) {
1232 if (eir
& I915_ERROR_PAGE_TABLE
) {
1233 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1234 pr_err("page table error\n");
1235 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1236 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1237 POSTING_READ(PGTBL_ER
);
1241 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1242 pr_err("memory refresh error:\n");
1244 pr_err("pipe %c stat: 0x%08x\n",
1245 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1246 /* pipestat has already been acked */
1248 if (eir
& I915_ERROR_INSTRUCTION
) {
1249 pr_err("instruction error\n");
1250 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1251 if (INTEL_INFO(dev
)->gen
< 4) {
1252 u32 ipeir
= I915_READ(IPEIR
);
1254 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1255 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1256 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE
));
1257 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1258 I915_WRITE(IPEIR
, ipeir
);
1259 POSTING_READ(IPEIR
);
1261 u32 ipeir
= I915_READ(IPEIR_I965
);
1263 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1264 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1265 pr_err(" INSTDONE: 0x%08x\n",
1266 I915_READ(INSTDONE_I965
));
1267 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1268 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1
));
1269 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1270 I915_WRITE(IPEIR_I965
, ipeir
);
1271 POSTING_READ(IPEIR_I965
);
1275 I915_WRITE(EIR
, eir
);
1277 eir
= I915_READ(EIR
);
1280 * some errors might have become stuck,
1283 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1284 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1285 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1290 * i915_handle_error - handle an error interrupt
1293 * Do some basic checking of regsiter state at error interrupt time and
1294 * dump it to the syslog. Also call i915_capture_error_state() to make
1295 * sure we get a record and make it available in debugfs. Fire a uevent
1296 * so userspace knows something bad happened (should trigger collection
1297 * of a ring dump etc.).
1299 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1303 i915_capture_error_state(dev
);
1304 i915_report_and_clear_eir(dev
);
1307 INIT_COMPLETION(dev_priv
->error_completion
);
1308 atomic_set(&dev_priv
->mm
.wedged
, 1);
1311 * Wakeup waiting processes so they don't hang
1313 wake_up_all(&dev_priv
->ring
[RCS
].irq_queue
);
1315 wake_up_all(&dev_priv
->ring
[VCS
].irq_queue
);
1317 wake_up_all(&dev_priv
->ring
[BCS
].irq_queue
);
1320 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
1323 static void i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1325 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1326 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1327 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1328 struct drm_i915_gem_object
*obj
;
1329 struct intel_unpin_work
*work
;
1330 unsigned long flags
;
1331 bool stall_detected
;
1333 /* Ignore early vblank irqs */
1334 if (intel_crtc
== NULL
)
1337 spin_lock_irqsave(&dev
->event_lock
, flags
);
1338 work
= intel_crtc
->unpin_work
;
1340 if (work
== NULL
|| work
->pending
|| !work
->enable_stall_check
) {
1341 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1342 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1346 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1347 obj
= work
->pending_flip_obj
;
1348 if (INTEL_INFO(dev
)->gen
>= 4) {
1349 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1350 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1353 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1354 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
1355 crtc
->y
* crtc
->fb
->pitches
[0] +
1356 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1359 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1361 if (stall_detected
) {
1362 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1363 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1367 /* Called from drm generic code, passed 'crtc' which
1368 * we use as a pipe index
1370 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1372 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1373 unsigned long irqflags
;
1375 if (!i915_pipe_enabled(dev
, pipe
))
1378 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1379 if (INTEL_INFO(dev
)->gen
>= 4)
1380 i915_enable_pipestat(dev_priv
, pipe
,
1381 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1383 i915_enable_pipestat(dev_priv
, pipe
,
1384 PIPE_VBLANK_INTERRUPT_ENABLE
);
1386 /* maintain vblank delivery even in deep C-states */
1387 if (dev_priv
->info
->gen
== 3)
1388 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1389 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1394 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1396 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1397 unsigned long irqflags
;
1399 if (!i915_pipe_enabled(dev
, pipe
))
1402 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1403 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1404 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1405 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1410 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1412 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1413 unsigned long irqflags
;
1415 if (!i915_pipe_enabled(dev
, pipe
))
1418 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1419 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1420 DE_PIPEA_VBLANK_IVB
: DE_PIPEB_VBLANK_IVB
);
1421 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1426 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1428 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1429 unsigned long irqflags
;
1432 if (!i915_pipe_enabled(dev
, pipe
))
1435 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1436 dpfl
= I915_READ(VLV_DPFLIPSTAT
);
1437 imr
= I915_READ(VLV_IMR
);
1439 dpfl
|= PIPEA_VBLANK_INT_EN
;
1440 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1442 dpfl
|= PIPEA_VBLANK_INT_EN
;
1443 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1445 I915_WRITE(VLV_DPFLIPSTAT
, dpfl
);
1446 I915_WRITE(VLV_IMR
, imr
);
1447 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1452 /* Called from drm generic code, passed 'crtc' which
1453 * we use as a pipe index
1455 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1457 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1458 unsigned long irqflags
;
1460 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1461 if (dev_priv
->info
->gen
== 3)
1462 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1464 i915_disable_pipestat(dev_priv
, pipe
,
1465 PIPE_VBLANK_INTERRUPT_ENABLE
|
1466 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1467 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1470 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1472 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1473 unsigned long irqflags
;
1475 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1476 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1477 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1478 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1481 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1483 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1484 unsigned long irqflags
;
1486 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1487 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1488 DE_PIPEA_VBLANK_IVB
: DE_PIPEB_VBLANK_IVB
);
1489 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1492 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1494 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1495 unsigned long irqflags
;
1498 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1499 dpfl
= I915_READ(VLV_DPFLIPSTAT
);
1500 imr
= I915_READ(VLV_IMR
);
1502 dpfl
&= ~PIPEA_VBLANK_INT_EN
;
1503 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1505 dpfl
&= ~PIPEB_VBLANK_INT_EN
;
1506 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1508 I915_WRITE(VLV_IMR
, imr
);
1509 I915_WRITE(VLV_DPFLIPSTAT
, dpfl
);
1510 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1514 ring_last_seqno(struct intel_ring_buffer
*ring
)
1516 return list_entry(ring
->request_list
.prev
,
1517 struct drm_i915_gem_request
, list
)->seqno
;
1520 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
1522 /* We don't check whether the ring even exists before calling this
1523 * function. Hence check whether it's initialized. */
1524 if (ring
->obj
== NULL
)
1527 if (list_empty(&ring
->request_list
) ||
1528 i915_seqno_passed(ring
->get_seqno(ring
), ring_last_seqno(ring
))) {
1529 /* Issue a wake-up to catch stuck h/w. */
1530 if (waitqueue_active(&ring
->irq_queue
)) {
1531 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1533 wake_up_all(&ring
->irq_queue
);
1541 static bool kick_ring(struct intel_ring_buffer
*ring
)
1543 struct drm_device
*dev
= ring
->dev
;
1544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1545 u32 tmp
= I915_READ_CTL(ring
);
1546 if (tmp
& RING_WAIT
) {
1547 DRM_ERROR("Kicking stuck wait on %s\n",
1549 I915_WRITE_CTL(ring
, tmp
);
1555 static bool i915_hangcheck_hung(struct drm_device
*dev
)
1557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1559 if (dev_priv
->hangcheck_count
++ > 1) {
1560 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1561 i915_handle_error(dev
, true);
1563 if (!IS_GEN2(dev
)) {
1564 /* Is the chip hanging on a WAIT_FOR_EVENT?
1565 * If so we can simply poke the RB_WAIT bit
1566 * and break the hang. This should work on
1567 * all but the second generation chipsets.
1569 if (kick_ring(&dev_priv
->ring
[RCS
]))
1572 if (HAS_BSD(dev
) && kick_ring(&dev_priv
->ring
[VCS
]))
1575 if (HAS_BLT(dev
) && kick_ring(&dev_priv
->ring
[BCS
]))
1586 * This is called when the chip hasn't reported back with completed
1587 * batchbuffers in a long time. The first time this is called we simply record
1588 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1589 * again, we assume the chip is wedged and try to fix it.
1591 void i915_hangcheck_elapsed(unsigned long data
)
1593 struct drm_device
*dev
= (struct drm_device
*)data
;
1594 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1595 uint32_t acthd
, instdone
, instdone1
, acthd_bsd
, acthd_blt
;
1598 if (!i915_enable_hangcheck
)
1601 /* If all work is done then ACTHD clearly hasn't advanced. */
1602 if (i915_hangcheck_ring_idle(&dev_priv
->ring
[RCS
], &err
) &&
1603 i915_hangcheck_ring_idle(&dev_priv
->ring
[VCS
], &err
) &&
1604 i915_hangcheck_ring_idle(&dev_priv
->ring
[BCS
], &err
)) {
1606 if (i915_hangcheck_hung(dev
))
1612 dev_priv
->hangcheck_count
= 0;
1616 if (INTEL_INFO(dev
)->gen
< 4) {
1617 instdone
= I915_READ(INSTDONE
);
1620 instdone
= I915_READ(INSTDONE_I965
);
1621 instdone1
= I915_READ(INSTDONE1
);
1623 acthd
= intel_ring_get_active_head(&dev_priv
->ring
[RCS
]);
1624 acthd_bsd
= HAS_BSD(dev
) ?
1625 intel_ring_get_active_head(&dev_priv
->ring
[VCS
]) : 0;
1626 acthd_blt
= HAS_BLT(dev
) ?
1627 intel_ring_get_active_head(&dev_priv
->ring
[BCS
]) : 0;
1629 if (dev_priv
->last_acthd
== acthd
&&
1630 dev_priv
->last_acthd_bsd
== acthd_bsd
&&
1631 dev_priv
->last_acthd_blt
== acthd_blt
&&
1632 dev_priv
->last_instdone
== instdone
&&
1633 dev_priv
->last_instdone1
== instdone1
) {
1634 if (i915_hangcheck_hung(dev
))
1637 dev_priv
->hangcheck_count
= 0;
1639 dev_priv
->last_acthd
= acthd
;
1640 dev_priv
->last_acthd_bsd
= acthd_bsd
;
1641 dev_priv
->last_acthd_blt
= acthd_blt
;
1642 dev_priv
->last_instdone
= instdone
;
1643 dev_priv
->last_instdone1
= instdone1
;
1647 /* Reset timer case chip hangs without another request being added */
1648 mod_timer(&dev_priv
->hangcheck_timer
,
1649 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1654 static void ironlake_irq_preinstall(struct drm_device
*dev
)
1656 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1658 atomic_set(&dev_priv
->irq_received
, 0);
1661 I915_WRITE(HWSTAM
, 0xeffe);
1663 /* XXX hotplug from PCH */
1665 I915_WRITE(DEIMR
, 0xffffffff);
1666 I915_WRITE(DEIER
, 0x0);
1667 POSTING_READ(DEIER
);
1670 I915_WRITE(GTIMR
, 0xffffffff);
1671 I915_WRITE(GTIER
, 0x0);
1672 POSTING_READ(GTIER
);
1674 /* south display irq */
1675 I915_WRITE(SDEIMR
, 0xffffffff);
1676 I915_WRITE(SDEIER
, 0x0);
1677 POSTING_READ(SDEIER
);
1680 static void valleyview_irq_preinstall(struct drm_device
*dev
)
1682 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1685 atomic_set(&dev_priv
->irq_received
, 0);
1688 I915_WRITE(VLV_IMR
, 0);
1689 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
1690 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
1691 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
1694 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1695 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1696 I915_WRITE(GTIMR
, 0xffffffff);
1697 I915_WRITE(GTIER
, 0x0);
1698 POSTING_READ(GTIER
);
1700 I915_WRITE(DPINVGTT
, 0xff);
1702 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1703 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1705 I915_WRITE(PIPESTAT(pipe
), 0xffff);
1706 I915_WRITE(VLV_IIR
, 0xffffffff);
1707 I915_WRITE(VLV_IMR
, 0xffffffff);
1708 I915_WRITE(VLV_IER
, 0x0);
1709 POSTING_READ(VLV_IER
);
1713 * Enable digital hotplug on the PCH, and configure the DP short pulse
1714 * duration to 2ms (which is the minimum in the Display Port spec)
1716 * This register is the same on all known PCH chips.
1719 static void ironlake_enable_pch_hotplug(struct drm_device
*dev
)
1721 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1724 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
1725 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
1726 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
1727 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
1728 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
1729 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
1732 static int ironlake_irq_postinstall(struct drm_device
*dev
)
1734 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1735 /* enable kind of interrupts always enabled */
1736 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
1737 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
;
1741 dev_priv
->irq_mask
= ~display_mask
;
1743 /* should always can generate irq */
1744 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1745 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1746 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
1747 POSTING_READ(DEIER
);
1749 dev_priv
->gt_irq_mask
= ~0;
1751 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1752 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1757 GEN6_BSD_USER_INTERRUPT
|
1758 GEN6_BLITTER_USER_INTERRUPT
;
1763 GT_BSD_USER_INTERRUPT
;
1764 I915_WRITE(GTIER
, render_irqs
);
1765 POSTING_READ(GTIER
);
1767 if (HAS_PCH_CPT(dev
)) {
1768 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1769 SDE_PORTB_HOTPLUG_CPT
|
1770 SDE_PORTC_HOTPLUG_CPT
|
1771 SDE_PORTD_HOTPLUG_CPT
);
1773 hotplug_mask
= (SDE_CRT_HOTPLUG
|
1780 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1782 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1783 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1784 I915_WRITE(SDEIER
, hotplug_mask
);
1785 POSTING_READ(SDEIER
);
1787 ironlake_enable_pch_hotplug(dev
);
1789 if (IS_IRONLAKE_M(dev
)) {
1790 /* Clear & enable PCU event interrupts */
1791 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
1792 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
1793 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
1799 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
1801 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1802 /* enable kind of interrupts always enabled */
1803 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
1804 DE_PCH_EVENT_IVB
| DE_PLANEA_FLIP_DONE_IVB
|
1805 DE_PLANEB_FLIP_DONE_IVB
;
1809 dev_priv
->irq_mask
= ~display_mask
;
1811 /* should always can generate irq */
1812 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1813 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1814 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK_IVB
|
1815 DE_PIPEB_VBLANK_IVB
);
1816 POSTING_READ(DEIER
);
1818 dev_priv
->gt_irq_mask
= ~0;
1820 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1821 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1823 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
1824 GEN6_BLITTER_USER_INTERRUPT
;
1825 I915_WRITE(GTIER
, render_irqs
);
1826 POSTING_READ(GTIER
);
1828 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1829 SDE_PORTB_HOTPLUG_CPT
|
1830 SDE_PORTC_HOTPLUG_CPT
|
1831 SDE_PORTD_HOTPLUG_CPT
);
1832 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1834 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1835 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1836 I915_WRITE(SDEIER
, hotplug_mask
);
1837 POSTING_READ(SDEIER
);
1839 ironlake_enable_pch_hotplug(dev
);
1844 static int valleyview_irq_postinstall(struct drm_device
*dev
)
1846 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1849 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1852 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
1853 enable_mask
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
1854 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1856 dev_priv
->irq_mask
= ~enable_mask
;
1858 dev_priv
->pipestat
[0] = 0;
1859 dev_priv
->pipestat
[1] = 0;
1861 /* Hack for broken MSIs on VLV */
1862 pci_write_config_dword(dev_priv
->dev
->pdev
, 0x94, 0xfee00000);
1863 pci_read_config_word(dev
->pdev
, 0x98, &msid
);
1864 msid
&= 0xff; /* mask out delivery bits */
1866 pci_write_config_word(dev_priv
->dev
->pdev
, 0x98, msid
);
1868 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
1869 I915_WRITE(VLV_IER
, enable_mask
);
1870 I915_WRITE(VLV_IIR
, 0xffffffff);
1871 I915_WRITE(PIPESTAT(0), 0xffff);
1872 I915_WRITE(PIPESTAT(1), 0xffff);
1873 POSTING_READ(VLV_IER
);
1875 I915_WRITE(VLV_IIR
, 0xffffffff);
1876 I915_WRITE(VLV_IIR
, 0xffffffff);
1878 render_irqs
= GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT
|
1879 GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
1880 GT_GEN6_BLT_USER_INTERRUPT
|
1881 GT_GEN6_BSD_USER_INTERRUPT
|
1882 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
1883 GT_GEN7_L3_PARITY_ERROR_INTERRUPT
|
1885 GT_RENDER_CS_ERROR_INTERRUPT
|
1889 dev_priv
->gt_irq_mask
= ~render_irqs
;
1891 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1892 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1893 I915_WRITE(GTIMR
, 0);
1894 I915_WRITE(GTIER
, render_irqs
);
1895 POSTING_READ(GTIER
);
1897 /* ack & enable invalid PTE error interrupts */
1898 #if 0 /* FIXME: add support to irq handler for checking these bits */
1899 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
1900 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
1903 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1904 #if 0 /* FIXME: check register definitions; some have moved */
1905 /* Note HDMI and DP share bits */
1906 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
1907 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
1908 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
1909 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
1910 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
1911 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
1912 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
1913 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
1914 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
1915 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
1916 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
1917 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
1918 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
1922 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
1927 static void valleyview_irq_uninstall(struct drm_device
*dev
)
1929 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1936 I915_WRITE(PIPESTAT(pipe
), 0xffff);
1938 I915_WRITE(HWSTAM
, 0xffffffff);
1939 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1940 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1942 I915_WRITE(PIPESTAT(pipe
), 0xffff);
1943 I915_WRITE(VLV_IIR
, 0xffffffff);
1944 I915_WRITE(VLV_IMR
, 0xffffffff);
1945 I915_WRITE(VLV_IER
, 0x0);
1946 POSTING_READ(VLV_IER
);
1949 static void ironlake_irq_uninstall(struct drm_device
*dev
)
1951 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1956 I915_WRITE(HWSTAM
, 0xffffffff);
1958 I915_WRITE(DEIMR
, 0xffffffff);
1959 I915_WRITE(DEIER
, 0x0);
1960 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1962 I915_WRITE(GTIMR
, 0xffffffff);
1963 I915_WRITE(GTIER
, 0x0);
1964 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1966 I915_WRITE(SDEIMR
, 0xffffffff);
1967 I915_WRITE(SDEIER
, 0x0);
1968 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1971 static void i8xx_irq_preinstall(struct drm_device
* dev
)
1973 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1976 atomic_set(&dev_priv
->irq_received
, 0);
1979 I915_WRITE(PIPESTAT(pipe
), 0);
1980 I915_WRITE16(IMR
, 0xffff);
1981 I915_WRITE16(IER
, 0x0);
1982 POSTING_READ16(IER
);
1985 static int i8xx_irq_postinstall(struct drm_device
*dev
)
1987 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1989 dev_priv
->pipestat
[0] = 0;
1990 dev_priv
->pipestat
[1] = 0;
1993 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
1995 /* Unmask the interrupts that we always want on. */
1996 dev_priv
->irq_mask
=
1997 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
1998 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
1999 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2000 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2001 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2002 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2005 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2006 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2007 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2008 I915_USER_INTERRUPT
);
2009 POSTING_READ16(IER
);
2014 static irqreturn_t
i8xx_irq_handler(DRM_IRQ_ARGS
)
2016 struct drm_device
*dev
= (struct drm_device
*) arg
;
2017 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2020 unsigned long irqflags
;
2024 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2025 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2027 atomic_inc(&dev_priv
->irq_received
);
2029 iir
= I915_READ16(IIR
);
2033 while (iir
& ~flip_mask
) {
2034 /* Can't rely on pipestat interrupt bit in iir as it might
2035 * have been cleared after the pipestat interrupt was received.
2036 * It doesn't set the bit in iir again, but it still produces
2037 * interrupts (for non-MSI).
2039 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2040 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2041 i915_handle_error(dev
, false);
2043 for_each_pipe(pipe
) {
2044 int reg
= PIPESTAT(pipe
);
2045 pipe_stats
[pipe
] = I915_READ(reg
);
2048 * Clear the PIPE*STAT regs before the IIR
2050 if (pipe_stats
[pipe
] & 0x8000ffff) {
2051 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2052 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2054 I915_WRITE(reg
, pipe_stats
[pipe
]);
2058 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2060 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2061 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2063 i915_update_dri1_breadcrumb(dev
);
2065 if (iir
& I915_USER_INTERRUPT
)
2066 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2068 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2069 drm_handle_vblank(dev
, 0)) {
2070 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
) {
2071 intel_prepare_page_flip(dev
, 0);
2072 intel_finish_page_flip(dev
, 0);
2073 flip_mask
&= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
;
2077 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2078 drm_handle_vblank(dev
, 1)) {
2079 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
) {
2080 intel_prepare_page_flip(dev
, 1);
2081 intel_finish_page_flip(dev
, 1);
2082 flip_mask
&= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2092 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2094 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2097 for_each_pipe(pipe
) {
2098 /* Clear enable bits; then clear status bits */
2099 I915_WRITE(PIPESTAT(pipe
), 0);
2100 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2102 I915_WRITE16(IMR
, 0xffff);
2103 I915_WRITE16(IER
, 0x0);
2104 I915_WRITE16(IIR
, I915_READ16(IIR
));
2107 static void i915_irq_preinstall(struct drm_device
* dev
)
2109 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2112 atomic_set(&dev_priv
->irq_received
, 0);
2114 if (I915_HAS_HOTPLUG(dev
)) {
2115 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2116 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2119 I915_WRITE16(HWSTAM
, 0xeffe);
2121 I915_WRITE(PIPESTAT(pipe
), 0);
2122 I915_WRITE(IMR
, 0xffffffff);
2123 I915_WRITE(IER
, 0x0);
2127 static int i915_irq_postinstall(struct drm_device
*dev
)
2129 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2132 dev_priv
->pipestat
[0] = 0;
2133 dev_priv
->pipestat
[1] = 0;
2135 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2137 /* Unmask the interrupts that we always want on. */
2138 dev_priv
->irq_mask
=
2139 ~(I915_ASLE_INTERRUPT
|
2140 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2141 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2142 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2143 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2144 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2147 I915_ASLE_INTERRUPT
|
2148 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2149 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2150 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2151 I915_USER_INTERRUPT
;
2153 if (I915_HAS_HOTPLUG(dev
)) {
2154 /* Enable in IER... */
2155 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2156 /* and unmask in IMR */
2157 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2160 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2161 I915_WRITE(IER
, enable_mask
);
2164 if (I915_HAS_HOTPLUG(dev
)) {
2165 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2167 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2168 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2169 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2170 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2171 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2172 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2173 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
2174 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2175 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
2176 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2177 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2178 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2179 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2182 /* Ignore TV since it's buggy */
2184 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2187 intel_opregion_enable_asle(dev
);
2192 static irqreturn_t
i915_irq_handler(DRM_IRQ_ARGS
)
2194 struct drm_device
*dev
= (struct drm_device
*) arg
;
2195 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2196 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2197 unsigned long irqflags
;
2199 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2200 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2202 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
,
2203 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2205 int pipe
, ret
= IRQ_NONE
;
2207 atomic_inc(&dev_priv
->irq_received
);
2209 iir
= I915_READ(IIR
);
2211 bool irq_received
= (iir
& ~flip_mask
) != 0;
2212 bool blc_event
= false;
2214 /* Can't rely on pipestat interrupt bit in iir as it might
2215 * have been cleared after the pipestat interrupt was received.
2216 * It doesn't set the bit in iir again, but it still produces
2217 * interrupts (for non-MSI).
2219 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2220 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2221 i915_handle_error(dev
, false);
2223 for_each_pipe(pipe
) {
2224 int reg
= PIPESTAT(pipe
);
2225 pipe_stats
[pipe
] = I915_READ(reg
);
2227 /* Clear the PIPE*STAT regs before the IIR */
2228 if (pipe_stats
[pipe
] & 0x8000ffff) {
2229 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2230 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2232 I915_WRITE(reg
, pipe_stats
[pipe
]);
2233 irq_received
= true;
2236 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2241 /* Consume port. Then clear IIR or we'll miss events */
2242 if ((I915_HAS_HOTPLUG(dev
)) &&
2243 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2244 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2246 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2248 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2249 queue_work(dev_priv
->wq
,
2250 &dev_priv
->hotplug_work
);
2252 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2253 POSTING_READ(PORT_HOTPLUG_STAT
);
2256 I915_WRITE(IIR
, iir
& ~flip_mask
);
2257 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2259 if (iir
& I915_USER_INTERRUPT
)
2260 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2262 for_each_pipe(pipe
) {
2266 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2267 drm_handle_vblank(dev
, pipe
)) {
2268 if (iir
& flip
[plane
]) {
2269 intel_prepare_page_flip(dev
, plane
);
2270 intel_finish_page_flip(dev
, pipe
);
2271 flip_mask
&= ~flip
[plane
];
2275 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2279 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2280 intel_opregion_asle_intr(dev
);
2282 /* With MSI, interrupts are only generated when iir
2283 * transitions from zero to nonzero. If another bit got
2284 * set while we were handling the existing iir bits, then
2285 * we would never get another interrupt.
2287 * This is fine on non-MSI as well, as if we hit this path
2288 * we avoid exiting the interrupt handler only to generate
2291 * Note that for MSI this could cause a stray interrupt report
2292 * if an interrupt landed in the time between writing IIR and
2293 * the posting read. This should be rare enough to never
2294 * trigger the 99% of 100,000 interrupts test for disabling
2299 } while (iir
& ~flip_mask
);
2301 i915_update_dri1_breadcrumb(dev
);
2306 static void i915_irq_uninstall(struct drm_device
* dev
)
2308 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2311 if (I915_HAS_HOTPLUG(dev
)) {
2312 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2313 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2316 I915_WRITE16(HWSTAM
, 0xffff);
2317 for_each_pipe(pipe
) {
2318 /* Clear enable bits; then clear status bits */
2319 I915_WRITE(PIPESTAT(pipe
), 0);
2320 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2322 I915_WRITE(IMR
, 0xffffffff);
2323 I915_WRITE(IER
, 0x0);
2325 I915_WRITE(IIR
, I915_READ(IIR
));
2328 static void i965_irq_preinstall(struct drm_device
* dev
)
2330 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2333 atomic_set(&dev_priv
->irq_received
, 0);
2335 if (I915_HAS_HOTPLUG(dev
)) {
2336 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2337 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2340 I915_WRITE(HWSTAM
, 0xeffe);
2342 I915_WRITE(PIPESTAT(pipe
), 0);
2343 I915_WRITE(IMR
, 0xffffffff);
2344 I915_WRITE(IER
, 0x0);
2348 static int i965_irq_postinstall(struct drm_device
*dev
)
2350 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2354 /* Unmask the interrupts that we always want on. */
2355 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2356 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2358 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2359 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2360 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2362 enable_mask
= ~dev_priv
->irq_mask
;
2363 enable_mask
|= I915_USER_INTERRUPT
;
2366 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2368 dev_priv
->pipestat
[0] = 0;
2369 dev_priv
->pipestat
[1] = 0;
2371 if (I915_HAS_HOTPLUG(dev
)) {
2372 /* Enable in IER... */
2373 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2374 /* and unmask in IMR */
2375 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2379 * Enable some error detection, note the instruction error mask
2380 * bit is reserved, so we leave it masked.
2383 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2384 GM45_ERROR_MEM_PRIV
|
2385 GM45_ERROR_CP_PRIV
|
2386 I915_ERROR_MEMORY_REFRESH
);
2388 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2389 I915_ERROR_MEMORY_REFRESH
);
2391 I915_WRITE(EMR
, error_mask
);
2393 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2394 I915_WRITE(IER
, enable_mask
);
2397 if (I915_HAS_HOTPLUG(dev
)) {
2398 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2400 /* Note HDMI and DP share bits */
2401 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2402 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2403 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2404 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2405 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2406 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2407 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
2408 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2409 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
2410 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2411 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2412 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2414 /* Programming the CRT detection parameters tends
2415 to generate a spurious hotplug event about three
2416 seconds later. So just do it once.
2419 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2420 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2423 /* Ignore TV since it's buggy */
2425 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2428 intel_opregion_enable_asle(dev
);
2433 static irqreturn_t
i965_irq_handler(DRM_IRQ_ARGS
)
2435 struct drm_device
*dev
= (struct drm_device
*) arg
;
2436 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2438 u32 pipe_stats
[I915_MAX_PIPES
];
2439 unsigned long irqflags
;
2441 int ret
= IRQ_NONE
, pipe
;
2443 atomic_inc(&dev_priv
->irq_received
);
2445 iir
= I915_READ(IIR
);
2448 bool blc_event
= false;
2450 irq_received
= iir
!= 0;
2452 /* Can't rely on pipestat interrupt bit in iir as it might
2453 * have been cleared after the pipestat interrupt was received.
2454 * It doesn't set the bit in iir again, but it still produces
2455 * interrupts (for non-MSI).
2457 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2458 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2459 i915_handle_error(dev
, false);
2461 for_each_pipe(pipe
) {
2462 int reg
= PIPESTAT(pipe
);
2463 pipe_stats
[pipe
] = I915_READ(reg
);
2466 * Clear the PIPE*STAT regs before the IIR
2468 if (pipe_stats
[pipe
] & 0x8000ffff) {
2469 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2470 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2472 I915_WRITE(reg
, pipe_stats
[pipe
]);
2476 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2483 /* Consume port. Then clear IIR or we'll miss events */
2484 if ((I915_HAS_HOTPLUG(dev
)) &&
2485 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2486 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2488 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2490 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2491 queue_work(dev_priv
->wq
,
2492 &dev_priv
->hotplug_work
);
2494 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2495 I915_READ(PORT_HOTPLUG_STAT
);
2498 I915_WRITE(IIR
, iir
);
2499 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2501 if (iir
& I915_USER_INTERRUPT
)
2502 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2503 if (iir
& I915_BSD_USER_INTERRUPT
)
2504 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2506 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
)
2507 intel_prepare_page_flip(dev
, 0);
2509 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
)
2510 intel_prepare_page_flip(dev
, 1);
2512 for_each_pipe(pipe
) {
2513 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2514 drm_handle_vblank(dev
, pipe
)) {
2515 i915_pageflip_stall_check(dev
, pipe
);
2516 intel_finish_page_flip(dev
, pipe
);
2519 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2524 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2525 intel_opregion_asle_intr(dev
);
2527 /* With MSI, interrupts are only generated when iir
2528 * transitions from zero to nonzero. If another bit got
2529 * set while we were handling the existing iir bits, then
2530 * we would never get another interrupt.
2532 * This is fine on non-MSI as well, as if we hit this path
2533 * we avoid exiting the interrupt handler only to generate
2536 * Note that for MSI this could cause a stray interrupt report
2537 * if an interrupt landed in the time between writing IIR and
2538 * the posting read. This should be rare enough to never
2539 * trigger the 99% of 100,000 interrupts test for disabling
2545 i915_update_dri1_breadcrumb(dev
);
2550 static void i965_irq_uninstall(struct drm_device
* dev
)
2552 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2558 if (I915_HAS_HOTPLUG(dev
)) {
2559 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2560 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2563 I915_WRITE(HWSTAM
, 0xffffffff);
2565 I915_WRITE(PIPESTAT(pipe
), 0);
2566 I915_WRITE(IMR
, 0xffffffff);
2567 I915_WRITE(IER
, 0x0);
2570 I915_WRITE(PIPESTAT(pipe
),
2571 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2572 I915_WRITE(IIR
, I915_READ(IIR
));
2575 void intel_irq_init(struct drm_device
*dev
)
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2579 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
2580 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
2581 INIT_WORK(&dev_priv
->rps_work
, gen6_pm_rps_work
);
2583 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2584 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2585 if (IS_G4X(dev
) || IS_GEN5(dev
) || IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) ||
2586 IS_VALLEYVIEW(dev
)) {
2587 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2588 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2591 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
2592 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
2594 dev
->driver
->get_vblank_timestamp
= NULL
;
2595 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
2597 if (IS_VALLEYVIEW(dev
)) {
2598 dev
->driver
->irq_handler
= valleyview_irq_handler
;
2599 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
2600 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
2601 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
2602 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
2603 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
2604 } else if (IS_IVYBRIDGE(dev
)) {
2605 /* Share pre & uninstall handlers with ILK/SNB */
2606 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2607 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2608 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2609 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2610 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2611 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2612 } else if (HAS_PCH_SPLIT(dev
)) {
2613 dev
->driver
->irq_handler
= ironlake_irq_handler
;
2614 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2615 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
2616 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2617 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
2618 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
2620 if (INTEL_INFO(dev
)->gen
== 2) {
2621 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
2622 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
2623 dev
->driver
->irq_handler
= i8xx_irq_handler
;
2624 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
2625 } else if (INTEL_INFO(dev
)->gen
== 3) {
2626 /* IIR "flip pending" means done if this bit is set */
2627 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
2629 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
2630 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
2631 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
2632 dev
->driver
->irq_handler
= i915_irq_handler
;
2634 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
2635 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
2636 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
2637 dev
->driver
->irq_handler
= i965_irq_handler
;
2639 dev
->driver
->enable_vblank
= i915_enable_vblank
;
2640 dev
->driver
->disable_vblank
= i915_disable_vblank
;