1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ibx
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
56 static const u32 hpd_cpt
[] = {
57 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
58 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
59 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
60 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
61 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
64 static const u32 hpd_mask_i915
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
73 static const u32 hpd_status_g4x
[] = {
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
83 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
84 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
85 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
86 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
88 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
120 I915_WRITE((reg), 0xffffffff); \
122 I915_WRITE((reg), 0xffffffff); \
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
141 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
143 /* For display hotplug interrupt */
145 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
147 assert_spin_locked(&dev_priv
->irq_lock
);
149 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
152 if ((dev_priv
->irq_mask
& mask
) != 0) {
153 dev_priv
->irq_mask
&= ~mask
;
154 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
160 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
162 assert_spin_locked(&dev_priv
->irq_lock
);
164 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
167 if ((dev_priv
->irq_mask
& mask
) != mask
) {
168 dev_priv
->irq_mask
|= mask
;
169 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
180 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
181 uint32_t interrupt_mask
,
182 uint32_t enabled_irq_mask
)
184 assert_spin_locked(&dev_priv
->irq_lock
);
186 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
188 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
191 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
192 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
193 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
197 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
199 ilk_update_gt_irq(dev_priv
, mask
, mask
);
202 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
204 ilk_update_gt_irq(dev_priv
, mask
, 0);
207 static u32
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
209 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
212 static u32
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
214 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
217 static u32
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
219 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
223 * snb_update_pm_irq - update GEN6_PMIMR
224 * @dev_priv: driver private
225 * @interrupt_mask: mask of interrupt bits to update
226 * @enabled_irq_mask: mask of interrupt bits to enable
228 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
229 uint32_t interrupt_mask
,
230 uint32_t enabled_irq_mask
)
234 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
236 assert_spin_locked(&dev_priv
->irq_lock
);
238 new_val
= dev_priv
->pm_irq_mask
;
239 new_val
&= ~interrupt_mask
;
240 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
242 if (new_val
!= dev_priv
->pm_irq_mask
) {
243 dev_priv
->pm_irq_mask
= new_val
;
244 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
245 POSTING_READ(gen6_pm_imr(dev_priv
));
249 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
251 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
254 snb_update_pm_irq(dev_priv
, mask
, mask
);
257 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
260 snb_update_pm_irq(dev_priv
, mask
, 0);
263 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
265 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
268 __gen6_disable_pm_irq(dev_priv
, mask
);
271 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
274 uint32_t reg
= gen6_pm_iir(dev_priv
);
276 spin_lock_irq(&dev_priv
->irq_lock
);
277 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
278 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
280 spin_unlock_irq(&dev_priv
->irq_lock
);
283 void gen6_enable_rps_interrupts(struct drm_device
*dev
)
285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
287 spin_lock_irq(&dev_priv
->irq_lock
);
289 WARN_ON(dev_priv
->rps
.pm_iir
);
290 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
291 dev_priv
->rps
.interrupts_enabled
= true;
292 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
293 dev_priv
->pm_rps_events
);
294 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
296 spin_unlock_irq(&dev_priv
->irq_lock
);
299 void gen6_disable_rps_interrupts(struct drm_device
*dev
)
301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
303 spin_lock_irq(&dev_priv
->irq_lock
);
304 dev_priv
->rps
.interrupts_enabled
= false;
305 spin_unlock_irq(&dev_priv
->irq_lock
);
307 cancel_work_sync(&dev_priv
->rps
.work
);
309 spin_lock_irq(&dev_priv
->irq_lock
);
311 I915_WRITE(GEN6_PMINTRMSK
, INTEL_INFO(dev_priv
)->gen
>= 8 ?
312 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
: ~0);
314 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
315 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
316 ~dev_priv
->pm_rps_events
);
317 I915_WRITE(gen6_pm_iir(dev_priv
), dev_priv
->pm_rps_events
);
318 I915_WRITE(gen6_pm_iir(dev_priv
), dev_priv
->pm_rps_events
);
320 dev_priv
->rps
.pm_iir
= 0;
322 spin_unlock_irq(&dev_priv
->irq_lock
);
326 * ibx_display_interrupt_update - update SDEIMR
327 * @dev_priv: driver private
328 * @interrupt_mask: mask of interrupt bits to update
329 * @enabled_irq_mask: mask of interrupt bits to enable
331 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
332 uint32_t interrupt_mask
,
333 uint32_t enabled_irq_mask
)
335 uint32_t sdeimr
= I915_READ(SDEIMR
);
336 sdeimr
&= ~interrupt_mask
;
337 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
339 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
341 assert_spin_locked(&dev_priv
->irq_lock
);
343 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
346 I915_WRITE(SDEIMR
, sdeimr
);
347 POSTING_READ(SDEIMR
);
351 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
352 u32 enable_mask
, u32 status_mask
)
354 u32 reg
= PIPESTAT(pipe
);
355 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
357 assert_spin_locked(&dev_priv
->irq_lock
);
358 WARN_ON(!intel_irqs_enabled(dev_priv
));
360 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
361 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
362 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
363 pipe_name(pipe
), enable_mask
, status_mask
))
366 if ((pipestat
& enable_mask
) == enable_mask
)
369 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
371 /* Enable the interrupt, clear any pending status */
372 pipestat
|= enable_mask
| status_mask
;
373 I915_WRITE(reg
, pipestat
);
378 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
379 u32 enable_mask
, u32 status_mask
)
381 u32 reg
= PIPESTAT(pipe
);
382 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
384 assert_spin_locked(&dev_priv
->irq_lock
);
385 WARN_ON(!intel_irqs_enabled(dev_priv
));
387 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
388 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
389 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
390 pipe_name(pipe
), enable_mask
, status_mask
))
393 if ((pipestat
& enable_mask
) == 0)
396 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
398 pipestat
&= ~enable_mask
;
399 I915_WRITE(reg
, pipestat
);
403 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
405 u32 enable_mask
= status_mask
<< 16;
408 * On pipe A we don't support the PSR interrupt yet,
409 * on pipe B and C the same bit MBZ.
411 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
414 * On pipe B and C we don't support the PSR interrupt yet, on pipe
415 * A the same bit is for perf counters which we don't use either.
417 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
420 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
421 SPRITE0_FLIP_DONE_INT_EN_VLV
|
422 SPRITE1_FLIP_DONE_INT_EN_VLV
);
423 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
424 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
425 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
426 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
432 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
437 if (IS_VALLEYVIEW(dev_priv
->dev
))
438 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
441 enable_mask
= status_mask
<< 16;
442 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
446 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
451 if (IS_VALLEYVIEW(dev_priv
->dev
))
452 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
455 enable_mask
= status_mask
<< 16;
456 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
460 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
462 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
466 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
469 spin_lock_irq(&dev_priv
->irq_lock
);
471 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
472 if (INTEL_INFO(dev
)->gen
>= 4)
473 i915_enable_pipestat(dev_priv
, PIPE_A
,
474 PIPE_LEGACY_BLC_EVENT_STATUS
);
476 spin_unlock_irq(&dev_priv
->irq_lock
);
480 * i915_pipe_enabled - check if a pipe is enabled
482 * @pipe: pipe to check
484 * Reading certain registers when the pipe is disabled can hang the chip.
485 * Use this routine to make sure the PLL is running and the pipe is active
486 * before reading such registers if unsure.
489 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
493 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
494 /* Locking is horribly broken here, but whatever. */
495 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
498 return intel_crtc
->active
;
500 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
505 * This timing diagram depicts the video signal in and
506 * around the vertical blanking period.
508 * Assumptions about the fictitious mode used in this example:
510 * vsync_start = vblank_start + 1
511 * vsync_end = vblank_start + 2
512 * vtotal = vblank_start + 3
515 * latch double buffered registers
516 * increment frame counter (ctg+)
517 * generate start of vblank interrupt (gen4+)
520 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
521 * | may be shifted forward 1-3 extra lines via PIPECONF
523 * | | start of vsync:
524 * | | generate vsync interrupt
526 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
527 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
528 * ----va---> <-----------------vb--------------------> <--------va-------------
529 * | | <----vs-----> |
530 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
531 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
532 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
534 * last visible pixel first visible pixel
535 * | increment frame counter (gen3/4)
536 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
538 * x = horizontal active
539 * _ = horizontal blanking
540 * hs = horizontal sync
541 * va = vertical active
542 * vb = vertical blanking
544 * vbs = vblank_start (number)
547 * - most events happen at the start of horizontal sync
548 * - frame start happens at the start of horizontal blank, 1-4 lines
549 * (depending on PIPECONF settings) after the start of vblank
550 * - gen3/4 pixel and frame counter are synchronized with the start
551 * of horizontal active on the first line of vertical active
554 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
556 /* Gen2 doesn't have a hardware frame counter */
560 /* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
563 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 unsigned long high_frame
;
567 unsigned long low_frame
;
568 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
570 if (!i915_pipe_enabled(dev
, pipe
)) {
571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
572 "pipe %c\n", pipe_name(pipe
));
576 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
577 struct intel_crtc
*intel_crtc
=
578 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
579 const struct drm_display_mode
*mode
=
580 &intel_crtc
->config
.adjusted_mode
;
582 htotal
= mode
->crtc_htotal
;
583 hsync_start
= mode
->crtc_hsync_start
;
584 vbl_start
= mode
->crtc_vblank_start
;
585 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
586 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
588 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
590 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
591 hsync_start
= (I915_READ(HSYNC(cpu_transcoder
)) & 0x1fff) + 1;
592 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
593 if ((I915_READ(PIPECONF(cpu_transcoder
)) &
594 PIPECONF_INTERLACE_MASK
) != PIPECONF_PROGRESSIVE
)
595 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
598 /* Convert to pixel count */
601 /* Start of vblank event occurs at start of hsync */
602 vbl_start
-= htotal
- hsync_start
;
604 high_frame
= PIPEFRAME(pipe
);
605 low_frame
= PIPEFRAMEPIXEL(pipe
);
608 * High & low register fields aren't synchronized, so make sure
609 * we get a low value that's stable across two reads of the high
613 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
614 low
= I915_READ(low_frame
);
615 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
616 } while (high1
!= high2
);
618 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
619 pixel
= low
& PIPE_PIXEL_MASK
;
620 low
>>= PIPE_FRAME_LOW_SHIFT
;
623 * The frame counter increments at beginning of active.
624 * Cook up a vblank counter by also checking the pixel
625 * counter against vblank start.
627 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
630 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
635 if (!i915_pipe_enabled(dev
, pipe
)) {
636 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
637 "pipe %c\n", pipe_name(pipe
));
641 return I915_READ(reg
);
644 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
645 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
647 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
649 struct drm_device
*dev
= crtc
->base
.dev
;
650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
651 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
652 enum pipe pipe
= crtc
->pipe
;
653 int position
, vtotal
;
655 vtotal
= mode
->crtc_vtotal
;
656 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
660 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
662 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
665 * See update_scanline_offset() for the details on the
666 * scanline_offset adjustment.
668 return (position
+ crtc
->scanline_offset
) % vtotal
;
671 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
672 unsigned int flags
, int *vpos
, int *hpos
,
673 ktime_t
*stime
, ktime_t
*etime
)
675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
676 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
678 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
680 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
683 unsigned long irqflags
;
685 if (!intel_crtc
->active
) {
686 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
687 "pipe %c\n", pipe_name(pipe
));
691 htotal
= mode
->crtc_htotal
;
692 hsync_start
= mode
->crtc_hsync_start
;
693 vtotal
= mode
->crtc_vtotal
;
694 vbl_start
= mode
->crtc_vblank_start
;
695 vbl_end
= mode
->crtc_vblank_end
;
697 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
698 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
703 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
706 * Lock uncore.lock, as we will do multiple timing critical raw
707 * register reads, potentially with preemption disabled, so the
708 * following code must not block on uncore.lock.
710 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
712 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
714 /* Get optional system timestamp before query. */
716 *stime
= ktime_get();
718 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
719 /* No obvious pixelcount register. Only query vertical
720 * scanout position from Display scan line register.
722 position
= __intel_get_crtc_scanline(intel_crtc
);
724 /* Have access to pixelcount since start of frame.
725 * We can split this into vertical and horizontal
728 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
730 /* convert to pixel counts */
736 * In interlaced modes, the pixel counter counts all pixels,
737 * so one field will have htotal more pixels. In order to avoid
738 * the reported position from jumping backwards when the pixel
739 * counter is beyond the length of the shorter field, just
740 * clamp the position the length of the shorter field. This
741 * matches how the scanline counter based position works since
742 * the scanline counter doesn't count the two half lines.
744 if (position
>= vtotal
)
745 position
= vtotal
- 1;
748 * Start of vblank interrupt is triggered at start of hsync,
749 * just prior to the first active line of vblank. However we
750 * consider lines to start at the leading edge of horizontal
751 * active. So, should we get here before we've crossed into
752 * the horizontal active of the first line in vblank, we would
753 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
754 * always add htotal-hsync_start to the current pixel position.
756 position
= (position
+ htotal
- hsync_start
) % vtotal
;
759 /* Get optional system timestamp after query. */
761 *etime
= ktime_get();
763 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
765 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
767 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
770 * While in vblank, position will be negative
771 * counting up towards 0 at vbl_end. And outside
772 * vblank, position will be positive counting
775 if (position
>= vbl_start
)
778 position
+= vtotal
- vbl_end
;
780 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
784 *vpos
= position
/ htotal
;
785 *hpos
= position
- (*vpos
* htotal
);
790 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
795 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
797 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
798 unsigned long irqflags
;
801 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
802 position
= __intel_get_crtc_scanline(crtc
);
803 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
808 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
810 struct timeval
*vblank_time
,
813 struct drm_crtc
*crtc
;
815 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
816 DRM_ERROR("Invalid crtc %d\n", pipe
);
820 /* Get drm_crtc to timestamp: */
821 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
823 DRM_ERROR("Invalid crtc %d\n", pipe
);
827 if (!crtc
->enabled
) {
828 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
832 /* Helper routine in DRM core does all the work: */
833 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
836 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
839 static bool intel_hpd_irq_event(struct drm_device
*dev
,
840 struct drm_connector
*connector
)
842 enum drm_connector_status old_status
;
844 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
845 old_status
= connector
->status
;
847 connector
->status
= connector
->funcs
->detect(connector
, false);
848 if (old_status
== connector
->status
)
851 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
854 drm_get_connector_status_name(old_status
),
855 drm_get_connector_status_name(connector
->status
));
860 static void i915_digport_work_func(struct work_struct
*work
)
862 struct drm_i915_private
*dev_priv
=
863 container_of(work
, struct drm_i915_private
, dig_port_work
);
864 u32 long_port_mask
, short_port_mask
;
865 struct intel_digital_port
*intel_dig_port
;
869 spin_lock_irq(&dev_priv
->irq_lock
);
870 long_port_mask
= dev_priv
->long_hpd_port_mask
;
871 dev_priv
->long_hpd_port_mask
= 0;
872 short_port_mask
= dev_priv
->short_hpd_port_mask
;
873 dev_priv
->short_hpd_port_mask
= 0;
874 spin_unlock_irq(&dev_priv
->irq_lock
);
876 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
878 bool long_hpd
= false;
879 intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
880 if (!intel_dig_port
|| !intel_dig_port
->hpd_pulse
)
883 if (long_port_mask
& (1 << i
)) {
886 } else if (short_port_mask
& (1 << i
))
890 ret
= intel_dig_port
->hpd_pulse(intel_dig_port
, long_hpd
);
892 /* if we get true fallback to old school hpd */
893 old_bits
|= (1 << intel_dig_port
->base
.hpd_pin
);
899 spin_lock_irq(&dev_priv
->irq_lock
);
900 dev_priv
->hpd_event_bits
|= old_bits
;
901 spin_unlock_irq(&dev_priv
->irq_lock
);
902 schedule_work(&dev_priv
->hotplug_work
);
907 * Handle hotplug events outside the interrupt handler proper.
909 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
911 static void i915_hotplug_work_func(struct work_struct
*work
)
913 struct drm_i915_private
*dev_priv
=
914 container_of(work
, struct drm_i915_private
, hotplug_work
);
915 struct drm_device
*dev
= dev_priv
->dev
;
916 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
917 struct intel_connector
*intel_connector
;
918 struct intel_encoder
*intel_encoder
;
919 struct drm_connector
*connector
;
920 bool hpd_disabled
= false;
921 bool changed
= false;
924 mutex_lock(&mode_config
->mutex
);
925 DRM_DEBUG_KMS("running encoder hotplug functions\n");
927 spin_lock_irq(&dev_priv
->irq_lock
);
929 hpd_event_bits
= dev_priv
->hpd_event_bits
;
930 dev_priv
->hpd_event_bits
= 0;
931 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
932 intel_connector
= to_intel_connector(connector
);
933 if (!intel_connector
->encoder
)
935 intel_encoder
= intel_connector
->encoder
;
936 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
937 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
938 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
939 DRM_INFO("HPD interrupt storm detected on connector %s: "
940 "switching from hotplug detection to polling\n",
942 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
943 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
944 | DRM_CONNECTOR_POLL_DISCONNECT
;
947 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
948 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
949 connector
->name
, intel_encoder
->hpd_pin
);
952 /* if there were no outputs to poll, poll was disabled,
953 * therefore make sure it's enabled when disabling HPD on
956 drm_kms_helper_poll_enable(dev
);
957 mod_delayed_work(system_wq
, &dev_priv
->hotplug_reenable_work
,
958 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
961 spin_unlock_irq(&dev_priv
->irq_lock
);
963 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
964 intel_connector
= to_intel_connector(connector
);
965 if (!intel_connector
->encoder
)
967 intel_encoder
= intel_connector
->encoder
;
968 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
969 if (intel_encoder
->hot_plug
)
970 intel_encoder
->hot_plug(intel_encoder
);
971 if (intel_hpd_irq_event(dev
, connector
))
975 mutex_unlock(&mode_config
->mutex
);
978 drm_kms_helper_hotplug_event(dev
);
981 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
984 u32 busy_up
, busy_down
, max_avg
, min_avg
;
987 spin_lock(&mchdev_lock
);
989 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
991 new_delay
= dev_priv
->ips
.cur_delay
;
993 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
994 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
995 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
996 max_avg
= I915_READ(RCBMAXAVG
);
997 min_avg
= I915_READ(RCBMINAVG
);
999 /* Handle RCS change request from hw */
1000 if (busy_up
> max_avg
) {
1001 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
1002 new_delay
= dev_priv
->ips
.cur_delay
- 1;
1003 if (new_delay
< dev_priv
->ips
.max_delay
)
1004 new_delay
= dev_priv
->ips
.max_delay
;
1005 } else if (busy_down
< min_avg
) {
1006 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
1007 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
1008 if (new_delay
> dev_priv
->ips
.min_delay
)
1009 new_delay
= dev_priv
->ips
.min_delay
;
1012 if (ironlake_set_drps(dev
, new_delay
))
1013 dev_priv
->ips
.cur_delay
= new_delay
;
1015 spin_unlock(&mchdev_lock
);
1020 static void notify_ring(struct drm_device
*dev
,
1021 struct intel_engine_cs
*ring
)
1023 if (!intel_ring_initialized(ring
))
1026 trace_i915_gem_request_notify(ring
);
1028 wake_up_all(&ring
->irq_queue
);
1031 static u32
vlv_c0_residency(struct drm_i915_private
*dev_priv
,
1032 struct intel_rps_ei
*rps_ei
)
1034 u32 cz_ts
, cz_freq_khz
;
1035 u32 render_count
, media_count
;
1036 u32 elapsed_render
, elapsed_media
, elapsed_time
;
1039 cz_ts
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1040 cz_freq_khz
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* 1000, 4);
1042 render_count
= I915_READ(VLV_RENDER_C0_COUNT_REG
);
1043 media_count
= I915_READ(VLV_MEDIA_C0_COUNT_REG
);
1045 if (rps_ei
->cz_clock
== 0) {
1046 rps_ei
->cz_clock
= cz_ts
;
1047 rps_ei
->render_c0
= render_count
;
1048 rps_ei
->media_c0
= media_count
;
1050 return dev_priv
->rps
.cur_freq
;
1053 elapsed_time
= cz_ts
- rps_ei
->cz_clock
;
1054 rps_ei
->cz_clock
= cz_ts
;
1056 elapsed_render
= render_count
- rps_ei
->render_c0
;
1057 rps_ei
->render_c0
= render_count
;
1059 elapsed_media
= media_count
- rps_ei
->media_c0
;
1060 rps_ei
->media_c0
= media_count
;
1062 /* Convert all the counters into common unit of milli sec */
1063 elapsed_time
/= VLV_CZ_CLOCK_TO_MILLI_SEC
;
1064 elapsed_render
/= cz_freq_khz
;
1065 elapsed_media
/= cz_freq_khz
;
1068 * Calculate overall C0 residency percentage
1069 * only if elapsed time is non zero
1073 ((max(elapsed_render
, elapsed_media
) * 100)
1081 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1082 * busy-ness calculated from C0 counters of render & media power wells
1083 * @dev_priv: DRM device private
1086 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private
*dev_priv
)
1088 u32 residency_C0_up
= 0, residency_C0_down
= 0;
1091 dev_priv
->rps
.ei_interrupt_count
++;
1093 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
1096 if (dev_priv
->rps
.up_ei
.cz_clock
== 0) {
1097 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.up_ei
);
1098 vlv_c0_residency(dev_priv
, &dev_priv
->rps
.down_ei
);
1099 return dev_priv
->rps
.cur_freq
;
1104 * To down throttle, C0 residency should be less than down threshold
1105 * for continous EI intervals. So calculate down EI counters
1106 * once in VLV_INT_COUNT_FOR_DOWN_EI
1108 if (dev_priv
->rps
.ei_interrupt_count
== VLV_INT_COUNT_FOR_DOWN_EI
) {
1110 dev_priv
->rps
.ei_interrupt_count
= 0;
1112 residency_C0_down
= vlv_c0_residency(dev_priv
,
1113 &dev_priv
->rps
.down_ei
);
1115 residency_C0_up
= vlv_c0_residency(dev_priv
,
1116 &dev_priv
->rps
.up_ei
);
1119 new_delay
= dev_priv
->rps
.cur_freq
;
1121 adj
= dev_priv
->rps
.last_adj
;
1122 /* C0 residency is greater than UP threshold. Increase Frequency */
1123 if (residency_C0_up
>= VLV_RP_UP_EI_THRESHOLD
) {
1129 if (dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
)
1130 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1133 * For better performance, jump directly
1134 * to RPe if we're below it.
1136 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1137 new_delay
= dev_priv
->rps
.efficient_freq
;
1139 } else if (!dev_priv
->rps
.ei_interrupt_count
&&
1140 (residency_C0_down
< VLV_RP_DOWN_EI_THRESHOLD
)) {
1146 * This means, C0 residency is less than down threshold over
1147 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1149 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.min_freq_softlimit
)
1150 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1156 static void gen6_pm_rps_work(struct work_struct
*work
)
1158 struct drm_i915_private
*dev_priv
=
1159 container_of(work
, struct drm_i915_private
, rps
.work
);
1163 spin_lock_irq(&dev_priv
->irq_lock
);
1164 /* Speed up work cancelation during disabling rps interrupts. */
1165 if (!dev_priv
->rps
.interrupts_enabled
) {
1166 spin_unlock_irq(&dev_priv
->irq_lock
);
1169 pm_iir
= dev_priv
->rps
.pm_iir
;
1170 dev_priv
->rps
.pm_iir
= 0;
1171 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1172 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1173 spin_unlock_irq(&dev_priv
->irq_lock
);
1175 /* Make sure we didn't queue anything we're not going to process. */
1176 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1178 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1181 mutex_lock(&dev_priv
->rps
.hw_lock
);
1183 adj
= dev_priv
->rps
.last_adj
;
1184 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1188 /* CHV needs even encode values */
1189 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? 2 : 1;
1191 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1194 * For better performance, jump directly
1195 * to RPe if we're below it.
1197 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1198 new_delay
= dev_priv
->rps
.efficient_freq
;
1199 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1200 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1201 new_delay
= dev_priv
->rps
.efficient_freq
;
1203 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1205 } else if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1206 new_delay
= vlv_calc_delay_from_C0_counters(dev_priv
);
1207 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1211 /* CHV needs even encode values */
1212 adj
= IS_CHERRYVIEW(dev_priv
->dev
) ? -2 : -1;
1214 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1215 } else { /* unknown event */
1216 new_delay
= dev_priv
->rps
.cur_freq
;
1219 /* sysfs frequency interfaces may have snuck in while servicing the
1222 new_delay
= clamp_t(int, new_delay
,
1223 dev_priv
->rps
.min_freq_softlimit
,
1224 dev_priv
->rps
.max_freq_softlimit
);
1226 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1228 if (IS_VALLEYVIEW(dev_priv
->dev
))
1229 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1231 gen6_set_rps(dev_priv
->dev
, new_delay
);
1233 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1238 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1240 * @work: workqueue struct
1242 * Doesn't actually do anything except notify userspace. As a consequence of
1243 * this event, userspace should try to remap the bad rows since statistically
1244 * it is likely the same row is more likely to go bad again.
1246 static void ivybridge_parity_work(struct work_struct
*work
)
1248 struct drm_i915_private
*dev_priv
=
1249 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1250 u32 error_status
, row
, bank
, subbank
;
1251 char *parity_event
[6];
1255 /* We must turn off DOP level clock gating to access the L3 registers.
1256 * In order to prevent a get/put style interface, acquire struct mutex
1257 * any time we access those registers.
1259 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1261 /* If we've screwed up tracking, just let the interrupt fire again */
1262 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1265 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1266 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1267 POSTING_READ(GEN7_MISCCPCTL
);
1269 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1273 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1276 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1278 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1280 error_status
= I915_READ(reg
);
1281 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1282 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1283 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1285 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1288 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1289 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1290 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1291 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1292 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1293 parity_event
[5] = NULL
;
1295 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1296 KOBJ_CHANGE
, parity_event
);
1298 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1299 slice
, row
, bank
, subbank
);
1301 kfree(parity_event
[4]);
1302 kfree(parity_event
[3]);
1303 kfree(parity_event
[2]);
1304 kfree(parity_event
[1]);
1307 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1310 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1311 spin_lock_irq(&dev_priv
->irq_lock
);
1312 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1313 spin_unlock_irq(&dev_priv
->irq_lock
);
1315 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1318 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1322 if (!HAS_L3_DPF(dev
))
1325 spin_lock(&dev_priv
->irq_lock
);
1326 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1327 spin_unlock(&dev_priv
->irq_lock
);
1329 iir
&= GT_PARITY_ERROR(dev
);
1330 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1331 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1333 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1334 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1336 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1339 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1340 struct drm_i915_private
*dev_priv
,
1344 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1345 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1346 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1347 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1350 static void snb_gt_irq_handler(struct drm_device
*dev
,
1351 struct drm_i915_private
*dev_priv
,
1356 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1357 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1358 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1359 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1360 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1361 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1363 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1364 GT_BSD_CS_ERROR_INTERRUPT
|
1365 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1366 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1368 if (gt_iir
& GT_PARITY_ERROR(dev
))
1369 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1372 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1373 struct drm_i915_private
*dev_priv
,
1376 struct intel_engine_cs
*ring
;
1379 irqreturn_t ret
= IRQ_NONE
;
1381 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1382 tmp
= I915_READ(GEN8_GT_IIR(0));
1384 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1387 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1388 ring
= &dev_priv
->ring
[RCS
];
1389 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1390 notify_ring(dev
, ring
);
1391 if (rcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1392 intel_lrc_irq_handler(ring
);
1394 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1395 ring
= &dev_priv
->ring
[BCS
];
1396 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1397 notify_ring(dev
, ring
);
1398 if (bcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1399 intel_lrc_irq_handler(ring
);
1401 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1404 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1405 tmp
= I915_READ(GEN8_GT_IIR(1));
1407 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1410 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1411 ring
= &dev_priv
->ring
[VCS
];
1412 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1413 notify_ring(dev
, ring
);
1414 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1415 intel_lrc_irq_handler(ring
);
1417 vcs
= tmp
>> GEN8_VCS2_IRQ_SHIFT
;
1418 ring
= &dev_priv
->ring
[VCS2
];
1419 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1420 notify_ring(dev
, ring
);
1421 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1422 intel_lrc_irq_handler(ring
);
1424 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1427 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1428 tmp
= I915_READ(GEN8_GT_IIR(2));
1429 if (tmp
& dev_priv
->pm_rps_events
) {
1430 I915_WRITE(GEN8_GT_IIR(2),
1431 tmp
& dev_priv
->pm_rps_events
);
1433 gen6_rps_irq_handler(dev_priv
, tmp
);
1435 DRM_ERROR("The master control interrupt lied (PM)!\n");
1438 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1439 tmp
= I915_READ(GEN8_GT_IIR(3));
1441 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1444 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1445 ring
= &dev_priv
->ring
[VECS
];
1446 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1447 notify_ring(dev
, ring
);
1448 if (vcs
& GT_CONTEXT_SWITCH_INTERRUPT
)
1449 intel_lrc_irq_handler(ring
);
1451 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1457 #define HPD_STORM_DETECT_PERIOD 1000
1458 #define HPD_STORM_THRESHOLD 5
1460 static int pch_port_to_hotplug_shift(enum port port
)
1476 static int i915_port_to_hotplug_shift(enum port port
)
1492 static inline enum port
get_port_from_pin(enum hpd_pin pin
)
1502 return PORT_A
; /* no hpd */
1506 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1507 u32 hotplug_trigger
,
1508 u32 dig_hotplug_reg
,
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1514 bool storm_detected
= false;
1515 bool queue_dig
= false, queue_hp
= false;
1517 u32 dig_port_mask
= 0;
1519 if (!hotplug_trigger
)
1522 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1523 hotplug_trigger
, dig_hotplug_reg
);
1525 spin_lock(&dev_priv
->irq_lock
);
1526 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1527 if (!(hpd
[i
] & hotplug_trigger
))
1530 port
= get_port_from_pin(i
);
1531 if (port
&& dev_priv
->hpd_irq_port
[port
]) {
1534 if (HAS_PCH_SPLIT(dev
)) {
1535 dig_shift
= pch_port_to_hotplug_shift(port
);
1536 long_hpd
= (dig_hotplug_reg
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1538 dig_shift
= i915_port_to_hotplug_shift(port
);
1539 long_hpd
= (hotplug_trigger
>> dig_shift
) & PORTB_HOTPLUG_LONG_DETECT
;
1542 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1544 long_hpd
? "long" : "short");
1545 /* for long HPD pulses we want to have the digital queue happen,
1546 but we still want HPD storm detection to function. */
1548 dev_priv
->long_hpd_port_mask
|= (1 << port
);
1549 dig_port_mask
|= hpd
[i
];
1551 /* for short HPD just trigger the digital queue */
1552 dev_priv
->short_hpd_port_mask
|= (1 << port
);
1553 hotplug_trigger
&= ~hpd
[i
];
1559 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1560 if (hpd
[i
] & hotplug_trigger
&&
1561 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
) {
1563 * On GMCH platforms the interrupt mask bits only
1564 * prevent irq generation, not the setting of the
1565 * hotplug bits itself. So only WARN about unexpected
1566 * interrupts on saner platforms.
1568 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1569 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1570 hotplug_trigger
, i
, hpd
[i
]);
1575 if (!(hpd
[i
] & hotplug_trigger
) ||
1576 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1579 if (!(dig_port_mask
& hpd
[i
])) {
1580 dev_priv
->hpd_event_bits
|= (1 << i
);
1584 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1585 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1586 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1587 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1588 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1589 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1590 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1591 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1592 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1593 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1594 storm_detected
= true;
1596 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1597 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1598 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1603 dev_priv
->display
.hpd_irq_setup(dev
);
1604 spin_unlock(&dev_priv
->irq_lock
);
1607 * Our hotplug handler can grab modeset locks (by calling down into the
1608 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1609 * queue for otherwise the flush_work in the pageflip code will
1613 queue_work(dev_priv
->dp_wq
, &dev_priv
->dig_port_work
);
1615 schedule_work(&dev_priv
->hotplug_work
);
1618 static void gmbus_irq_handler(struct drm_device
*dev
)
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1622 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1625 static void dp_aux_irq_handler(struct drm_device
*dev
)
1627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1632 #if defined(CONFIG_DEBUG_FS)
1633 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1634 uint32_t crc0
, uint32_t crc1
,
1635 uint32_t crc2
, uint32_t crc3
,
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1640 struct intel_pipe_crc_entry
*entry
;
1643 spin_lock(&pipe_crc
->lock
);
1645 if (!pipe_crc
->entries
) {
1646 spin_unlock(&pipe_crc
->lock
);
1647 DRM_DEBUG_KMS("spurious interrupt\n");
1651 head
= pipe_crc
->head
;
1652 tail
= pipe_crc
->tail
;
1654 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1655 spin_unlock(&pipe_crc
->lock
);
1656 DRM_ERROR("CRC buffer overflowing\n");
1660 entry
= &pipe_crc
->entries
[head
];
1662 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1663 entry
->crc
[0] = crc0
;
1664 entry
->crc
[1] = crc1
;
1665 entry
->crc
[2] = crc2
;
1666 entry
->crc
[3] = crc3
;
1667 entry
->crc
[4] = crc4
;
1669 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1670 pipe_crc
->head
= head
;
1672 spin_unlock(&pipe_crc
->lock
);
1674 wake_up_interruptible(&pipe_crc
->wq
);
1678 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1679 uint32_t crc0
, uint32_t crc1
,
1680 uint32_t crc2
, uint32_t crc3
,
1685 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 display_pipe_crc_irq_handler(dev
, pipe
,
1690 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1694 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1698 display_pipe_crc_irq_handler(dev
, pipe
,
1699 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1700 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1701 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1702 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1703 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1706 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1709 uint32_t res1
, res2
;
1711 if (INTEL_INFO(dev
)->gen
>= 3)
1712 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1716 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1717 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1721 display_pipe_crc_irq_handler(dev
, pipe
,
1722 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1723 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1724 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1728 /* The RPS events need forcewake, so we add them to a work queue and mask their
1729 * IMR bits until the work is done. Other interrupts can be processed without
1730 * the work queue. */
1731 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1733 /* TODO: RPS on GEN9+ is not supported yet. */
1734 if (WARN_ONCE(INTEL_INFO(dev_priv
)->gen
>= 9,
1735 "GEN9+: unexpected RPS IRQ\n"))
1738 if (pm_iir
& dev_priv
->pm_rps_events
) {
1739 spin_lock(&dev_priv
->irq_lock
);
1740 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1741 if (dev_priv
->rps
.interrupts_enabled
) {
1742 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1743 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1745 spin_unlock(&dev_priv
->irq_lock
);
1748 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1751 if (HAS_VEBOX(dev_priv
->dev
)) {
1752 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1753 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1755 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1756 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1760 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1762 if (!drm_handle_vblank(dev
, pipe
))
1768 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1774 spin_lock(&dev_priv
->irq_lock
);
1775 for_each_pipe(dev_priv
, pipe
) {
1777 u32 mask
, iir_bit
= 0;
1780 * PIPESTAT bits get signalled even when the interrupt is
1781 * disabled with the mask bits, and some of the status bits do
1782 * not generate interrupts at all (like the underrun bit). Hence
1783 * we need to be careful that we only handle what we want to
1787 /* fifo underruns are filterered in the underrun handler. */
1788 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1792 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1795 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1798 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1802 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1807 reg
= PIPESTAT(pipe
);
1808 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1809 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1812 * Clear the PIPE*STAT regs before the IIR
1814 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1815 PIPESTAT_INT_STATUS_MASK
))
1816 I915_WRITE(reg
, pipe_stats
[pipe
]);
1818 spin_unlock(&dev_priv
->irq_lock
);
1820 for_each_pipe(dev_priv
, pipe
) {
1821 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1822 intel_pipe_handle_vblank(dev
, pipe
))
1823 intel_check_page_flip(dev
, pipe
);
1825 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1826 intel_prepare_page_flip(dev
, pipe
);
1827 intel_finish_page_flip(dev
, pipe
);
1830 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1831 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1833 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1834 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1837 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1838 gmbus_irq_handler(dev
);
1841 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1844 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1846 if (hotplug_status
) {
1847 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1849 * Make sure hotplug status is cleared before we clear IIR, or else we
1850 * may miss hotplug events.
1852 POSTING_READ(PORT_HOTPLUG_STAT
);
1855 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1857 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_g4x
);
1859 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1861 intel_hpd_irq_handler(dev
, hotplug_trigger
, 0, hpd_status_i915
);
1864 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1865 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1866 dp_aux_irq_handler(dev
);
1870 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1872 struct drm_device
*dev
= arg
;
1873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1874 u32 iir
, gt_iir
, pm_iir
;
1875 irqreturn_t ret
= IRQ_NONE
;
1878 /* Find, clear, then process each source of interrupt */
1880 gt_iir
= I915_READ(GTIIR
);
1882 I915_WRITE(GTIIR
, gt_iir
);
1884 pm_iir
= I915_READ(GEN6_PMIIR
);
1886 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1888 iir
= I915_READ(VLV_IIR
);
1890 /* Consume port before clearing IIR or we'll miss events */
1891 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1892 i9xx_hpd_irq_handler(dev
);
1893 I915_WRITE(VLV_IIR
, iir
);
1896 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1902 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1904 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1905 /* Call regardless, as some status bits might not be
1906 * signalled in iir */
1907 valleyview_pipestat_irq_handler(dev
, iir
);
1914 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1916 struct drm_device
*dev
= arg
;
1917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 u32 master_ctl
, iir
;
1919 irqreturn_t ret
= IRQ_NONE
;
1922 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1923 iir
= I915_READ(VLV_IIR
);
1925 if (master_ctl
== 0 && iir
== 0)
1930 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1932 /* Find, clear, then process each source of interrupt */
1935 /* Consume port before clearing IIR or we'll miss events */
1936 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1937 i9xx_hpd_irq_handler(dev
);
1938 I915_WRITE(VLV_IIR
, iir
);
1941 gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1943 /* Call regardless, as some status bits might not be
1944 * signalled in iir */
1945 valleyview_pipestat_irq_handler(dev
, iir
);
1947 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1948 POSTING_READ(GEN8_MASTER_IRQ
);
1954 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1959 u32 dig_hotplug_reg
;
1961 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1962 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1964 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_ibx
);
1966 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1967 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1968 SDE_AUDIO_POWER_SHIFT
);
1969 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1973 if (pch_iir
& SDE_AUX_MASK
)
1974 dp_aux_irq_handler(dev
);
1976 if (pch_iir
& SDE_GMBUS
)
1977 gmbus_irq_handler(dev
);
1979 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1980 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1982 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1983 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1985 if (pch_iir
& SDE_POISON
)
1986 DRM_ERROR("PCH poison interrupt\n");
1988 if (pch_iir
& SDE_FDI_MASK
)
1989 for_each_pipe(dev_priv
, pipe
)
1990 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1992 I915_READ(FDI_RX_IIR(pipe
)));
1994 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1995 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1997 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1998 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2000 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
2001 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2003 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
2004 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2007 static void ivb_err_int_handler(struct drm_device
*dev
)
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2013 if (err_int
& ERR_INT_POISON
)
2014 DRM_ERROR("Poison interrupt\n");
2016 for_each_pipe(dev_priv
, pipe
) {
2017 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2018 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2020 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2021 if (IS_IVYBRIDGE(dev
))
2022 ivb_pipe_crc_irq_handler(dev
, pipe
);
2024 hsw_pipe_crc_irq_handler(dev
, pipe
);
2028 I915_WRITE(GEN7_ERR_INT
, err_int
);
2031 static void cpt_serr_int_handler(struct drm_device
*dev
)
2033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2034 u32 serr_int
= I915_READ(SERR_INT
);
2036 if (serr_int
& SERR_INT_POISON
)
2037 DRM_ERROR("PCH poison interrupt\n");
2039 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2040 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2042 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2043 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2045 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2046 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2048 I915_WRITE(SERR_INT
, serr_int
);
2051 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2055 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2056 u32 dig_hotplug_reg
;
2058 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2059 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2061 intel_hpd_irq_handler(dev
, hotplug_trigger
, dig_hotplug_reg
, hpd_cpt
);
2063 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2064 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2065 SDE_AUDIO_POWER_SHIFT_CPT
);
2066 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2070 if (pch_iir
& SDE_AUX_MASK_CPT
)
2071 dp_aux_irq_handler(dev
);
2073 if (pch_iir
& SDE_GMBUS_CPT
)
2074 gmbus_irq_handler(dev
);
2076 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2077 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2079 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2080 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2082 if (pch_iir
& SDE_FDI_MASK_CPT
)
2083 for_each_pipe(dev_priv
, pipe
)
2084 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2086 I915_READ(FDI_RX_IIR(pipe
)));
2088 if (pch_iir
& SDE_ERROR_CPT
)
2089 cpt_serr_int_handler(dev
);
2092 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2097 if (de_iir
& DE_AUX_CHANNEL_A
)
2098 dp_aux_irq_handler(dev
);
2100 if (de_iir
& DE_GSE
)
2101 intel_opregion_asle_intr(dev
);
2103 if (de_iir
& DE_POISON
)
2104 DRM_ERROR("Poison interrupt\n");
2106 for_each_pipe(dev_priv
, pipe
) {
2107 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2108 intel_pipe_handle_vblank(dev
, pipe
))
2109 intel_check_page_flip(dev
, pipe
);
2111 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2112 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2114 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2115 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2117 /* plane/pipes map 1:1 on ilk+ */
2118 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2119 intel_prepare_page_flip(dev
, pipe
);
2120 intel_finish_page_flip_plane(dev
, pipe
);
2124 /* check event from PCH */
2125 if (de_iir
& DE_PCH_EVENT
) {
2126 u32 pch_iir
= I915_READ(SDEIIR
);
2128 if (HAS_PCH_CPT(dev
))
2129 cpt_irq_handler(dev
, pch_iir
);
2131 ibx_irq_handler(dev
, pch_iir
);
2133 /* should clear PCH hotplug event before clear CPU irq */
2134 I915_WRITE(SDEIIR
, pch_iir
);
2137 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2138 ironlake_rps_change_irq_handler(dev
);
2141 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 if (de_iir
& DE_ERR_INT_IVB
)
2147 ivb_err_int_handler(dev
);
2149 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2150 dp_aux_irq_handler(dev
);
2152 if (de_iir
& DE_GSE_IVB
)
2153 intel_opregion_asle_intr(dev
);
2155 for_each_pipe(dev_priv
, pipe
) {
2156 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2157 intel_pipe_handle_vblank(dev
, pipe
))
2158 intel_check_page_flip(dev
, pipe
);
2160 /* plane/pipes map 1:1 on ilk+ */
2161 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2162 intel_prepare_page_flip(dev
, pipe
);
2163 intel_finish_page_flip_plane(dev
, pipe
);
2167 /* check event from PCH */
2168 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2169 u32 pch_iir
= I915_READ(SDEIIR
);
2171 cpt_irq_handler(dev
, pch_iir
);
2173 /* clear PCH hotplug event before clear CPU irq */
2174 I915_WRITE(SDEIIR
, pch_iir
);
2179 * To handle irqs with the minimum potential races with fresh interrupts, we:
2180 * 1 - Disable Master Interrupt Control.
2181 * 2 - Find the source(s) of the interrupt.
2182 * 3 - Clear the Interrupt Identity bits (IIR).
2183 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2184 * 5 - Re-enable Master Interrupt Control.
2186 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2188 struct drm_device
*dev
= arg
;
2189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2190 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2191 irqreturn_t ret
= IRQ_NONE
;
2193 /* We get interrupts on unclaimed registers, so check for this before we
2194 * do any I915_{READ,WRITE}. */
2195 intel_uncore_check_errors(dev
);
2197 /* disable master interrupt before clearing iir */
2198 de_ier
= I915_READ(DEIER
);
2199 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2200 POSTING_READ(DEIER
);
2202 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2203 * interrupts will will be stored on its back queue, and then we'll be
2204 * able to process them after we restore SDEIER (as soon as we restore
2205 * it, we'll get an interrupt if SDEIIR still has something to process
2206 * due to its back queue). */
2207 if (!HAS_PCH_NOP(dev
)) {
2208 sde_ier
= I915_READ(SDEIER
);
2209 I915_WRITE(SDEIER
, 0);
2210 POSTING_READ(SDEIER
);
2213 /* Find, clear, then process each source of interrupt */
2215 gt_iir
= I915_READ(GTIIR
);
2217 I915_WRITE(GTIIR
, gt_iir
);
2219 if (INTEL_INFO(dev
)->gen
>= 6)
2220 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2222 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2225 de_iir
= I915_READ(DEIIR
);
2227 I915_WRITE(DEIIR
, de_iir
);
2229 if (INTEL_INFO(dev
)->gen
>= 7)
2230 ivb_display_irq_handler(dev
, de_iir
);
2232 ilk_display_irq_handler(dev
, de_iir
);
2235 if (INTEL_INFO(dev
)->gen
>= 6) {
2236 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2238 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2240 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2244 I915_WRITE(DEIER
, de_ier
);
2245 POSTING_READ(DEIER
);
2246 if (!HAS_PCH_NOP(dev
)) {
2247 I915_WRITE(SDEIER
, sde_ier
);
2248 POSTING_READ(SDEIER
);
2254 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2256 struct drm_device
*dev
= arg
;
2257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 irqreturn_t ret
= IRQ_NONE
;
2262 u32 aux_mask
= GEN8_AUX_CHANNEL_A
;
2265 aux_mask
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
2268 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
2269 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2273 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2274 POSTING_READ(GEN8_MASTER_IRQ
);
2276 /* Find, clear, then process each source of interrupt */
2278 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
2280 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2281 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2283 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2285 if (tmp
& GEN8_DE_MISC_GSE
)
2286 intel_opregion_asle_intr(dev
);
2288 DRM_ERROR("Unexpected DE Misc interrupt\n");
2291 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2294 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2295 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2297 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2301 dp_aux_irq_handler(dev
);
2303 DRM_ERROR("Unexpected DE Port interrupt\n");
2306 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2309 for_each_pipe(dev_priv
, pipe
) {
2310 uint32_t pipe_iir
, flip_done
= 0, fault_errors
= 0;
2312 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2315 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2318 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2320 if (pipe_iir
& GEN8_PIPE_VBLANK
&&
2321 intel_pipe_handle_vblank(dev
, pipe
))
2322 intel_check_page_flip(dev
, pipe
);
2325 flip_done
= pipe_iir
& GEN9_PIPE_PLANE1_FLIP_DONE
;
2327 flip_done
= pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
;
2330 intel_prepare_page_flip(dev
, pipe
);
2331 intel_finish_page_flip_plane(dev
, pipe
);
2334 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2335 hsw_pipe_crc_irq_handler(dev
, pipe
);
2337 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2338 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
2343 fault_errors
= pipe_iir
& GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2345 fault_errors
= pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2348 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2350 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2352 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2355 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2357 * FIXME(BDW): Assume for now that the new interrupt handling
2358 * scheme also closed the SDE interrupt handling race we've seen
2359 * on older pch-split platforms. But this needs testing.
2361 u32 pch_iir
= I915_READ(SDEIIR
);
2363 I915_WRITE(SDEIIR
, pch_iir
);
2365 cpt_irq_handler(dev
, pch_iir
);
2367 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2371 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2372 POSTING_READ(GEN8_MASTER_IRQ
);
2377 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2378 bool reset_completed
)
2380 struct intel_engine_cs
*ring
;
2384 * Notify all waiters for GPU completion events that reset state has
2385 * been changed, and that they need to restart their wait after
2386 * checking for potential errors (and bail out to drop locks if there is
2387 * a gpu reset pending so that i915_error_work_func can acquire them).
2390 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2391 for_each_ring(ring
, dev_priv
, i
)
2392 wake_up_all(&ring
->irq_queue
);
2394 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2395 wake_up_all(&dev_priv
->pending_flip_queue
);
2398 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2399 * reset state is cleared.
2401 if (reset_completed
)
2402 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2406 * i915_error_work_func - do process context error handling work
2407 * @work: work struct
2409 * Fire an error uevent so userspace can see that a hang or error
2412 static void i915_error_work_func(struct work_struct
*work
)
2414 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2416 struct drm_i915_private
*dev_priv
=
2417 container_of(error
, struct drm_i915_private
, gpu_error
);
2418 struct drm_device
*dev
= dev_priv
->dev
;
2419 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2420 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2421 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2424 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2427 * Note that there's only one work item which does gpu resets, so we
2428 * need not worry about concurrent gpu resets potentially incrementing
2429 * error->reset_counter twice. We only need to take care of another
2430 * racing irq/hangcheck declaring the gpu dead for a second time. A
2431 * quick check for that is good enough: schedule_work ensures the
2432 * correct ordering between hang detection and this work item, and since
2433 * the reset in-progress bit is only ever set by code outside of this
2434 * work we don't need to worry about any other races.
2436 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2437 DRM_DEBUG_DRIVER("resetting chip\n");
2438 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2442 * In most cases it's guaranteed that we get here with an RPM
2443 * reference held, for example because there is a pending GPU
2444 * request that won't finish until the reset is done. This
2445 * isn't the case at least when we get here by doing a
2446 * simulated reset via debugs, so get an RPM reference.
2448 intel_runtime_pm_get(dev_priv
);
2450 intel_prepare_reset(dev
);
2453 * All state reset _must_ be completed before we update the
2454 * reset counter, for otherwise waiters might miss the reset
2455 * pending state and not properly drop locks, resulting in
2456 * deadlocks with the reset work.
2458 ret
= i915_reset(dev
);
2460 intel_finish_reset(dev
);
2462 intel_runtime_pm_put(dev_priv
);
2466 * After all the gem state is reset, increment the reset
2467 * counter and wake up everyone waiting for the reset to
2470 * Since unlock operations are a one-sided barrier only,
2471 * we need to insert a barrier here to order any seqno
2473 * the counter increment.
2475 smp_mb__before_atomic();
2476 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2478 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2479 KOBJ_CHANGE
, reset_done_event
);
2481 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2485 * Note: The wake_up also serves as a memory barrier so that
2486 * waiters see the update value of the reset counter atomic_t.
2488 i915_error_wake_up(dev_priv
, true);
2492 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2495 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2496 u32 eir
= I915_READ(EIR
);
2502 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2504 i915_get_extra_instdone(dev
, instdone
);
2507 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2508 u32 ipeir
= I915_READ(IPEIR_I965
);
2510 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2511 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2512 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2513 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2514 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2515 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2516 I915_WRITE(IPEIR_I965
, ipeir
);
2517 POSTING_READ(IPEIR_I965
);
2519 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2520 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2521 pr_err("page table error\n");
2522 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2523 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2524 POSTING_READ(PGTBL_ER
);
2528 if (!IS_GEN2(dev
)) {
2529 if (eir
& I915_ERROR_PAGE_TABLE
) {
2530 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2531 pr_err("page table error\n");
2532 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2533 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2534 POSTING_READ(PGTBL_ER
);
2538 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2539 pr_err("memory refresh error:\n");
2540 for_each_pipe(dev_priv
, pipe
)
2541 pr_err("pipe %c stat: 0x%08x\n",
2542 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2543 /* pipestat has already been acked */
2545 if (eir
& I915_ERROR_INSTRUCTION
) {
2546 pr_err("instruction error\n");
2547 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2548 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2549 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2550 if (INTEL_INFO(dev
)->gen
< 4) {
2551 u32 ipeir
= I915_READ(IPEIR
);
2553 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2554 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2555 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2556 I915_WRITE(IPEIR
, ipeir
);
2557 POSTING_READ(IPEIR
);
2559 u32 ipeir
= I915_READ(IPEIR_I965
);
2561 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2562 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2563 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2564 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2565 I915_WRITE(IPEIR_I965
, ipeir
);
2566 POSTING_READ(IPEIR_I965
);
2570 I915_WRITE(EIR
, eir
);
2572 eir
= I915_READ(EIR
);
2575 * some errors might have become stuck,
2578 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2579 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2580 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2585 * i915_handle_error - handle an error interrupt
2588 * Do some basic checking of regsiter state at error interrupt time and
2589 * dump it to the syslog. Also call i915_capture_error_state() to make
2590 * sure we get a record and make it available in debugfs. Fire a uevent
2591 * so userspace knows something bad happened (should trigger collection
2592 * of a ring dump etc.).
2594 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2595 const char *fmt
, ...)
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2601 va_start(args
, fmt
);
2602 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2605 i915_capture_error_state(dev
, wedged
, error_msg
);
2606 i915_report_and_clear_eir(dev
);
2609 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2610 &dev_priv
->gpu_error
.reset_counter
);
2613 * Wakeup waiting processes so that the reset work function
2614 * i915_error_work_func doesn't deadlock trying to grab various
2615 * locks. By bumping the reset counter first, the woken
2616 * processes will see a reset in progress and back off,
2617 * releasing their locks and then wait for the reset completion.
2618 * We must do this for _all_ gpu waiters that might hold locks
2619 * that the reset work needs to acquire.
2621 * Note: The wake_up serves as the required memory barrier to
2622 * ensure that the waiters see the updated value of the reset
2625 i915_error_wake_up(dev_priv
, false);
2629 * Our reset work can grab modeset locks (since it needs to reset the
2630 * state of outstanding pagelips). Hence it must not be run on our own
2631 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2632 * code will deadlock.
2634 schedule_work(&dev_priv
->gpu_error
.work
);
2637 /* Called from drm generic code, passed 'crtc' which
2638 * we use as a pipe index
2640 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2643 unsigned long irqflags
;
2645 if (!i915_pipe_enabled(dev
, pipe
))
2648 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2649 if (INTEL_INFO(dev
)->gen
>= 4)
2650 i915_enable_pipestat(dev_priv
, pipe
,
2651 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2653 i915_enable_pipestat(dev_priv
, pipe
,
2654 PIPE_VBLANK_INTERRUPT_STATUS
);
2655 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2660 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2663 unsigned long irqflags
;
2664 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2665 DE_PIPE_VBLANK(pipe
);
2667 if (!i915_pipe_enabled(dev
, pipe
))
2670 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2671 ironlake_enable_display_irq(dev_priv
, bit
);
2672 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2677 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2680 unsigned long irqflags
;
2682 if (!i915_pipe_enabled(dev
, pipe
))
2685 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2686 i915_enable_pipestat(dev_priv
, pipe
,
2687 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2688 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2693 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2696 unsigned long irqflags
;
2698 if (!i915_pipe_enabled(dev
, pipe
))
2701 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2702 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2703 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2704 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2705 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2709 /* Called from drm generic code, passed 'crtc' which
2710 * we use as a pipe index
2712 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2715 unsigned long irqflags
;
2717 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2718 i915_disable_pipestat(dev_priv
, pipe
,
2719 PIPE_VBLANK_INTERRUPT_STATUS
|
2720 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2721 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2724 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2727 unsigned long irqflags
;
2728 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2729 DE_PIPE_VBLANK(pipe
);
2731 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2732 ironlake_disable_display_irq(dev_priv
, bit
);
2733 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2736 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 unsigned long irqflags
;
2741 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2742 i915_disable_pipestat(dev_priv
, pipe
,
2743 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2744 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2747 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2750 unsigned long irqflags
;
2752 if (!i915_pipe_enabled(dev
, pipe
))
2755 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2756 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2757 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2758 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2759 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2762 static struct drm_i915_gem_request
*
2763 ring_last_request(struct intel_engine_cs
*ring
)
2765 return list_entry(ring
->request_list
.prev
,
2766 struct drm_i915_gem_request
, list
);
2770 ring_idle(struct intel_engine_cs
*ring
)
2772 return (list_empty(&ring
->request_list
) ||
2773 i915_gem_request_completed(ring_last_request(ring
), false));
2777 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2779 if (INTEL_INFO(dev
)->gen
>= 8) {
2780 return (ipehr
>> 23) == 0x1c;
2782 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2783 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2784 MI_SEMAPHORE_REGISTER
);
2788 static struct intel_engine_cs
*
2789 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring
, u32 ipehr
, u64 offset
)
2791 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2792 struct intel_engine_cs
*signaller
;
2795 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2796 for_each_ring(signaller
, dev_priv
, i
) {
2797 if (ring
== signaller
)
2800 if (offset
== signaller
->semaphore
.signal_ggtt
[ring
->id
])
2804 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2806 for_each_ring(signaller
, dev_priv
, i
) {
2807 if(ring
== signaller
)
2810 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2815 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2816 ring
->id
, ipehr
, offset
);
2821 static struct intel_engine_cs
*
2822 semaphore_waits_for(struct intel_engine_cs
*ring
, u32
*seqno
)
2824 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2825 u32 cmd
, ipehr
, head
;
2829 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2830 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2834 * HEAD is likely pointing to the dword after the actual command,
2835 * so scan backwards until we find the MBOX. But limit it to just 3
2836 * or 4 dwords depending on the semaphore wait command size.
2837 * Note that we don't care about ACTHD here since that might
2838 * point at at batch, and semaphores are always emitted into the
2839 * ringbuffer itself.
2841 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2842 backwards
= (INTEL_INFO(ring
->dev
)->gen
>= 8) ? 5 : 4;
2844 for (i
= backwards
; i
; --i
) {
2846 * Be paranoid and presume the hw has gone off into the wild -
2847 * our ring is smaller than what the hardware (and hence
2848 * HEAD_ADDR) allows. Also handles wrap-around.
2850 head
&= ring
->buffer
->size
- 1;
2852 /* This here seems to blow up */
2853 cmd
= ioread32(ring
->buffer
->virtual_start
+ head
);
2863 *seqno
= ioread32(ring
->buffer
->virtual_start
+ head
+ 4) + 1;
2864 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2865 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 12);
2867 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 8);
2869 return semaphore_wait_to_signaller_ring(ring
, ipehr
, offset
);
2872 static int semaphore_passed(struct intel_engine_cs
*ring
)
2874 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2875 struct intel_engine_cs
*signaller
;
2878 ring
->hangcheck
.deadlock
++;
2880 signaller
= semaphore_waits_for(ring
, &seqno
);
2881 if (signaller
== NULL
)
2884 /* Prevent pathological recursion due to driver bugs */
2885 if (signaller
->hangcheck
.deadlock
>= I915_NUM_RINGS
)
2888 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2891 /* cursory check for an unkickable deadlock */
2892 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2893 semaphore_passed(signaller
) < 0)
2899 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2901 struct intel_engine_cs
*ring
;
2904 for_each_ring(ring
, dev_priv
, i
)
2905 ring
->hangcheck
.deadlock
= 0;
2908 static enum intel_ring_hangcheck_action
2909 ring_stuck(struct intel_engine_cs
*ring
, u64 acthd
)
2911 struct drm_device
*dev
= ring
->dev
;
2912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2915 if (acthd
!= ring
->hangcheck
.acthd
) {
2916 if (acthd
> ring
->hangcheck
.max_acthd
) {
2917 ring
->hangcheck
.max_acthd
= acthd
;
2918 return HANGCHECK_ACTIVE
;
2921 return HANGCHECK_ACTIVE_LOOP
;
2925 return HANGCHECK_HUNG
;
2927 /* Is the chip hanging on a WAIT_FOR_EVENT?
2928 * If so we can simply poke the RB_WAIT bit
2929 * and break the hang. This should work on
2930 * all but the second generation chipsets.
2932 tmp
= I915_READ_CTL(ring
);
2933 if (tmp
& RING_WAIT
) {
2934 i915_handle_error(dev
, false,
2935 "Kicking stuck wait on %s",
2937 I915_WRITE_CTL(ring
, tmp
);
2938 return HANGCHECK_KICK
;
2941 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2942 switch (semaphore_passed(ring
)) {
2944 return HANGCHECK_HUNG
;
2946 i915_handle_error(dev
, false,
2947 "Kicking stuck semaphore on %s",
2949 I915_WRITE_CTL(ring
, tmp
);
2950 return HANGCHECK_KICK
;
2952 return HANGCHECK_WAIT
;
2956 return HANGCHECK_HUNG
;
2960 * This is called when the chip hasn't reported back with completed
2961 * batchbuffers in a long time. We keep track per ring seqno progress and
2962 * if there are no progress, hangcheck score for that ring is increased.
2963 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2964 * we kick the ring. If we see no progress on three subsequent calls
2965 * we assume chip is wedged and try to fix it by resetting the chip.
2967 static void i915_hangcheck_elapsed(unsigned long data
)
2969 struct drm_device
*dev
= (struct drm_device
*)data
;
2970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2971 struct intel_engine_cs
*ring
;
2973 int busy_count
= 0, rings_hung
= 0;
2974 bool stuck
[I915_NUM_RINGS
] = { 0 };
2979 if (!i915
.enable_hangcheck
)
2982 for_each_ring(ring
, dev_priv
, i
) {
2987 semaphore_clear_deadlocks(dev_priv
);
2989 seqno
= ring
->get_seqno(ring
, false);
2990 acthd
= intel_ring_get_active_head(ring
);
2992 if (ring
->hangcheck
.seqno
== seqno
) {
2993 if (ring_idle(ring
)) {
2994 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2996 if (waitqueue_active(&ring
->irq_queue
)) {
2997 /* Issue a wake-up to catch stuck h/w. */
2998 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2999 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
3000 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3003 DRM_INFO("Fake missed irq on %s\n",
3005 wake_up_all(&ring
->irq_queue
);
3007 /* Safeguard against driver failure */
3008 ring
->hangcheck
.score
+= BUSY
;
3012 /* We always increment the hangcheck score
3013 * if the ring is busy and still processing
3014 * the same request, so that no single request
3015 * can run indefinitely (such as a chain of
3016 * batches). The only time we do not increment
3017 * the hangcheck score on this ring, if this
3018 * ring is in a legitimate wait for another
3019 * ring. In that case the waiting ring is a
3020 * victim and we want to be sure we catch the
3021 * right culprit. Then every time we do kick
3022 * the ring, add a small increment to the
3023 * score so that we can catch a batch that is
3024 * being repeatedly kicked and so responsible
3025 * for stalling the machine.
3027 ring
->hangcheck
.action
= ring_stuck(ring
,
3030 switch (ring
->hangcheck
.action
) {
3031 case HANGCHECK_IDLE
:
3032 case HANGCHECK_WAIT
:
3033 case HANGCHECK_ACTIVE
:
3035 case HANGCHECK_ACTIVE_LOOP
:
3036 ring
->hangcheck
.score
+= BUSY
;
3038 case HANGCHECK_KICK
:
3039 ring
->hangcheck
.score
+= KICK
;
3041 case HANGCHECK_HUNG
:
3042 ring
->hangcheck
.score
+= HUNG
;
3048 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3050 /* Gradually reduce the count so that we catch DoS
3051 * attempts across multiple batches.
3053 if (ring
->hangcheck
.score
> 0)
3054 ring
->hangcheck
.score
--;
3056 ring
->hangcheck
.acthd
= ring
->hangcheck
.max_acthd
= 0;
3059 ring
->hangcheck
.seqno
= seqno
;
3060 ring
->hangcheck
.acthd
= acthd
;
3064 for_each_ring(ring
, dev_priv
, i
) {
3065 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3066 DRM_INFO("%s on %s\n",
3067 stuck
[i
] ? "stuck" : "no progress",
3074 return i915_handle_error(dev
, true, "Ring hung");
3077 /* Reset timer case chip hangs without another request
3079 i915_queue_hangcheck(dev
);
3082 void i915_queue_hangcheck(struct drm_device
*dev
)
3084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3085 struct timer_list
*timer
= &dev_priv
->gpu_error
.hangcheck_timer
;
3087 if (!i915
.enable_hangcheck
)
3090 /* Don't continually defer the hangcheck, but make sure it is active */
3091 if (timer_pending(timer
))
3094 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
3097 static void ibx_irq_reset(struct drm_device
*dev
)
3099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3101 if (HAS_PCH_NOP(dev
))
3104 GEN5_IRQ_RESET(SDE
);
3106 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3107 I915_WRITE(SERR_INT
, 0xffffffff);
3111 * SDEIER is also touched by the interrupt handler to work around missed PCH
3112 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3113 * instead we unconditionally enable all PCH interrupt sources here, but then
3114 * only unmask them as needed with SDEIMR.
3116 * This function needs to be called before interrupts are enabled.
3118 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3122 if (HAS_PCH_NOP(dev
))
3125 WARN_ON(I915_READ(SDEIER
) != 0);
3126 I915_WRITE(SDEIER
, 0xffffffff);
3127 POSTING_READ(SDEIER
);
3130 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3135 if (INTEL_INFO(dev
)->gen
>= 6)
3136 GEN5_IRQ_RESET(GEN6_PM
);
3141 static void ironlake_irq_reset(struct drm_device
*dev
)
3143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 I915_WRITE(HWSTAM
, 0xffffffff);
3149 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3151 gen5_gt_irq_reset(dev
);
3156 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3160 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3161 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3163 for_each_pipe(dev_priv
, pipe
)
3164 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3166 GEN5_IRQ_RESET(VLV_
);
3169 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3174 I915_WRITE(VLV_IMR
, 0);
3175 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3176 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3177 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3179 gen5_gt_irq_reset(dev
);
3181 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3183 vlv_display_irq_reset(dev_priv
);
3186 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3188 GEN8_IRQ_RESET_NDX(GT
, 0);
3189 GEN8_IRQ_RESET_NDX(GT
, 1);
3190 GEN8_IRQ_RESET_NDX(GT
, 2);
3191 GEN8_IRQ_RESET_NDX(GT
, 3);
3194 static void gen8_irq_reset(struct drm_device
*dev
)
3196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3199 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3200 POSTING_READ(GEN8_MASTER_IRQ
);
3202 gen8_gt_irq_reset(dev_priv
);
3204 for_each_pipe(dev_priv
, pipe
)
3205 if (intel_display_power_is_enabled(dev_priv
,
3206 POWER_DOMAIN_PIPE(pipe
)))
3207 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3209 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3210 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3211 GEN5_IRQ_RESET(GEN8_PCU_
);
3216 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
)
3218 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3220 spin_lock_irq(&dev_priv
->irq_lock
);
3221 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_B
, dev_priv
->de_irq_mask
[PIPE_B
],
3222 ~dev_priv
->de_irq_mask
[PIPE_B
] | extra_ier
);
3223 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_C
, dev_priv
->de_irq_mask
[PIPE_C
],
3224 ~dev_priv
->de_irq_mask
[PIPE_C
] | extra_ier
);
3225 spin_unlock_irq(&dev_priv
->irq_lock
);
3228 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3232 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3233 POSTING_READ(GEN8_MASTER_IRQ
);
3235 gen8_gt_irq_reset(dev_priv
);
3237 GEN5_IRQ_RESET(GEN8_PCU_
);
3239 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3241 vlv_display_irq_reset(dev_priv
);
3244 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3247 struct intel_encoder
*intel_encoder
;
3248 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
3250 if (HAS_PCH_IBX(dev
)) {
3251 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3252 for_each_intel_encoder(dev
, intel_encoder
)
3253 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3254 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3256 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3257 for_each_intel_encoder(dev
, intel_encoder
)
3258 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3259 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3262 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3265 * Enable digital hotplug on the PCH, and configure the DP short pulse
3266 * duration to 2ms (which is the minimum in the Display Port spec)
3268 * This register is the same on all known PCH chips.
3270 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3271 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3272 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3273 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3274 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3275 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3278 static void ibx_irq_postinstall(struct drm_device
*dev
)
3280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3283 if (HAS_PCH_NOP(dev
))
3286 if (HAS_PCH_IBX(dev
))
3287 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3289 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3291 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3292 I915_WRITE(SDEIMR
, ~mask
);
3295 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3298 u32 pm_irqs
, gt_irqs
;
3300 pm_irqs
= gt_irqs
= 0;
3302 dev_priv
->gt_irq_mask
= ~0;
3303 if (HAS_L3_DPF(dev
)) {
3304 /* L3 parity interrupt is always unmasked. */
3305 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3306 gt_irqs
|= GT_PARITY_ERROR(dev
);
3309 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3311 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3312 ILK_BSD_USER_INTERRUPT
;
3314 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3317 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3319 if (INTEL_INFO(dev
)->gen
>= 6) {
3321 * RPS interrupts will get enabled/disabled on demand when RPS
3322 * itself is enabled/disabled.
3325 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3327 dev_priv
->pm_irq_mask
= 0xffffffff;
3328 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3332 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3335 u32 display_mask
, extra_mask
;
3337 if (INTEL_INFO(dev
)->gen
>= 7) {
3338 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3339 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3340 DE_PLANEB_FLIP_DONE_IVB
|
3341 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3342 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3343 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3345 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3346 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3348 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3350 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3351 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3354 dev_priv
->irq_mask
= ~display_mask
;
3356 I915_WRITE(HWSTAM
, 0xeffe);
3358 ibx_irq_pre_postinstall(dev
);
3360 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3362 gen5_gt_irq_postinstall(dev
);
3364 ibx_irq_postinstall(dev
);
3366 if (IS_IRONLAKE_M(dev
)) {
3367 /* Enable PCU event interrupts
3369 * spinlocking not required here for correctness since interrupt
3370 * setup is guaranteed to run in single-threaded context. But we
3371 * need it to make the assert_spin_locked happy. */
3372 spin_lock_irq(&dev_priv
->irq_lock
);
3373 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3374 spin_unlock_irq(&dev_priv
->irq_lock
);
3380 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3386 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3387 PIPE_FIFO_UNDERRUN_STATUS
;
3389 for_each_pipe(dev_priv
, pipe
)
3390 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3391 POSTING_READ(PIPESTAT(PIPE_A
));
3393 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3394 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3396 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3397 for_each_pipe(dev_priv
, pipe
)
3398 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3400 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3401 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3402 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3403 if (IS_CHERRYVIEW(dev_priv
))
3404 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3405 dev_priv
->irq_mask
&= ~iir_mask
;
3407 I915_WRITE(VLV_IIR
, iir_mask
);
3408 I915_WRITE(VLV_IIR
, iir_mask
);
3409 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3410 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3411 POSTING_READ(VLV_IMR
);
3414 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3420 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3421 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3422 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3423 if (IS_CHERRYVIEW(dev_priv
))
3424 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3426 dev_priv
->irq_mask
|= iir_mask
;
3427 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3428 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3429 I915_WRITE(VLV_IIR
, iir_mask
);
3430 I915_WRITE(VLV_IIR
, iir_mask
);
3431 POSTING_READ(VLV_IIR
);
3433 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3434 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3436 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3437 for_each_pipe(dev_priv
, pipe
)
3438 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3440 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3441 PIPE_FIFO_UNDERRUN_STATUS
;
3443 for_each_pipe(dev_priv
, pipe
)
3444 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3445 POSTING_READ(PIPESTAT(PIPE_A
));
3448 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3450 assert_spin_locked(&dev_priv
->irq_lock
);
3452 if (dev_priv
->display_irqs_enabled
)
3455 dev_priv
->display_irqs_enabled
= true;
3457 if (intel_irqs_enabled(dev_priv
))
3458 valleyview_display_irqs_install(dev_priv
);
3461 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3463 assert_spin_locked(&dev_priv
->irq_lock
);
3465 if (!dev_priv
->display_irqs_enabled
)
3468 dev_priv
->display_irqs_enabled
= false;
3470 if (intel_irqs_enabled(dev_priv
))
3471 valleyview_display_irqs_uninstall(dev_priv
);
3474 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3476 dev_priv
->irq_mask
= ~0;
3478 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3479 POSTING_READ(PORT_HOTPLUG_EN
);
3481 I915_WRITE(VLV_IIR
, 0xffffffff);
3482 I915_WRITE(VLV_IIR
, 0xffffffff);
3483 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3484 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3485 POSTING_READ(VLV_IMR
);
3487 /* Interrupt setup is already guaranteed to be single-threaded, this is
3488 * just to make the assert_spin_locked check happy. */
3489 spin_lock_irq(&dev_priv
->irq_lock
);
3490 if (dev_priv
->display_irqs_enabled
)
3491 valleyview_display_irqs_install(dev_priv
);
3492 spin_unlock_irq(&dev_priv
->irq_lock
);
3495 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3499 vlv_display_irq_postinstall(dev_priv
);
3501 gen5_gt_irq_postinstall(dev
);
3503 /* ack & enable invalid PTE error interrupts */
3504 #if 0 /* FIXME: add support to irq handler for checking these bits */
3505 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3506 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3509 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3514 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3516 /* These are interrupts we'll toggle with the ring mask register */
3517 uint32_t gt_interrupts
[] = {
3518 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3519 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3520 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3521 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3522 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3523 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3524 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3525 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3526 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3528 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3529 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3532 dev_priv
->pm_irq_mask
= 0xffffffff;
3533 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3534 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3536 * RPS interrupts will get enabled/disabled on demand when RPS itself
3537 * is enabled/disabled.
3539 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3540 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3543 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3545 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3546 uint32_t de_pipe_enables
;
3548 u32 aux_en
= GEN8_AUX_CHANNEL_A
;
3550 if (IS_GEN9(dev_priv
)) {
3551 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3552 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3553 aux_en
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3556 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3557 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3559 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3560 GEN8_PIPE_FIFO_UNDERRUN
;
3562 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3563 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3564 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3566 for_each_pipe(dev_priv
, pipe
)
3567 if (intel_display_power_is_enabled(dev_priv
,
3568 POWER_DOMAIN_PIPE(pipe
)))
3569 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3570 dev_priv
->de_irq_mask
[pipe
],
3573 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~aux_en
, aux_en
);
3576 static int gen8_irq_postinstall(struct drm_device
*dev
)
3578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3580 ibx_irq_pre_postinstall(dev
);
3582 gen8_gt_irq_postinstall(dev_priv
);
3583 gen8_de_irq_postinstall(dev_priv
);
3585 ibx_irq_postinstall(dev
);
3587 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3588 POSTING_READ(GEN8_MASTER_IRQ
);
3593 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 vlv_display_irq_postinstall(dev_priv
);
3599 gen8_gt_irq_postinstall(dev_priv
);
3601 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3602 POSTING_READ(GEN8_MASTER_IRQ
);
3607 static void gen8_irq_uninstall(struct drm_device
*dev
)
3609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3614 gen8_irq_reset(dev
);
3617 static void vlv_display_irq_uninstall(struct drm_i915_private
*dev_priv
)
3619 /* Interrupt setup is already guaranteed to be single-threaded, this is
3620 * just to make the assert_spin_locked check happy. */
3621 spin_lock_irq(&dev_priv
->irq_lock
);
3622 if (dev_priv
->display_irqs_enabled
)
3623 valleyview_display_irqs_uninstall(dev_priv
);
3624 spin_unlock_irq(&dev_priv
->irq_lock
);
3626 vlv_display_irq_reset(dev_priv
);
3628 dev_priv
->irq_mask
= ~0;
3631 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3638 I915_WRITE(VLV_MASTER_IER
, 0);
3640 gen5_gt_irq_reset(dev
);
3642 I915_WRITE(HWSTAM
, 0xffffffff);
3644 vlv_display_irq_uninstall(dev_priv
);
3647 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3654 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3655 POSTING_READ(GEN8_MASTER_IRQ
);
3657 gen8_gt_irq_reset(dev_priv
);
3659 GEN5_IRQ_RESET(GEN8_PCU_
);
3661 vlv_display_irq_uninstall(dev_priv
);
3664 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3671 ironlake_irq_reset(dev
);
3674 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3679 for_each_pipe(dev_priv
, pipe
)
3680 I915_WRITE(PIPESTAT(pipe
), 0);
3681 I915_WRITE16(IMR
, 0xffff);
3682 I915_WRITE16(IER
, 0x0);
3683 POSTING_READ16(IER
);
3686 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3691 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3693 /* Unmask the interrupts that we always want on. */
3694 dev_priv
->irq_mask
=
3695 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3696 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3697 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3698 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3699 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3700 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3703 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3704 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3705 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3706 I915_USER_INTERRUPT
);
3707 POSTING_READ16(IER
);
3709 /* Interrupt setup is already guaranteed to be single-threaded, this is
3710 * just to make the assert_spin_locked check happy. */
3711 spin_lock_irq(&dev_priv
->irq_lock
);
3712 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3713 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3714 spin_unlock_irq(&dev_priv
->irq_lock
);
3720 * Returns true when a page flip has completed.
3722 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3723 int plane
, int pipe
, u32 iir
)
3725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3726 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3728 if (!intel_pipe_handle_vblank(dev
, pipe
))
3731 if ((iir
& flip_pending
) == 0)
3732 goto check_page_flip
;
3734 intel_prepare_page_flip(dev
, plane
);
3736 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3737 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3738 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3739 * the flip is completed (no longer pending). Since this doesn't raise
3740 * an interrupt per se, we watch for the change at vblank.
3742 if (I915_READ16(ISR
) & flip_pending
)
3743 goto check_page_flip
;
3745 intel_finish_page_flip(dev
, pipe
);
3749 intel_check_page_flip(dev
, pipe
);
3753 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3755 struct drm_device
*dev
= arg
;
3756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3761 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3762 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3764 iir
= I915_READ16(IIR
);
3768 while (iir
& ~flip_mask
) {
3769 /* Can't rely on pipestat interrupt bit in iir as it might
3770 * have been cleared after the pipestat interrupt was received.
3771 * It doesn't set the bit in iir again, but it still produces
3772 * interrupts (for non-MSI).
3774 spin_lock(&dev_priv
->irq_lock
);
3775 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3776 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3778 for_each_pipe(dev_priv
, pipe
) {
3779 int reg
= PIPESTAT(pipe
);
3780 pipe_stats
[pipe
] = I915_READ(reg
);
3783 * Clear the PIPE*STAT regs before the IIR
3785 if (pipe_stats
[pipe
] & 0x8000ffff)
3786 I915_WRITE(reg
, pipe_stats
[pipe
]);
3788 spin_unlock(&dev_priv
->irq_lock
);
3790 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3791 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3793 if (iir
& I915_USER_INTERRUPT
)
3794 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3796 for_each_pipe(dev_priv
, pipe
) {
3801 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3802 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3803 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3805 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3806 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3808 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3809 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3819 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 for_each_pipe(dev_priv
, pipe
) {
3825 /* Clear enable bits; then clear status bits */
3826 I915_WRITE(PIPESTAT(pipe
), 0);
3827 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3829 I915_WRITE16(IMR
, 0xffff);
3830 I915_WRITE16(IER
, 0x0);
3831 I915_WRITE16(IIR
, I915_READ16(IIR
));
3834 static void i915_irq_preinstall(struct drm_device
* dev
)
3836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3839 if (I915_HAS_HOTPLUG(dev
)) {
3840 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3841 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3844 I915_WRITE16(HWSTAM
, 0xeffe);
3845 for_each_pipe(dev_priv
, pipe
)
3846 I915_WRITE(PIPESTAT(pipe
), 0);
3847 I915_WRITE(IMR
, 0xffffffff);
3848 I915_WRITE(IER
, 0x0);
3852 static int i915_irq_postinstall(struct drm_device
*dev
)
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3857 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3859 /* Unmask the interrupts that we always want on. */
3860 dev_priv
->irq_mask
=
3861 ~(I915_ASLE_INTERRUPT
|
3862 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3863 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3864 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3865 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3866 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3869 I915_ASLE_INTERRUPT
|
3870 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3871 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3872 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3873 I915_USER_INTERRUPT
;
3875 if (I915_HAS_HOTPLUG(dev
)) {
3876 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3877 POSTING_READ(PORT_HOTPLUG_EN
);
3879 /* Enable in IER... */
3880 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3881 /* and unmask in IMR */
3882 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3885 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3886 I915_WRITE(IER
, enable_mask
);
3889 i915_enable_asle_pipestat(dev
);
3891 /* Interrupt setup is already guaranteed to be single-threaded, this is
3892 * just to make the assert_spin_locked check happy. */
3893 spin_lock_irq(&dev_priv
->irq_lock
);
3894 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3895 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3896 spin_unlock_irq(&dev_priv
->irq_lock
);
3902 * Returns true when a page flip has completed.
3904 static bool i915_handle_vblank(struct drm_device
*dev
,
3905 int plane
, int pipe
, u32 iir
)
3907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3908 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3910 if (!intel_pipe_handle_vblank(dev
, pipe
))
3913 if ((iir
& flip_pending
) == 0)
3914 goto check_page_flip
;
3916 intel_prepare_page_flip(dev
, plane
);
3918 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3919 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3920 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3921 * the flip is completed (no longer pending). Since this doesn't raise
3922 * an interrupt per se, we watch for the change at vblank.
3924 if (I915_READ(ISR
) & flip_pending
)
3925 goto check_page_flip
;
3927 intel_finish_page_flip(dev
, pipe
);
3931 intel_check_page_flip(dev
, pipe
);
3935 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3937 struct drm_device
*dev
= arg
;
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3939 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3941 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3942 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3943 int pipe
, ret
= IRQ_NONE
;
3945 iir
= I915_READ(IIR
);
3947 bool irq_received
= (iir
& ~flip_mask
) != 0;
3948 bool blc_event
= false;
3950 /* Can't rely on pipestat interrupt bit in iir as it might
3951 * have been cleared after the pipestat interrupt was received.
3952 * It doesn't set the bit in iir again, but it still produces
3953 * interrupts (for non-MSI).
3955 spin_lock(&dev_priv
->irq_lock
);
3956 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3957 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3959 for_each_pipe(dev_priv
, pipe
) {
3960 int reg
= PIPESTAT(pipe
);
3961 pipe_stats
[pipe
] = I915_READ(reg
);
3963 /* Clear the PIPE*STAT regs before the IIR */
3964 if (pipe_stats
[pipe
] & 0x8000ffff) {
3965 I915_WRITE(reg
, pipe_stats
[pipe
]);
3966 irq_received
= true;
3969 spin_unlock(&dev_priv
->irq_lock
);
3974 /* Consume port. Then clear IIR or we'll miss events */
3975 if (I915_HAS_HOTPLUG(dev
) &&
3976 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3977 i9xx_hpd_irq_handler(dev
);
3979 I915_WRITE(IIR
, iir
& ~flip_mask
);
3980 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3982 if (iir
& I915_USER_INTERRUPT
)
3983 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3985 for_each_pipe(dev_priv
, pipe
) {
3990 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3991 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3992 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3994 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3997 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3998 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4000 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4001 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4005 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4006 intel_opregion_asle_intr(dev
);
4008 /* With MSI, interrupts are only generated when iir
4009 * transitions from zero to nonzero. If another bit got
4010 * set while we were handling the existing iir bits, then
4011 * we would never get another interrupt.
4013 * This is fine on non-MSI as well, as if we hit this path
4014 * we avoid exiting the interrupt handler only to generate
4017 * Note that for MSI this could cause a stray interrupt report
4018 * if an interrupt landed in the time between writing IIR and
4019 * the posting read. This should be rare enough to never
4020 * trigger the 99% of 100,000 interrupts test for disabling
4025 } while (iir
& ~flip_mask
);
4030 static void i915_irq_uninstall(struct drm_device
* dev
)
4032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4035 if (I915_HAS_HOTPLUG(dev
)) {
4036 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4037 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4040 I915_WRITE16(HWSTAM
, 0xffff);
4041 for_each_pipe(dev_priv
, pipe
) {
4042 /* Clear enable bits; then clear status bits */
4043 I915_WRITE(PIPESTAT(pipe
), 0);
4044 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4046 I915_WRITE(IMR
, 0xffffffff);
4047 I915_WRITE(IER
, 0x0);
4049 I915_WRITE(IIR
, I915_READ(IIR
));
4052 static void i965_irq_preinstall(struct drm_device
* dev
)
4054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4057 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4058 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4060 I915_WRITE(HWSTAM
, 0xeffe);
4061 for_each_pipe(dev_priv
, pipe
)
4062 I915_WRITE(PIPESTAT(pipe
), 0);
4063 I915_WRITE(IMR
, 0xffffffff);
4064 I915_WRITE(IER
, 0x0);
4068 static int i965_irq_postinstall(struct drm_device
*dev
)
4070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4074 /* Unmask the interrupts that we always want on. */
4075 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4076 I915_DISPLAY_PORT_INTERRUPT
|
4077 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4078 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4079 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4080 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4081 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4083 enable_mask
= ~dev_priv
->irq_mask
;
4084 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4085 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4086 enable_mask
|= I915_USER_INTERRUPT
;
4089 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4091 /* Interrupt setup is already guaranteed to be single-threaded, this is
4092 * just to make the assert_spin_locked check happy. */
4093 spin_lock_irq(&dev_priv
->irq_lock
);
4094 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4095 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4096 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4097 spin_unlock_irq(&dev_priv
->irq_lock
);
4100 * Enable some error detection, note the instruction error mask
4101 * bit is reserved, so we leave it masked.
4104 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4105 GM45_ERROR_MEM_PRIV
|
4106 GM45_ERROR_CP_PRIV
|
4107 I915_ERROR_MEMORY_REFRESH
);
4109 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4110 I915_ERROR_MEMORY_REFRESH
);
4112 I915_WRITE(EMR
, error_mask
);
4114 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4115 I915_WRITE(IER
, enable_mask
);
4118 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4119 POSTING_READ(PORT_HOTPLUG_EN
);
4121 i915_enable_asle_pipestat(dev
);
4126 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4129 struct intel_encoder
*intel_encoder
;
4132 assert_spin_locked(&dev_priv
->irq_lock
);
4134 if (I915_HAS_HOTPLUG(dev
)) {
4135 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
4136 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
4137 /* Note HDMI and DP share hotplug bits */
4138 /* enable bits are the same for all generations */
4139 for_each_intel_encoder(dev
, intel_encoder
)
4140 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
4141 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
4142 /* Programming the CRT detection parameters tends
4143 to generate a spurious hotplug event about three
4144 seconds later. So just do it once.
4147 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4148 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
4149 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4151 /* Ignore TV since it's buggy */
4152 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
4156 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4158 struct drm_device
*dev
= arg
;
4159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4161 u32 pipe_stats
[I915_MAX_PIPES
];
4162 int ret
= IRQ_NONE
, pipe
;
4164 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4165 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4167 iir
= I915_READ(IIR
);
4170 bool irq_received
= (iir
& ~flip_mask
) != 0;
4171 bool blc_event
= false;
4173 /* Can't rely on pipestat interrupt bit in iir as it might
4174 * have been cleared after the pipestat interrupt was received.
4175 * It doesn't set the bit in iir again, but it still produces
4176 * interrupts (for non-MSI).
4178 spin_lock(&dev_priv
->irq_lock
);
4179 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4180 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4182 for_each_pipe(dev_priv
, pipe
) {
4183 int reg
= PIPESTAT(pipe
);
4184 pipe_stats
[pipe
] = I915_READ(reg
);
4187 * Clear the PIPE*STAT regs before the IIR
4189 if (pipe_stats
[pipe
] & 0x8000ffff) {
4190 I915_WRITE(reg
, pipe_stats
[pipe
]);
4191 irq_received
= true;
4194 spin_unlock(&dev_priv
->irq_lock
);
4201 /* Consume port. Then clear IIR or we'll miss events */
4202 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4203 i9xx_hpd_irq_handler(dev
);
4205 I915_WRITE(IIR
, iir
& ~flip_mask
);
4206 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4208 if (iir
& I915_USER_INTERRUPT
)
4209 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
4210 if (iir
& I915_BSD_USER_INTERRUPT
)
4211 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
4213 for_each_pipe(dev_priv
, pipe
) {
4214 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4215 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4216 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4218 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4221 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4222 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4224 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4225 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4228 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4229 intel_opregion_asle_intr(dev
);
4231 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4232 gmbus_irq_handler(dev
);
4234 /* With MSI, interrupts are only generated when iir
4235 * transitions from zero to nonzero. If another bit got
4236 * set while we were handling the existing iir bits, then
4237 * we would never get another interrupt.
4239 * This is fine on non-MSI as well, as if we hit this path
4240 * we avoid exiting the interrupt handler only to generate
4243 * Note that for MSI this could cause a stray interrupt report
4244 * if an interrupt landed in the time between writing IIR and
4245 * the posting read. This should be rare enough to never
4246 * trigger the 99% of 100,000 interrupts test for disabling
4255 static void i965_irq_uninstall(struct drm_device
* dev
)
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4263 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4264 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4266 I915_WRITE(HWSTAM
, 0xffffffff);
4267 for_each_pipe(dev_priv
, pipe
)
4268 I915_WRITE(PIPESTAT(pipe
), 0);
4269 I915_WRITE(IMR
, 0xffffffff);
4270 I915_WRITE(IER
, 0x0);
4272 for_each_pipe(dev_priv
, pipe
)
4273 I915_WRITE(PIPESTAT(pipe
),
4274 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4275 I915_WRITE(IIR
, I915_READ(IIR
));
4278 static void intel_hpd_irq_reenable_work(struct work_struct
*work
)
4280 struct drm_i915_private
*dev_priv
=
4281 container_of(work
, typeof(*dev_priv
),
4282 hotplug_reenable_work
.work
);
4283 struct drm_device
*dev
= dev_priv
->dev
;
4284 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4287 intel_runtime_pm_get(dev_priv
);
4289 spin_lock_irq(&dev_priv
->irq_lock
);
4290 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
4291 struct drm_connector
*connector
;
4293 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
4296 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4298 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4299 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4301 if (intel_connector
->encoder
->hpd_pin
== i
) {
4302 if (connector
->polled
!= intel_connector
->polled
)
4303 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4305 connector
->polled
= intel_connector
->polled
;
4306 if (!connector
->polled
)
4307 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4311 if (dev_priv
->display
.hpd_irq_setup
)
4312 dev_priv
->display
.hpd_irq_setup(dev
);
4313 spin_unlock_irq(&dev_priv
->irq_lock
);
4315 intel_runtime_pm_put(dev_priv
);
4319 * intel_irq_init - initializes irq support
4320 * @dev_priv: i915 device instance
4322 * This function initializes all the irq support including work items, timers
4323 * and all the vtables. It does not setup the interrupt itself though.
4325 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4327 struct drm_device
*dev
= dev_priv
->dev
;
4329 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
4330 INIT_WORK(&dev_priv
->dig_port_work
, i915_digport_work_func
);
4331 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
4332 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4333 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4335 /* Let's track the enabled rps events */
4336 if (IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
4337 /* WaGsvRC0ResidencyMethod:vlv */
4338 dev_priv
->pm_rps_events
= GEN6_PM_RP_UP_EI_EXPIRED
;
4340 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4342 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
4343 i915_hangcheck_elapsed
,
4344 (unsigned long) dev
);
4345 INIT_DELAYED_WORK(&dev_priv
->hotplug_reenable_work
,
4346 intel_hpd_irq_reenable_work
);
4348 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4350 if (IS_GEN2(dev_priv
)) {
4351 dev
->max_vblank_count
= 0;
4352 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4353 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4354 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4355 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4357 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4358 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4362 * Opt out of the vblank disable timer on everything except gen2.
4363 * Gen2 doesn't have a hardware frame counter and so depends on
4364 * vblank interrupts to produce sane vblank seuquence numbers.
4366 if (!IS_GEN2(dev_priv
))
4367 dev
->vblank_disable_immediate
= true;
4369 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4370 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4371 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4374 if (IS_CHERRYVIEW(dev_priv
)) {
4375 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4376 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4377 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4378 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4379 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4380 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4381 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4382 } else if (IS_VALLEYVIEW(dev_priv
)) {
4383 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4384 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4385 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4386 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4387 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4388 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4389 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4390 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4391 dev
->driver
->irq_handler
= gen8_irq_handler
;
4392 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4393 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4394 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4395 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4396 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4397 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4398 } else if (HAS_PCH_SPLIT(dev
)) {
4399 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4400 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4401 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4402 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4403 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4404 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4405 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4407 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4408 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4409 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4410 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4411 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4412 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4413 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4414 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4415 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4416 dev
->driver
->irq_handler
= i915_irq_handler
;
4417 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4419 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4420 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4421 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4422 dev
->driver
->irq_handler
= i965_irq_handler
;
4423 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4425 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4426 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4431 * intel_hpd_init - initializes and enables hpd support
4432 * @dev_priv: i915 device instance
4434 * This function enables the hotplug support. It requires that interrupts have
4435 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4436 * poll request can run concurrently to other code, so locking rules must be
4439 * This is a separate step from interrupt enabling to simplify the locking rules
4440 * in the driver load and resume code.
4442 void intel_hpd_init(struct drm_i915_private
*dev_priv
)
4444 struct drm_device
*dev
= dev_priv
->dev
;
4445 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4446 struct drm_connector
*connector
;
4449 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4450 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4451 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4453 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4454 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4455 connector
->polled
= intel_connector
->polled
;
4456 if (connector
->encoder
&& !connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4457 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4458 if (intel_connector
->mst_port
)
4459 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4462 /* Interrupt setup is already guaranteed to be single-threaded, this is
4463 * just to make the assert_spin_locked checks happy. */
4464 spin_lock_irq(&dev_priv
->irq_lock
);
4465 if (dev_priv
->display
.hpd_irq_setup
)
4466 dev_priv
->display
.hpd_irq_setup(dev
);
4467 spin_unlock_irq(&dev_priv
->irq_lock
);
4471 * intel_irq_install - enables the hardware interrupt
4472 * @dev_priv: i915 device instance
4474 * This function enables the hardware interrupt handling, but leaves the hotplug
4475 * handling still disabled. It is called after intel_irq_init().
4477 * In the driver load and resume code we need working interrupts in a few places
4478 * but don't want to deal with the hassle of concurrent probe and hotplug
4479 * workers. Hence the split into this two-stage approach.
4481 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4484 * We enable some interrupt sources in our postinstall hooks, so mark
4485 * interrupts as enabled _before_ actually enabling them to avoid
4486 * special cases in our ordering checks.
4488 dev_priv
->pm
.irqs_enabled
= true;
4490 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4494 * intel_irq_uninstall - finilizes all irq handling
4495 * @dev_priv: i915 device instance
4497 * This stops interrupt and hotplug handling and unregisters and frees all
4498 * resources acquired in the init functions.
4500 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4502 drm_irq_uninstall(dev_priv
->dev
);
4503 intel_hpd_cancel_work(dev_priv
);
4504 dev_priv
->pm
.irqs_enabled
= false;
4508 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4509 * @dev_priv: i915 device instance
4511 * This function is used to disable interrupts at runtime, both in the runtime
4512 * pm and the system suspend/resume code.
4514 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4516 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4517 dev_priv
->pm
.irqs_enabled
= false;
4521 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4522 * @dev_priv: i915 device instance
4524 * This function is used to enable interrupts at runtime, both in the runtime
4525 * pm and the system suspend/resume code.
4527 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4529 dev_priv
->pm
.irqs_enabled
= true;
4530 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4531 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);