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drm/i915: Rename 'tmp_mask'
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
34
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
37
38 #include "display/intel_display_types.h"
39 #include "display/intel_fifo_underrun.h"
40 #include "display/intel_hotplug.h"
41 #include "display/intel_lpe_audio.h"
42 #include "display/intel_psr.h"
43
44 #include "gt/intel_breadcrumbs.h"
45 #include "gt/intel_gt.h"
46 #include "gt/intel_gt_irq.h"
47 #include "gt/intel_gt_pm_irq.h"
48 #include "gt/intel_rps.h"
49
50 #include "i915_drv.h"
51 #include "i915_irq.h"
52 #include "i915_trace.h"
53 #include "intel_pm.h"
54
55 /**
56 * DOC: interrupt handling
57 *
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
61 */
62
63 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
64
65 static const u32 hpd_ilk[HPD_NUM_PINS] = {
66 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
67 };
68
69 static const u32 hpd_ivb[HPD_NUM_PINS] = {
70 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
71 };
72
73 static const u32 hpd_bdw[HPD_NUM_PINS] = {
74 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
75 };
76
77 static const u32 hpd_ibx[HPD_NUM_PINS] = {
78 [HPD_CRT] = SDE_CRT_HOTPLUG,
79 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
80 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
81 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
82 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
83 };
84
85 static const u32 hpd_cpt[HPD_NUM_PINS] = {
86 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
87 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
88 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
89 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
90 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
91 };
92
93 static const u32 hpd_spt[HPD_NUM_PINS] = {
94 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
95 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
96 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
97 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
98 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
99 };
100
101 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
102 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
103 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
104 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
105 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
106 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
107 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
108 };
109
110 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
111 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
112 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
113 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
114 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
115 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
116 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
117 };
118
119 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
120 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
121 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
122 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
123 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
124 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
125 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
126 };
127
128 static const u32 hpd_bxt[HPD_NUM_PINS] = {
129 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
130 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
131 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
132 };
133
134 static const u32 hpd_gen11[HPD_NUM_PINS] = {
135 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
136 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
137 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
138 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
139 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
140 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
141 };
142
143 static const u32 hpd_icp[HPD_NUM_PINS] = {
144 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
145 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
146 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
147 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
148 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
149 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
150 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
151 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
152 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
153 };
154
155 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
156 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
157 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
158 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
159 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
160 };
161
162 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
163 {
164 struct i915_hotplug *hpd = &dev_priv->hotplug;
165
166 if (HAS_GMCH(dev_priv)) {
167 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
168 IS_CHERRYVIEW(dev_priv))
169 hpd->hpd = hpd_status_g4x;
170 else
171 hpd->hpd = hpd_status_i915;
172 return;
173 }
174
175 if (INTEL_GEN(dev_priv) >= 11)
176 hpd->hpd = hpd_gen11;
177 else if (IS_GEN9_LP(dev_priv))
178 hpd->hpd = hpd_bxt;
179 else if (INTEL_GEN(dev_priv) >= 8)
180 hpd->hpd = hpd_bdw;
181 else if (INTEL_GEN(dev_priv) >= 7)
182 hpd->hpd = hpd_ivb;
183 else
184 hpd->hpd = hpd_ilk;
185
186 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
187 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
188 return;
189
190 if (HAS_PCH_DG1(dev_priv))
191 hpd->pch_hpd = hpd_sde_dg1;
192 else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
193 HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
194 hpd->pch_hpd = hpd_icp;
195 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
196 hpd->pch_hpd = hpd_spt;
197 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
198 hpd->pch_hpd = hpd_cpt;
199 else if (HAS_PCH_IBX(dev_priv))
200 hpd->pch_hpd = hpd_ibx;
201 else
202 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
203 }
204
205 static void
206 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
207 {
208 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
209
210 drm_crtc_handle_vblank(&crtc->base);
211 }
212
213 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
214 i915_reg_t iir, i915_reg_t ier)
215 {
216 intel_uncore_write(uncore, imr, 0xffffffff);
217 intel_uncore_posting_read(uncore, imr);
218
219 intel_uncore_write(uncore, ier, 0);
220
221 /* IIR can theoretically queue up two events. Be paranoid. */
222 intel_uncore_write(uncore, iir, 0xffffffff);
223 intel_uncore_posting_read(uncore, iir);
224 intel_uncore_write(uncore, iir, 0xffffffff);
225 intel_uncore_posting_read(uncore, iir);
226 }
227
228 void gen2_irq_reset(struct intel_uncore *uncore)
229 {
230 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
231 intel_uncore_posting_read16(uncore, GEN2_IMR);
232
233 intel_uncore_write16(uncore, GEN2_IER, 0);
234
235 /* IIR can theoretically queue up two events. Be paranoid. */
236 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
237 intel_uncore_posting_read16(uncore, GEN2_IIR);
238 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
239 intel_uncore_posting_read16(uncore, GEN2_IIR);
240 }
241
242 /*
243 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
244 */
245 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
246 {
247 u32 val = intel_uncore_read(uncore, reg);
248
249 if (val == 0)
250 return;
251
252 drm_WARN(&uncore->i915->drm, 1,
253 "Interrupt register 0x%x is not zero: 0x%08x\n",
254 i915_mmio_reg_offset(reg), val);
255 intel_uncore_write(uncore, reg, 0xffffffff);
256 intel_uncore_posting_read(uncore, reg);
257 intel_uncore_write(uncore, reg, 0xffffffff);
258 intel_uncore_posting_read(uncore, reg);
259 }
260
261 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
262 {
263 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
264
265 if (val == 0)
266 return;
267
268 drm_WARN(&uncore->i915->drm, 1,
269 "Interrupt register 0x%x is not zero: 0x%08x\n",
270 i915_mmio_reg_offset(GEN2_IIR), val);
271 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
272 intel_uncore_posting_read16(uncore, GEN2_IIR);
273 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
274 intel_uncore_posting_read16(uncore, GEN2_IIR);
275 }
276
277 void gen3_irq_init(struct intel_uncore *uncore,
278 i915_reg_t imr, u32 imr_val,
279 i915_reg_t ier, u32 ier_val,
280 i915_reg_t iir)
281 {
282 gen3_assert_iir_is_zero(uncore, iir);
283
284 intel_uncore_write(uncore, ier, ier_val);
285 intel_uncore_write(uncore, imr, imr_val);
286 intel_uncore_posting_read(uncore, imr);
287 }
288
289 void gen2_irq_init(struct intel_uncore *uncore,
290 u32 imr_val, u32 ier_val)
291 {
292 gen2_assert_iir_is_zero(uncore);
293
294 intel_uncore_write16(uncore, GEN2_IER, ier_val);
295 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
296 intel_uncore_posting_read16(uncore, GEN2_IMR);
297 }
298
299 /* For display hotplug interrupt */
300 static inline void
301 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
302 u32 mask,
303 u32 bits)
304 {
305 u32 val;
306
307 lockdep_assert_held(&dev_priv->irq_lock);
308 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
309
310 val = I915_READ(PORT_HOTPLUG_EN);
311 val &= ~mask;
312 val |= bits;
313 I915_WRITE(PORT_HOTPLUG_EN, val);
314 }
315
316 /**
317 * i915_hotplug_interrupt_update - update hotplug interrupt enable
318 * @dev_priv: driver private
319 * @mask: bits to update
320 * @bits: bits to enable
321 * NOTE: the HPD enable bits are modified both inside and outside
322 * of an interrupt context. To avoid that read-modify-write cycles
323 * interfer, these bits are protected by a spinlock. Since this
324 * function is usually not called from a context where the lock is
325 * held already, this function acquires the lock itself. A non-locking
326 * version is also available.
327 */
328 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
329 u32 mask,
330 u32 bits)
331 {
332 spin_lock_irq(&dev_priv->irq_lock);
333 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
334 spin_unlock_irq(&dev_priv->irq_lock);
335 }
336
337 /**
338 * ilk_update_display_irq - update DEIMR
339 * @dev_priv: driver private
340 * @interrupt_mask: mask of interrupt bits to update
341 * @enabled_irq_mask: mask of interrupt bits to enable
342 */
343 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
344 u32 interrupt_mask,
345 u32 enabled_irq_mask)
346 {
347 u32 new_val;
348
349 lockdep_assert_held(&dev_priv->irq_lock);
350 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
351
352 new_val = dev_priv->irq_mask;
353 new_val &= ~interrupt_mask;
354 new_val |= (~enabled_irq_mask & interrupt_mask);
355
356 if (new_val != dev_priv->irq_mask &&
357 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
358 dev_priv->irq_mask = new_val;
359 I915_WRITE(DEIMR, dev_priv->irq_mask);
360 POSTING_READ(DEIMR);
361 }
362 }
363
364 /**
365 * bdw_update_port_irq - update DE port interrupt
366 * @dev_priv: driver private
367 * @interrupt_mask: mask of interrupt bits to update
368 * @enabled_irq_mask: mask of interrupt bits to enable
369 */
370 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
371 u32 interrupt_mask,
372 u32 enabled_irq_mask)
373 {
374 u32 new_val;
375 u32 old_val;
376
377 lockdep_assert_held(&dev_priv->irq_lock);
378
379 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
380
381 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
382 return;
383
384 old_val = I915_READ(GEN8_DE_PORT_IMR);
385
386 new_val = old_val;
387 new_val &= ~interrupt_mask;
388 new_val |= (~enabled_irq_mask & interrupt_mask);
389
390 if (new_val != old_val) {
391 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
392 POSTING_READ(GEN8_DE_PORT_IMR);
393 }
394 }
395
396 /**
397 * bdw_update_pipe_irq - update DE pipe interrupt
398 * @dev_priv: driver private
399 * @pipe: pipe whose interrupt to update
400 * @interrupt_mask: mask of interrupt bits to update
401 * @enabled_irq_mask: mask of interrupt bits to enable
402 */
403 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
404 enum pipe pipe,
405 u32 interrupt_mask,
406 u32 enabled_irq_mask)
407 {
408 u32 new_val;
409
410 lockdep_assert_held(&dev_priv->irq_lock);
411
412 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
413
414 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
415 return;
416
417 new_val = dev_priv->de_irq_mask[pipe];
418 new_val &= ~interrupt_mask;
419 new_val |= (~enabled_irq_mask & interrupt_mask);
420
421 if (new_val != dev_priv->de_irq_mask[pipe]) {
422 dev_priv->de_irq_mask[pipe] = new_val;
423 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
424 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
425 }
426 }
427
428 /**
429 * ibx_display_interrupt_update - update SDEIMR
430 * @dev_priv: driver private
431 * @interrupt_mask: mask of interrupt bits to update
432 * @enabled_irq_mask: mask of interrupt bits to enable
433 */
434 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
435 u32 interrupt_mask,
436 u32 enabled_irq_mask)
437 {
438 u32 sdeimr = I915_READ(SDEIMR);
439 sdeimr &= ~interrupt_mask;
440 sdeimr |= (~enabled_irq_mask & interrupt_mask);
441
442 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
443
444 lockdep_assert_held(&dev_priv->irq_lock);
445
446 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
447 return;
448
449 I915_WRITE(SDEIMR, sdeimr);
450 POSTING_READ(SDEIMR);
451 }
452
453 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
454 enum pipe pipe)
455 {
456 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
457 u32 enable_mask = status_mask << 16;
458
459 lockdep_assert_held(&dev_priv->irq_lock);
460
461 if (INTEL_GEN(dev_priv) < 5)
462 goto out;
463
464 /*
465 * On pipe A we don't support the PSR interrupt yet,
466 * on pipe B and C the same bit MBZ.
467 */
468 if (drm_WARN_ON_ONCE(&dev_priv->drm,
469 status_mask & PIPE_A_PSR_STATUS_VLV))
470 return 0;
471 /*
472 * On pipe B and C we don't support the PSR interrupt yet, on pipe
473 * A the same bit is for perf counters which we don't use either.
474 */
475 if (drm_WARN_ON_ONCE(&dev_priv->drm,
476 status_mask & PIPE_B_PSR_STATUS_VLV))
477 return 0;
478
479 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
480 SPRITE0_FLIP_DONE_INT_EN_VLV |
481 SPRITE1_FLIP_DONE_INT_EN_VLV);
482 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
483 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
484 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
485 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
486
487 out:
488 drm_WARN_ONCE(&dev_priv->drm,
489 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
490 status_mask & ~PIPESTAT_INT_STATUS_MASK,
491 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
492 pipe_name(pipe), enable_mask, status_mask);
493
494 return enable_mask;
495 }
496
497 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
498 enum pipe pipe, u32 status_mask)
499 {
500 i915_reg_t reg = PIPESTAT(pipe);
501 u32 enable_mask;
502
503 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
504 "pipe %c: status_mask=0x%x\n",
505 pipe_name(pipe), status_mask);
506
507 lockdep_assert_held(&dev_priv->irq_lock);
508 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
509
510 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
511 return;
512
513 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
514 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
515
516 I915_WRITE(reg, enable_mask | status_mask);
517 POSTING_READ(reg);
518 }
519
520 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
521 enum pipe pipe, u32 status_mask)
522 {
523 i915_reg_t reg = PIPESTAT(pipe);
524 u32 enable_mask;
525
526 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
527 "pipe %c: status_mask=0x%x\n",
528 pipe_name(pipe), status_mask);
529
530 lockdep_assert_held(&dev_priv->irq_lock);
531 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
532
533 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
534 return;
535
536 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
537 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
538
539 I915_WRITE(reg, enable_mask | status_mask);
540 POSTING_READ(reg);
541 }
542
543 static bool i915_has_asle(struct drm_i915_private *dev_priv)
544 {
545 if (!dev_priv->opregion.asle)
546 return false;
547
548 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
549 }
550
551 /**
552 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
553 * @dev_priv: i915 device private
554 */
555 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
556 {
557 if (!i915_has_asle(dev_priv))
558 return;
559
560 spin_lock_irq(&dev_priv->irq_lock);
561
562 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
563 if (INTEL_GEN(dev_priv) >= 4)
564 i915_enable_pipestat(dev_priv, PIPE_A,
565 PIPE_LEGACY_BLC_EVENT_STATUS);
566
567 spin_unlock_irq(&dev_priv->irq_lock);
568 }
569
570 /*
571 * This timing diagram depicts the video signal in and
572 * around the vertical blanking period.
573 *
574 * Assumptions about the fictitious mode used in this example:
575 * vblank_start >= 3
576 * vsync_start = vblank_start + 1
577 * vsync_end = vblank_start + 2
578 * vtotal = vblank_start + 3
579 *
580 * start of vblank:
581 * latch double buffered registers
582 * increment frame counter (ctg+)
583 * generate start of vblank interrupt (gen4+)
584 * |
585 * | frame start:
586 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
587 * | may be shifted forward 1-3 extra lines via PIPECONF
588 * | |
589 * | | start of vsync:
590 * | | generate vsync interrupt
591 * | | |
592 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
593 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
594 * ----va---> <-----------------vb--------------------> <--------va-------------
595 * | | <----vs-----> |
596 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
597 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
598 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
599 * | | |
600 * last visible pixel first visible pixel
601 * | increment frame counter (gen3/4)
602 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
603 *
604 * x = horizontal active
605 * _ = horizontal blanking
606 * hs = horizontal sync
607 * va = vertical active
608 * vb = vertical blanking
609 * vs = vertical sync
610 * vbs = vblank_start (number)
611 *
612 * Summary:
613 * - most events happen at the start of horizontal sync
614 * - frame start happens at the start of horizontal blank, 1-4 lines
615 * (depending on PIPECONF settings) after the start of vblank
616 * - gen3/4 pixel and frame counter are synchronized with the start
617 * of horizontal active on the first line of vertical active
618 */
619
620 /* Called from drm generic code, passed a 'crtc', which
621 * we use as a pipe index
622 */
623 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
624 {
625 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
626 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
627 const struct drm_display_mode *mode = &vblank->hwmode;
628 enum pipe pipe = to_intel_crtc(crtc)->pipe;
629 i915_reg_t high_frame, low_frame;
630 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
631 unsigned long irqflags;
632
633 /*
634 * On i965gm TV output the frame counter only works up to
635 * the point when we enable the TV encoder. After that the
636 * frame counter ceases to work and reads zero. We need a
637 * vblank wait before enabling the TV encoder and so we
638 * have to enable vblank interrupts while the frame counter
639 * is still in a working state. However the core vblank code
640 * does not like us returning non-zero frame counter values
641 * when we've told it that we don't have a working frame
642 * counter. Thus we must stop non-zero values leaking out.
643 */
644 if (!vblank->max_vblank_count)
645 return 0;
646
647 htotal = mode->crtc_htotal;
648 hsync_start = mode->crtc_hsync_start;
649 vbl_start = mode->crtc_vblank_start;
650 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
651 vbl_start = DIV_ROUND_UP(vbl_start, 2);
652
653 /* Convert to pixel count */
654 vbl_start *= htotal;
655
656 /* Start of vblank event occurs at start of hsync */
657 vbl_start -= htotal - hsync_start;
658
659 high_frame = PIPEFRAME(pipe);
660 low_frame = PIPEFRAMEPIXEL(pipe);
661
662 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
663
664 /*
665 * High & low register fields aren't synchronized, so make sure
666 * we get a low value that's stable across two reads of the high
667 * register.
668 */
669 do {
670 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
671 low = intel_de_read_fw(dev_priv, low_frame);
672 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
673 } while (high1 != high2);
674
675 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
676
677 high1 >>= PIPE_FRAME_HIGH_SHIFT;
678 pixel = low & PIPE_PIXEL_MASK;
679 low >>= PIPE_FRAME_LOW_SHIFT;
680
681 /*
682 * The frame counter increments at beginning of active.
683 * Cook up a vblank counter by also checking the pixel
684 * counter against vblank start.
685 */
686 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
687 }
688
689 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
690 {
691 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
692 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
693 enum pipe pipe = to_intel_crtc(crtc)->pipe;
694
695 if (!vblank->max_vblank_count)
696 return 0;
697
698 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
699 }
700
701 /*
702 * On certain encoders on certain platforms, pipe
703 * scanline register will not work to get the scanline,
704 * since the timings are driven from the PORT or issues
705 * with scanline register updates.
706 * This function will use Framestamp and current
707 * timestamp registers to calculate the scanline.
708 */
709 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
710 {
711 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
712 struct drm_vblank_crtc *vblank =
713 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
714 const struct drm_display_mode *mode = &vblank->hwmode;
715 u32 vblank_start = mode->crtc_vblank_start;
716 u32 vtotal = mode->crtc_vtotal;
717 u32 htotal = mode->crtc_htotal;
718 u32 clock = mode->crtc_clock;
719 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
720
721 /*
722 * To avoid the race condition where we might cross into the
723 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
724 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
725 * during the same frame.
726 */
727 do {
728 /*
729 * This field provides read back of the display
730 * pipe frame time stamp. The time stamp value
731 * is sampled at every start of vertical blank.
732 */
733 scan_prev_time = intel_de_read_fw(dev_priv,
734 PIPE_FRMTMSTMP(crtc->pipe));
735
736 /*
737 * The TIMESTAMP_CTR register has the current
738 * time stamp value.
739 */
740 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
741
742 scan_post_time = intel_de_read_fw(dev_priv,
743 PIPE_FRMTMSTMP(crtc->pipe));
744 } while (scan_post_time != scan_prev_time);
745
746 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
747 clock), 1000 * htotal);
748 scanline = min(scanline, vtotal - 1);
749 scanline = (scanline + vblank_start) % vtotal;
750
751 return scanline;
752 }
753
754 /*
755 * intel_de_read_fw(), only for fast reads of display block, no need for
756 * forcewake etc.
757 */
758 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
759 {
760 struct drm_device *dev = crtc->base.dev;
761 struct drm_i915_private *dev_priv = to_i915(dev);
762 const struct drm_display_mode *mode;
763 struct drm_vblank_crtc *vblank;
764 enum pipe pipe = crtc->pipe;
765 int position, vtotal;
766
767 if (!crtc->active)
768 return -1;
769
770 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
771 mode = &vblank->hwmode;
772
773 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
774 return __intel_get_crtc_scanline_from_timestamp(crtc);
775
776 vtotal = mode->crtc_vtotal;
777 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
778 vtotal /= 2;
779
780 if (IS_GEN(dev_priv, 2))
781 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
782 else
783 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
784
785 /*
786 * On HSW, the DSL reg (0x70000) appears to return 0 if we
787 * read it just before the start of vblank. So try it again
788 * so we don't accidentally end up spanning a vblank frame
789 * increment, causing the pipe_update_end() code to squak at us.
790 *
791 * The nature of this problem means we can't simply check the ISR
792 * bit and return the vblank start value; nor can we use the scanline
793 * debug register in the transcoder as it appears to have the same
794 * problem. We may need to extend this to include other platforms,
795 * but so far testing only shows the problem on HSW.
796 */
797 if (HAS_DDI(dev_priv) && !position) {
798 int i, temp;
799
800 for (i = 0; i < 100; i++) {
801 udelay(1);
802 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
803 if (temp != position) {
804 position = temp;
805 break;
806 }
807 }
808 }
809
810 /*
811 * See update_scanline_offset() for the details on the
812 * scanline_offset adjustment.
813 */
814 return (position + crtc->scanline_offset) % vtotal;
815 }
816
817 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
818 bool in_vblank_irq,
819 int *vpos, int *hpos,
820 ktime_t *stime, ktime_t *etime,
821 const struct drm_display_mode *mode)
822 {
823 struct drm_device *dev = _crtc->dev;
824 struct drm_i915_private *dev_priv = to_i915(dev);
825 struct intel_crtc *crtc = to_intel_crtc(_crtc);
826 enum pipe pipe = crtc->pipe;
827 int position;
828 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
829 unsigned long irqflags;
830 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
831 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
832 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
833
834 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
835 drm_dbg(&dev_priv->drm,
836 "trying to get scanoutpos for disabled "
837 "pipe %c\n", pipe_name(pipe));
838 return false;
839 }
840
841 htotal = mode->crtc_htotal;
842 hsync_start = mode->crtc_hsync_start;
843 vtotal = mode->crtc_vtotal;
844 vbl_start = mode->crtc_vblank_start;
845 vbl_end = mode->crtc_vblank_end;
846
847 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
848 vbl_start = DIV_ROUND_UP(vbl_start, 2);
849 vbl_end /= 2;
850 vtotal /= 2;
851 }
852
853 /*
854 * Lock uncore.lock, as we will do multiple timing critical raw
855 * register reads, potentially with preemption disabled, so the
856 * following code must not block on uncore.lock.
857 */
858 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
859
860 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
861
862 /* Get optional system timestamp before query. */
863 if (stime)
864 *stime = ktime_get();
865
866 if (use_scanline_counter) {
867 /* No obvious pixelcount register. Only query vertical
868 * scanout position from Display scan line register.
869 */
870 position = __intel_get_crtc_scanline(crtc);
871 } else {
872 /* Have access to pixelcount since start of frame.
873 * We can split this into vertical and horizontal
874 * scanout position.
875 */
876 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
877
878 /* convert to pixel counts */
879 vbl_start *= htotal;
880 vbl_end *= htotal;
881 vtotal *= htotal;
882
883 /*
884 * In interlaced modes, the pixel counter counts all pixels,
885 * so one field will have htotal more pixels. In order to avoid
886 * the reported position from jumping backwards when the pixel
887 * counter is beyond the length of the shorter field, just
888 * clamp the position the length of the shorter field. This
889 * matches how the scanline counter based position works since
890 * the scanline counter doesn't count the two half lines.
891 */
892 if (position >= vtotal)
893 position = vtotal - 1;
894
895 /*
896 * Start of vblank interrupt is triggered at start of hsync,
897 * just prior to the first active line of vblank. However we
898 * consider lines to start at the leading edge of horizontal
899 * active. So, should we get here before we've crossed into
900 * the horizontal active of the first line in vblank, we would
901 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
902 * always add htotal-hsync_start to the current pixel position.
903 */
904 position = (position + htotal - hsync_start) % vtotal;
905 }
906
907 /* Get optional system timestamp after query. */
908 if (etime)
909 *etime = ktime_get();
910
911 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
912
913 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
914
915 /*
916 * While in vblank, position will be negative
917 * counting up towards 0 at vbl_end. And outside
918 * vblank, position will be positive counting
919 * up since vbl_end.
920 */
921 if (position >= vbl_start)
922 position -= vbl_end;
923 else
924 position += vtotal - vbl_end;
925
926 if (use_scanline_counter) {
927 *vpos = position;
928 *hpos = 0;
929 } else {
930 *vpos = position / htotal;
931 *hpos = position - (*vpos * htotal);
932 }
933
934 return true;
935 }
936
937 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
938 ktime_t *vblank_time, bool in_vblank_irq)
939 {
940 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
941 crtc, max_error, vblank_time, in_vblank_irq,
942 i915_get_crtc_scanoutpos);
943 }
944
945 int intel_get_crtc_scanline(struct intel_crtc *crtc)
946 {
947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
948 unsigned long irqflags;
949 int position;
950
951 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
952 position = __intel_get_crtc_scanline(crtc);
953 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
954
955 return position;
956 }
957
958 /**
959 * ivb_parity_work - Workqueue called when a parity error interrupt
960 * occurred.
961 * @work: workqueue struct
962 *
963 * Doesn't actually do anything except notify userspace. As a consequence of
964 * this event, userspace should try to remap the bad rows since statistically
965 * it is likely the same row is more likely to go bad again.
966 */
967 static void ivb_parity_work(struct work_struct *work)
968 {
969 struct drm_i915_private *dev_priv =
970 container_of(work, typeof(*dev_priv), l3_parity.error_work);
971 struct intel_gt *gt = &dev_priv->gt;
972 u32 error_status, row, bank, subbank;
973 char *parity_event[6];
974 u32 misccpctl;
975 u8 slice = 0;
976
977 /* We must turn off DOP level clock gating to access the L3 registers.
978 * In order to prevent a get/put style interface, acquire struct mutex
979 * any time we access those registers.
980 */
981 mutex_lock(&dev_priv->drm.struct_mutex);
982
983 /* If we've screwed up tracking, just let the interrupt fire again */
984 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
985 goto out;
986
987 misccpctl = I915_READ(GEN7_MISCCPCTL);
988 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
989 POSTING_READ(GEN7_MISCCPCTL);
990
991 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
992 i915_reg_t reg;
993
994 slice--;
995 if (drm_WARN_ON_ONCE(&dev_priv->drm,
996 slice >= NUM_L3_SLICES(dev_priv)))
997 break;
998
999 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1000
1001 reg = GEN7_L3CDERRST1(slice);
1002
1003 error_status = I915_READ(reg);
1004 row = GEN7_PARITY_ERROR_ROW(error_status);
1005 bank = GEN7_PARITY_ERROR_BANK(error_status);
1006 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1007
1008 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1009 POSTING_READ(reg);
1010
1011 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1012 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1013 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1014 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1015 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1016 parity_event[5] = NULL;
1017
1018 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1019 KOBJ_CHANGE, parity_event);
1020
1021 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1022 slice, row, bank, subbank);
1023
1024 kfree(parity_event[4]);
1025 kfree(parity_event[3]);
1026 kfree(parity_event[2]);
1027 kfree(parity_event[1]);
1028 }
1029
1030 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1031
1032 out:
1033 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1034 spin_lock_irq(&gt->irq_lock);
1035 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1036 spin_unlock_irq(&gt->irq_lock);
1037
1038 mutex_unlock(&dev_priv->drm.struct_mutex);
1039 }
1040
1041 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1042 {
1043 switch (pin) {
1044 case HPD_PORT_TC1:
1045 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
1046 case HPD_PORT_TC2:
1047 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
1048 case HPD_PORT_TC3:
1049 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
1050 case HPD_PORT_TC4:
1051 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
1052 case HPD_PORT_TC5:
1053 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
1054 case HPD_PORT_TC6:
1055 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
1056 default:
1057 return false;
1058 }
1059 }
1060
1061 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1062 {
1063 switch (pin) {
1064 case HPD_PORT_A:
1065 return val & PORTA_HOTPLUG_LONG_DETECT;
1066 case HPD_PORT_B:
1067 return val & PORTB_HOTPLUG_LONG_DETECT;
1068 case HPD_PORT_C:
1069 return val & PORTC_HOTPLUG_LONG_DETECT;
1070 default:
1071 return false;
1072 }
1073 }
1074
1075 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1076 {
1077 switch (pin) {
1078 case HPD_PORT_A:
1079 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
1080 case HPD_PORT_B:
1081 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
1082 case HPD_PORT_C:
1083 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
1084 case HPD_PORT_D:
1085 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
1086 default:
1087 return false;
1088 }
1089 }
1090
1091 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1092 {
1093 switch (pin) {
1094 case HPD_PORT_TC1:
1095 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
1096 case HPD_PORT_TC2:
1097 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
1098 case HPD_PORT_TC3:
1099 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
1100 case HPD_PORT_TC4:
1101 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
1102 case HPD_PORT_TC5:
1103 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
1104 case HPD_PORT_TC6:
1105 return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
1106 default:
1107 return false;
1108 }
1109 }
1110
1111 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1112 {
1113 switch (pin) {
1114 case HPD_PORT_E:
1115 return val & PORTE_HOTPLUG_LONG_DETECT;
1116 default:
1117 return false;
1118 }
1119 }
1120
1121 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1122 {
1123 switch (pin) {
1124 case HPD_PORT_A:
1125 return val & PORTA_HOTPLUG_LONG_DETECT;
1126 case HPD_PORT_B:
1127 return val & PORTB_HOTPLUG_LONG_DETECT;
1128 case HPD_PORT_C:
1129 return val & PORTC_HOTPLUG_LONG_DETECT;
1130 case HPD_PORT_D:
1131 return val & PORTD_HOTPLUG_LONG_DETECT;
1132 default:
1133 return false;
1134 }
1135 }
1136
1137 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1138 {
1139 switch (pin) {
1140 case HPD_PORT_A:
1141 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1142 default:
1143 return false;
1144 }
1145 }
1146
1147 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1148 {
1149 switch (pin) {
1150 case HPD_PORT_B:
1151 return val & PORTB_HOTPLUG_LONG_DETECT;
1152 case HPD_PORT_C:
1153 return val & PORTC_HOTPLUG_LONG_DETECT;
1154 case HPD_PORT_D:
1155 return val & PORTD_HOTPLUG_LONG_DETECT;
1156 default:
1157 return false;
1158 }
1159 }
1160
1161 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1162 {
1163 switch (pin) {
1164 case HPD_PORT_B:
1165 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1166 case HPD_PORT_C:
1167 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1168 case HPD_PORT_D:
1169 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1170 default:
1171 return false;
1172 }
1173 }
1174
1175 /*
1176 * Get a bit mask of pins that have triggered, and which ones may be long.
1177 * This can be called multiple times with the same masks to accumulate
1178 * hotplug detection results from several registers.
1179 *
1180 * Note that the caller is expected to zero out the masks initially.
1181 */
1182 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1183 u32 *pin_mask, u32 *long_mask,
1184 u32 hotplug_trigger, u32 dig_hotplug_reg,
1185 const u32 hpd[HPD_NUM_PINS],
1186 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1187 {
1188 enum hpd_pin pin;
1189
1190 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1191
1192 for_each_hpd_pin(pin) {
1193 if ((hpd[pin] & hotplug_trigger) == 0)
1194 continue;
1195
1196 *pin_mask |= BIT(pin);
1197
1198 if (long_pulse_detect(pin, dig_hotplug_reg))
1199 *long_mask |= BIT(pin);
1200 }
1201
1202 drm_dbg(&dev_priv->drm,
1203 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1204 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1205
1206 }
1207
1208 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
1209 const u32 hpd[HPD_NUM_PINS])
1210 {
1211 struct intel_encoder *encoder;
1212 u32 enabled_irqs = 0;
1213
1214 for_each_intel_encoder(&dev_priv->drm, encoder)
1215 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
1216 enabled_irqs |= hpd[encoder->hpd_pin];
1217
1218 return enabled_irqs;
1219 }
1220
1221 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
1222 const u32 hpd[HPD_NUM_PINS])
1223 {
1224 struct intel_encoder *encoder;
1225 u32 hotplug_irqs = 0;
1226
1227 for_each_intel_encoder(&dev_priv->drm, encoder)
1228 hotplug_irqs |= hpd[encoder->hpd_pin];
1229
1230 return hotplug_irqs;
1231 }
1232
1233 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1234 {
1235 wake_up_all(&dev_priv->gmbus_wait_queue);
1236 }
1237
1238 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1239 {
1240 wake_up_all(&dev_priv->gmbus_wait_queue);
1241 }
1242
1243 #if defined(CONFIG_DEBUG_FS)
1244 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1245 enum pipe pipe,
1246 u32 crc0, u32 crc1,
1247 u32 crc2, u32 crc3,
1248 u32 crc4)
1249 {
1250 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1251 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1252 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1253
1254 trace_intel_pipe_crc(crtc, crcs);
1255
1256 spin_lock(&pipe_crc->lock);
1257 /*
1258 * For some not yet identified reason, the first CRC is
1259 * bonkers. So let's just wait for the next vblank and read
1260 * out the buggy result.
1261 *
1262 * On GEN8+ sometimes the second CRC is bonkers as well, so
1263 * don't trust that one either.
1264 */
1265 if (pipe_crc->skipped <= 0 ||
1266 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1267 pipe_crc->skipped++;
1268 spin_unlock(&pipe_crc->lock);
1269 return;
1270 }
1271 spin_unlock(&pipe_crc->lock);
1272
1273 drm_crtc_add_crc_entry(&crtc->base, true,
1274 drm_crtc_accurate_vblank_count(&crtc->base),
1275 crcs);
1276 }
1277 #else
1278 static inline void
1279 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1280 enum pipe pipe,
1281 u32 crc0, u32 crc1,
1282 u32 crc2, u32 crc3,
1283 u32 crc4) {}
1284 #endif
1285
1286 static void flip_done_handler(struct drm_i915_private *i915,
1287 enum pipe pipe)
1288 {
1289 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1290 struct drm_crtc_state *crtc_state = crtc->base.state;
1291 struct drm_pending_vblank_event *e = crtc_state->event;
1292 struct drm_device *dev = &i915->drm;
1293 unsigned long irqflags;
1294
1295 spin_lock_irqsave(&dev->event_lock, irqflags);
1296
1297 crtc_state->event = NULL;
1298
1299 drm_crtc_send_vblank_event(&crtc->base, e);
1300
1301 spin_unlock_irqrestore(&dev->event_lock, irqflags);
1302 }
1303
1304 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1305 enum pipe pipe)
1306 {
1307 display_pipe_crc_irq_handler(dev_priv, pipe,
1308 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1309 0, 0, 0, 0);
1310 }
1311
1312 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1313 enum pipe pipe)
1314 {
1315 display_pipe_crc_irq_handler(dev_priv, pipe,
1316 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1317 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1318 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1319 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1320 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1321 }
1322
1323 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1324 enum pipe pipe)
1325 {
1326 u32 res1, res2;
1327
1328 if (INTEL_GEN(dev_priv) >= 3)
1329 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1330 else
1331 res1 = 0;
1332
1333 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1334 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1335 else
1336 res2 = 0;
1337
1338 display_pipe_crc_irq_handler(dev_priv, pipe,
1339 I915_READ(PIPE_CRC_RES_RED(pipe)),
1340 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1341 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1342 res1, res2);
1343 }
1344
1345 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1346 {
1347 enum pipe pipe;
1348
1349 for_each_pipe(dev_priv, pipe) {
1350 I915_WRITE(PIPESTAT(pipe),
1351 PIPESTAT_INT_STATUS_MASK |
1352 PIPE_FIFO_UNDERRUN_STATUS);
1353
1354 dev_priv->pipestat_irq_mask[pipe] = 0;
1355 }
1356 }
1357
1358 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1359 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1360 {
1361 enum pipe pipe;
1362
1363 spin_lock(&dev_priv->irq_lock);
1364
1365 if (!dev_priv->display_irqs_enabled) {
1366 spin_unlock(&dev_priv->irq_lock);
1367 return;
1368 }
1369
1370 for_each_pipe(dev_priv, pipe) {
1371 i915_reg_t reg;
1372 u32 status_mask, enable_mask, iir_bit = 0;
1373
1374 /*
1375 * PIPESTAT bits get signalled even when the interrupt is
1376 * disabled with the mask bits, and some of the status bits do
1377 * not generate interrupts at all (like the underrun bit). Hence
1378 * we need to be careful that we only handle what we want to
1379 * handle.
1380 */
1381
1382 /* fifo underruns are filterered in the underrun handler. */
1383 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1384
1385 switch (pipe) {
1386 default:
1387 case PIPE_A:
1388 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1389 break;
1390 case PIPE_B:
1391 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1392 break;
1393 case PIPE_C:
1394 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1395 break;
1396 }
1397 if (iir & iir_bit)
1398 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1399
1400 if (!status_mask)
1401 continue;
1402
1403 reg = PIPESTAT(pipe);
1404 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1405 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1406
1407 /*
1408 * Clear the PIPE*STAT regs before the IIR
1409 *
1410 * Toggle the enable bits to make sure we get an
1411 * edge in the ISR pipe event bit if we don't clear
1412 * all the enabled status bits. Otherwise the edge
1413 * triggered IIR on i965/g4x wouldn't notice that
1414 * an interrupt is still pending.
1415 */
1416 if (pipe_stats[pipe]) {
1417 I915_WRITE(reg, pipe_stats[pipe]);
1418 I915_WRITE(reg, enable_mask);
1419 }
1420 }
1421 spin_unlock(&dev_priv->irq_lock);
1422 }
1423
1424 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1425 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1426 {
1427 enum pipe pipe;
1428
1429 for_each_pipe(dev_priv, pipe) {
1430 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1431 intel_handle_vblank(dev_priv, pipe);
1432
1433 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1434 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1435
1436 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1437 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1438 }
1439 }
1440
1441 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1442 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1443 {
1444 bool blc_event = false;
1445 enum pipe pipe;
1446
1447 for_each_pipe(dev_priv, pipe) {
1448 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1449 intel_handle_vblank(dev_priv, pipe);
1450
1451 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1452 blc_event = true;
1453
1454 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1455 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1456
1457 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1458 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1459 }
1460
1461 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1462 intel_opregion_asle_intr(dev_priv);
1463 }
1464
1465 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1466 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1467 {
1468 bool blc_event = false;
1469 enum pipe pipe;
1470
1471 for_each_pipe(dev_priv, pipe) {
1472 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1473 intel_handle_vblank(dev_priv, pipe);
1474
1475 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1476 blc_event = true;
1477
1478 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1479 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1480
1481 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1482 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1483 }
1484
1485 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1486 intel_opregion_asle_intr(dev_priv);
1487
1488 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1489 gmbus_irq_handler(dev_priv);
1490 }
1491
1492 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1493 u32 pipe_stats[I915_MAX_PIPES])
1494 {
1495 enum pipe pipe;
1496
1497 for_each_pipe(dev_priv, pipe) {
1498 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1499 intel_handle_vblank(dev_priv, pipe);
1500
1501 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1502 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1503
1504 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1505 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1506 }
1507
1508 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1509 gmbus_irq_handler(dev_priv);
1510 }
1511
1512 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1513 {
1514 u32 hotplug_status = 0, hotplug_status_mask;
1515 int i;
1516
1517 if (IS_G4X(dev_priv) ||
1518 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1519 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1520 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1521 else
1522 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1523
1524 /*
1525 * We absolutely have to clear all the pending interrupt
1526 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1527 * interrupt bit won't have an edge, and the i965/g4x
1528 * edge triggered IIR will not notice that an interrupt
1529 * is still pending. We can't use PORT_HOTPLUG_EN to
1530 * guarantee the edge as the act of toggling the enable
1531 * bits can itself generate a new hotplug interrupt :(
1532 */
1533 for (i = 0; i < 10; i++) {
1534 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1535
1536 if (tmp == 0)
1537 return hotplug_status;
1538
1539 hotplug_status |= tmp;
1540 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1541 }
1542
1543 drm_WARN_ONCE(&dev_priv->drm, 1,
1544 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1545 I915_READ(PORT_HOTPLUG_STAT));
1546
1547 return hotplug_status;
1548 }
1549
1550 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1551 u32 hotplug_status)
1552 {
1553 u32 pin_mask = 0, long_mask = 0;
1554 u32 hotplug_trigger;
1555
1556 if (IS_G4X(dev_priv) ||
1557 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1558 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1559 else
1560 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1561
1562 if (hotplug_trigger) {
1563 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1564 hotplug_trigger, hotplug_trigger,
1565 dev_priv->hotplug.hpd,
1566 i9xx_port_hotplug_long_detect);
1567
1568 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1569 }
1570
1571 if ((IS_G4X(dev_priv) ||
1572 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1573 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1574 dp_aux_irq_handler(dev_priv);
1575 }
1576
1577 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1578 {
1579 struct drm_i915_private *dev_priv = arg;
1580 irqreturn_t ret = IRQ_NONE;
1581
1582 if (!intel_irqs_enabled(dev_priv))
1583 return IRQ_NONE;
1584
1585 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1586 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1587
1588 do {
1589 u32 iir, gt_iir, pm_iir;
1590 u32 pipe_stats[I915_MAX_PIPES] = {};
1591 u32 hotplug_status = 0;
1592 u32 ier = 0;
1593
1594 gt_iir = I915_READ(GTIIR);
1595 pm_iir = I915_READ(GEN6_PMIIR);
1596 iir = I915_READ(VLV_IIR);
1597
1598 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1599 break;
1600
1601 ret = IRQ_HANDLED;
1602
1603 /*
1604 * Theory on interrupt generation, based on empirical evidence:
1605 *
1606 * x = ((VLV_IIR & VLV_IER) ||
1607 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1608 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1609 *
1610 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1611 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1612 * guarantee the CPU interrupt will be raised again even if we
1613 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1614 * bits this time around.
1615 */
1616 I915_WRITE(VLV_MASTER_IER, 0);
1617 ier = I915_READ(VLV_IER);
1618 I915_WRITE(VLV_IER, 0);
1619
1620 if (gt_iir)
1621 I915_WRITE(GTIIR, gt_iir);
1622 if (pm_iir)
1623 I915_WRITE(GEN6_PMIIR, pm_iir);
1624
1625 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1626 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1627
1628 /* Call regardless, as some status bits might not be
1629 * signalled in iir */
1630 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1631
1632 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1633 I915_LPE_PIPE_B_INTERRUPT))
1634 intel_lpe_audio_irq_handler(dev_priv);
1635
1636 /*
1637 * VLV_IIR is single buffered, and reflects the level
1638 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1639 */
1640 if (iir)
1641 I915_WRITE(VLV_IIR, iir);
1642
1643 I915_WRITE(VLV_IER, ier);
1644 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1645
1646 if (gt_iir)
1647 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1648 if (pm_iir)
1649 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1650
1651 if (hotplug_status)
1652 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1653
1654 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1655 } while (0);
1656
1657 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1658
1659 return ret;
1660 }
1661
1662 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1663 {
1664 struct drm_i915_private *dev_priv = arg;
1665 irqreturn_t ret = IRQ_NONE;
1666
1667 if (!intel_irqs_enabled(dev_priv))
1668 return IRQ_NONE;
1669
1670 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1671 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1672
1673 do {
1674 u32 master_ctl, iir;
1675 u32 pipe_stats[I915_MAX_PIPES] = {};
1676 u32 hotplug_status = 0;
1677 u32 ier = 0;
1678
1679 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1680 iir = I915_READ(VLV_IIR);
1681
1682 if (master_ctl == 0 && iir == 0)
1683 break;
1684
1685 ret = IRQ_HANDLED;
1686
1687 /*
1688 * Theory on interrupt generation, based on empirical evidence:
1689 *
1690 * x = ((VLV_IIR & VLV_IER) ||
1691 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1692 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1693 *
1694 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1695 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1696 * guarantee the CPU interrupt will be raised again even if we
1697 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1698 * bits this time around.
1699 */
1700 I915_WRITE(GEN8_MASTER_IRQ, 0);
1701 ier = I915_READ(VLV_IER);
1702 I915_WRITE(VLV_IER, 0);
1703
1704 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1705
1706 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1707 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1708
1709 /* Call regardless, as some status bits might not be
1710 * signalled in iir */
1711 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1712
1713 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1714 I915_LPE_PIPE_B_INTERRUPT |
1715 I915_LPE_PIPE_C_INTERRUPT))
1716 intel_lpe_audio_irq_handler(dev_priv);
1717
1718 /*
1719 * VLV_IIR is single buffered, and reflects the level
1720 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1721 */
1722 if (iir)
1723 I915_WRITE(VLV_IIR, iir);
1724
1725 I915_WRITE(VLV_IER, ier);
1726 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1727
1728 if (hotplug_status)
1729 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1730
1731 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1732 } while (0);
1733
1734 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1735
1736 return ret;
1737 }
1738
1739 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1740 u32 hotplug_trigger)
1741 {
1742 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1743
1744 /*
1745 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1746 * unless we touch the hotplug register, even if hotplug_trigger is
1747 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1748 * errors.
1749 */
1750 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1751 if (!hotplug_trigger) {
1752 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1753 PORTD_HOTPLUG_STATUS_MASK |
1754 PORTC_HOTPLUG_STATUS_MASK |
1755 PORTB_HOTPLUG_STATUS_MASK;
1756 dig_hotplug_reg &= ~mask;
1757 }
1758
1759 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1760 if (!hotplug_trigger)
1761 return;
1762
1763 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1764 hotplug_trigger, dig_hotplug_reg,
1765 dev_priv->hotplug.pch_hpd,
1766 pch_port_hotplug_long_detect);
1767
1768 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1769 }
1770
1771 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1772 {
1773 enum pipe pipe;
1774 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1775
1776 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1777
1778 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1779 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1780 SDE_AUDIO_POWER_SHIFT);
1781 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1782 port_name(port));
1783 }
1784
1785 if (pch_iir & SDE_AUX_MASK)
1786 dp_aux_irq_handler(dev_priv);
1787
1788 if (pch_iir & SDE_GMBUS)
1789 gmbus_irq_handler(dev_priv);
1790
1791 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1792 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1793
1794 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1795 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1796
1797 if (pch_iir & SDE_POISON)
1798 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1799
1800 if (pch_iir & SDE_FDI_MASK) {
1801 for_each_pipe(dev_priv, pipe)
1802 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1803 pipe_name(pipe),
1804 I915_READ(FDI_RX_IIR(pipe)));
1805 }
1806
1807 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1808 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1809
1810 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1811 drm_dbg(&dev_priv->drm,
1812 "PCH transcoder CRC error interrupt\n");
1813
1814 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1815 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1816
1817 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1818 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1819 }
1820
1821 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1822 {
1823 u32 err_int = I915_READ(GEN7_ERR_INT);
1824 enum pipe pipe;
1825
1826 if (err_int & ERR_INT_POISON)
1827 drm_err(&dev_priv->drm, "Poison interrupt\n");
1828
1829 for_each_pipe(dev_priv, pipe) {
1830 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1831 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1832
1833 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1834 if (IS_IVYBRIDGE(dev_priv))
1835 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1836 else
1837 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1838 }
1839 }
1840
1841 I915_WRITE(GEN7_ERR_INT, err_int);
1842 }
1843
1844 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1845 {
1846 u32 serr_int = I915_READ(SERR_INT);
1847 enum pipe pipe;
1848
1849 if (serr_int & SERR_INT_POISON)
1850 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1851
1852 for_each_pipe(dev_priv, pipe)
1853 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1854 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1855
1856 I915_WRITE(SERR_INT, serr_int);
1857 }
1858
1859 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1860 {
1861 enum pipe pipe;
1862 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1863
1864 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1865
1866 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1867 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1868 SDE_AUDIO_POWER_SHIFT_CPT);
1869 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1870 port_name(port));
1871 }
1872
1873 if (pch_iir & SDE_AUX_MASK_CPT)
1874 dp_aux_irq_handler(dev_priv);
1875
1876 if (pch_iir & SDE_GMBUS_CPT)
1877 gmbus_irq_handler(dev_priv);
1878
1879 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1880 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1881
1882 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1883 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1884
1885 if (pch_iir & SDE_FDI_MASK_CPT) {
1886 for_each_pipe(dev_priv, pipe)
1887 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1888 pipe_name(pipe),
1889 I915_READ(FDI_RX_IIR(pipe)));
1890 }
1891
1892 if (pch_iir & SDE_ERROR_CPT)
1893 cpt_serr_int_handler(dev_priv);
1894 }
1895
1896 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1897 {
1898 u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1899 u32 pin_mask = 0, long_mask = 0;
1900
1901 if (HAS_PCH_DG1(dev_priv)) {
1902 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
1903 tc_hotplug_trigger = 0;
1904 } else if (HAS_PCH_TGP(dev_priv)) {
1905 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1906 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1907 } else if (HAS_PCH_JSP(dev_priv)) {
1908 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1909 tc_hotplug_trigger = 0;
1910 } else if (HAS_PCH_MCC(dev_priv)) {
1911 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1912 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
1913 } else {
1914 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1915 "Unrecognized PCH type 0x%x\n",
1916 INTEL_PCH_TYPE(dev_priv));
1917
1918 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1919 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1920 }
1921
1922 if (ddi_hotplug_trigger) {
1923 u32 dig_hotplug_reg;
1924
1925 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1926 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1927
1928 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1929 ddi_hotplug_trigger, dig_hotplug_reg,
1930 dev_priv->hotplug.pch_hpd,
1931 icp_ddi_port_hotplug_long_detect);
1932 }
1933
1934 if (tc_hotplug_trigger) {
1935 u32 dig_hotplug_reg;
1936
1937 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1938 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1939
1940 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1941 tc_hotplug_trigger, dig_hotplug_reg,
1942 dev_priv->hotplug.pch_hpd,
1943 icp_tc_port_hotplug_long_detect);
1944 }
1945
1946 if (pin_mask)
1947 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1948
1949 if (pch_iir & SDE_GMBUS_ICP)
1950 gmbus_irq_handler(dev_priv);
1951 }
1952
1953 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1954 {
1955 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1956 ~SDE_PORTE_HOTPLUG_SPT;
1957 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1958 u32 pin_mask = 0, long_mask = 0;
1959
1960 if (hotplug_trigger) {
1961 u32 dig_hotplug_reg;
1962
1963 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1964 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1965
1966 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1967 hotplug_trigger, dig_hotplug_reg,
1968 dev_priv->hotplug.pch_hpd,
1969 spt_port_hotplug_long_detect);
1970 }
1971
1972 if (hotplug2_trigger) {
1973 u32 dig_hotplug_reg;
1974
1975 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1976 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1977
1978 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1979 hotplug2_trigger, dig_hotplug_reg,
1980 dev_priv->hotplug.pch_hpd,
1981 spt_port_hotplug2_long_detect);
1982 }
1983
1984 if (pin_mask)
1985 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1986
1987 if (pch_iir & SDE_GMBUS_CPT)
1988 gmbus_irq_handler(dev_priv);
1989 }
1990
1991 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1992 u32 hotplug_trigger)
1993 {
1994 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1995
1996 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1997 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1998
1999 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2000 hotplug_trigger, dig_hotplug_reg,
2001 dev_priv->hotplug.hpd,
2002 ilk_port_hotplug_long_detect);
2003
2004 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2005 }
2006
2007 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2008 u32 de_iir)
2009 {
2010 enum pipe pipe;
2011 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2012
2013 if (hotplug_trigger)
2014 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2015
2016 if (de_iir & DE_AUX_CHANNEL_A)
2017 dp_aux_irq_handler(dev_priv);
2018
2019 if (de_iir & DE_GSE)
2020 intel_opregion_asle_intr(dev_priv);
2021
2022 if (de_iir & DE_POISON)
2023 drm_err(&dev_priv->drm, "Poison interrupt\n");
2024
2025 for_each_pipe(dev_priv, pipe) {
2026 if (de_iir & DE_PIPE_VBLANK(pipe))
2027 intel_handle_vblank(dev_priv, pipe);
2028
2029 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2030 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2031
2032 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2033 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2034 }
2035
2036 /* check event from PCH */
2037 if (de_iir & DE_PCH_EVENT) {
2038 u32 pch_iir = I915_READ(SDEIIR);
2039
2040 if (HAS_PCH_CPT(dev_priv))
2041 cpt_irq_handler(dev_priv, pch_iir);
2042 else
2043 ibx_irq_handler(dev_priv, pch_iir);
2044
2045 /* should clear PCH hotplug event before clear CPU irq */
2046 I915_WRITE(SDEIIR, pch_iir);
2047 }
2048
2049 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2050 gen5_rps_irq_handler(&dev_priv->gt.rps);
2051 }
2052
2053 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2054 u32 de_iir)
2055 {
2056 enum pipe pipe;
2057 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2058
2059 if (hotplug_trigger)
2060 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2061
2062 if (de_iir & DE_ERR_INT_IVB)
2063 ivb_err_int_handler(dev_priv);
2064
2065 if (de_iir & DE_EDP_PSR_INT_HSW) {
2066 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2067
2068 intel_psr_irq_handler(dev_priv, psr_iir);
2069 I915_WRITE(EDP_PSR_IIR, psr_iir);
2070 }
2071
2072 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2073 dp_aux_irq_handler(dev_priv);
2074
2075 if (de_iir & DE_GSE_IVB)
2076 intel_opregion_asle_intr(dev_priv);
2077
2078 for_each_pipe(dev_priv, pipe) {
2079 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2080 intel_handle_vblank(dev_priv, pipe);
2081 }
2082
2083 /* check event from PCH */
2084 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2085 u32 pch_iir = I915_READ(SDEIIR);
2086
2087 cpt_irq_handler(dev_priv, pch_iir);
2088
2089 /* clear PCH hotplug event before clear CPU irq */
2090 I915_WRITE(SDEIIR, pch_iir);
2091 }
2092 }
2093
2094 /*
2095 * To handle irqs with the minimum potential races with fresh interrupts, we:
2096 * 1 - Disable Master Interrupt Control.
2097 * 2 - Find the source(s) of the interrupt.
2098 * 3 - Clear the Interrupt Identity bits (IIR).
2099 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2100 * 5 - Re-enable Master Interrupt Control.
2101 */
2102 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2103 {
2104 struct drm_i915_private *i915 = arg;
2105 void __iomem * const regs = i915->uncore.regs;
2106 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2107 irqreturn_t ret = IRQ_NONE;
2108
2109 if (unlikely(!intel_irqs_enabled(i915)))
2110 return IRQ_NONE;
2111
2112 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2113 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2114
2115 /* disable master interrupt before clearing iir */
2116 de_ier = raw_reg_read(regs, DEIER);
2117 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2118
2119 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2120 * interrupts will will be stored on its back queue, and then we'll be
2121 * able to process them after we restore SDEIER (as soon as we restore
2122 * it, we'll get an interrupt if SDEIIR still has something to process
2123 * due to its back queue). */
2124 if (!HAS_PCH_NOP(i915)) {
2125 sde_ier = raw_reg_read(regs, SDEIER);
2126 raw_reg_write(regs, SDEIER, 0);
2127 }
2128
2129 /* Find, clear, then process each source of interrupt */
2130
2131 gt_iir = raw_reg_read(regs, GTIIR);
2132 if (gt_iir) {
2133 raw_reg_write(regs, GTIIR, gt_iir);
2134 if (INTEL_GEN(i915) >= 6)
2135 gen6_gt_irq_handler(&i915->gt, gt_iir);
2136 else
2137 gen5_gt_irq_handler(&i915->gt, gt_iir);
2138 ret = IRQ_HANDLED;
2139 }
2140
2141 de_iir = raw_reg_read(regs, DEIIR);
2142 if (de_iir) {
2143 raw_reg_write(regs, DEIIR, de_iir);
2144 if (INTEL_GEN(i915) >= 7)
2145 ivb_display_irq_handler(i915, de_iir);
2146 else
2147 ilk_display_irq_handler(i915, de_iir);
2148 ret = IRQ_HANDLED;
2149 }
2150
2151 if (INTEL_GEN(i915) >= 6) {
2152 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2153 if (pm_iir) {
2154 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2155 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2156 ret = IRQ_HANDLED;
2157 }
2158 }
2159
2160 raw_reg_write(regs, DEIER, de_ier);
2161 if (sde_ier)
2162 raw_reg_write(regs, SDEIER, sde_ier);
2163
2164 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2165 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2166
2167 return ret;
2168 }
2169
2170 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2171 u32 hotplug_trigger)
2172 {
2173 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2174
2175 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2176 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2177
2178 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2179 hotplug_trigger, dig_hotplug_reg,
2180 dev_priv->hotplug.hpd,
2181 bxt_port_hotplug_long_detect);
2182
2183 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2184 }
2185
2186 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2187 {
2188 u32 pin_mask = 0, long_mask = 0;
2189 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2190 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2191
2192 if (trigger_tc) {
2193 u32 dig_hotplug_reg;
2194
2195 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2196 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2197
2198 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2199 trigger_tc, dig_hotplug_reg,
2200 dev_priv->hotplug.hpd,
2201 gen11_port_hotplug_long_detect);
2202 }
2203
2204 if (trigger_tbt) {
2205 u32 dig_hotplug_reg;
2206
2207 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2208 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2209
2210 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2211 trigger_tbt, dig_hotplug_reg,
2212 dev_priv->hotplug.hpd,
2213 gen11_port_hotplug_long_detect);
2214 }
2215
2216 if (pin_mask)
2217 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2218 else
2219 drm_err(&dev_priv->drm,
2220 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2221 }
2222
2223 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2224 {
2225 u32 mask;
2226
2227 if (INTEL_GEN(dev_priv) >= 12)
2228 return TGL_DE_PORT_AUX_DDIA |
2229 TGL_DE_PORT_AUX_DDIB |
2230 TGL_DE_PORT_AUX_DDIC |
2231 TGL_DE_PORT_AUX_USBC1 |
2232 TGL_DE_PORT_AUX_USBC2 |
2233 TGL_DE_PORT_AUX_USBC3 |
2234 TGL_DE_PORT_AUX_USBC4 |
2235 TGL_DE_PORT_AUX_USBC5 |
2236 TGL_DE_PORT_AUX_USBC6;
2237
2238
2239 mask = GEN8_AUX_CHANNEL_A;
2240 if (INTEL_GEN(dev_priv) >= 9)
2241 mask |= GEN9_AUX_CHANNEL_B |
2242 GEN9_AUX_CHANNEL_C |
2243 GEN9_AUX_CHANNEL_D;
2244
2245 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2246 mask |= CNL_AUX_CHANNEL_F;
2247
2248 if (IS_GEN(dev_priv, 11))
2249 mask |= ICL_AUX_CHANNEL_E;
2250
2251 return mask;
2252 }
2253
2254 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2255 {
2256 if (IS_ROCKETLAKE(dev_priv))
2257 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2258 else if (INTEL_GEN(dev_priv) >= 11)
2259 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2260 else if (INTEL_GEN(dev_priv) >= 9)
2261 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2262 else
2263 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2264 }
2265
2266 static void
2267 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2268 {
2269 bool found = false;
2270
2271 if (iir & GEN8_DE_MISC_GSE) {
2272 intel_opregion_asle_intr(dev_priv);
2273 found = true;
2274 }
2275
2276 if (iir & GEN8_DE_EDP_PSR) {
2277 u32 psr_iir;
2278 i915_reg_t iir_reg;
2279
2280 if (INTEL_GEN(dev_priv) >= 12)
2281 iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2282 else
2283 iir_reg = EDP_PSR_IIR;
2284
2285 psr_iir = I915_READ(iir_reg);
2286 I915_WRITE(iir_reg, psr_iir);
2287
2288 if (psr_iir)
2289 found = true;
2290
2291 intel_psr_irq_handler(dev_priv, psr_iir);
2292 }
2293
2294 if (!found)
2295 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2296 }
2297
2298 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2299 u32 te_trigger)
2300 {
2301 enum pipe pipe = INVALID_PIPE;
2302 enum transcoder dsi_trans;
2303 enum port port;
2304 u32 val, tmp;
2305
2306 /*
2307 * Incase of dual link, TE comes from DSI_1
2308 * this is to check if dual link is enabled
2309 */
2310 val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2311 val &= PORT_SYNC_MODE_ENABLE;
2312
2313 /*
2314 * if dual link is enabled, then read DSI_0
2315 * transcoder registers
2316 */
2317 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2318 PORT_A : PORT_B;
2319 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2320
2321 /* Check if DSI configured in command mode */
2322 val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
2323 val = val & OP_MODE_MASK;
2324
2325 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2326 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2327 return;
2328 }
2329
2330 /* Get PIPE for handling VBLANK event */
2331 val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
2332 switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2333 case TRANS_DDI_EDP_INPUT_A_ON:
2334 pipe = PIPE_A;
2335 break;
2336 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2337 pipe = PIPE_B;
2338 break;
2339 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2340 pipe = PIPE_C;
2341 break;
2342 default:
2343 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2344 return;
2345 }
2346
2347 intel_handle_vblank(dev_priv, pipe);
2348
2349 /* clear TE in dsi IIR */
2350 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2351 tmp = I915_READ(DSI_INTR_IDENT_REG(port));
2352 I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
2353 }
2354
2355 static irqreturn_t
2356 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2357 {
2358 irqreturn_t ret = IRQ_NONE;
2359 u32 iir;
2360 enum pipe pipe;
2361
2362 if (master_ctl & GEN8_DE_MISC_IRQ) {
2363 iir = I915_READ(GEN8_DE_MISC_IIR);
2364 if (iir) {
2365 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2366 ret = IRQ_HANDLED;
2367 gen8_de_misc_irq_handler(dev_priv, iir);
2368 } else {
2369 drm_err(&dev_priv->drm,
2370 "The master control interrupt lied (DE MISC)!\n");
2371 }
2372 }
2373
2374 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2375 iir = I915_READ(GEN11_DE_HPD_IIR);
2376 if (iir) {
2377 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2378 ret = IRQ_HANDLED;
2379 gen11_hpd_irq_handler(dev_priv, iir);
2380 } else {
2381 drm_err(&dev_priv->drm,
2382 "The master control interrupt lied, (DE HPD)!\n");
2383 }
2384 }
2385
2386 if (master_ctl & GEN8_DE_PORT_IRQ) {
2387 iir = I915_READ(GEN8_DE_PORT_IIR);
2388 if (iir) {
2389 bool found = false;
2390
2391 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2392 ret = IRQ_HANDLED;
2393
2394 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2395 dp_aux_irq_handler(dev_priv);
2396 found = true;
2397 }
2398
2399 if (IS_GEN9_LP(dev_priv)) {
2400 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
2401
2402 if (hotplug_trigger) {
2403 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
2404 found = true;
2405 }
2406 } else if (IS_BROADWELL(dev_priv)) {
2407 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
2408
2409 if (hotplug_trigger) {
2410 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2411 found = true;
2412 }
2413 }
2414
2415 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2416 gmbus_irq_handler(dev_priv);
2417 found = true;
2418 }
2419
2420 if (INTEL_GEN(dev_priv) >= 11) {
2421 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
2422
2423 if (te_trigger) {
2424 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
2425 found = true;
2426 }
2427 }
2428
2429 if (!found)
2430 drm_err(&dev_priv->drm,
2431 "Unexpected DE Port interrupt\n");
2432 }
2433 else
2434 drm_err(&dev_priv->drm,
2435 "The master control interrupt lied (DE PORT)!\n");
2436 }
2437
2438 for_each_pipe(dev_priv, pipe) {
2439 u32 fault_errors;
2440
2441 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2442 continue;
2443
2444 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2445 if (!iir) {
2446 drm_err(&dev_priv->drm,
2447 "The master control interrupt lied (DE PIPE)!\n");
2448 continue;
2449 }
2450
2451 ret = IRQ_HANDLED;
2452 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2453
2454 if (iir & GEN8_PIPE_VBLANK)
2455 intel_handle_vblank(dev_priv, pipe);
2456
2457 if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
2458 flip_done_handler(dev_priv, pipe);
2459
2460 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2461 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2462
2463 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2464 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2465
2466 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2467 if (fault_errors)
2468 drm_err(&dev_priv->drm,
2469 "Fault errors on pipe %c: 0x%08x\n",
2470 pipe_name(pipe),
2471 fault_errors);
2472 }
2473
2474 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2475 master_ctl & GEN8_DE_PCH_IRQ) {
2476 /*
2477 * FIXME(BDW): Assume for now that the new interrupt handling
2478 * scheme also closed the SDE interrupt handling race we've seen
2479 * on older pch-split platforms. But this needs testing.
2480 */
2481 iir = I915_READ(SDEIIR);
2482 if (iir) {
2483 I915_WRITE(SDEIIR, iir);
2484 ret = IRQ_HANDLED;
2485
2486 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2487 icp_irq_handler(dev_priv, iir);
2488 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2489 spt_irq_handler(dev_priv, iir);
2490 else
2491 cpt_irq_handler(dev_priv, iir);
2492 } else {
2493 /*
2494 * Like on previous PCH there seems to be something
2495 * fishy going on with forwarding PCH interrupts.
2496 */
2497 drm_dbg(&dev_priv->drm,
2498 "The master control interrupt lied (SDE)!\n");
2499 }
2500 }
2501
2502 return ret;
2503 }
2504
2505 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2506 {
2507 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2508
2509 /*
2510 * Now with master disabled, get a sample of level indications
2511 * for this interrupt. Indications will be cleared on related acks.
2512 * New indications can and will light up during processing,
2513 * and will generate new interrupt after enabling master.
2514 */
2515 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2516 }
2517
2518 static inline void gen8_master_intr_enable(void __iomem * const regs)
2519 {
2520 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2521 }
2522
2523 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2524 {
2525 struct drm_i915_private *dev_priv = arg;
2526 void __iomem * const regs = dev_priv->uncore.regs;
2527 u32 master_ctl;
2528
2529 if (!intel_irqs_enabled(dev_priv))
2530 return IRQ_NONE;
2531
2532 master_ctl = gen8_master_intr_disable(regs);
2533 if (!master_ctl) {
2534 gen8_master_intr_enable(regs);
2535 return IRQ_NONE;
2536 }
2537
2538 /* Find, queue (onto bottom-halves), then clear each source */
2539 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2540
2541 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2542 if (master_ctl & ~GEN8_GT_IRQS) {
2543 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2544 gen8_de_irq_handler(dev_priv, master_ctl);
2545 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2546 }
2547
2548 gen8_master_intr_enable(regs);
2549
2550 return IRQ_HANDLED;
2551 }
2552
2553 static u32
2554 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2555 {
2556 void __iomem * const regs = gt->uncore->regs;
2557 u32 iir;
2558
2559 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2560 return 0;
2561
2562 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2563 if (likely(iir))
2564 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2565
2566 return iir;
2567 }
2568
2569 static void
2570 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2571 {
2572 if (iir & GEN11_GU_MISC_GSE)
2573 intel_opregion_asle_intr(gt->i915);
2574 }
2575
2576 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2577 {
2578 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2579
2580 /*
2581 * Now with master disabled, get a sample of level indications
2582 * for this interrupt. Indications will be cleared on related acks.
2583 * New indications can and will light up during processing,
2584 * and will generate new interrupt after enabling master.
2585 */
2586 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2587 }
2588
2589 static inline void gen11_master_intr_enable(void __iomem * const regs)
2590 {
2591 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2592 }
2593
2594 static void
2595 gen11_display_irq_handler(struct drm_i915_private *i915)
2596 {
2597 void __iomem * const regs = i915->uncore.regs;
2598 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2599
2600 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2601 /*
2602 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2603 * for the display related bits.
2604 */
2605 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2606 gen8_de_irq_handler(i915, disp_ctl);
2607 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2608 GEN11_DISPLAY_IRQ_ENABLE);
2609
2610 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2611 }
2612
2613 static __always_inline irqreturn_t
2614 __gen11_irq_handler(struct drm_i915_private * const i915,
2615 u32 (*intr_disable)(void __iomem * const regs),
2616 void (*intr_enable)(void __iomem * const regs))
2617 {
2618 void __iomem * const regs = i915->uncore.regs;
2619 struct intel_gt *gt = &i915->gt;
2620 u32 master_ctl;
2621 u32 gu_misc_iir;
2622
2623 if (!intel_irqs_enabled(i915))
2624 return IRQ_NONE;
2625
2626 master_ctl = intr_disable(regs);
2627 if (!master_ctl) {
2628 intr_enable(regs);
2629 return IRQ_NONE;
2630 }
2631
2632 /* Find, queue (onto bottom-halves), then clear each source */
2633 gen11_gt_irq_handler(gt, master_ctl);
2634
2635 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2636 if (master_ctl & GEN11_DISPLAY_IRQ)
2637 gen11_display_irq_handler(i915);
2638
2639 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2640
2641 intr_enable(regs);
2642
2643 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2644
2645 return IRQ_HANDLED;
2646 }
2647
2648 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2649 {
2650 return __gen11_irq_handler(arg,
2651 gen11_master_intr_disable,
2652 gen11_master_intr_enable);
2653 }
2654
2655 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2656 {
2657 u32 val;
2658
2659 /* First disable interrupts */
2660 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2661
2662 /* Get the indication levels and ack the master unit */
2663 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2664 if (unlikely(!val))
2665 return 0;
2666
2667 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2668
2669 /*
2670 * Now with master disabled, get a sample of level indications
2671 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2672 * out as this bit doesn't exist anymore for DG1
2673 */
2674 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2675 if (unlikely(!val))
2676 return 0;
2677
2678 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2679
2680 return val;
2681 }
2682
2683 static inline void dg1_master_intr_enable(void __iomem * const regs)
2684 {
2685 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2686 }
2687
2688 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2689 {
2690 return __gen11_irq_handler(arg,
2691 dg1_master_intr_disable_and_ack,
2692 dg1_master_intr_enable);
2693 }
2694
2695 /* Called from drm generic code, passed 'crtc' which
2696 * we use as a pipe index
2697 */
2698 int i8xx_enable_vblank(struct drm_crtc *crtc)
2699 {
2700 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2701 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2702 unsigned long irqflags;
2703
2704 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2705 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2706 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2707
2708 return 0;
2709 }
2710
2711 int i915gm_enable_vblank(struct drm_crtc *crtc)
2712 {
2713 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2714
2715 /*
2716 * Vblank interrupts fail to wake the device up from C2+.
2717 * Disabling render clock gating during C-states avoids
2718 * the problem. There is a small power cost so we do this
2719 * only when vblank interrupts are actually enabled.
2720 */
2721 if (dev_priv->vblank_enabled++ == 0)
2722 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2723
2724 return i8xx_enable_vblank(crtc);
2725 }
2726
2727 int i965_enable_vblank(struct drm_crtc *crtc)
2728 {
2729 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2730 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2731 unsigned long irqflags;
2732
2733 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2734 i915_enable_pipestat(dev_priv, pipe,
2735 PIPE_START_VBLANK_INTERRUPT_STATUS);
2736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2737
2738 return 0;
2739 }
2740
2741 int ilk_enable_vblank(struct drm_crtc *crtc)
2742 {
2743 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2744 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2745 unsigned long irqflags;
2746 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2747 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2748
2749 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2750 ilk_enable_display_irq(dev_priv, bit);
2751 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2752
2753 /* Even though there is no DMC, frame counter can get stuck when
2754 * PSR is active as no frames are generated.
2755 */
2756 if (HAS_PSR(dev_priv))
2757 drm_crtc_vblank_restore(crtc);
2758
2759 return 0;
2760 }
2761
2762 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2763 bool enable)
2764 {
2765 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2766 enum port port;
2767 u32 tmp;
2768
2769 if (!(intel_crtc->mode_flags &
2770 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2771 return false;
2772
2773 /* for dual link cases we consider TE from slave */
2774 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2775 port = PORT_B;
2776 else
2777 port = PORT_A;
2778
2779 tmp = I915_READ(DSI_INTR_MASK_REG(port));
2780 if (enable)
2781 tmp &= ~DSI_TE_EVENT;
2782 else
2783 tmp |= DSI_TE_EVENT;
2784
2785 I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
2786
2787 tmp = I915_READ(DSI_INTR_IDENT_REG(port));
2788 I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
2789
2790 return true;
2791 }
2792
2793 int bdw_enable_vblank(struct drm_crtc *crtc)
2794 {
2795 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797 enum pipe pipe = intel_crtc->pipe;
2798 unsigned long irqflags;
2799
2800 if (gen11_dsi_configure_te(intel_crtc, true))
2801 return 0;
2802
2803 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2804 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2805 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2806
2807 /* Even if there is no DMC, frame counter can get stuck when
2808 * PSR is active as no frames are generated, so check only for PSR.
2809 */
2810 if (HAS_PSR(dev_priv))
2811 drm_crtc_vblank_restore(crtc);
2812
2813 return 0;
2814 }
2815
2816 void skl_enable_flip_done(struct intel_crtc *crtc)
2817 {
2818 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2819 enum pipe pipe = crtc->pipe;
2820 unsigned long irqflags;
2821
2822 spin_lock_irqsave(&i915->irq_lock, irqflags);
2823
2824 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
2825
2826 spin_unlock_irqrestore(&i915->irq_lock, irqflags);
2827 }
2828
2829 /* Called from drm generic code, passed 'crtc' which
2830 * we use as a pipe index
2831 */
2832 void i8xx_disable_vblank(struct drm_crtc *crtc)
2833 {
2834 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2835 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2836 unsigned long irqflags;
2837
2838 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2839 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2840 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2841 }
2842
2843 void i915gm_disable_vblank(struct drm_crtc *crtc)
2844 {
2845 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2846
2847 i8xx_disable_vblank(crtc);
2848
2849 if (--dev_priv->vblank_enabled == 0)
2850 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2851 }
2852
2853 void i965_disable_vblank(struct drm_crtc *crtc)
2854 {
2855 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2856 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2857 unsigned long irqflags;
2858
2859 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2860 i915_disable_pipestat(dev_priv, pipe,
2861 PIPE_START_VBLANK_INTERRUPT_STATUS);
2862 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2863 }
2864
2865 void ilk_disable_vblank(struct drm_crtc *crtc)
2866 {
2867 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2868 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2869 unsigned long irqflags;
2870 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2871 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2872
2873 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2874 ilk_disable_display_irq(dev_priv, bit);
2875 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2876 }
2877
2878 void bdw_disable_vblank(struct drm_crtc *crtc)
2879 {
2880 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2882 enum pipe pipe = intel_crtc->pipe;
2883 unsigned long irqflags;
2884
2885 if (gen11_dsi_configure_te(intel_crtc, false))
2886 return;
2887
2888 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2889 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2890 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2891 }
2892
2893 void skl_disable_flip_done(struct intel_crtc *crtc)
2894 {
2895 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2896 enum pipe pipe = crtc->pipe;
2897 unsigned long irqflags;
2898
2899 spin_lock_irqsave(&i915->irq_lock, irqflags);
2900
2901 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
2902
2903 spin_unlock_irqrestore(&i915->irq_lock, irqflags);
2904 }
2905
2906 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2907 {
2908 struct intel_uncore *uncore = &dev_priv->uncore;
2909
2910 if (HAS_PCH_NOP(dev_priv))
2911 return;
2912
2913 GEN3_IRQ_RESET(uncore, SDE);
2914
2915 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2916 I915_WRITE(SERR_INT, 0xffffffff);
2917 }
2918
2919 /*
2920 * SDEIER is also touched by the interrupt handler to work around missed PCH
2921 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2922 * instead we unconditionally enable all PCH interrupt sources here, but then
2923 * only unmask them as needed with SDEIMR.
2924 *
2925 * This function needs to be called before interrupts are enabled.
2926 */
2927 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2928 {
2929 if (HAS_PCH_NOP(dev_priv))
2930 return;
2931
2932 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2933 I915_WRITE(SDEIER, 0xffffffff);
2934 POSTING_READ(SDEIER);
2935 }
2936
2937 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2938 {
2939 struct intel_uncore *uncore = &dev_priv->uncore;
2940
2941 if (IS_CHERRYVIEW(dev_priv))
2942 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2943 else
2944 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2945
2946 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2947 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2948
2949 i9xx_pipestat_irq_reset(dev_priv);
2950
2951 GEN3_IRQ_RESET(uncore, VLV_);
2952 dev_priv->irq_mask = ~0u;
2953 }
2954
2955 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2956 {
2957 struct intel_uncore *uncore = &dev_priv->uncore;
2958
2959 u32 pipestat_mask;
2960 u32 enable_mask;
2961 enum pipe pipe;
2962
2963 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2964
2965 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2966 for_each_pipe(dev_priv, pipe)
2967 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2968
2969 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2970 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2971 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2972 I915_LPE_PIPE_A_INTERRUPT |
2973 I915_LPE_PIPE_B_INTERRUPT;
2974
2975 if (IS_CHERRYVIEW(dev_priv))
2976 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2977 I915_LPE_PIPE_C_INTERRUPT;
2978
2979 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2980
2981 dev_priv->irq_mask = ~enable_mask;
2982
2983 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2984 }
2985
2986 /* drm_dma.h hooks
2987 */
2988 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2989 {
2990 struct intel_uncore *uncore = &dev_priv->uncore;
2991
2992 GEN3_IRQ_RESET(uncore, DE);
2993 dev_priv->irq_mask = ~0u;
2994
2995 if (IS_GEN(dev_priv, 7))
2996 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2997
2998 if (IS_HASWELL(dev_priv)) {
2999 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3000 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3001 }
3002
3003 gen5_gt_irq_reset(&dev_priv->gt);
3004
3005 ibx_irq_reset(dev_priv);
3006 }
3007
3008 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3009 {
3010 I915_WRITE(VLV_MASTER_IER, 0);
3011 POSTING_READ(VLV_MASTER_IER);
3012
3013 gen5_gt_irq_reset(&dev_priv->gt);
3014
3015 spin_lock_irq(&dev_priv->irq_lock);
3016 if (dev_priv->display_irqs_enabled)
3017 vlv_display_irq_reset(dev_priv);
3018 spin_unlock_irq(&dev_priv->irq_lock);
3019 }
3020
3021 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3022 {
3023 struct intel_uncore *uncore = &dev_priv->uncore;
3024 enum pipe pipe;
3025
3026 gen8_master_intr_disable(dev_priv->uncore.regs);
3027
3028 gen8_gt_irq_reset(&dev_priv->gt);
3029
3030 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3031 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3032
3033 for_each_pipe(dev_priv, pipe)
3034 if (intel_display_power_is_enabled(dev_priv,
3035 POWER_DOMAIN_PIPE(pipe)))
3036 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3037
3038 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3039 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3040 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3041
3042 if (HAS_PCH_SPLIT(dev_priv))
3043 ibx_irq_reset(dev_priv);
3044 }
3045
3046 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3047 {
3048 struct intel_uncore *uncore = &dev_priv->uncore;
3049 enum pipe pipe;
3050 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3051 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3052
3053 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3054
3055 if (INTEL_GEN(dev_priv) >= 12) {
3056 enum transcoder trans;
3057
3058 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3059 enum intel_display_power_domain domain;
3060
3061 domain = POWER_DOMAIN_TRANSCODER(trans);
3062 if (!intel_display_power_is_enabled(dev_priv, domain))
3063 continue;
3064
3065 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3066 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3067 }
3068 } else {
3069 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3070 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3071 }
3072
3073 for_each_pipe(dev_priv, pipe)
3074 if (intel_display_power_is_enabled(dev_priv,
3075 POWER_DOMAIN_PIPE(pipe)))
3076 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3077
3078 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3079 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3080 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3081
3082 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3083 GEN3_IRQ_RESET(uncore, SDE);
3084
3085 /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
3086 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
3087 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
3088 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
3089 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
3090 SBCLK_RUN_REFCLK_DIS, 0);
3091 }
3092 }
3093
3094 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3095 {
3096 struct intel_uncore *uncore = &dev_priv->uncore;
3097
3098 if (HAS_MASTER_UNIT_IRQ(dev_priv))
3099 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
3100 else
3101 gen11_master_intr_disable(dev_priv->uncore.regs);
3102
3103 gen11_gt_irq_reset(&dev_priv->gt);
3104 gen11_display_irq_reset(dev_priv);
3105
3106 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3107 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3108 }
3109
3110 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3111 u8 pipe_mask)
3112 {
3113 struct intel_uncore *uncore = &dev_priv->uncore;
3114
3115 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3116 enum pipe pipe;
3117
3118 if (INTEL_GEN(dev_priv) >= 9)
3119 extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
3120
3121 spin_lock_irq(&dev_priv->irq_lock);
3122
3123 if (!intel_irqs_enabled(dev_priv)) {
3124 spin_unlock_irq(&dev_priv->irq_lock);
3125 return;
3126 }
3127
3128 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3129 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3130 dev_priv->de_irq_mask[pipe],
3131 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3132
3133 spin_unlock_irq(&dev_priv->irq_lock);
3134 }
3135
3136 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3137 u8 pipe_mask)
3138 {
3139 struct intel_uncore *uncore = &dev_priv->uncore;
3140 enum pipe pipe;
3141
3142 spin_lock_irq(&dev_priv->irq_lock);
3143
3144 if (!intel_irqs_enabled(dev_priv)) {
3145 spin_unlock_irq(&dev_priv->irq_lock);
3146 return;
3147 }
3148
3149 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3150 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3151
3152 spin_unlock_irq(&dev_priv->irq_lock);
3153
3154 /* make sure we're done processing display irqs */
3155 intel_synchronize_irq(dev_priv);
3156 }
3157
3158 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3159 {
3160 struct intel_uncore *uncore = &dev_priv->uncore;
3161
3162 I915_WRITE(GEN8_MASTER_IRQ, 0);
3163 POSTING_READ(GEN8_MASTER_IRQ);
3164
3165 gen8_gt_irq_reset(&dev_priv->gt);
3166
3167 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3168
3169 spin_lock_irq(&dev_priv->irq_lock);
3170 if (dev_priv->display_irqs_enabled)
3171 vlv_display_irq_reset(dev_priv);
3172 spin_unlock_irq(&dev_priv->irq_lock);
3173 }
3174
3175 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3176 {
3177 u32 hotplug;
3178
3179 /*
3180 * Enable digital hotplug on the PCH, and configure the DP short pulse
3181 * duration to 2ms (which is the minimum in the Display Port spec).
3182 * The pulse duration bits are reserved on LPT+.
3183 */
3184 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3185 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3186 PORTC_PULSE_DURATION_MASK |
3187 PORTD_PULSE_DURATION_MASK);
3188 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3189 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3190 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3191 /*
3192 * When CPU and PCH are on the same package, port A
3193 * HPD must be enabled in both north and south.
3194 */
3195 if (HAS_PCH_LPT_LP(dev_priv))
3196 hotplug |= PORTA_HOTPLUG_ENABLE;
3197 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3198 }
3199
3200 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3201 {
3202 u32 hotplug_irqs, enabled_irqs;
3203
3204 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3205 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3206
3207 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3208
3209 ibx_hpd_detection_setup(dev_priv);
3210 }
3211
3212 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
3213 u32 enable_mask)
3214 {
3215 u32 hotplug;
3216
3217 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3218 hotplug |= enable_mask;
3219 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3220 }
3221
3222 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
3223 u32 enable_mask)
3224 {
3225 u32 hotplug;
3226
3227 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3228 hotplug |= enable_mask;
3229 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3230 }
3231
3232 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3233 u32 ddi_enable_mask, u32 tc_enable_mask)
3234 {
3235 u32 hotplug_irqs, enabled_irqs;
3236
3237 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3238 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3239
3240 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3241 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3242
3243 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3244
3245 icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
3246 if (tc_enable_mask)
3247 icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
3248 }
3249
3250 /*
3251 * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3252 * equivalent of SDE.
3253 */
3254 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3255 {
3256 icp_hpd_irq_setup(dev_priv,
3257 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
3258 }
3259
3260 /*
3261 * JSP behaves exactly the same as MCC above except that port C is mapped to
3262 * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
3263 * masks & tables rather than ICP's masks & tables.
3264 */
3265 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3266 {
3267 icp_hpd_irq_setup(dev_priv,
3268 TGP_DDI_HPD_ENABLE_MASK, 0);
3269 }
3270
3271 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3272 {
3273 u32 val;
3274
3275 val = I915_READ(SOUTH_CHICKEN1);
3276 val |= (INVERT_DDIA_HPD |
3277 INVERT_DDIB_HPD |
3278 INVERT_DDIC_HPD |
3279 INVERT_DDID_HPD);
3280 I915_WRITE(SOUTH_CHICKEN1, val);
3281
3282 icp_hpd_irq_setup(dev_priv,
3283 DG1_DDI_HPD_ENABLE_MASK, 0);
3284 }
3285
3286 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3287 {
3288 u32 hotplug;
3289
3290 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3291 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3292 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3293 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3294 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3295 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3296 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
3297 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3298 }
3299
3300 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3301 {
3302 u32 hotplug;
3303
3304 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3305 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3306 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3307 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3308 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3309 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3310 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
3311 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3312 }
3313
3314 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3315 {
3316 u32 hotplug_irqs, enabled_irqs;
3317 u32 val;
3318
3319 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3320 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3321
3322 val = I915_READ(GEN11_DE_HPD_IMR);
3323 val &= ~hotplug_irqs;
3324 val |= ~enabled_irqs & hotplug_irqs;
3325 I915_WRITE(GEN11_DE_HPD_IMR, val);
3326 POSTING_READ(GEN11_DE_HPD_IMR);
3327
3328 gen11_tc_hpd_detection_setup(dev_priv);
3329 gen11_tbt_hpd_detection_setup(dev_priv);
3330
3331 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3332 icp_hpd_irq_setup(dev_priv,
3333 TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
3334 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3335 icp_hpd_irq_setup(dev_priv,
3336 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3337 }
3338
3339 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3340 {
3341 u32 val, hotplug;
3342
3343 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3344 if (HAS_PCH_CNP(dev_priv)) {
3345 val = I915_READ(SOUTH_CHICKEN1);
3346 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3347 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3348 I915_WRITE(SOUTH_CHICKEN1, val);
3349 }
3350
3351 /* Enable digital hotplug on the PCH */
3352 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3353 hotplug |= PORTA_HOTPLUG_ENABLE |
3354 PORTB_HOTPLUG_ENABLE |
3355 PORTC_HOTPLUG_ENABLE |
3356 PORTD_HOTPLUG_ENABLE;
3357 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3358
3359 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3360 hotplug |= PORTE_HOTPLUG_ENABLE;
3361 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3362 }
3363
3364 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3365 {
3366 u32 hotplug_irqs, enabled_irqs;
3367
3368 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3369 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3370
3371 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3372 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3373
3374 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3375
3376 spt_hpd_detection_setup(dev_priv);
3377 }
3378
3379 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3380 {
3381 u32 hotplug;
3382
3383 /*
3384 * Enable digital hotplug on the CPU, and configure the DP short pulse
3385 * duration to 2ms (which is the minimum in the Display Port spec)
3386 * The pulse duration bits are reserved on HSW+.
3387 */
3388 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3389 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3390 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3391 DIGITAL_PORTA_PULSE_DURATION_2ms;
3392 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3393 }
3394
3395 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3396 {
3397 u32 hotplug_irqs, enabled_irqs;
3398
3399 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3400 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3401
3402 if (INTEL_GEN(dev_priv) >= 8)
3403 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3404 else
3405 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3406
3407 ilk_hpd_detection_setup(dev_priv);
3408
3409 ibx_hpd_irq_setup(dev_priv);
3410 }
3411
3412 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3413 u32 enabled_irqs)
3414 {
3415 u32 hotplug;
3416
3417 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3418 hotplug |= PORTA_HOTPLUG_ENABLE |
3419 PORTB_HOTPLUG_ENABLE |
3420 PORTC_HOTPLUG_ENABLE;
3421
3422 drm_dbg_kms(&dev_priv->drm,
3423 "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3424 hotplug, enabled_irqs);
3425 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3426
3427 /*
3428 * For BXT invert bit has to be set based on AOB design
3429 * for HPD detection logic, update it based on VBT fields.
3430 */
3431 if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
3432 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3433 hotplug |= BXT_DDIA_HPD_INVERT;
3434 if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
3435 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3436 hotplug |= BXT_DDIB_HPD_INVERT;
3437 if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
3438 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3439 hotplug |= BXT_DDIC_HPD_INVERT;
3440
3441 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3442 }
3443
3444 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3445 {
3446 u32 hotplug_irqs, enabled_irqs;
3447
3448 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3449 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3450
3451 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3452
3453 bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3454 }
3455
3456 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3457 {
3458 u32 mask;
3459
3460 if (HAS_PCH_NOP(dev_priv))
3461 return;
3462
3463 if (HAS_PCH_IBX(dev_priv))
3464 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3465 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3466 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3467 else
3468 mask = SDE_GMBUS_CPT;
3469
3470 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3471 I915_WRITE(SDEIMR, ~mask);
3472 }
3473
3474 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3475 {
3476 struct intel_uncore *uncore = &dev_priv->uncore;
3477 u32 display_mask, extra_mask;
3478
3479 if (INTEL_GEN(dev_priv) >= 7) {
3480 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3481 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3482 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3483 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3484 DE_DP_A_HOTPLUG_IVB);
3485 } else {
3486 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3487 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3488 DE_PIPEA_CRC_DONE | DE_POISON);
3489 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3490 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3491 DE_DP_A_HOTPLUG);
3492 }
3493
3494 if (IS_HASWELL(dev_priv)) {
3495 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3496 display_mask |= DE_EDP_PSR_INT_HSW;
3497 }
3498
3499 if (IS_IRONLAKE_M(dev_priv))
3500 extra_mask |= DE_PCU_EVENT;
3501
3502 dev_priv->irq_mask = ~display_mask;
3503
3504 ibx_irq_pre_postinstall(dev_priv);
3505
3506 gen5_gt_irq_postinstall(&dev_priv->gt);
3507
3508 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3509 display_mask | extra_mask);
3510
3511 ibx_irq_postinstall(dev_priv);
3512 }
3513
3514 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3515 {
3516 lockdep_assert_held(&dev_priv->irq_lock);
3517
3518 if (dev_priv->display_irqs_enabled)
3519 return;
3520
3521 dev_priv->display_irqs_enabled = true;
3522
3523 if (intel_irqs_enabled(dev_priv)) {
3524 vlv_display_irq_reset(dev_priv);
3525 vlv_display_irq_postinstall(dev_priv);
3526 }
3527 }
3528
3529 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3530 {
3531 lockdep_assert_held(&dev_priv->irq_lock);
3532
3533 if (!dev_priv->display_irqs_enabled)
3534 return;
3535
3536 dev_priv->display_irqs_enabled = false;
3537
3538 if (intel_irqs_enabled(dev_priv))
3539 vlv_display_irq_reset(dev_priv);
3540 }
3541
3542
3543 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3544 {
3545 gen5_gt_irq_postinstall(&dev_priv->gt);
3546
3547 spin_lock_irq(&dev_priv->irq_lock);
3548 if (dev_priv->display_irqs_enabled)
3549 vlv_display_irq_postinstall(dev_priv);
3550 spin_unlock_irq(&dev_priv->irq_lock);
3551
3552 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3553 POSTING_READ(VLV_MASTER_IER);
3554 }
3555
3556 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3557 {
3558 struct intel_uncore *uncore = &dev_priv->uncore;
3559
3560 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3561 GEN8_PIPE_CDCLK_CRC_DONE;
3562 u32 de_pipe_enables;
3563 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3564 u32 de_port_enables;
3565 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3566 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3567 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3568 enum pipe pipe;
3569
3570 if (INTEL_GEN(dev_priv) <= 10)
3571 de_misc_masked |= GEN8_DE_MISC_GSE;
3572
3573 if (IS_GEN9_LP(dev_priv))
3574 de_port_masked |= BXT_DE_PORT_GMBUS;
3575
3576 if (INTEL_GEN(dev_priv) >= 11) {
3577 enum port port;
3578
3579 if (intel_bios_is_dsi_present(dev_priv, &port))
3580 de_port_masked |= DSI0_TE | DSI1_TE;
3581 }
3582
3583 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3584 GEN8_PIPE_FIFO_UNDERRUN;
3585
3586 if (INTEL_GEN(dev_priv) >= 9)
3587 de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
3588
3589 de_port_enables = de_port_masked;
3590 if (IS_GEN9_LP(dev_priv))
3591 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3592 else if (IS_BROADWELL(dev_priv))
3593 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3594
3595 if (INTEL_GEN(dev_priv) >= 12) {
3596 enum transcoder trans;
3597
3598 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3599 enum intel_display_power_domain domain;
3600
3601 domain = POWER_DOMAIN_TRANSCODER(trans);
3602 if (!intel_display_power_is_enabled(dev_priv, domain))
3603 continue;
3604
3605 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3606 }
3607 } else {
3608 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3609 }
3610
3611 for_each_pipe(dev_priv, pipe) {
3612 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3613
3614 if (intel_display_power_is_enabled(dev_priv,
3615 POWER_DOMAIN_PIPE(pipe)))
3616 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3617 dev_priv->de_irq_mask[pipe],
3618 de_pipe_enables);
3619 }
3620
3621 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3622 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3623
3624 if (INTEL_GEN(dev_priv) >= 11) {
3625 u32 de_hpd_masked = 0;
3626 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3627 GEN11_DE_TBT_HOTPLUG_MASK;
3628
3629 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3630 de_hpd_enables);
3631 }
3632 }
3633
3634 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3635 {
3636 if (HAS_PCH_SPLIT(dev_priv))
3637 ibx_irq_pre_postinstall(dev_priv);
3638
3639 gen8_gt_irq_postinstall(&dev_priv->gt);
3640 gen8_de_irq_postinstall(dev_priv);
3641
3642 if (HAS_PCH_SPLIT(dev_priv))
3643 ibx_irq_postinstall(dev_priv);
3644
3645 gen8_master_intr_enable(dev_priv->uncore.regs);
3646 }
3647
3648 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3649 {
3650 u32 mask = SDE_GMBUS_ICP;
3651
3652 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3653 I915_WRITE(SDEIER, 0xffffffff);
3654 POSTING_READ(SDEIER);
3655
3656 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3657 I915_WRITE(SDEIMR, ~mask);
3658 }
3659
3660 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3661 {
3662 struct intel_uncore *uncore = &dev_priv->uncore;
3663 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3664
3665 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3666 icp_irq_postinstall(dev_priv);
3667
3668 gen11_gt_irq_postinstall(&dev_priv->gt);
3669 gen8_de_irq_postinstall(dev_priv);
3670
3671 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3672
3673 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3674
3675 if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3676 dg1_master_intr_enable(uncore->regs);
3677 POSTING_READ(DG1_MSTR_UNIT_INTR);
3678 } else {
3679 gen11_master_intr_enable(uncore->regs);
3680 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3681 }
3682 }
3683
3684 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3685 {
3686 gen8_gt_irq_postinstall(&dev_priv->gt);
3687
3688 spin_lock_irq(&dev_priv->irq_lock);
3689 if (dev_priv->display_irqs_enabled)
3690 vlv_display_irq_postinstall(dev_priv);
3691 spin_unlock_irq(&dev_priv->irq_lock);
3692
3693 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3694 POSTING_READ(GEN8_MASTER_IRQ);
3695 }
3696
3697 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3698 {
3699 struct intel_uncore *uncore = &dev_priv->uncore;
3700
3701 i9xx_pipestat_irq_reset(dev_priv);
3702
3703 GEN2_IRQ_RESET(uncore);
3704 dev_priv->irq_mask = ~0u;
3705 }
3706
3707 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3708 {
3709 struct intel_uncore *uncore = &dev_priv->uncore;
3710 u16 enable_mask;
3711
3712 intel_uncore_write16(uncore,
3713 EMR,
3714 ~(I915_ERROR_PAGE_TABLE |
3715 I915_ERROR_MEMORY_REFRESH));
3716
3717 /* Unmask the interrupts that we always want on. */
3718 dev_priv->irq_mask =
3719 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3720 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3721 I915_MASTER_ERROR_INTERRUPT);
3722
3723 enable_mask =
3724 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3725 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3726 I915_MASTER_ERROR_INTERRUPT |
3727 I915_USER_INTERRUPT;
3728
3729 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3730
3731 /* Interrupt setup is already guaranteed to be single-threaded, this is
3732 * just to make the assert_spin_locked check happy. */
3733 spin_lock_irq(&dev_priv->irq_lock);
3734 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3735 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3736 spin_unlock_irq(&dev_priv->irq_lock);
3737 }
3738
3739 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3740 u16 *eir, u16 *eir_stuck)
3741 {
3742 struct intel_uncore *uncore = &i915->uncore;
3743 u16 emr;
3744
3745 *eir = intel_uncore_read16(uncore, EIR);
3746
3747 if (*eir)
3748 intel_uncore_write16(uncore, EIR, *eir);
3749
3750 *eir_stuck = intel_uncore_read16(uncore, EIR);
3751 if (*eir_stuck == 0)
3752 return;
3753
3754 /*
3755 * Toggle all EMR bits to make sure we get an edge
3756 * in the ISR master error bit if we don't clear
3757 * all the EIR bits. Otherwise the edge triggered
3758 * IIR on i965/g4x wouldn't notice that an interrupt
3759 * is still pending. Also some EIR bits can't be
3760 * cleared except by handling the underlying error
3761 * (or by a GPU reset) so we mask any bit that
3762 * remains set.
3763 */
3764 emr = intel_uncore_read16(uncore, EMR);
3765 intel_uncore_write16(uncore, EMR, 0xffff);
3766 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3767 }
3768
3769 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3770 u16 eir, u16 eir_stuck)
3771 {
3772 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3773
3774 if (eir_stuck)
3775 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3776 eir_stuck);
3777 }
3778
3779 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3780 u32 *eir, u32 *eir_stuck)
3781 {
3782 u32 emr;
3783
3784 *eir = I915_READ(EIR);
3785
3786 I915_WRITE(EIR, *eir);
3787
3788 *eir_stuck = I915_READ(EIR);
3789 if (*eir_stuck == 0)
3790 return;
3791
3792 /*
3793 * Toggle all EMR bits to make sure we get an edge
3794 * in the ISR master error bit if we don't clear
3795 * all the EIR bits. Otherwise the edge triggered
3796 * IIR on i965/g4x wouldn't notice that an interrupt
3797 * is still pending. Also some EIR bits can't be
3798 * cleared except by handling the underlying error
3799 * (or by a GPU reset) so we mask any bit that
3800 * remains set.
3801 */
3802 emr = I915_READ(EMR);
3803 I915_WRITE(EMR, 0xffffffff);
3804 I915_WRITE(EMR, emr | *eir_stuck);
3805 }
3806
3807 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3808 u32 eir, u32 eir_stuck)
3809 {
3810 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3811
3812 if (eir_stuck)
3813 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3814 eir_stuck);
3815 }
3816
3817 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3818 {
3819 struct drm_i915_private *dev_priv = arg;
3820 irqreturn_t ret = IRQ_NONE;
3821
3822 if (!intel_irqs_enabled(dev_priv))
3823 return IRQ_NONE;
3824
3825 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3826 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3827
3828 do {
3829 u32 pipe_stats[I915_MAX_PIPES] = {};
3830 u16 eir = 0, eir_stuck = 0;
3831 u16 iir;
3832
3833 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3834 if (iir == 0)
3835 break;
3836
3837 ret = IRQ_HANDLED;
3838
3839 /* Call regardless, as some status bits might not be
3840 * signalled in iir */
3841 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3842
3843 if (iir & I915_MASTER_ERROR_INTERRUPT)
3844 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3845
3846 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3847
3848 if (iir & I915_USER_INTERRUPT)
3849 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3850
3851 if (iir & I915_MASTER_ERROR_INTERRUPT)
3852 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3853
3854 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3855 } while (0);
3856
3857 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3858
3859 return ret;
3860 }
3861
3862 static void i915_irq_reset(struct drm_i915_private *dev_priv)
3863 {
3864 struct intel_uncore *uncore = &dev_priv->uncore;
3865
3866 if (I915_HAS_HOTPLUG(dev_priv)) {
3867 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3868 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3869 }
3870
3871 i9xx_pipestat_irq_reset(dev_priv);
3872
3873 GEN3_IRQ_RESET(uncore, GEN2_);
3874 dev_priv->irq_mask = ~0u;
3875 }
3876
3877 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3878 {
3879 struct intel_uncore *uncore = &dev_priv->uncore;
3880 u32 enable_mask;
3881
3882 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3883 I915_ERROR_MEMORY_REFRESH));
3884
3885 /* Unmask the interrupts that we always want on. */
3886 dev_priv->irq_mask =
3887 ~(I915_ASLE_INTERRUPT |
3888 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3889 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3890 I915_MASTER_ERROR_INTERRUPT);
3891
3892 enable_mask =
3893 I915_ASLE_INTERRUPT |
3894 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3895 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3896 I915_MASTER_ERROR_INTERRUPT |
3897 I915_USER_INTERRUPT;
3898
3899 if (I915_HAS_HOTPLUG(dev_priv)) {
3900 /* Enable in IER... */
3901 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3902 /* and unmask in IMR */
3903 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3904 }
3905
3906 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3907
3908 /* Interrupt setup is already guaranteed to be single-threaded, this is
3909 * just to make the assert_spin_locked check happy. */
3910 spin_lock_irq(&dev_priv->irq_lock);
3911 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3912 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3913 spin_unlock_irq(&dev_priv->irq_lock);
3914
3915 i915_enable_asle_pipestat(dev_priv);
3916 }
3917
3918 static irqreturn_t i915_irq_handler(int irq, void *arg)
3919 {
3920 struct drm_i915_private *dev_priv = arg;
3921 irqreturn_t ret = IRQ_NONE;
3922
3923 if (!intel_irqs_enabled(dev_priv))
3924 return IRQ_NONE;
3925
3926 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3927 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3928
3929 do {
3930 u32 pipe_stats[I915_MAX_PIPES] = {};
3931 u32 eir = 0, eir_stuck = 0;
3932 u32 hotplug_status = 0;
3933 u32 iir;
3934
3935 iir = I915_READ(GEN2_IIR);
3936 if (iir == 0)
3937 break;
3938
3939 ret = IRQ_HANDLED;
3940
3941 if (I915_HAS_HOTPLUG(dev_priv) &&
3942 iir & I915_DISPLAY_PORT_INTERRUPT)
3943 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3944
3945 /* Call regardless, as some status bits might not be
3946 * signalled in iir */
3947 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3948
3949 if (iir & I915_MASTER_ERROR_INTERRUPT)
3950 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3951
3952 I915_WRITE(GEN2_IIR, iir);
3953
3954 if (iir & I915_USER_INTERRUPT)
3955 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3956
3957 if (iir & I915_MASTER_ERROR_INTERRUPT)
3958 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3959
3960 if (hotplug_status)
3961 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3962
3963 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3964 } while (0);
3965
3966 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3967
3968 return ret;
3969 }
3970
3971 static void i965_irq_reset(struct drm_i915_private *dev_priv)
3972 {
3973 struct intel_uncore *uncore = &dev_priv->uncore;
3974
3975 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3976 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3977
3978 i9xx_pipestat_irq_reset(dev_priv);
3979
3980 GEN3_IRQ_RESET(uncore, GEN2_);
3981 dev_priv->irq_mask = ~0u;
3982 }
3983
3984 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
3985 {
3986 struct intel_uncore *uncore = &dev_priv->uncore;
3987 u32 enable_mask;
3988 u32 error_mask;
3989
3990 /*
3991 * Enable some error detection, note the instruction error mask
3992 * bit is reserved, so we leave it masked.
3993 */
3994 if (IS_G4X(dev_priv)) {
3995 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3996 GM45_ERROR_MEM_PRIV |
3997 GM45_ERROR_CP_PRIV |
3998 I915_ERROR_MEMORY_REFRESH);
3999 } else {
4000 error_mask = ~(I915_ERROR_PAGE_TABLE |
4001 I915_ERROR_MEMORY_REFRESH);
4002 }
4003 I915_WRITE(EMR, error_mask);
4004
4005 /* Unmask the interrupts that we always want on. */
4006 dev_priv->irq_mask =
4007 ~(I915_ASLE_INTERRUPT |
4008 I915_DISPLAY_PORT_INTERRUPT |
4009 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4010 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4011 I915_MASTER_ERROR_INTERRUPT);
4012
4013 enable_mask =
4014 I915_ASLE_INTERRUPT |
4015 I915_DISPLAY_PORT_INTERRUPT |
4016 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4017 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4018 I915_MASTER_ERROR_INTERRUPT |
4019 I915_USER_INTERRUPT;
4020
4021 if (IS_G4X(dev_priv))
4022 enable_mask |= I915_BSD_USER_INTERRUPT;
4023
4024 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4025
4026 /* Interrupt setup is already guaranteed to be single-threaded, this is
4027 * just to make the assert_spin_locked check happy. */
4028 spin_lock_irq(&dev_priv->irq_lock);
4029 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4030 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4031 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4032 spin_unlock_irq(&dev_priv->irq_lock);
4033
4034 i915_enable_asle_pipestat(dev_priv);
4035 }
4036
4037 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4038 {
4039 u32 hotplug_en;
4040
4041 lockdep_assert_held(&dev_priv->irq_lock);
4042
4043 /* Note HDMI and DP share hotplug bits */
4044 /* enable bits are the same for all generations */
4045 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4046 /* Programming the CRT detection parameters tends
4047 to generate a spurious hotplug event about three
4048 seconds later. So just do it once.
4049 */
4050 if (IS_G4X(dev_priv))
4051 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4052 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4053
4054 /* Ignore TV since it's buggy */
4055 i915_hotplug_interrupt_update_locked(dev_priv,
4056 HOTPLUG_INT_EN_MASK |
4057 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4058 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4059 hotplug_en);
4060 }
4061
4062 static irqreturn_t i965_irq_handler(int irq, void *arg)
4063 {
4064 struct drm_i915_private *dev_priv = arg;
4065 irqreturn_t ret = IRQ_NONE;
4066
4067 if (!intel_irqs_enabled(dev_priv))
4068 return IRQ_NONE;
4069
4070 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4071 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4072
4073 do {
4074 u32 pipe_stats[I915_MAX_PIPES] = {};
4075 u32 eir = 0, eir_stuck = 0;
4076 u32 hotplug_status = 0;
4077 u32 iir;
4078
4079 iir = I915_READ(GEN2_IIR);
4080 if (iir == 0)
4081 break;
4082
4083 ret = IRQ_HANDLED;
4084
4085 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4086 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4087
4088 /* Call regardless, as some status bits might not be
4089 * signalled in iir */
4090 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4091
4092 if (iir & I915_MASTER_ERROR_INTERRUPT)
4093 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4094
4095 I915_WRITE(GEN2_IIR, iir);
4096
4097 if (iir & I915_USER_INTERRUPT)
4098 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4099
4100 if (iir & I915_BSD_USER_INTERRUPT)
4101 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
4102
4103 if (iir & I915_MASTER_ERROR_INTERRUPT)
4104 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4105
4106 if (hotplug_status)
4107 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4108
4109 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4110 } while (0);
4111
4112 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4113
4114 return ret;
4115 }
4116
4117 /**
4118 * intel_irq_init - initializes irq support
4119 * @dev_priv: i915 device instance
4120 *
4121 * This function initializes all the irq support including work items, timers
4122 * and all the vtables. It does not setup the interrupt itself though.
4123 */
4124 void intel_irq_init(struct drm_i915_private *dev_priv)
4125 {
4126 struct drm_device *dev = &dev_priv->drm;
4127 int i;
4128
4129 intel_hpd_init_pins(dev_priv);
4130
4131 intel_hpd_init_work(dev_priv);
4132
4133 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4134 for (i = 0; i < MAX_L3_SLICES; ++i)
4135 dev_priv->l3_parity.remap_info[i] = NULL;
4136
4137 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4138 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4139 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4140
4141 dev->vblank_disable_immediate = true;
4142
4143 /* Most platforms treat the display irq block as an always-on
4144 * power domain. vlv/chv can disable it at runtime and need
4145 * special care to avoid writing any of the display block registers
4146 * outside of the power domain. We defer setting up the display irqs
4147 * in this case to the runtime pm.
4148 */
4149 dev_priv->display_irqs_enabled = true;
4150 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4151 dev_priv->display_irqs_enabled = false;
4152
4153 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4154 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4155 * detection, as short HPD storms will occur as a natural part of
4156 * sideband messaging with MST.
4157 * On older platforms however, IRQ storms can occur with both long and
4158 * short pulses, as seen on some G4x systems.
4159 */
4160 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4161
4162 if (HAS_GMCH(dev_priv)) {
4163 if (I915_HAS_HOTPLUG(dev_priv))
4164 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4165 } else {
4166 if (HAS_PCH_DG1(dev_priv))
4167 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4168 else if (HAS_PCH_JSP(dev_priv))
4169 dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
4170 else if (HAS_PCH_MCC(dev_priv))
4171 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4172 else if (INTEL_GEN(dev_priv) >= 11)
4173 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4174 else if (IS_GEN9_LP(dev_priv))
4175 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4176 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4177 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4178 else
4179 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4180 }
4181 }
4182
4183 /**
4184 * intel_irq_fini - deinitializes IRQ support
4185 * @i915: i915 device instance
4186 *
4187 * This function deinitializes all the IRQ support.
4188 */
4189 void intel_irq_fini(struct drm_i915_private *i915)
4190 {
4191 int i;
4192
4193 for (i = 0; i < MAX_L3_SLICES; ++i)
4194 kfree(i915->l3_parity.remap_info[i]);
4195 }
4196
4197 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4198 {
4199 if (HAS_GMCH(dev_priv)) {
4200 if (IS_CHERRYVIEW(dev_priv))
4201 return cherryview_irq_handler;
4202 else if (IS_VALLEYVIEW(dev_priv))
4203 return valleyview_irq_handler;
4204 else if (IS_GEN(dev_priv, 4))
4205 return i965_irq_handler;
4206 else if (IS_GEN(dev_priv, 3))
4207 return i915_irq_handler;
4208 else
4209 return i8xx_irq_handler;
4210 } else {
4211 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4212 return dg1_irq_handler;
4213 if (INTEL_GEN(dev_priv) >= 11)
4214 return gen11_irq_handler;
4215 else if (INTEL_GEN(dev_priv) >= 8)
4216 return gen8_irq_handler;
4217 else
4218 return ilk_irq_handler;
4219 }
4220 }
4221
4222 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4223 {
4224 if (HAS_GMCH(dev_priv)) {
4225 if (IS_CHERRYVIEW(dev_priv))
4226 cherryview_irq_reset(dev_priv);
4227 else if (IS_VALLEYVIEW(dev_priv))
4228 valleyview_irq_reset(dev_priv);
4229 else if (IS_GEN(dev_priv, 4))
4230 i965_irq_reset(dev_priv);
4231 else if (IS_GEN(dev_priv, 3))
4232 i915_irq_reset(dev_priv);
4233 else
4234 i8xx_irq_reset(dev_priv);
4235 } else {
4236 if (INTEL_GEN(dev_priv) >= 11)
4237 gen11_irq_reset(dev_priv);
4238 else if (INTEL_GEN(dev_priv) >= 8)
4239 gen8_irq_reset(dev_priv);
4240 else
4241 ilk_irq_reset(dev_priv);
4242 }
4243 }
4244
4245 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4246 {
4247 if (HAS_GMCH(dev_priv)) {
4248 if (IS_CHERRYVIEW(dev_priv))
4249 cherryview_irq_postinstall(dev_priv);
4250 else if (IS_VALLEYVIEW(dev_priv))
4251 valleyview_irq_postinstall(dev_priv);
4252 else if (IS_GEN(dev_priv, 4))
4253 i965_irq_postinstall(dev_priv);
4254 else if (IS_GEN(dev_priv, 3))
4255 i915_irq_postinstall(dev_priv);
4256 else
4257 i8xx_irq_postinstall(dev_priv);
4258 } else {
4259 if (INTEL_GEN(dev_priv) >= 11)
4260 gen11_irq_postinstall(dev_priv);
4261 else if (INTEL_GEN(dev_priv) >= 8)
4262 gen8_irq_postinstall(dev_priv);
4263 else
4264 ilk_irq_postinstall(dev_priv);
4265 }
4266 }
4267
4268 /**
4269 * intel_irq_install - enables the hardware interrupt
4270 * @dev_priv: i915 device instance
4271 *
4272 * This function enables the hardware interrupt handling, but leaves the hotplug
4273 * handling still disabled. It is called after intel_irq_init().
4274 *
4275 * In the driver load and resume code we need working interrupts in a few places
4276 * but don't want to deal with the hassle of concurrent probe and hotplug
4277 * workers. Hence the split into this two-stage approach.
4278 */
4279 int intel_irq_install(struct drm_i915_private *dev_priv)
4280 {
4281 int irq = dev_priv->drm.pdev->irq;
4282 int ret;
4283
4284 /*
4285 * We enable some interrupt sources in our postinstall hooks, so mark
4286 * interrupts as enabled _before_ actually enabling them to avoid
4287 * special cases in our ordering checks.
4288 */
4289 dev_priv->runtime_pm.irqs_enabled = true;
4290
4291 dev_priv->drm.irq_enabled = true;
4292
4293 intel_irq_reset(dev_priv);
4294
4295 ret = request_irq(irq, intel_irq_handler(dev_priv),
4296 IRQF_SHARED, DRIVER_NAME, dev_priv);
4297 if (ret < 0) {
4298 dev_priv->drm.irq_enabled = false;
4299 return ret;
4300 }
4301
4302 intel_irq_postinstall(dev_priv);
4303
4304 return ret;
4305 }
4306
4307 /**
4308 * intel_irq_uninstall - finilizes all irq handling
4309 * @dev_priv: i915 device instance
4310 *
4311 * This stops interrupt and hotplug handling and unregisters and frees all
4312 * resources acquired in the init functions.
4313 */
4314 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4315 {
4316 int irq = dev_priv->drm.pdev->irq;
4317
4318 /*
4319 * FIXME we can get called twice during driver probe
4320 * error handling as well as during driver remove due to
4321 * intel_modeset_driver_remove() calling us out of sequence.
4322 * Would be nice if it didn't do that...
4323 */
4324 if (!dev_priv->drm.irq_enabled)
4325 return;
4326
4327 dev_priv->drm.irq_enabled = false;
4328
4329 intel_irq_reset(dev_priv);
4330
4331 free_irq(irq, dev_priv);
4332
4333 intel_hpd_cancel_work(dev_priv);
4334 dev_priv->runtime_pm.irqs_enabled = false;
4335 }
4336
4337 /**
4338 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4339 * @dev_priv: i915 device instance
4340 *
4341 * This function is used to disable interrupts at runtime, both in the runtime
4342 * pm and the system suspend/resume code.
4343 */
4344 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4345 {
4346 intel_irq_reset(dev_priv);
4347 dev_priv->runtime_pm.irqs_enabled = false;
4348 intel_synchronize_irq(dev_priv);
4349 }
4350
4351 /**
4352 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4353 * @dev_priv: i915 device instance
4354 *
4355 * This function is used to enable interrupts at runtime, both in the runtime
4356 * pm and the system suspend/resume code.
4357 */
4358 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4359 {
4360 dev_priv->runtime_pm.irqs_enabled = true;
4361 intel_irq_reset(dev_priv);
4362 intel_irq_postinstall(dev_priv);
4363 }
4364
4365 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4366 {
4367 /*
4368 * We only use drm_irq_uninstall() at unload and VT switch, so
4369 * this is the only thing we need to check.
4370 */
4371 return dev_priv->runtime_pm.irqs_enabled;
4372 }
4373
4374 void intel_synchronize_irq(struct drm_i915_private *i915)
4375 {
4376 synchronize_irq(i915->drm.pdev->irq);
4377 }
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