1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_gen4
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* For display hotplug interrupt */
85 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
87 assert_spin_locked(&dev_priv
->irq_lock
);
89 if (dev_priv
->pc8
.irqs_disabled
) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
95 if ((dev_priv
->irq_mask
& mask
) != 0) {
96 dev_priv
->irq_mask
&= ~mask
;
97 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
103 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
105 assert_spin_locked(&dev_priv
->irq_lock
);
107 if (dev_priv
->pc8
.irqs_disabled
) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv
->pc8
.regsave
.deimr
|= mask
;
113 if ((dev_priv
->irq_mask
& mask
) != mask
) {
114 dev_priv
->irq_mask
|= mask
;
115 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
126 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
127 uint32_t interrupt_mask
,
128 uint32_t enabled_irq_mask
)
130 assert_spin_locked(&dev_priv
->irq_lock
);
132 if (dev_priv
->pc8
.irqs_disabled
) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
135 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
140 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
141 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
142 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
146 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
148 ilk_update_gt_irq(dev_priv
, mask
, mask
);
151 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
153 ilk_update_gt_irq(dev_priv
, mask
, 0);
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
162 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
163 uint32_t interrupt_mask
,
164 uint32_t enabled_irq_mask
)
168 assert_spin_locked(&dev_priv
->irq_lock
);
170 if (dev_priv
->pc8
.irqs_disabled
) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
173 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
178 new_val
= dev_priv
->pm_irq_mask
;
179 new_val
&= ~interrupt_mask
;
180 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
182 if (new_val
!= dev_priv
->pm_irq_mask
) {
183 dev_priv
->pm_irq_mask
= new_val
;
184 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
185 POSTING_READ(GEN6_PMIMR
);
189 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
191 snb_update_pm_irq(dev_priv
, mask
, mask
);
194 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
196 snb_update_pm_irq(dev_priv
, mask
, 0);
199 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
202 struct intel_crtc
*crtc
;
205 assert_spin_locked(&dev_priv
->irq_lock
);
207 for_each_pipe(pipe
) {
208 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
210 if (crtc
->cpu_fifo_underrun_disabled
)
217 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
221 struct intel_crtc
*crtc
;
223 assert_spin_locked(&dev_priv
->irq_lock
);
225 for_each_pipe(pipe
) {
226 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
228 if (crtc
->pch_fifo_underrun_disabled
)
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
236 enum pipe pipe
, bool enable
)
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
240 DE_PIPEB_FIFO_UNDERRUN
;
243 ironlake_enable_display_irq(dev_priv
, bit
);
245 ironlake_disable_display_irq(dev_priv
, bit
);
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
249 enum pipe pipe
, bool enable
)
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
255 if (!ivb_can_enable_err_int(dev
))
258 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
260 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
266 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
279 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
280 uint32_t interrupt_mask
,
281 uint32_t enabled_irq_mask
)
283 uint32_t sdeimr
= I915_READ(SDEIMR
);
284 sdeimr
&= ~interrupt_mask
;
285 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
287 assert_spin_locked(&dev_priv
->irq_lock
);
289 if (dev_priv
->pc8
.irqs_disabled
&&
290 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
293 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
298 I915_WRITE(SDEIMR
, sdeimr
);
299 POSTING_READ(SDEIMR
);
301 #define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303 #define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
306 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
307 enum transcoder pch_transcoder
,
310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
311 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
312 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
315 ibx_enable_display_interrupt(dev_priv
, bit
);
317 ibx_disable_display_interrupt(dev_priv
, bit
);
320 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
321 enum transcoder pch_transcoder
,
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
330 if (!cpt_can_enable_serr_int(dev
))
333 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
335 uint32_t tmp
= I915_READ(SERR_INT
);
336 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
338 /* Change the state _after_ we've read out the current one. */
339 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
342 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder
));
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
361 * Returns the previous state of underrun reporting.
363 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
364 enum pipe pipe
, bool enable
)
366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
367 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
372 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
374 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
379 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
381 if (IS_GEN5(dev
) || IS_GEN6(dev
))
382 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
383 else if (IS_GEN7(dev
))
384 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
387 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
403 * Returns the previous state of underrun reporting.
405 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
406 enum transcoder pch_transcoder
,
409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
410 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
411 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
424 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
426 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
431 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
433 if (HAS_PCH_IBX(dev
))
434 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
436 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
439 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
445 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
)
447 u32 reg
= PIPESTAT(pipe
);
448 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
450 assert_spin_locked(&dev_priv
->irq_lock
);
452 if ((pipestat
& mask
) == mask
)
455 /* Enable the interrupt, clear any pending status */
456 pipestat
|= mask
| (mask
>> 16);
457 I915_WRITE(reg
, pipestat
);
462 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
)
464 u32 reg
= PIPESTAT(pipe
);
465 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
467 assert_spin_locked(&dev_priv
->irq_lock
);
469 if ((pipestat
& mask
) == 0)
473 I915_WRITE(reg
, pipestat
);
478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
480 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
483 unsigned long irqflags
;
485 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
488 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
490 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_ENABLE
);
491 if (INTEL_INFO(dev
)->gen
>= 4)
492 i915_enable_pipestat(dev_priv
, PIPE_A
,
493 PIPE_LEGACY_BLC_EVENT_ENABLE
);
495 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
499 * i915_pipe_enabled - check if a pipe is enabled
501 * @pipe: pipe to check
503 * Reading certain registers when the pipe is disabled can hang the chip.
504 * Use this routine to make sure the PLL is running and the pipe is active
505 * before reading such registers if unsure.
508 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
510 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
512 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
513 /* Locking is horribly broken here, but whatever. */
514 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
515 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
517 return intel_crtc
->active
;
519 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
523 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
525 /* Gen2 doesn't have a hardware frame counter */
529 /* Called from drm generic code, passed a 'crtc', which
530 * we use as a pipe index
532 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
534 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
535 unsigned long high_frame
;
536 unsigned long low_frame
;
537 u32 high1
, high2
, low
, pixel
, vbl_start
;
539 if (!i915_pipe_enabled(dev
, pipe
)) {
540 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
541 "pipe %c\n", pipe_name(pipe
));
545 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
546 struct intel_crtc
*intel_crtc
=
547 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
548 const struct drm_display_mode
*mode
=
549 &intel_crtc
->config
.adjusted_mode
;
551 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
553 enum transcoder cpu_transcoder
=
554 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
557 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
558 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
563 high_frame
= PIPEFRAME(pipe
);
564 low_frame
= PIPEFRAMEPIXEL(pipe
);
567 * High & low register fields aren't synchronized, so make sure
568 * we get a low value that's stable across two reads of the high
572 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
573 low
= I915_READ(low_frame
);
574 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
575 } while (high1
!= high2
);
577 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
578 pixel
= low
& PIPE_PIXEL_MASK
;
579 low
>>= PIPE_FRAME_LOW_SHIFT
;
582 * The frame counter increments at beginning of active.
583 * Cook up a vblank counter by also checking the pixel
584 * counter against vblank start.
586 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
589 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
591 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
592 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
594 if (!i915_pipe_enabled(dev
, pipe
)) {
595 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
596 "pipe %c\n", pipe_name(pipe
));
600 return I915_READ(reg
);
603 static bool intel_pipe_in_vblank(struct drm_device
*dev
, enum pipe pipe
)
605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
608 if (IS_VALLEYVIEW(dev
)) {
609 status
= pipe
== PIPE_A
?
610 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
611 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
613 return I915_READ(VLV_ISR
) & status
;
614 } else if (IS_GEN2(dev
)) {
615 status
= pipe
== PIPE_A
?
616 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
617 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
619 return I915_READ16(ISR
) & status
;
620 } else if (INTEL_INFO(dev
)->gen
< 5) {
621 status
= pipe
== PIPE_A
?
622 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
623 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
625 return I915_READ(ISR
) & status
;
626 } else if (INTEL_INFO(dev
)->gen
< 7) {
627 status
= pipe
== PIPE_A
?
631 return I915_READ(DEISR
) & status
;
636 status
= DE_PIPEA_VBLANK_IVB
;
639 status
= DE_PIPEB_VBLANK_IVB
;
642 status
= DE_PIPEC_VBLANK_IVB
;
646 return I915_READ(DEISR
) & status
;
650 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
651 int *vpos
, int *hpos
)
653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
654 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
656 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
658 int vbl_start
, vbl_end
, htotal
, vtotal
;
662 if (!intel_crtc
->active
) {
663 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
664 "pipe %c\n", pipe_name(pipe
));
668 htotal
= mode
->crtc_htotal
;
669 vtotal
= mode
->crtc_vtotal
;
670 vbl_start
= mode
->crtc_vblank_start
;
671 vbl_end
= mode
->crtc_vblank_end
;
673 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
675 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
676 /* No obvious pixelcount register. Only query vertical
677 * scanout position from Display scan line register.
680 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
682 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
685 * The scanline counter increments at the leading edge
686 * of hsync, ie. it completely misses the active portion
687 * of the line. Fix up the counter at both edges of vblank
688 * to get a more accurate picture whether we're in vblank
691 in_vbl
= intel_pipe_in_vblank(dev
, pipe
);
692 if ((in_vbl
&& position
== vbl_start
- 1) ||
693 (!in_vbl
&& position
== vbl_end
- 1))
694 position
= (position
+ 1) % vtotal
;
696 /* Have access to pixelcount since start of frame.
697 * We can split this into vertical and horizontal
700 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
702 /* convert to pixel counts */
708 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
711 * While in vblank, position will be negative
712 * counting up towards 0 at vbl_end. And outside
713 * vblank, position will be positive counting
716 if (position
>= vbl_start
)
719 position
+= vtotal
- vbl_end
;
721 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
725 *vpos
= position
/ htotal
;
726 *hpos
= position
- (*vpos
* htotal
);
731 ret
|= DRM_SCANOUTPOS_INVBL
;
736 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
738 struct timeval
*vblank_time
,
741 struct drm_crtc
*crtc
;
743 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
744 DRM_ERROR("Invalid crtc %d\n", pipe
);
748 /* Get drm_crtc to timestamp: */
749 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
751 DRM_ERROR("Invalid crtc %d\n", pipe
);
755 if (!crtc
->enabled
) {
756 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
760 /* Helper routine in DRM core does all the work: */
761 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
766 static bool intel_hpd_irq_event(struct drm_device
*dev
,
767 struct drm_connector
*connector
)
769 enum drm_connector_status old_status
;
771 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
772 old_status
= connector
->status
;
774 connector
->status
= connector
->funcs
->detect(connector
, false);
775 if (old_status
== connector
->status
)
778 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
780 drm_get_connector_name(connector
),
781 drm_get_connector_status_name(old_status
),
782 drm_get_connector_status_name(connector
->status
));
788 * Handle hotplug events outside the interrupt handler proper.
790 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
792 static void i915_hotplug_work_func(struct work_struct
*work
)
794 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
796 struct drm_device
*dev
= dev_priv
->dev
;
797 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
798 struct intel_connector
*intel_connector
;
799 struct intel_encoder
*intel_encoder
;
800 struct drm_connector
*connector
;
801 unsigned long irqflags
;
802 bool hpd_disabled
= false;
803 bool changed
= false;
806 /* HPD irq before everything is fully set up. */
807 if (!dev_priv
->enable_hotplug_processing
)
810 mutex_lock(&mode_config
->mutex
);
811 DRM_DEBUG_KMS("running encoder hotplug functions\n");
813 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
815 hpd_event_bits
= dev_priv
->hpd_event_bits
;
816 dev_priv
->hpd_event_bits
= 0;
817 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
818 intel_connector
= to_intel_connector(connector
);
819 intel_encoder
= intel_connector
->encoder
;
820 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
821 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
822 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
823 DRM_INFO("HPD interrupt storm detected on connector %s: "
824 "switching from hotplug detection to polling\n",
825 drm_get_connector_name(connector
));
826 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
827 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
828 | DRM_CONNECTOR_POLL_DISCONNECT
;
831 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
832 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
833 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
836 /* if there were no outputs to poll, poll was disabled,
837 * therefore make sure it's enabled when disabling HPD on
840 drm_kms_helper_poll_enable(dev
);
841 mod_timer(&dev_priv
->hotplug_reenable_timer
,
842 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
845 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
847 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
848 intel_connector
= to_intel_connector(connector
);
849 intel_encoder
= intel_connector
->encoder
;
850 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
851 if (intel_encoder
->hot_plug
)
852 intel_encoder
->hot_plug(intel_encoder
);
853 if (intel_hpd_irq_event(dev
, connector
))
857 mutex_unlock(&mode_config
->mutex
);
860 drm_kms_helper_hotplug_event(dev
);
863 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
866 u32 busy_up
, busy_down
, max_avg
, min_avg
;
869 spin_lock(&mchdev_lock
);
871 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
873 new_delay
= dev_priv
->ips
.cur_delay
;
875 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
876 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
877 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
878 max_avg
= I915_READ(RCBMAXAVG
);
879 min_avg
= I915_READ(RCBMINAVG
);
881 /* Handle RCS change request from hw */
882 if (busy_up
> max_avg
) {
883 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
884 new_delay
= dev_priv
->ips
.cur_delay
- 1;
885 if (new_delay
< dev_priv
->ips
.max_delay
)
886 new_delay
= dev_priv
->ips
.max_delay
;
887 } else if (busy_down
< min_avg
) {
888 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
889 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
890 if (new_delay
> dev_priv
->ips
.min_delay
)
891 new_delay
= dev_priv
->ips
.min_delay
;
894 if (ironlake_set_drps(dev
, new_delay
))
895 dev_priv
->ips
.cur_delay
= new_delay
;
897 spin_unlock(&mchdev_lock
);
902 static void notify_ring(struct drm_device
*dev
,
903 struct intel_ring_buffer
*ring
)
905 if (ring
->obj
== NULL
)
908 trace_i915_gem_request_complete(ring
);
910 wake_up_all(&ring
->irq_queue
);
911 i915_queue_hangcheck(dev
);
914 static void gen6_pm_rps_work(struct work_struct
*work
)
916 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
921 spin_lock_irq(&dev_priv
->irq_lock
);
922 pm_iir
= dev_priv
->rps
.pm_iir
;
923 dev_priv
->rps
.pm_iir
= 0;
924 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
925 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
926 spin_unlock_irq(&dev_priv
->irq_lock
);
928 /* Make sure we didn't queue anything we're not going to process. */
929 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
931 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
934 mutex_lock(&dev_priv
->rps
.hw_lock
);
936 adj
= dev_priv
->rps
.last_adj
;
937 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
942 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
945 * For better performance, jump directly
946 * to RPe if we're below it.
948 if (new_delay
< dev_priv
->rps
.rpe_delay
)
949 new_delay
= dev_priv
->rps
.rpe_delay
;
950 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
951 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
952 new_delay
= dev_priv
->rps
.rpe_delay
;
954 new_delay
= dev_priv
->rps
.min_delay
;
956 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
961 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
962 } else { /* unknown event */
963 new_delay
= dev_priv
->rps
.cur_delay
;
966 /* sysfs frequency interfaces may have snuck in while servicing the
969 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
970 new_delay
= dev_priv
->rps
.min_delay
;
971 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
972 new_delay
= dev_priv
->rps
.max_delay
;
973 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
975 if (IS_VALLEYVIEW(dev_priv
->dev
))
976 valleyview_set_rps(dev_priv
->dev
, new_delay
);
978 gen6_set_rps(dev_priv
->dev
, new_delay
);
980 mutex_unlock(&dev_priv
->rps
.hw_lock
);
985 * ivybridge_parity_work - Workqueue called when a parity error interrupt
987 * @work: workqueue struct
989 * Doesn't actually do anything except notify userspace. As a consequence of
990 * this event, userspace should try to remap the bad rows since statistically
991 * it is likely the same row is more likely to go bad again.
993 static void ivybridge_parity_work(struct work_struct
*work
)
995 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
996 l3_parity
.error_work
);
997 u32 error_status
, row
, bank
, subbank
;
998 char *parity_event
[6];
1000 unsigned long flags
;
1003 /* We must turn off DOP level clock gating to access the L3 registers.
1004 * In order to prevent a get/put style interface, acquire struct mutex
1005 * any time we access those registers.
1007 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1009 /* If we've screwed up tracking, just let the interrupt fire again */
1010 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1013 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1014 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1015 POSTING_READ(GEN7_MISCCPCTL
);
1017 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1021 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1024 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1026 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1028 error_status
= I915_READ(reg
);
1029 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1030 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1031 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1033 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1036 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1037 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1038 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1039 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1040 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1041 parity_event
[5] = NULL
;
1043 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
1044 KOBJ_CHANGE
, parity_event
);
1046 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1047 slice
, row
, bank
, subbank
);
1049 kfree(parity_event
[4]);
1050 kfree(parity_event
[3]);
1051 kfree(parity_event
[2]);
1052 kfree(parity_event
[1]);
1055 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1058 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1059 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1060 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1061 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1063 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1066 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1068 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1070 if (!HAS_L3_DPF(dev
))
1073 spin_lock(&dev_priv
->irq_lock
);
1074 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1075 spin_unlock(&dev_priv
->irq_lock
);
1077 iir
&= GT_PARITY_ERROR(dev
);
1078 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1079 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1081 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1082 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1084 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1087 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1088 struct drm_i915_private
*dev_priv
,
1092 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1093 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1094 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1095 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1098 static void snb_gt_irq_handler(struct drm_device
*dev
,
1099 struct drm_i915_private
*dev_priv
,
1104 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1105 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1106 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1107 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1108 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1109 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1111 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1112 GT_BSD_CS_ERROR_INTERRUPT
|
1113 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1114 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1115 i915_handle_error(dev
, false);
1118 if (gt_iir
& GT_PARITY_ERROR(dev
))
1119 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1122 #define HPD_STORM_DETECT_PERIOD 1000
1123 #define HPD_STORM_THRESHOLD 5
1125 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1126 u32 hotplug_trigger
,
1129 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1131 bool storm_detected
= false;
1133 if (!hotplug_trigger
)
1136 spin_lock(&dev_priv
->irq_lock
);
1137 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1139 WARN(((hpd
[i
] & hotplug_trigger
) &&
1140 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1141 "Received HPD interrupt although disabled\n");
1143 if (!(hpd
[i
] & hotplug_trigger
) ||
1144 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1147 dev_priv
->hpd_event_bits
|= (1 << i
);
1148 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1149 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1150 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1151 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1152 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1153 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1154 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1155 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1156 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1157 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1158 storm_detected
= true;
1160 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1161 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1162 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1167 dev_priv
->display
.hpd_irq_setup(dev
);
1168 spin_unlock(&dev_priv
->irq_lock
);
1171 * Our hotplug handler can grab modeset locks (by calling down into the
1172 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1173 * queue for otherwise the flush_work in the pageflip code will
1176 schedule_work(&dev_priv
->hotplug_work
);
1179 static void gmbus_irq_handler(struct drm_device
*dev
)
1181 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1183 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1186 static void dp_aux_irq_handler(struct drm_device
*dev
)
1188 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1190 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1193 #if defined(CONFIG_DEBUG_FS)
1194 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1195 uint32_t crc0
, uint32_t crc1
,
1196 uint32_t crc2
, uint32_t crc3
,
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1201 struct intel_pipe_crc_entry
*entry
;
1204 spin_lock(&pipe_crc
->lock
);
1206 if (!pipe_crc
->entries
) {
1207 spin_unlock(&pipe_crc
->lock
);
1208 DRM_ERROR("spurious interrupt\n");
1212 head
= pipe_crc
->head
;
1213 tail
= pipe_crc
->tail
;
1215 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1216 spin_unlock(&pipe_crc
->lock
);
1217 DRM_ERROR("CRC buffer overflowing\n");
1221 entry
= &pipe_crc
->entries
[head
];
1223 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1224 entry
->crc
[0] = crc0
;
1225 entry
->crc
[1] = crc1
;
1226 entry
->crc
[2] = crc2
;
1227 entry
->crc
[3] = crc3
;
1228 entry
->crc
[4] = crc4
;
1230 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1231 pipe_crc
->head
= head
;
1233 spin_unlock(&pipe_crc
->lock
);
1235 wake_up_interruptible(&pipe_crc
->wq
);
1239 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1240 uint32_t crc0
, uint32_t crc1
,
1241 uint32_t crc2
, uint32_t crc3
,
1246 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1250 display_pipe_crc_irq_handler(dev
, pipe
,
1251 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1255 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 display_pipe_crc_irq_handler(dev
, pipe
,
1260 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1261 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1262 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1263 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1264 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1267 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 uint32_t res1
, res2
;
1272 if (INTEL_INFO(dev
)->gen
>= 3)
1273 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1277 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1278 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1282 display_pipe_crc_irq_handler(dev
, pipe
,
1283 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1284 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1285 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1289 /* The RPS events need forcewake, so we add them to a work queue and mask their
1290 * IMR bits until the work is done. Other interrupts can be processed without
1291 * the work queue. */
1292 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1294 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1295 spin_lock(&dev_priv
->irq_lock
);
1296 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1297 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1298 spin_unlock(&dev_priv
->irq_lock
);
1300 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1303 if (HAS_VEBOX(dev_priv
->dev
)) {
1304 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1305 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1307 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1308 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1309 i915_handle_error(dev_priv
->dev
, false);
1314 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1316 struct drm_device
*dev
= (struct drm_device
*) arg
;
1317 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1318 u32 iir
, gt_iir
, pm_iir
;
1319 irqreturn_t ret
= IRQ_NONE
;
1320 unsigned long irqflags
;
1322 u32 pipe_stats
[I915_MAX_PIPES
];
1324 atomic_inc(&dev_priv
->irq_received
);
1327 iir
= I915_READ(VLV_IIR
);
1328 gt_iir
= I915_READ(GTIIR
);
1329 pm_iir
= I915_READ(GEN6_PMIIR
);
1331 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1336 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1338 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1339 for_each_pipe(pipe
) {
1340 int reg
= PIPESTAT(pipe
);
1341 pipe_stats
[pipe
] = I915_READ(reg
);
1344 * Clear the PIPE*STAT regs before the IIR
1346 if (pipe_stats
[pipe
] & 0x8000ffff) {
1347 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1348 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1350 I915_WRITE(reg
, pipe_stats
[pipe
]);
1353 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1355 for_each_pipe(pipe
) {
1356 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1357 drm_handle_vblank(dev
, pipe
);
1359 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1360 intel_prepare_page_flip(dev
, pipe
);
1361 intel_finish_page_flip(dev
, pipe
);
1364 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1365 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1368 /* Consume port. Then clear IIR or we'll miss events */
1369 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1370 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1371 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1373 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1376 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1378 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1379 I915_READ(PORT_HOTPLUG_STAT
);
1382 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1383 gmbus_irq_handler(dev
);
1386 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1388 I915_WRITE(GTIIR
, gt_iir
);
1389 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1390 I915_WRITE(VLV_IIR
, iir
);
1397 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1399 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1401 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1403 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1405 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1406 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1407 SDE_AUDIO_POWER_SHIFT
);
1408 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1412 if (pch_iir
& SDE_AUX_MASK
)
1413 dp_aux_irq_handler(dev
);
1415 if (pch_iir
& SDE_GMBUS
)
1416 gmbus_irq_handler(dev
);
1418 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1419 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1421 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1422 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1424 if (pch_iir
& SDE_POISON
)
1425 DRM_ERROR("PCH poison interrupt\n");
1427 if (pch_iir
& SDE_FDI_MASK
)
1429 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1431 I915_READ(FDI_RX_IIR(pipe
)));
1433 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1434 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1436 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1437 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1439 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1440 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1442 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1444 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1445 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1447 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1450 static void ivb_err_int_handler(struct drm_device
*dev
)
1452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1453 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1456 if (err_int
& ERR_INT_POISON
)
1457 DRM_ERROR("Poison interrupt\n");
1459 for_each_pipe(pipe
) {
1460 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) {
1461 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1463 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1467 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1468 if (IS_IVYBRIDGE(dev
))
1469 ivb_pipe_crc_irq_handler(dev
, pipe
);
1471 hsw_pipe_crc_irq_handler(dev
, pipe
);
1475 I915_WRITE(GEN7_ERR_INT
, err_int
);
1478 static void cpt_serr_int_handler(struct drm_device
*dev
)
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1481 u32 serr_int
= I915_READ(SERR_INT
);
1483 if (serr_int
& SERR_INT_POISON
)
1484 DRM_ERROR("PCH poison interrupt\n");
1486 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1487 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1489 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1491 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1492 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1494 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1496 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1497 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1499 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1501 I915_WRITE(SERR_INT
, serr_int
);
1504 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1506 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1508 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1510 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1512 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1513 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1514 SDE_AUDIO_POWER_SHIFT_CPT
);
1515 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1519 if (pch_iir
& SDE_AUX_MASK_CPT
)
1520 dp_aux_irq_handler(dev
);
1522 if (pch_iir
& SDE_GMBUS_CPT
)
1523 gmbus_irq_handler(dev
);
1525 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1526 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1528 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1529 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1531 if (pch_iir
& SDE_FDI_MASK_CPT
)
1533 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1535 I915_READ(FDI_RX_IIR(pipe
)));
1537 if (pch_iir
& SDE_ERROR_CPT
)
1538 cpt_serr_int_handler(dev
);
1541 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1545 if (de_iir
& DE_AUX_CHANNEL_A
)
1546 dp_aux_irq_handler(dev
);
1548 if (de_iir
& DE_GSE
)
1549 intel_opregion_asle_intr(dev
);
1551 if (de_iir
& DE_PIPEA_VBLANK
)
1552 drm_handle_vblank(dev
, 0);
1554 if (de_iir
& DE_PIPEB_VBLANK
)
1555 drm_handle_vblank(dev
, 1);
1557 if (de_iir
& DE_POISON
)
1558 DRM_ERROR("Poison interrupt\n");
1560 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1561 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1562 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1564 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1565 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1566 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1568 if (de_iir
& DE_PIPEA_CRC_DONE
)
1569 i9xx_pipe_crc_irq_handler(dev
, PIPE_A
);
1571 if (de_iir
& DE_PIPEB_CRC_DONE
)
1572 i9xx_pipe_crc_irq_handler(dev
, PIPE_B
);
1574 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1575 intel_prepare_page_flip(dev
, 0);
1576 intel_finish_page_flip_plane(dev
, 0);
1579 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1580 intel_prepare_page_flip(dev
, 1);
1581 intel_finish_page_flip_plane(dev
, 1);
1584 /* check event from PCH */
1585 if (de_iir
& DE_PCH_EVENT
) {
1586 u32 pch_iir
= I915_READ(SDEIIR
);
1588 if (HAS_PCH_CPT(dev
))
1589 cpt_irq_handler(dev
, pch_iir
);
1591 ibx_irq_handler(dev
, pch_iir
);
1593 /* should clear PCH hotplug event before clear CPU irq */
1594 I915_WRITE(SDEIIR
, pch_iir
);
1597 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1598 ironlake_rps_change_irq_handler(dev
);
1601 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1606 if (de_iir
& DE_ERR_INT_IVB
)
1607 ivb_err_int_handler(dev
);
1609 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1610 dp_aux_irq_handler(dev
);
1612 if (de_iir
& DE_GSE_IVB
)
1613 intel_opregion_asle_intr(dev
);
1616 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1617 drm_handle_vblank(dev
, i
);
1618 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1619 intel_prepare_page_flip(dev
, i
);
1620 intel_finish_page_flip_plane(dev
, i
);
1624 /* check event from PCH */
1625 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1626 u32 pch_iir
= I915_READ(SDEIIR
);
1628 cpt_irq_handler(dev
, pch_iir
);
1630 /* clear PCH hotplug event before clear CPU irq */
1631 I915_WRITE(SDEIIR
, pch_iir
);
1635 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1637 struct drm_device
*dev
= (struct drm_device
*) arg
;
1638 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1639 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1640 irqreturn_t ret
= IRQ_NONE
;
1642 atomic_inc(&dev_priv
->irq_received
);
1644 /* We get interrupts on unclaimed registers, so check for this before we
1645 * do any I915_{READ,WRITE}. */
1646 intel_uncore_check_errors(dev
);
1648 /* disable master interrupt before clearing iir */
1649 de_ier
= I915_READ(DEIER
);
1650 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1651 POSTING_READ(DEIER
);
1653 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1654 * interrupts will will be stored on its back queue, and then we'll be
1655 * able to process them after we restore SDEIER (as soon as we restore
1656 * it, we'll get an interrupt if SDEIIR still has something to process
1657 * due to its back queue). */
1658 if (!HAS_PCH_NOP(dev
)) {
1659 sde_ier
= I915_READ(SDEIER
);
1660 I915_WRITE(SDEIER
, 0);
1661 POSTING_READ(SDEIER
);
1664 gt_iir
= I915_READ(GTIIR
);
1666 if (INTEL_INFO(dev
)->gen
>= 6)
1667 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1669 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1670 I915_WRITE(GTIIR
, gt_iir
);
1674 de_iir
= I915_READ(DEIIR
);
1676 if (INTEL_INFO(dev
)->gen
>= 7)
1677 ivb_display_irq_handler(dev
, de_iir
);
1679 ilk_display_irq_handler(dev
, de_iir
);
1680 I915_WRITE(DEIIR
, de_iir
);
1684 if (INTEL_INFO(dev
)->gen
>= 6) {
1685 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1687 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1688 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1693 I915_WRITE(DEIER
, de_ier
);
1694 POSTING_READ(DEIER
);
1695 if (!HAS_PCH_NOP(dev
)) {
1696 I915_WRITE(SDEIER
, sde_ier
);
1697 POSTING_READ(SDEIER
);
1703 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1704 bool reset_completed
)
1706 struct intel_ring_buffer
*ring
;
1710 * Notify all waiters for GPU completion events that reset state has
1711 * been changed, and that they need to restart their wait after
1712 * checking for potential errors (and bail out to drop locks if there is
1713 * a gpu reset pending so that i915_error_work_func can acquire them).
1716 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1717 for_each_ring(ring
, dev_priv
, i
)
1718 wake_up_all(&ring
->irq_queue
);
1720 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1721 wake_up_all(&dev_priv
->pending_flip_queue
);
1724 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1725 * reset state is cleared.
1727 if (reset_completed
)
1728 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1732 * i915_error_work_func - do process context error handling work
1733 * @work: work struct
1735 * Fire an error uevent so userspace can see that a hang or error
1738 static void i915_error_work_func(struct work_struct
*work
)
1740 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1742 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1744 struct drm_device
*dev
= dev_priv
->dev
;
1745 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1746 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1747 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1750 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1753 * Note that there's only one work item which does gpu resets, so we
1754 * need not worry about concurrent gpu resets potentially incrementing
1755 * error->reset_counter twice. We only need to take care of another
1756 * racing irq/hangcheck declaring the gpu dead for a second time. A
1757 * quick check for that is good enough: schedule_work ensures the
1758 * correct ordering between hang detection and this work item, and since
1759 * the reset in-progress bit is only ever set by code outside of this
1760 * work we don't need to worry about any other races.
1762 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1763 DRM_DEBUG_DRIVER("resetting chip\n");
1764 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1768 * All state reset _must_ be completed before we update the
1769 * reset counter, for otherwise waiters might miss the reset
1770 * pending state and not properly drop locks, resulting in
1771 * deadlocks with the reset work.
1773 ret
= i915_reset(dev
);
1775 intel_display_handle_reset(dev
);
1779 * After all the gem state is reset, increment the reset
1780 * counter and wake up everyone waiting for the reset to
1783 * Since unlock operations are a one-sided barrier only,
1784 * we need to insert a barrier here to order any seqno
1786 * the counter increment.
1788 smp_mb__before_atomic_inc();
1789 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1791 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1792 KOBJ_CHANGE
, reset_done_event
);
1794 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1798 * Note: The wake_up also serves as a memory barrier so that
1799 * waiters see the update value of the reset counter atomic_t.
1801 i915_error_wake_up(dev_priv
, true);
1805 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1808 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1809 u32 eir
= I915_READ(EIR
);
1815 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1817 i915_get_extra_instdone(dev
, instdone
);
1820 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1821 u32 ipeir
= I915_READ(IPEIR_I965
);
1823 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1824 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1825 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1826 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1827 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1828 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1829 I915_WRITE(IPEIR_I965
, ipeir
);
1830 POSTING_READ(IPEIR_I965
);
1832 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1833 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1834 pr_err("page table error\n");
1835 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1836 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1837 POSTING_READ(PGTBL_ER
);
1841 if (!IS_GEN2(dev
)) {
1842 if (eir
& I915_ERROR_PAGE_TABLE
) {
1843 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1844 pr_err("page table error\n");
1845 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1846 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1847 POSTING_READ(PGTBL_ER
);
1851 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1852 pr_err("memory refresh error:\n");
1854 pr_err("pipe %c stat: 0x%08x\n",
1855 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1856 /* pipestat has already been acked */
1858 if (eir
& I915_ERROR_INSTRUCTION
) {
1859 pr_err("instruction error\n");
1860 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1861 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1862 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1863 if (INTEL_INFO(dev
)->gen
< 4) {
1864 u32 ipeir
= I915_READ(IPEIR
);
1866 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1867 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1868 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1869 I915_WRITE(IPEIR
, ipeir
);
1870 POSTING_READ(IPEIR
);
1872 u32 ipeir
= I915_READ(IPEIR_I965
);
1874 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1875 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1876 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1877 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1878 I915_WRITE(IPEIR_I965
, ipeir
);
1879 POSTING_READ(IPEIR_I965
);
1883 I915_WRITE(EIR
, eir
);
1885 eir
= I915_READ(EIR
);
1888 * some errors might have become stuck,
1891 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1892 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1893 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1898 * i915_handle_error - handle an error interrupt
1901 * Do some basic checking of regsiter state at error interrupt time and
1902 * dump it to the syslog. Also call i915_capture_error_state() to make
1903 * sure we get a record and make it available in debugfs. Fire a uevent
1904 * so userspace knows something bad happened (should trigger collection
1905 * of a ring dump etc.).
1907 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 i915_capture_error_state(dev
);
1912 i915_report_and_clear_eir(dev
);
1915 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1916 &dev_priv
->gpu_error
.reset_counter
);
1919 * Wakeup waiting processes so that the reset work function
1920 * i915_error_work_func doesn't deadlock trying to grab various
1921 * locks. By bumping the reset counter first, the woken
1922 * processes will see a reset in progress and back off,
1923 * releasing their locks and then wait for the reset completion.
1924 * We must do this for _all_ gpu waiters that might hold locks
1925 * that the reset work needs to acquire.
1927 * Note: The wake_up serves as the required memory barrier to
1928 * ensure that the waiters see the updated value of the reset
1931 i915_error_wake_up(dev_priv
, false);
1935 * Our reset work can grab modeset locks (since it needs to reset the
1936 * state of outstanding pagelips). Hence it must not be run on our own
1937 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1938 * code will deadlock.
1940 schedule_work(&dev_priv
->gpu_error
.work
);
1943 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1945 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1946 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1948 struct drm_i915_gem_object
*obj
;
1949 struct intel_unpin_work
*work
;
1950 unsigned long flags
;
1951 bool stall_detected
;
1953 /* Ignore early vblank irqs */
1954 if (intel_crtc
== NULL
)
1957 spin_lock_irqsave(&dev
->event_lock
, flags
);
1958 work
= intel_crtc
->unpin_work
;
1961 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1962 !work
->enable_stall_check
) {
1963 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1964 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1968 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1969 obj
= work
->pending_flip_obj
;
1970 if (INTEL_INFO(dev
)->gen
>= 4) {
1971 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1972 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1973 i915_gem_obj_ggtt_offset(obj
);
1975 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1976 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1977 crtc
->y
* crtc
->fb
->pitches
[0] +
1978 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1981 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1983 if (stall_detected
) {
1984 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1985 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1989 /* Called from drm generic code, passed 'crtc' which
1990 * we use as a pipe index
1992 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1994 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1995 unsigned long irqflags
;
1997 if (!i915_pipe_enabled(dev
, pipe
))
2000 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2001 if (INTEL_INFO(dev
)->gen
>= 4)
2002 i915_enable_pipestat(dev_priv
, pipe
,
2003 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2005 i915_enable_pipestat(dev_priv
, pipe
,
2006 PIPE_VBLANK_INTERRUPT_ENABLE
);
2008 /* maintain vblank delivery even in deep C-states */
2009 if (dev_priv
->info
->gen
== 3)
2010 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2011 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2016 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2018 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2019 unsigned long irqflags
;
2020 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2021 DE_PIPE_VBLANK_ILK(pipe
);
2023 if (!i915_pipe_enabled(dev
, pipe
))
2026 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2027 ironlake_enable_display_irq(dev_priv
, bit
);
2028 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2033 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2035 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2036 unsigned long irqflags
;
2039 if (!i915_pipe_enabled(dev
, pipe
))
2042 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2043 imr
= I915_READ(VLV_IMR
);
2045 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2047 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2048 I915_WRITE(VLV_IMR
, imr
);
2049 i915_enable_pipestat(dev_priv
, pipe
,
2050 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2051 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2056 /* Called from drm generic code, passed 'crtc' which
2057 * we use as a pipe index
2059 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2061 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2062 unsigned long irqflags
;
2064 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2065 if (dev_priv
->info
->gen
== 3)
2066 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2068 i915_disable_pipestat(dev_priv
, pipe
,
2069 PIPE_VBLANK_INTERRUPT_ENABLE
|
2070 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2071 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2074 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2076 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2077 unsigned long irqflags
;
2078 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2079 DE_PIPE_VBLANK_ILK(pipe
);
2081 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2082 ironlake_disable_display_irq(dev_priv
, bit
);
2083 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2086 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2088 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2089 unsigned long irqflags
;
2092 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2093 i915_disable_pipestat(dev_priv
, pipe
,
2094 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2095 imr
= I915_READ(VLV_IMR
);
2097 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2099 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2100 I915_WRITE(VLV_IMR
, imr
);
2101 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2105 ring_last_seqno(struct intel_ring_buffer
*ring
)
2107 return list_entry(ring
->request_list
.prev
,
2108 struct drm_i915_gem_request
, list
)->seqno
;
2112 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2114 return (list_empty(&ring
->request_list
) ||
2115 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2118 static struct intel_ring_buffer
*
2119 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2121 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2122 u32 cmd
, ipehr
, acthd
, acthd_min
;
2124 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2125 if ((ipehr
& ~(0x3 << 16)) !=
2126 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2129 /* ACTHD is likely pointing to the dword after the actual command,
2130 * so scan backwards until we find the MBOX.
2132 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2133 acthd_min
= max((int)acthd
- 3 * 4, 0);
2135 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2140 if (acthd
< acthd_min
)
2144 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2145 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2148 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2150 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2151 struct intel_ring_buffer
*signaller
;
2154 ring
->hangcheck
.deadlock
= true;
2156 signaller
= semaphore_waits_for(ring
, &seqno
);
2157 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2160 /* cursory check for an unkickable deadlock */
2161 ctl
= I915_READ_CTL(signaller
);
2162 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2165 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2168 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2170 struct intel_ring_buffer
*ring
;
2173 for_each_ring(ring
, dev_priv
, i
)
2174 ring
->hangcheck
.deadlock
= false;
2177 static enum intel_ring_hangcheck_action
2178 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2180 struct drm_device
*dev
= ring
->dev
;
2181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2184 if (ring
->hangcheck
.acthd
!= acthd
)
2185 return HANGCHECK_ACTIVE
;
2188 return HANGCHECK_HUNG
;
2190 /* Is the chip hanging on a WAIT_FOR_EVENT?
2191 * If so we can simply poke the RB_WAIT bit
2192 * and break the hang. This should work on
2193 * all but the second generation chipsets.
2195 tmp
= I915_READ_CTL(ring
);
2196 if (tmp
& RING_WAIT
) {
2197 DRM_ERROR("Kicking stuck wait on %s\n",
2199 i915_handle_error(dev
, false);
2200 I915_WRITE_CTL(ring
, tmp
);
2201 return HANGCHECK_KICK
;
2204 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2205 switch (semaphore_passed(ring
)) {
2207 return HANGCHECK_HUNG
;
2209 DRM_ERROR("Kicking stuck semaphore on %s\n",
2211 i915_handle_error(dev
, false);
2212 I915_WRITE_CTL(ring
, tmp
);
2213 return HANGCHECK_KICK
;
2215 return HANGCHECK_WAIT
;
2219 return HANGCHECK_HUNG
;
2223 * This is called when the chip hasn't reported back with completed
2224 * batchbuffers in a long time. We keep track per ring seqno progress and
2225 * if there are no progress, hangcheck score for that ring is increased.
2226 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2227 * we kick the ring. If we see no progress on three subsequent calls
2228 * we assume chip is wedged and try to fix it by resetting the chip.
2230 static void i915_hangcheck_elapsed(unsigned long data
)
2232 struct drm_device
*dev
= (struct drm_device
*)data
;
2233 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2234 struct intel_ring_buffer
*ring
;
2236 int busy_count
= 0, rings_hung
= 0;
2237 bool stuck
[I915_NUM_RINGS
] = { 0 };
2243 if (!i915_enable_hangcheck
)
2246 for_each_ring(ring
, dev_priv
, i
) {
2250 semaphore_clear_deadlocks(dev_priv
);
2252 seqno
= ring
->get_seqno(ring
, false);
2253 acthd
= intel_ring_get_active_head(ring
);
2255 if (ring
->hangcheck
.seqno
== seqno
) {
2256 if (ring_idle(ring
, seqno
)) {
2257 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2259 if (waitqueue_active(&ring
->irq_queue
)) {
2260 /* Issue a wake-up to catch stuck h/w. */
2261 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2262 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2263 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2266 DRM_INFO("Fake missed irq on %s\n",
2268 wake_up_all(&ring
->irq_queue
);
2270 /* Safeguard against driver failure */
2271 ring
->hangcheck
.score
+= BUSY
;
2275 /* We always increment the hangcheck score
2276 * if the ring is busy and still processing
2277 * the same request, so that no single request
2278 * can run indefinitely (such as a chain of
2279 * batches). The only time we do not increment
2280 * the hangcheck score on this ring, if this
2281 * ring is in a legitimate wait for another
2282 * ring. In that case the waiting ring is a
2283 * victim and we want to be sure we catch the
2284 * right culprit. Then every time we do kick
2285 * the ring, add a small increment to the
2286 * score so that we can catch a batch that is
2287 * being repeatedly kicked and so responsible
2288 * for stalling the machine.
2290 ring
->hangcheck
.action
= ring_stuck(ring
,
2293 switch (ring
->hangcheck
.action
) {
2294 case HANGCHECK_IDLE
:
2295 case HANGCHECK_WAIT
:
2297 case HANGCHECK_ACTIVE
:
2298 ring
->hangcheck
.score
+= BUSY
;
2300 case HANGCHECK_KICK
:
2301 ring
->hangcheck
.score
+= KICK
;
2303 case HANGCHECK_HUNG
:
2304 ring
->hangcheck
.score
+= HUNG
;
2310 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2312 /* Gradually reduce the count so that we catch DoS
2313 * attempts across multiple batches.
2315 if (ring
->hangcheck
.score
> 0)
2316 ring
->hangcheck
.score
--;
2319 ring
->hangcheck
.seqno
= seqno
;
2320 ring
->hangcheck
.acthd
= acthd
;
2324 for_each_ring(ring
, dev_priv
, i
) {
2325 if (ring
->hangcheck
.score
> FIRE
) {
2326 DRM_INFO("%s on %s\n",
2327 stuck
[i
] ? "stuck" : "no progress",
2334 return i915_handle_error(dev
, true);
2337 /* Reset timer case chip hangs without another request
2339 i915_queue_hangcheck(dev
);
2342 void i915_queue_hangcheck(struct drm_device
*dev
)
2344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2345 if (!i915_enable_hangcheck
)
2348 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2349 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2352 static void ibx_irq_preinstall(struct drm_device
*dev
)
2354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2356 if (HAS_PCH_NOP(dev
))
2359 /* south display irq */
2360 I915_WRITE(SDEIMR
, 0xffffffff);
2362 * SDEIER is also touched by the interrupt handler to work around missed
2363 * PCH interrupts. Hence we can't update it after the interrupt handler
2364 * is enabled - instead we unconditionally enable all PCH interrupt
2365 * sources here, but then only unmask them as needed with SDEIMR.
2367 I915_WRITE(SDEIER
, 0xffffffff);
2368 POSTING_READ(SDEIER
);
2371 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2376 I915_WRITE(GTIMR
, 0xffffffff);
2377 I915_WRITE(GTIER
, 0x0);
2378 POSTING_READ(GTIER
);
2380 if (INTEL_INFO(dev
)->gen
>= 6) {
2382 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2383 I915_WRITE(GEN6_PMIER
, 0x0);
2384 POSTING_READ(GEN6_PMIER
);
2390 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2392 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2394 atomic_set(&dev_priv
->irq_received
, 0);
2396 I915_WRITE(HWSTAM
, 0xeffe);
2398 I915_WRITE(DEIMR
, 0xffffffff);
2399 I915_WRITE(DEIER
, 0x0);
2400 POSTING_READ(DEIER
);
2402 gen5_gt_irq_preinstall(dev
);
2404 ibx_irq_preinstall(dev
);
2407 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2409 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2412 atomic_set(&dev_priv
->irq_received
, 0);
2415 I915_WRITE(VLV_IMR
, 0);
2416 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2417 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2418 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2421 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2422 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2424 gen5_gt_irq_preinstall(dev
);
2426 I915_WRITE(DPINVGTT
, 0xff);
2428 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2429 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2431 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2432 I915_WRITE(VLV_IIR
, 0xffffffff);
2433 I915_WRITE(VLV_IMR
, 0xffffffff);
2434 I915_WRITE(VLV_IER
, 0x0);
2435 POSTING_READ(VLV_IER
);
2438 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2440 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2441 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2442 struct intel_encoder
*intel_encoder
;
2443 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2445 if (HAS_PCH_IBX(dev
)) {
2446 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2447 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2448 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2449 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2451 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2452 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2453 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2454 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2457 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2460 * Enable digital hotplug on the PCH, and configure the DP short pulse
2461 * duration to 2ms (which is the minimum in the Display Port spec)
2463 * This register is the same on all known PCH chips.
2465 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2466 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2467 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2468 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2469 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2470 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2473 static void ibx_irq_postinstall(struct drm_device
*dev
)
2475 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2478 if (HAS_PCH_NOP(dev
))
2481 if (HAS_PCH_IBX(dev
)) {
2482 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2483 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2485 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2487 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2490 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2491 I915_WRITE(SDEIMR
, ~mask
);
2494 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2497 u32 pm_irqs
, gt_irqs
;
2499 pm_irqs
= gt_irqs
= 0;
2501 dev_priv
->gt_irq_mask
= ~0;
2502 if (HAS_L3_DPF(dev
)) {
2503 /* L3 parity interrupt is always unmasked. */
2504 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2505 gt_irqs
|= GT_PARITY_ERROR(dev
);
2508 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2510 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2511 ILK_BSD_USER_INTERRUPT
;
2513 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2516 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2517 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2518 I915_WRITE(GTIER
, gt_irqs
);
2519 POSTING_READ(GTIER
);
2521 if (INTEL_INFO(dev
)->gen
>= 6) {
2522 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2525 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2527 dev_priv
->pm_irq_mask
= 0xffffffff;
2528 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2529 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2530 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2531 POSTING_READ(GEN6_PMIER
);
2535 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2537 unsigned long irqflags
;
2538 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2539 u32 display_mask
, extra_mask
;
2541 if (INTEL_INFO(dev
)->gen
>= 7) {
2542 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2543 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2544 DE_PLANEB_FLIP_DONE_IVB
|
2545 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2547 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2548 DE_PIPEA_VBLANK_IVB
);
2550 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2552 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2553 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2555 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
2556 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
2558 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2561 dev_priv
->irq_mask
= ~display_mask
;
2563 /* should always can generate irq */
2564 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2565 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2566 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2567 POSTING_READ(DEIER
);
2569 gen5_gt_irq_postinstall(dev
);
2571 ibx_irq_postinstall(dev
);
2573 if (IS_IRONLAKE_M(dev
)) {
2574 /* Enable PCU event interrupts
2576 * spinlocking not required here for correctness since interrupt
2577 * setup is guaranteed to run in single-threaded context. But we
2578 * need it to make the assert_spin_locked happy. */
2579 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2580 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2581 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2587 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2589 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2591 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
|
2592 PIPE_CRC_DONE_ENABLE
;
2593 unsigned long irqflags
;
2595 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2596 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2597 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2598 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2599 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2602 *Leave vblank interrupts masked initially. enable/disable will
2603 * toggle them based on usage.
2605 dev_priv
->irq_mask
= (~enable_mask
) |
2606 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2607 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2609 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2610 POSTING_READ(PORT_HOTPLUG_EN
);
2612 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2613 I915_WRITE(VLV_IER
, enable_mask
);
2614 I915_WRITE(VLV_IIR
, 0xffffffff);
2615 I915_WRITE(PIPESTAT(0), 0xffff);
2616 I915_WRITE(PIPESTAT(1), 0xffff);
2617 POSTING_READ(VLV_IER
);
2619 /* Interrupt setup is already guaranteed to be single-threaded, this is
2620 * just to make the assert_spin_locked check happy. */
2621 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2622 i915_enable_pipestat(dev_priv
, PIPE_A
, pipestat_enable
);
2623 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_EVENT_ENABLE
);
2624 i915_enable_pipestat(dev_priv
, PIPE_B
, pipestat_enable
);
2625 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2627 I915_WRITE(VLV_IIR
, 0xffffffff);
2628 I915_WRITE(VLV_IIR
, 0xffffffff);
2630 gen5_gt_irq_postinstall(dev
);
2632 /* ack & enable invalid PTE error interrupts */
2633 #if 0 /* FIXME: add support to irq handler for checking these bits */
2634 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2635 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2638 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2643 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2645 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2651 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2654 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2656 I915_WRITE(HWSTAM
, 0xffffffff);
2657 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2658 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2660 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2661 I915_WRITE(VLV_IIR
, 0xffffffff);
2662 I915_WRITE(VLV_IMR
, 0xffffffff);
2663 I915_WRITE(VLV_IER
, 0x0);
2664 POSTING_READ(VLV_IER
);
2667 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2669 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2674 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2676 I915_WRITE(HWSTAM
, 0xffffffff);
2678 I915_WRITE(DEIMR
, 0xffffffff);
2679 I915_WRITE(DEIER
, 0x0);
2680 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2682 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2684 I915_WRITE(GTIMR
, 0xffffffff);
2685 I915_WRITE(GTIER
, 0x0);
2686 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2688 if (HAS_PCH_NOP(dev
))
2691 I915_WRITE(SDEIMR
, 0xffffffff);
2692 I915_WRITE(SDEIER
, 0x0);
2693 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2694 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2695 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2698 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2700 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2703 atomic_set(&dev_priv
->irq_received
, 0);
2706 I915_WRITE(PIPESTAT(pipe
), 0);
2707 I915_WRITE16(IMR
, 0xffff);
2708 I915_WRITE16(IER
, 0x0);
2709 POSTING_READ16(IER
);
2712 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2714 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2715 unsigned long irqflags
;
2718 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2720 /* Unmask the interrupts that we always want on. */
2721 dev_priv
->irq_mask
=
2722 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2723 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2724 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2725 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2726 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2727 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2730 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2731 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2732 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2733 I915_USER_INTERRUPT
);
2734 POSTING_READ16(IER
);
2736 /* Interrupt setup is already guaranteed to be single-threaded, this is
2737 * just to make the assert_spin_locked check happy. */
2738 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2739 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
2740 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
2741 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2747 * Returns true when a page flip has completed.
2749 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2752 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2753 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2755 if (!drm_handle_vblank(dev
, pipe
))
2758 if ((iir
& flip_pending
) == 0)
2761 intel_prepare_page_flip(dev
, pipe
);
2763 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2764 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2765 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2766 * the flip is completed (no longer pending). Since this doesn't raise
2767 * an interrupt per se, we watch for the change at vblank.
2769 if (I915_READ16(ISR
) & flip_pending
)
2772 intel_finish_page_flip(dev
, pipe
);
2777 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2779 struct drm_device
*dev
= (struct drm_device
*) arg
;
2780 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2783 unsigned long irqflags
;
2786 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2787 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2789 atomic_inc(&dev_priv
->irq_received
);
2791 iir
= I915_READ16(IIR
);
2795 while (iir
& ~flip_mask
) {
2796 /* Can't rely on pipestat interrupt bit in iir as it might
2797 * have been cleared after the pipestat interrupt was received.
2798 * It doesn't set the bit in iir again, but it still produces
2799 * interrupts (for non-MSI).
2801 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2802 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2803 i915_handle_error(dev
, false);
2805 for_each_pipe(pipe
) {
2806 int reg
= PIPESTAT(pipe
);
2807 pipe_stats
[pipe
] = I915_READ(reg
);
2810 * Clear the PIPE*STAT regs before the IIR
2812 if (pipe_stats
[pipe
] & 0x8000ffff) {
2813 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2814 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2816 I915_WRITE(reg
, pipe_stats
[pipe
]);
2819 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2821 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2822 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2824 i915_update_dri1_breadcrumb(dev
);
2826 if (iir
& I915_USER_INTERRUPT
)
2827 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2829 for_each_pipe(pipe
) {
2830 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2831 i8xx_handle_vblank(dev
, pipe
, iir
))
2832 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2834 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
2835 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2844 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2846 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2849 for_each_pipe(pipe
) {
2850 /* Clear enable bits; then clear status bits */
2851 I915_WRITE(PIPESTAT(pipe
), 0);
2852 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2854 I915_WRITE16(IMR
, 0xffff);
2855 I915_WRITE16(IER
, 0x0);
2856 I915_WRITE16(IIR
, I915_READ16(IIR
));
2859 static void i915_irq_preinstall(struct drm_device
* dev
)
2861 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2864 atomic_set(&dev_priv
->irq_received
, 0);
2866 if (I915_HAS_HOTPLUG(dev
)) {
2867 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2868 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2871 I915_WRITE16(HWSTAM
, 0xeffe);
2873 I915_WRITE(PIPESTAT(pipe
), 0);
2874 I915_WRITE(IMR
, 0xffffffff);
2875 I915_WRITE(IER
, 0x0);
2879 static int i915_irq_postinstall(struct drm_device
*dev
)
2881 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2883 unsigned long irqflags
;
2885 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2887 /* Unmask the interrupts that we always want on. */
2888 dev_priv
->irq_mask
=
2889 ~(I915_ASLE_INTERRUPT
|
2890 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2891 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2892 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2893 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2894 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2897 I915_ASLE_INTERRUPT
|
2898 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2899 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2900 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2901 I915_USER_INTERRUPT
;
2903 if (I915_HAS_HOTPLUG(dev
)) {
2904 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2905 POSTING_READ(PORT_HOTPLUG_EN
);
2907 /* Enable in IER... */
2908 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2909 /* and unmask in IMR */
2910 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2913 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2914 I915_WRITE(IER
, enable_mask
);
2917 i915_enable_asle_pipestat(dev
);
2919 /* Interrupt setup is already guaranteed to be single-threaded, this is
2920 * just to make the assert_spin_locked check happy. */
2921 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2922 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
2923 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
2924 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2930 * Returns true when a page flip has completed.
2932 static bool i915_handle_vblank(struct drm_device
*dev
,
2933 int plane
, int pipe
, u32 iir
)
2935 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2936 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2938 if (!drm_handle_vblank(dev
, pipe
))
2941 if ((iir
& flip_pending
) == 0)
2944 intel_prepare_page_flip(dev
, plane
);
2946 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2947 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2948 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2949 * the flip is completed (no longer pending). Since this doesn't raise
2950 * an interrupt per se, we watch for the change at vblank.
2952 if (I915_READ(ISR
) & flip_pending
)
2955 intel_finish_page_flip(dev
, pipe
);
2960 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2962 struct drm_device
*dev
= (struct drm_device
*) arg
;
2963 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2964 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2965 unsigned long irqflags
;
2967 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2968 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2969 int pipe
, ret
= IRQ_NONE
;
2971 atomic_inc(&dev_priv
->irq_received
);
2973 iir
= I915_READ(IIR
);
2975 bool irq_received
= (iir
& ~flip_mask
) != 0;
2976 bool blc_event
= false;
2978 /* Can't rely on pipestat interrupt bit in iir as it might
2979 * have been cleared after the pipestat interrupt was received.
2980 * It doesn't set the bit in iir again, but it still produces
2981 * interrupts (for non-MSI).
2983 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2984 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2985 i915_handle_error(dev
, false);
2987 for_each_pipe(pipe
) {
2988 int reg
= PIPESTAT(pipe
);
2989 pipe_stats
[pipe
] = I915_READ(reg
);
2991 /* Clear the PIPE*STAT regs before the IIR */
2992 if (pipe_stats
[pipe
] & 0x8000ffff) {
2993 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2994 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2996 I915_WRITE(reg
, pipe_stats
[pipe
]);
2997 irq_received
= true;
3000 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3005 /* Consume port. Then clear IIR or we'll miss events */
3006 if ((I915_HAS_HOTPLUG(dev
)) &&
3007 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3008 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3009 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3011 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3014 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
3016 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3017 POSTING_READ(PORT_HOTPLUG_STAT
);
3020 I915_WRITE(IIR
, iir
& ~flip_mask
);
3021 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3023 if (iir
& I915_USER_INTERRUPT
)
3024 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3026 for_each_pipe(pipe
) {
3031 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3032 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3033 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3035 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3038 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3039 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3042 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3043 intel_opregion_asle_intr(dev
);
3045 /* With MSI, interrupts are only generated when iir
3046 * transitions from zero to nonzero. If another bit got
3047 * set while we were handling the existing iir bits, then
3048 * we would never get another interrupt.
3050 * This is fine on non-MSI as well, as if we hit this path
3051 * we avoid exiting the interrupt handler only to generate
3054 * Note that for MSI this could cause a stray interrupt report
3055 * if an interrupt landed in the time between writing IIR and
3056 * the posting read. This should be rare enough to never
3057 * trigger the 99% of 100,000 interrupts test for disabling
3062 } while (iir
& ~flip_mask
);
3064 i915_update_dri1_breadcrumb(dev
);
3069 static void i915_irq_uninstall(struct drm_device
* dev
)
3071 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3074 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3076 if (I915_HAS_HOTPLUG(dev
)) {
3077 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3078 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3081 I915_WRITE16(HWSTAM
, 0xffff);
3082 for_each_pipe(pipe
) {
3083 /* Clear enable bits; then clear status bits */
3084 I915_WRITE(PIPESTAT(pipe
), 0);
3085 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3087 I915_WRITE(IMR
, 0xffffffff);
3088 I915_WRITE(IER
, 0x0);
3090 I915_WRITE(IIR
, I915_READ(IIR
));
3093 static void i965_irq_preinstall(struct drm_device
* dev
)
3095 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3098 atomic_set(&dev_priv
->irq_received
, 0);
3100 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3101 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3103 I915_WRITE(HWSTAM
, 0xeffe);
3105 I915_WRITE(PIPESTAT(pipe
), 0);
3106 I915_WRITE(IMR
, 0xffffffff);
3107 I915_WRITE(IER
, 0x0);
3111 static int i965_irq_postinstall(struct drm_device
*dev
)
3113 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3116 unsigned long irqflags
;
3118 /* Unmask the interrupts that we always want on. */
3119 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3120 I915_DISPLAY_PORT_INTERRUPT
|
3121 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3122 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3123 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3124 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3125 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3127 enable_mask
= ~dev_priv
->irq_mask
;
3128 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3129 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3130 enable_mask
|= I915_USER_INTERRUPT
;
3133 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3135 /* Interrupt setup is already guaranteed to be single-threaded, this is
3136 * just to make the assert_spin_locked check happy. */
3137 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3138 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_EVENT_ENABLE
);
3139 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
3140 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
3141 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3144 * Enable some error detection, note the instruction error mask
3145 * bit is reserved, so we leave it masked.
3148 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3149 GM45_ERROR_MEM_PRIV
|
3150 GM45_ERROR_CP_PRIV
|
3151 I915_ERROR_MEMORY_REFRESH
);
3153 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3154 I915_ERROR_MEMORY_REFRESH
);
3156 I915_WRITE(EMR
, error_mask
);
3158 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3159 I915_WRITE(IER
, enable_mask
);
3162 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3163 POSTING_READ(PORT_HOTPLUG_EN
);
3165 i915_enable_asle_pipestat(dev
);
3170 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3172 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3173 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3174 struct intel_encoder
*intel_encoder
;
3177 assert_spin_locked(&dev_priv
->irq_lock
);
3179 if (I915_HAS_HOTPLUG(dev
)) {
3180 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3181 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3182 /* Note HDMI and DP share hotplug bits */
3183 /* enable bits are the same for all generations */
3184 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3185 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3186 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3187 /* Programming the CRT detection parameters tends
3188 to generate a spurious hotplug event about three
3189 seconds later. So just do it once.
3192 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3193 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3194 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3196 /* Ignore TV since it's buggy */
3197 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3201 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3203 struct drm_device
*dev
= (struct drm_device
*) arg
;
3204 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3206 u32 pipe_stats
[I915_MAX_PIPES
];
3207 unsigned long irqflags
;
3209 int ret
= IRQ_NONE
, pipe
;
3211 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3212 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3214 atomic_inc(&dev_priv
->irq_received
);
3216 iir
= I915_READ(IIR
);
3219 bool blc_event
= false;
3221 irq_received
= (iir
& ~flip_mask
) != 0;
3223 /* Can't rely on pipestat interrupt bit in iir as it might
3224 * have been cleared after the pipestat interrupt was received.
3225 * It doesn't set the bit in iir again, but it still produces
3226 * interrupts (for non-MSI).
3228 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3229 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3230 i915_handle_error(dev
, false);
3232 for_each_pipe(pipe
) {
3233 int reg
= PIPESTAT(pipe
);
3234 pipe_stats
[pipe
] = I915_READ(reg
);
3237 * Clear the PIPE*STAT regs before the IIR
3239 if (pipe_stats
[pipe
] & 0x8000ffff) {
3240 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3241 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3243 I915_WRITE(reg
, pipe_stats
[pipe
]);
3247 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3254 /* Consume port. Then clear IIR or we'll miss events */
3255 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3256 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3257 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3258 HOTPLUG_INT_STATUS_G4X
:
3259 HOTPLUG_INT_STATUS_I915
);
3261 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3264 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3265 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3267 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3268 I915_READ(PORT_HOTPLUG_STAT
);
3271 I915_WRITE(IIR
, iir
& ~flip_mask
);
3272 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3274 if (iir
& I915_USER_INTERRUPT
)
3275 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3276 if (iir
& I915_BSD_USER_INTERRUPT
)
3277 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3279 for_each_pipe(pipe
) {
3280 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3281 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3282 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3284 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3287 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3288 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3292 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3293 intel_opregion_asle_intr(dev
);
3295 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3296 gmbus_irq_handler(dev
);
3298 /* With MSI, interrupts are only generated when iir
3299 * transitions from zero to nonzero. If another bit got
3300 * set while we were handling the existing iir bits, then
3301 * we would never get another interrupt.
3303 * This is fine on non-MSI as well, as if we hit this path
3304 * we avoid exiting the interrupt handler only to generate
3307 * Note that for MSI this could cause a stray interrupt report
3308 * if an interrupt landed in the time between writing IIR and
3309 * the posting read. This should be rare enough to never
3310 * trigger the 99% of 100,000 interrupts test for disabling
3316 i915_update_dri1_breadcrumb(dev
);
3321 static void i965_irq_uninstall(struct drm_device
* dev
)
3323 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3329 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3331 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3332 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3334 I915_WRITE(HWSTAM
, 0xffffffff);
3336 I915_WRITE(PIPESTAT(pipe
), 0);
3337 I915_WRITE(IMR
, 0xffffffff);
3338 I915_WRITE(IER
, 0x0);
3341 I915_WRITE(PIPESTAT(pipe
),
3342 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3343 I915_WRITE(IIR
, I915_READ(IIR
));
3346 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3348 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3349 struct drm_device
*dev
= dev_priv
->dev
;
3350 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3351 unsigned long irqflags
;
3354 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3355 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3356 struct drm_connector
*connector
;
3358 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3361 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3363 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3364 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3366 if (intel_connector
->encoder
->hpd_pin
== i
) {
3367 if (connector
->polled
!= intel_connector
->polled
)
3368 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3369 drm_get_connector_name(connector
));
3370 connector
->polled
= intel_connector
->polled
;
3371 if (!connector
->polled
)
3372 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3376 if (dev_priv
->display
.hpd_irq_setup
)
3377 dev_priv
->display
.hpd_irq_setup(dev
);
3378 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3381 void intel_irq_init(struct drm_device
*dev
)
3383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3385 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3386 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3387 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3388 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3390 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3391 i915_hangcheck_elapsed
,
3392 (unsigned long) dev
);
3393 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3394 (unsigned long) dev_priv
);
3396 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3399 dev
->max_vblank_count
= 0;
3400 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
3401 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3402 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3403 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3405 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3406 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3409 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3410 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3411 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3414 if (IS_VALLEYVIEW(dev
)) {
3415 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3416 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3417 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3418 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3419 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3420 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3421 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3422 } else if (HAS_PCH_SPLIT(dev
)) {
3423 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3424 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3425 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3426 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3427 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3428 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3429 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3431 if (INTEL_INFO(dev
)->gen
== 2) {
3432 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3433 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3434 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3435 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3436 } else if (INTEL_INFO(dev
)->gen
== 3) {
3437 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3438 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3439 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3440 dev
->driver
->irq_handler
= i915_irq_handler
;
3441 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3443 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3444 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3445 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3446 dev
->driver
->irq_handler
= i965_irq_handler
;
3447 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3449 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3450 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3454 void intel_hpd_init(struct drm_device
*dev
)
3456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3457 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3458 struct drm_connector
*connector
;
3459 unsigned long irqflags
;
3462 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3463 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3464 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3466 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3467 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3468 connector
->polled
= intel_connector
->polled
;
3469 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3470 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3473 /* Interrupt setup is already guaranteed to be single-threaded, this is
3474 * just to make the assert_spin_locked checks happy. */
3475 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3476 if (dev_priv
->display
.hpd_irq_setup
)
3477 dev_priv
->display
.hpd_irq_setup(dev
);
3478 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3481 /* Disable interrupts so we can allow Package C8+. */
3482 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3485 unsigned long irqflags
;
3487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3489 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3490 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3491 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3492 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3493 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3495 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3496 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3497 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3498 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3500 dev_priv
->pc8
.irqs_disabled
= true;
3502 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3505 /* Restore interrupts so we can recover from Package C8+. */
3506 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3509 unsigned long irqflags
;
3510 uint32_t val
, expected
;
3512 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3514 val
= I915_READ(DEIMR
);
3515 expected
= ~DE_PCH_EVENT_IVB
;
3516 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3518 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3519 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3520 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3523 val
= I915_READ(GTIMR
);
3524 expected
= 0xffffffff;
3525 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3527 val
= I915_READ(GEN6_PMIMR
);
3528 expected
= 0xffffffff;
3529 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3532 dev_priv
->pc8
.irqs_disabled
= false;
3534 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3535 ibx_enable_display_interrupt(dev_priv
,
3536 ~dev_priv
->pc8
.regsave
.sdeimr
&
3537 ~SDE_HOTPLUG_MASK_CPT
);
3538 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3539 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3540 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3542 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);