1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
56 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
57 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
58 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
59 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
60 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
61 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
64 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
73 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
83 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
84 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
85 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
86 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
87 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
88 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
92 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
93 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
94 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
97 /* IIR can theoretically queue up two events. Be paranoid. */
98 #define GEN8_IRQ_RESET_NDX(type, which) do { \
99 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
100 POSTING_READ(GEN8_##type##_IMR(which)); \
101 I915_WRITE(GEN8_##type##_IER(which), 0); \
102 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 POSTING_READ(GEN8_##type##_IIR(which)); \
104 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
105 POSTING_READ(GEN8_##type##_IIR(which)); \
108 #define GEN5_IRQ_RESET(type) do { \
109 I915_WRITE(type##IMR, 0xffffffff); \
110 POSTING_READ(type##IMR); \
111 I915_WRITE(type##IER, 0); \
112 I915_WRITE(type##IIR, 0xffffffff); \
113 POSTING_READ(type##IIR); \
114 I915_WRITE(type##IIR, 0xffffffff); \
115 POSTING_READ(type##IIR); \
119 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
121 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
122 u32 val = I915_READ(reg); \
124 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
126 I915_WRITE((reg), 0xffffffff); \
128 I915_WRITE((reg), 0xffffffff); \
133 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
134 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
135 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
136 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
137 POSTING_READ(GEN8_##type##_IMR(which)); \
140 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
141 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
142 I915_WRITE(type##IER, (ier_val)); \
143 I915_WRITE(type##IMR, (imr_val)); \
144 POSTING_READ(type##IMR); \
147 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
149 /* For display hotplug interrupt */
151 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
153 assert_spin_locked(&dev_priv
->irq_lock
);
155 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
158 if ((dev_priv
->irq_mask
& mask
) != 0) {
159 dev_priv
->irq_mask
&= ~mask
;
160 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
166 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
168 assert_spin_locked(&dev_priv
->irq_lock
);
170 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
173 if ((dev_priv
->irq_mask
& mask
) != mask
) {
174 dev_priv
->irq_mask
|= mask
;
175 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
181 * ilk_update_gt_irq - update GTIMR
182 * @dev_priv: driver private
183 * @interrupt_mask: mask of interrupt bits to update
184 * @enabled_irq_mask: mask of interrupt bits to enable
186 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
187 uint32_t interrupt_mask
,
188 uint32_t enabled_irq_mask
)
190 assert_spin_locked(&dev_priv
->irq_lock
);
192 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
194 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
197 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
198 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
199 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
203 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
205 ilk_update_gt_irq(dev_priv
, mask
, mask
);
208 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
210 ilk_update_gt_irq(dev_priv
, mask
, 0);
213 static u32
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
215 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
218 static u32
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
220 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
223 static u32
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
225 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
229 * snb_update_pm_irq - update GEN6_PMIMR
230 * @dev_priv: driver private
231 * @interrupt_mask: mask of interrupt bits to update
232 * @enabled_irq_mask: mask of interrupt bits to enable
234 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
235 uint32_t interrupt_mask
,
236 uint32_t enabled_irq_mask
)
240 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
242 assert_spin_locked(&dev_priv
->irq_lock
);
244 new_val
= dev_priv
->pm_irq_mask
;
245 new_val
&= ~interrupt_mask
;
246 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
248 if (new_val
!= dev_priv
->pm_irq_mask
) {
249 dev_priv
->pm_irq_mask
= new_val
;
250 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
251 POSTING_READ(gen6_pm_imr(dev_priv
));
255 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
257 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
260 snb_update_pm_irq(dev_priv
, mask
, mask
);
263 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
266 snb_update_pm_irq(dev_priv
, mask
, 0);
269 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
271 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
274 __gen6_disable_pm_irq(dev_priv
, mask
);
277 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
280 uint32_t reg
= gen6_pm_iir(dev_priv
);
282 spin_lock_irq(&dev_priv
->irq_lock
);
283 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
284 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
286 dev_priv
->rps
.pm_iir
= 0;
287 spin_unlock_irq(&dev_priv
->irq_lock
);
290 void gen6_enable_rps_interrupts(struct drm_device
*dev
)
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
294 spin_lock_irq(&dev_priv
->irq_lock
);
296 WARN_ON(dev_priv
->rps
.pm_iir
);
297 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
298 dev_priv
->rps
.interrupts_enabled
= true;
299 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
300 dev_priv
->pm_rps_events
);
301 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
303 spin_unlock_irq(&dev_priv
->irq_lock
);
306 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
309 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
310 * if GEN6_PM_UP_EI_EXPIRED is masked.
312 * TODO: verify if this can be reproduced on VLV,CHV.
314 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
315 mask
&= ~GEN6_PM_RP_UP_EI_EXPIRED
;
317 if (INTEL_INFO(dev_priv
)->gen
>= 8)
318 mask
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
323 void gen6_disable_rps_interrupts(struct drm_device
*dev
)
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 spin_lock_irq(&dev_priv
->irq_lock
);
328 dev_priv
->rps
.interrupts_enabled
= false;
329 spin_unlock_irq(&dev_priv
->irq_lock
);
331 cancel_work_sync(&dev_priv
->rps
.work
);
333 spin_lock_irq(&dev_priv
->irq_lock
);
335 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
337 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
338 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
339 ~dev_priv
->pm_rps_events
);
341 spin_unlock_irq(&dev_priv
->irq_lock
);
343 synchronize_irq(dev
->irq
);
347 * ibx_display_interrupt_update - update SDEIMR
348 * @dev_priv: driver private
349 * @interrupt_mask: mask of interrupt bits to update
350 * @enabled_irq_mask: mask of interrupt bits to enable
352 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
353 uint32_t interrupt_mask
,
354 uint32_t enabled_irq_mask
)
356 uint32_t sdeimr
= I915_READ(SDEIMR
);
357 sdeimr
&= ~interrupt_mask
;
358 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
360 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
362 assert_spin_locked(&dev_priv
->irq_lock
);
364 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
367 I915_WRITE(SDEIMR
, sdeimr
);
368 POSTING_READ(SDEIMR
);
372 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
373 u32 enable_mask
, u32 status_mask
)
375 u32 reg
= PIPESTAT(pipe
);
376 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
378 assert_spin_locked(&dev_priv
->irq_lock
);
379 WARN_ON(!intel_irqs_enabled(dev_priv
));
381 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
382 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
383 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
384 pipe_name(pipe
), enable_mask
, status_mask
))
387 if ((pipestat
& enable_mask
) == enable_mask
)
390 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
392 /* Enable the interrupt, clear any pending status */
393 pipestat
|= enable_mask
| status_mask
;
394 I915_WRITE(reg
, pipestat
);
399 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
400 u32 enable_mask
, u32 status_mask
)
402 u32 reg
= PIPESTAT(pipe
);
403 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
405 assert_spin_locked(&dev_priv
->irq_lock
);
406 WARN_ON(!intel_irqs_enabled(dev_priv
));
408 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
409 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
410 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
411 pipe_name(pipe
), enable_mask
, status_mask
))
414 if ((pipestat
& enable_mask
) == 0)
417 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
419 pipestat
&= ~enable_mask
;
420 I915_WRITE(reg
, pipestat
);
424 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
426 u32 enable_mask
= status_mask
<< 16;
429 * On pipe A we don't support the PSR interrupt yet,
430 * on pipe B and C the same bit MBZ.
432 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
435 * On pipe B and C we don't support the PSR interrupt yet, on pipe
436 * A the same bit is for perf counters which we don't use either.
438 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
441 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
442 SPRITE0_FLIP_DONE_INT_EN_VLV
|
443 SPRITE1_FLIP_DONE_INT_EN_VLV
);
444 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
445 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
446 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
447 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
453 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
458 if (IS_VALLEYVIEW(dev_priv
->dev
))
459 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
462 enable_mask
= status_mask
<< 16;
463 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
467 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
472 if (IS_VALLEYVIEW(dev_priv
->dev
))
473 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
476 enable_mask
= status_mask
<< 16;
477 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
481 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
483 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
487 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
490 spin_lock_irq(&dev_priv
->irq_lock
);
492 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
493 if (INTEL_INFO(dev
)->gen
>= 4)
494 i915_enable_pipestat(dev_priv
, PIPE_A
,
495 PIPE_LEGACY_BLC_EVENT_STATUS
);
497 spin_unlock_irq(&dev_priv
->irq_lock
);
501 * This timing diagram depicts the video signal in and
502 * around the vertical blanking period.
504 * Assumptions about the fictitious mode used in this example:
506 * vsync_start = vblank_start + 1
507 * vsync_end = vblank_start + 2
508 * vtotal = vblank_start + 3
511 * latch double buffered registers
512 * increment frame counter (ctg+)
513 * generate start of vblank interrupt (gen4+)
516 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
517 * | may be shifted forward 1-3 extra lines via PIPECONF
519 * | | start of vsync:
520 * | | generate vsync interrupt
522 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
523 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
524 * ----va---> <-----------------vb--------------------> <--------va-------------
525 * | | <----vs-----> |
526 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
527 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
528 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
530 * last visible pixel first visible pixel
531 * | increment frame counter (gen3/4)
532 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
534 * x = horizontal active
535 * _ = horizontal blanking
536 * hs = horizontal sync
537 * va = vertical active
538 * vb = vertical blanking
540 * vbs = vblank_start (number)
543 * - most events happen at the start of horizontal sync
544 * - frame start happens at the start of horizontal blank, 1-4 lines
545 * (depending on PIPECONF settings) after the start of vblank
546 * - gen3/4 pixel and frame counter are synchronized with the start
547 * of horizontal active on the first line of vertical active
550 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
552 /* Gen2 doesn't have a hardware frame counter */
556 /* Called from drm generic code, passed a 'crtc', which
557 * we use as a pipe index
559 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
562 unsigned long high_frame
;
563 unsigned long low_frame
;
564 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
565 struct intel_crtc
*intel_crtc
=
566 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
567 const struct drm_display_mode
*mode
=
568 &intel_crtc
->config
->base
.adjusted_mode
;
570 htotal
= mode
->crtc_htotal
;
571 hsync_start
= mode
->crtc_hsync_start
;
572 vbl_start
= mode
->crtc_vblank_start
;
573 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
574 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
576 /* Convert to pixel count */
579 /* Start of vblank event occurs at start of hsync */
580 vbl_start
-= htotal
- hsync_start
;
582 high_frame
= PIPEFRAME(pipe
);
583 low_frame
= PIPEFRAMEPIXEL(pipe
);
586 * High & low register fields aren't synchronized, so make sure
587 * we get a low value that's stable across two reads of the high
591 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
592 low
= I915_READ(low_frame
);
593 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
594 } while (high1
!= high2
);
596 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
597 pixel
= low
& PIPE_PIXEL_MASK
;
598 low
>>= PIPE_FRAME_LOW_SHIFT
;
601 * The frame counter increments at beginning of active.
602 * Cook up a vblank counter by also checking the pixel
603 * counter against vblank start.
605 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
608 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
611 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
613 return I915_READ(reg
);
616 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
617 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
619 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
621 struct drm_device
*dev
= crtc
->base
.dev
;
622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
623 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
624 enum pipe pipe
= crtc
->pipe
;
625 int position
, vtotal
;
627 vtotal
= mode
->crtc_vtotal
;
628 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
632 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
634 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
637 * See update_scanline_offset() for the details on the
638 * scanline_offset adjustment.
640 return (position
+ crtc
->scanline_offset
) % vtotal
;
643 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
644 unsigned int flags
, int *vpos
, int *hpos
,
645 ktime_t
*stime
, ktime_t
*etime
)
647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
648 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
650 const struct drm_display_mode
*mode
= &intel_crtc
->config
->base
.adjusted_mode
;
652 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
655 unsigned long irqflags
;
657 if (!intel_crtc
->active
) {
658 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
659 "pipe %c\n", pipe_name(pipe
));
663 htotal
= mode
->crtc_htotal
;
664 hsync_start
= mode
->crtc_hsync_start
;
665 vtotal
= mode
->crtc_vtotal
;
666 vbl_start
= mode
->crtc_vblank_start
;
667 vbl_end
= mode
->crtc_vblank_end
;
669 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
670 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
675 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
678 * Lock uncore.lock, as we will do multiple timing critical raw
679 * register reads, potentially with preemption disabled, so the
680 * following code must not block on uncore.lock.
682 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
684 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
686 /* Get optional system timestamp before query. */
688 *stime
= ktime_get();
690 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
691 /* No obvious pixelcount register. Only query vertical
692 * scanout position from Display scan line register.
694 position
= __intel_get_crtc_scanline(intel_crtc
);
696 /* Have access to pixelcount since start of frame.
697 * We can split this into vertical and horizontal
700 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
702 /* convert to pixel counts */
708 * In interlaced modes, the pixel counter counts all pixels,
709 * so one field will have htotal more pixels. In order to avoid
710 * the reported position from jumping backwards when the pixel
711 * counter is beyond the length of the shorter field, just
712 * clamp the position the length of the shorter field. This
713 * matches how the scanline counter based position works since
714 * the scanline counter doesn't count the two half lines.
716 if (position
>= vtotal
)
717 position
= vtotal
- 1;
720 * Start of vblank interrupt is triggered at start of hsync,
721 * just prior to the first active line of vblank. However we
722 * consider lines to start at the leading edge of horizontal
723 * active. So, should we get here before we've crossed into
724 * the horizontal active of the first line in vblank, we would
725 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
726 * always add htotal-hsync_start to the current pixel position.
728 position
= (position
+ htotal
- hsync_start
) % vtotal
;
731 /* Get optional system timestamp after query. */
733 *etime
= ktime_get();
735 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
737 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
739 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
742 * While in vblank, position will be negative
743 * counting up towards 0 at vbl_end. And outside
744 * vblank, position will be positive counting
747 if (position
>= vbl_start
)
750 position
+= vtotal
- vbl_end
;
752 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
756 *vpos
= position
/ htotal
;
757 *hpos
= position
- (*vpos
* htotal
);
762 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
767 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
769 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
770 unsigned long irqflags
;
773 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
774 position
= __intel_get_crtc_scanline(crtc
);
775 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
780 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
782 struct timeval
*vblank_time
,
785 struct drm_crtc
*crtc
;
787 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
788 DRM_ERROR("Invalid crtc %d\n", pipe
);
792 /* Get drm_crtc to timestamp: */
793 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
795 DRM_ERROR("Invalid crtc %d\n", pipe
);
799 if (!crtc
->state
->enable
) {
800 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
804 /* Helper routine in DRM core does all the work: */
805 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
808 &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
);
811 static bool intel_hpd_irq_event(struct drm_device
*dev
,
812 struct drm_connector
*connector
)
814 enum drm_connector_status old_status
;
816 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
817 old_status
= connector
->status
;
819 connector
->status
= connector
->funcs
->detect(connector
, false);
820 if (old_status
== connector
->status
)
823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
826 drm_get_connector_status_name(old_status
),
827 drm_get_connector_status_name(connector
->status
));
832 static void i915_digport_work_func(struct work_struct
*work
)
834 struct drm_i915_private
*dev_priv
=
835 container_of(work
, struct drm_i915_private
, hotplug
.dig_port_work
);
836 u32 long_port_mask
, short_port_mask
;
837 struct intel_digital_port
*intel_dig_port
;
841 spin_lock_irq(&dev_priv
->irq_lock
);
842 long_port_mask
= dev_priv
->hotplug
.long_port_mask
;
843 dev_priv
->hotplug
.long_port_mask
= 0;
844 short_port_mask
= dev_priv
->hotplug
.short_port_mask
;
845 dev_priv
->hotplug
.short_port_mask
= 0;
846 spin_unlock_irq(&dev_priv
->irq_lock
);
848 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
850 bool long_hpd
= false;
851 intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
852 if (!intel_dig_port
|| !intel_dig_port
->hpd_pulse
)
855 if (long_port_mask
& (1 << i
)) {
858 } else if (short_port_mask
& (1 << i
))
864 ret
= intel_dig_port
->hpd_pulse(intel_dig_port
, long_hpd
);
865 if (ret
== IRQ_NONE
) {
866 /* fall back to old school hpd */
867 old_bits
|= (1 << intel_dig_port
->base
.hpd_pin
);
873 spin_lock_irq(&dev_priv
->irq_lock
);
874 dev_priv
->hotplug
.event_bits
|= old_bits
;
875 spin_unlock_irq(&dev_priv
->irq_lock
);
876 schedule_work(&dev_priv
->hotplug
.hotplug_work
);
881 * Handle hotplug events outside the interrupt handler proper.
883 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
885 static void i915_hotplug_work_func(struct work_struct
*work
)
887 struct drm_i915_private
*dev_priv
=
888 container_of(work
, struct drm_i915_private
, hotplug
.hotplug_work
);
889 struct drm_device
*dev
= dev_priv
->dev
;
890 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
891 struct intel_connector
*intel_connector
;
892 struct intel_encoder
*intel_encoder
;
893 struct drm_connector
*connector
;
894 bool hpd_disabled
= false;
895 bool changed
= false;
898 mutex_lock(&mode_config
->mutex
);
899 DRM_DEBUG_KMS("running encoder hotplug functions\n");
901 spin_lock_irq(&dev_priv
->irq_lock
);
903 hpd_event_bits
= dev_priv
->hotplug
.event_bits
;
904 dev_priv
->hotplug
.event_bits
= 0;
905 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
906 intel_connector
= to_intel_connector(connector
);
907 if (!intel_connector
->encoder
)
909 intel_encoder
= intel_connector
->encoder
;
910 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
911 dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
== HPD_MARK_DISABLED
&&
912 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
913 DRM_INFO("HPD interrupt storm detected on connector %s: "
914 "switching from hotplug detection to polling\n",
916 dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
= HPD_DISABLED
;
917 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
918 | DRM_CONNECTOR_POLL_DISCONNECT
;
921 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
922 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
923 connector
->name
, intel_encoder
->hpd_pin
);
926 /* if there were no outputs to poll, poll was disabled,
927 * therefore make sure it's enabled when disabling HPD on
930 drm_kms_helper_poll_enable(dev
);
931 mod_delayed_work(system_wq
, &dev_priv
->hotplug
.reenable_work
,
932 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
935 spin_unlock_irq(&dev_priv
->irq_lock
);
937 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
938 intel_connector
= to_intel_connector(connector
);
939 if (!intel_connector
->encoder
)
941 intel_encoder
= intel_connector
->encoder
;
942 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
943 if (intel_encoder
->hot_plug
)
944 intel_encoder
->hot_plug(intel_encoder
);
945 if (intel_hpd_irq_event(dev
, connector
))
949 mutex_unlock(&mode_config
->mutex
);
952 drm_kms_helper_hotplug_event(dev
);
955 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
958 u32 busy_up
, busy_down
, max_avg
, min_avg
;
961 spin_lock(&mchdev_lock
);
963 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
965 new_delay
= dev_priv
->ips
.cur_delay
;
967 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
968 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
969 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
970 max_avg
= I915_READ(RCBMAXAVG
);
971 min_avg
= I915_READ(RCBMINAVG
);
973 /* Handle RCS change request from hw */
974 if (busy_up
> max_avg
) {
975 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
976 new_delay
= dev_priv
->ips
.cur_delay
- 1;
977 if (new_delay
< dev_priv
->ips
.max_delay
)
978 new_delay
= dev_priv
->ips
.max_delay
;
979 } else if (busy_down
< min_avg
) {
980 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
981 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
982 if (new_delay
> dev_priv
->ips
.min_delay
)
983 new_delay
= dev_priv
->ips
.min_delay
;
986 if (ironlake_set_drps(dev
, new_delay
))
987 dev_priv
->ips
.cur_delay
= new_delay
;
989 spin_unlock(&mchdev_lock
);
994 static void notify_ring(struct intel_engine_cs
*ring
)
996 if (!intel_ring_initialized(ring
))
999 trace_i915_gem_request_notify(ring
);
1001 wake_up_all(&ring
->irq_queue
);
1004 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1005 struct intel_rps_ei
*ei
)
1007 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1008 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1009 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1012 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
1013 const struct intel_rps_ei
*old
,
1014 const struct intel_rps_ei
*now
,
1019 if (old
->cz_clock
== 0)
1022 time
= now
->cz_clock
- old
->cz_clock
;
1023 time
*= threshold
* dev_priv
->mem_freq
;
1025 /* Workload can be split between render + media, e.g. SwapBuffers
1026 * being blitted in X after being rendered in mesa. To account for
1027 * this we need to combine both engines into our activity counter.
1029 c0
= now
->render_c0
- old
->render_c0
;
1030 c0
+= now
->media_c0
- old
->media_c0
;
1031 c0
*= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC
* 4 / 1000;
1036 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1038 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1039 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1042 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1044 struct intel_rps_ei now
;
1047 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1050 vlv_c0_read(dev_priv
, &now
);
1051 if (now
.cz_clock
== 0)
1054 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1055 if (!vlv_c0_above(dev_priv
,
1056 &dev_priv
->rps
.down_ei
, &now
,
1057 dev_priv
->rps
.down_threshold
))
1058 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1059 dev_priv
->rps
.down_ei
= now
;
1062 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1063 if (vlv_c0_above(dev_priv
,
1064 &dev_priv
->rps
.up_ei
, &now
,
1065 dev_priv
->rps
.up_threshold
))
1066 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1067 dev_priv
->rps
.up_ei
= now
;
1073 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1075 struct intel_engine_cs
*ring
;
1078 for_each_ring(ring
, dev_priv
, i
)
1079 if (ring
->irq_refcount
)
1085 static void gen6_pm_rps_work(struct work_struct
*work
)
1087 struct drm_i915_private
*dev_priv
=
1088 container_of(work
, struct drm_i915_private
, rps
.work
);
1090 int new_delay
, adj
, min
, max
;
1093 spin_lock_irq(&dev_priv
->irq_lock
);
1094 /* Speed up work cancelation during disabling rps interrupts. */
1095 if (!dev_priv
->rps
.interrupts_enabled
) {
1096 spin_unlock_irq(&dev_priv
->irq_lock
);
1099 pm_iir
= dev_priv
->rps
.pm_iir
;
1100 dev_priv
->rps
.pm_iir
= 0;
1101 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1102 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1103 client_boost
= dev_priv
->rps
.client_boost
;
1104 dev_priv
->rps
.client_boost
= false;
1105 spin_unlock_irq(&dev_priv
->irq_lock
);
1107 /* Make sure we didn't queue anything we're not going to process. */
1108 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1110 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1113 mutex_lock(&dev_priv
->rps
.hw_lock
);
1115 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1117 adj
= dev_priv
->rps
.last_adj
;
1118 new_delay
= dev_priv
->rps
.cur_freq
;
1119 min
= dev_priv
->rps
.min_freq_softlimit
;
1120 max
= dev_priv
->rps
.max_freq_softlimit
;
1123 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1125 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1128 else /* CHV needs even encode values */
1129 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1131 * For better performance, jump directly
1132 * to RPe if we're below it.
1134 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1135 new_delay
= dev_priv
->rps
.efficient_freq
;
1138 } else if (any_waiters(dev_priv
)) {
1140 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1141 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1142 new_delay
= dev_priv
->rps
.efficient_freq
;
1144 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1146 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1149 else /* CHV needs even encode values */
1150 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1151 } else { /* unknown event */
1155 dev_priv
->rps
.last_adj
= adj
;
1157 /* sysfs frequency interfaces may have snuck in while servicing the
1161 new_delay
= clamp_t(int, new_delay
, min
, max
);
1163 intel_set_rps(dev_priv
->dev
, new_delay
);
1165 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1170 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1172 * @work: workqueue struct
1174 * Doesn't actually do anything except notify userspace. As a consequence of
1175 * this event, userspace should try to remap the bad rows since statistically
1176 * it is likely the same row is more likely to go bad again.
1178 static void ivybridge_parity_work(struct work_struct
*work
)
1180 struct drm_i915_private
*dev_priv
=
1181 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1182 u32 error_status
, row
, bank
, subbank
;
1183 char *parity_event
[6];
1187 /* We must turn off DOP level clock gating to access the L3 registers.
1188 * In order to prevent a get/put style interface, acquire struct mutex
1189 * any time we access those registers.
1191 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1193 /* If we've screwed up tracking, just let the interrupt fire again */
1194 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1197 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1198 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1199 POSTING_READ(GEN7_MISCCPCTL
);
1201 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1205 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1208 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1210 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1212 error_status
= I915_READ(reg
);
1213 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1214 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1215 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1217 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1220 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1221 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1222 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1223 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1224 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1225 parity_event
[5] = NULL
;
1227 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1228 KOBJ_CHANGE
, parity_event
);
1230 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1231 slice
, row
, bank
, subbank
);
1233 kfree(parity_event
[4]);
1234 kfree(parity_event
[3]);
1235 kfree(parity_event
[2]);
1236 kfree(parity_event
[1]);
1239 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1242 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1243 spin_lock_irq(&dev_priv
->irq_lock
);
1244 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1245 spin_unlock_irq(&dev_priv
->irq_lock
);
1247 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1250 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1254 if (!HAS_L3_DPF(dev
))
1257 spin_lock(&dev_priv
->irq_lock
);
1258 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1259 spin_unlock(&dev_priv
->irq_lock
);
1261 iir
&= GT_PARITY_ERROR(dev
);
1262 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1263 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1265 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1266 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1268 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1271 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1272 struct drm_i915_private
*dev_priv
,
1276 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1277 notify_ring(&dev_priv
->ring
[RCS
]);
1278 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1279 notify_ring(&dev_priv
->ring
[VCS
]);
1282 static void snb_gt_irq_handler(struct drm_device
*dev
,
1283 struct drm_i915_private
*dev_priv
,
1288 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1289 notify_ring(&dev_priv
->ring
[RCS
]);
1290 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1291 notify_ring(&dev_priv
->ring
[VCS
]);
1292 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1293 notify_ring(&dev_priv
->ring
[BCS
]);
1295 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1296 GT_BSD_CS_ERROR_INTERRUPT
|
1297 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1298 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1300 if (gt_iir
& GT_PARITY_ERROR(dev
))
1301 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1304 static irqreturn_t
gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1307 irqreturn_t ret
= IRQ_NONE
;
1309 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1310 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(0));
1312 I915_WRITE_FW(GEN8_GT_IIR(0), tmp
);
1315 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
))
1316 intel_lrc_irq_handler(&dev_priv
->ring
[RCS
]);
1317 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
))
1318 notify_ring(&dev_priv
->ring
[RCS
]);
1320 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
))
1321 intel_lrc_irq_handler(&dev_priv
->ring
[BCS
]);
1322 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
))
1323 notify_ring(&dev_priv
->ring
[BCS
]);
1325 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1328 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1329 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(1));
1331 I915_WRITE_FW(GEN8_GT_IIR(1), tmp
);
1334 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
))
1335 intel_lrc_irq_handler(&dev_priv
->ring
[VCS
]);
1336 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
))
1337 notify_ring(&dev_priv
->ring
[VCS
]);
1339 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
))
1340 intel_lrc_irq_handler(&dev_priv
->ring
[VCS2
]);
1341 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
))
1342 notify_ring(&dev_priv
->ring
[VCS2
]);
1344 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1347 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1348 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(3));
1350 I915_WRITE_FW(GEN8_GT_IIR(3), tmp
);
1353 if (tmp
& (GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
))
1354 intel_lrc_irq_handler(&dev_priv
->ring
[VECS
]);
1355 if (tmp
& (GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
))
1356 notify_ring(&dev_priv
->ring
[VECS
]);
1358 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1361 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1362 u32 tmp
= I915_READ_FW(GEN8_GT_IIR(2));
1363 if (tmp
& dev_priv
->pm_rps_events
) {
1364 I915_WRITE_FW(GEN8_GT_IIR(2),
1365 tmp
& dev_priv
->pm_rps_events
);
1367 gen6_rps_irq_handler(dev_priv
, tmp
);
1369 DRM_ERROR("The master control interrupt lied (PM)!\n");
1375 #define HPD_STORM_DETECT_PERIOD 1000
1376 #define HPD_STORM_THRESHOLD 5
1379 * intel_hpd_irq_storm - gather stats and detect HPD irq storm on a pin
1380 * @dev_priv: private driver data pointer
1381 * @pin: the pin to gather stats on
1383 * Gather stats about HPD irqs from the specified @pin, and detect irq
1384 * storms. Only the pin specific stats and state are changed, the caller is
1385 * responsible for further action.
1387 * @HPD_STORM_THRESHOLD irqs are allowed within @HPD_STORM_DETECT_PERIOD ms,
1388 * otherwise it's considered an irq storm, and the irq state is set to
1389 * @HPD_MARK_DISABLED.
1391 * Return true if an irq storm was detected on @pin.
1393 static bool intel_hpd_irq_storm(struct drm_i915_private
*dev_priv
,
1396 unsigned long start
= dev_priv
->hotplug
.stats
[pin
].last_jiffies
;
1397 unsigned long end
= start
+ msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
);
1400 if (!time_in_range(jiffies
, start
, end
)) {
1401 dev_priv
->hotplug
.stats
[pin
].last_jiffies
= jiffies
;
1402 dev_priv
->hotplug
.stats
[pin
].count
= 0;
1403 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", pin
);
1404 } else if (dev_priv
->hotplug
.stats
[pin
].count
> HPD_STORM_THRESHOLD
) {
1405 dev_priv
->hotplug
.stats
[pin
].state
= HPD_MARK_DISABLED
;
1406 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin
);
1409 dev_priv
->hotplug
.stats
[pin
].count
++;
1410 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", pin
,
1411 dev_priv
->hotplug
.stats
[pin
].count
);
1417 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1421 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1423 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1425 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1431 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1435 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1437 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1439 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1445 static enum port
get_port_from_pin(enum hpd_pin pin
)
1455 return PORT_A
; /* no hpd */
1459 /* Get a bit mask of pins that have triggered, and which ones may be long. */
1460 static void pch_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1461 u32 hotplug_trigger
, u32 dig_hotplug_reg
, const u32 hpd
[HPD_NUM_PINS
])
1468 if (!hotplug_trigger
)
1471 for_each_hpd_pin(i
) {
1472 if (hpd
[i
] & hotplug_trigger
) {
1473 *pin_mask
|= BIT(i
);
1475 if (pch_port_hotplug_long_detect(get_port_from_pin(i
), dig_hotplug_reg
))
1476 *long_mask
|= BIT(i
);
1480 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1481 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1485 /* Get a bit mask of pins that have triggered, and which ones may be long. */
1486 static void i9xx_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1487 u32 hotplug_trigger
, const u32 hpd
[HPD_NUM_PINS
])
1494 if (!hotplug_trigger
)
1497 for_each_hpd_pin(i
) {
1498 if (hpd
[i
] & hotplug_trigger
) {
1499 *pin_mask
|= BIT(i
);
1501 if (i9xx_port_hotplug_long_detect(get_port_from_pin(i
), hotplug_trigger
))
1502 *long_mask
|= BIT(i
);
1506 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, pins 0x%08x\n",
1507 hotplug_trigger
, *pin_mask
);
1511 * intel_hpd_irq_handler - main hotplug irq handler
1513 * @pin_mask: a mask of hpd pins that have triggered the irq
1514 * @long_mask: a mask of hpd pins that may be long hpd pulses
1516 * This is the main hotplug irq handler for all platforms. The platform specific
1517 * irq handlers call the platform specific hotplug irq handlers, which read and
1518 * decode the appropriate registers into bitmasks about hpd pins that have
1519 * triggered (@pin_mask), and which of those pins may be long pulses
1520 * (@long_mask). The @long_mask is ignored if the port corresponding to the pin
1521 * is not a digital port.
1523 * Here, we do hotplug irq storm detection and mitigation, and pass further
1524 * processing to appropriate bottom halves.
1526 static void intel_hpd_irq_handler(struct drm_device
*dev
,
1527 u32 pin_mask
, u32 long_mask
)
1529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1532 bool storm_detected
= false;
1533 bool queue_dig
= false, queue_hp
= false;
1539 spin_lock(&dev_priv
->irq_lock
);
1540 for_each_hpd_pin(i
) {
1541 if (!(BIT(i
) & pin_mask
))
1544 port
= get_port_from_pin(i
);
1545 is_dig_port
= port
&& dev_priv
->hotplug
.irq_port
[port
];
1548 bool long_hpd
= long_mask
& BIT(i
);
1550 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port
),
1551 long_hpd
? "long" : "short");
1553 * For long HPD pulses we want to have the digital queue happen,
1554 * but we still want HPD storm detection to function.
1558 dev_priv
->hotplug
.long_port_mask
|= (1 << port
);
1560 /* for short HPD just trigger the digital queue */
1561 dev_priv
->hotplug
.short_port_mask
|= (1 << port
);
1566 if (dev_priv
->hotplug
.stats
[i
].state
== HPD_DISABLED
) {
1568 * On GMCH platforms the interrupt mask bits only
1569 * prevent irq generation, not the setting of the
1570 * hotplug bits itself. So only WARN about unexpected
1571 * interrupts on saner platforms.
1573 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1574 "Received HPD interrupt on pin %d although disabled\n", i
);
1578 if (dev_priv
->hotplug
.stats
[i
].state
!= HPD_ENABLED
)
1582 dev_priv
->hotplug
.event_bits
|= BIT(i
);
1586 if (intel_hpd_irq_storm(dev_priv
, i
)) {
1587 dev_priv
->hotplug
.event_bits
&= ~BIT(i
);
1588 storm_detected
= true;
1593 dev_priv
->display
.hpd_irq_setup(dev
);
1594 spin_unlock(&dev_priv
->irq_lock
);
1597 * Our hotplug handler can grab modeset locks (by calling down into the
1598 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1599 * queue for otherwise the flush_work in the pageflip code will
1603 queue_work(dev_priv
->hotplug
.dp_wq
, &dev_priv
->hotplug
.dig_port_work
);
1605 schedule_work(&dev_priv
->hotplug
.hotplug_work
);
1608 static void gmbus_irq_handler(struct drm_device
*dev
)
1610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1615 static void dp_aux_irq_handler(struct drm_device
*dev
)
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1622 #if defined(CONFIG_DEBUG_FS)
1623 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1624 uint32_t crc0
, uint32_t crc1
,
1625 uint32_t crc2
, uint32_t crc3
,
1628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1630 struct intel_pipe_crc_entry
*entry
;
1633 spin_lock(&pipe_crc
->lock
);
1635 if (!pipe_crc
->entries
) {
1636 spin_unlock(&pipe_crc
->lock
);
1637 DRM_DEBUG_KMS("spurious interrupt\n");
1641 head
= pipe_crc
->head
;
1642 tail
= pipe_crc
->tail
;
1644 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1645 spin_unlock(&pipe_crc
->lock
);
1646 DRM_ERROR("CRC buffer overflowing\n");
1650 entry
= &pipe_crc
->entries
[head
];
1652 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1653 entry
->crc
[0] = crc0
;
1654 entry
->crc
[1] = crc1
;
1655 entry
->crc
[2] = crc2
;
1656 entry
->crc
[3] = crc3
;
1657 entry
->crc
[4] = crc4
;
1659 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1660 pipe_crc
->head
= head
;
1662 spin_unlock(&pipe_crc
->lock
);
1664 wake_up_interruptible(&pipe_crc
->wq
);
1668 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1669 uint32_t crc0
, uint32_t crc1
,
1670 uint32_t crc2
, uint32_t crc3
,
1675 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1679 display_pipe_crc_irq_handler(dev
, pipe
,
1680 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1684 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 display_pipe_crc_irq_handler(dev
, pipe
,
1689 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1690 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1691 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1692 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1693 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1696 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1699 uint32_t res1
, res2
;
1701 if (INTEL_INFO(dev
)->gen
>= 3)
1702 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1706 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1707 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1711 display_pipe_crc_irq_handler(dev
, pipe
,
1712 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1713 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1714 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1718 /* The RPS events need forcewake, so we add them to a work queue and mask their
1719 * IMR bits until the work is done. Other interrupts can be processed without
1720 * the work queue. */
1721 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1723 if (pm_iir
& dev_priv
->pm_rps_events
) {
1724 spin_lock(&dev_priv
->irq_lock
);
1725 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1726 if (dev_priv
->rps
.interrupts_enabled
) {
1727 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1728 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1730 spin_unlock(&dev_priv
->irq_lock
);
1733 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1736 if (HAS_VEBOX(dev_priv
->dev
)) {
1737 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1738 notify_ring(&dev_priv
->ring
[VECS
]);
1740 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1741 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1745 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1747 if (!drm_handle_vblank(dev
, pipe
))
1753 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1756 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1759 spin_lock(&dev_priv
->irq_lock
);
1760 for_each_pipe(dev_priv
, pipe
) {
1762 u32 mask
, iir_bit
= 0;
1765 * PIPESTAT bits get signalled even when the interrupt is
1766 * disabled with the mask bits, and some of the status bits do
1767 * not generate interrupts at all (like the underrun bit). Hence
1768 * we need to be careful that we only handle what we want to
1772 /* fifo underruns are filterered in the underrun handler. */
1773 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1777 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1780 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1783 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1787 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1792 reg
= PIPESTAT(pipe
);
1793 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1794 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1797 * Clear the PIPE*STAT regs before the IIR
1799 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1800 PIPESTAT_INT_STATUS_MASK
))
1801 I915_WRITE(reg
, pipe_stats
[pipe
]);
1803 spin_unlock(&dev_priv
->irq_lock
);
1805 for_each_pipe(dev_priv
, pipe
) {
1806 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1807 intel_pipe_handle_vblank(dev
, pipe
))
1808 intel_check_page_flip(dev
, pipe
);
1810 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1811 intel_prepare_page_flip(dev
, pipe
);
1812 intel_finish_page_flip(dev
, pipe
);
1815 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1816 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1818 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1819 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1822 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1823 gmbus_irq_handler(dev
);
1826 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1829 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1830 u32 pin_mask
, long_mask
;
1832 if (!hotplug_status
)
1835 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1837 * Make sure hotplug status is cleared before we clear IIR, or else we
1838 * may miss hotplug events.
1840 POSTING_READ(PORT_HOTPLUG_STAT
);
1842 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
1843 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1845 i9xx_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
, hpd_status_g4x
);
1846 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1848 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1849 dp_aux_irq_handler(dev
);
1851 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1853 i9xx_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
, hpd_status_i915
);
1854 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1858 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1860 struct drm_device
*dev
= arg
;
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1862 u32 iir
, gt_iir
, pm_iir
;
1863 irqreturn_t ret
= IRQ_NONE
;
1865 if (!intel_irqs_enabled(dev_priv
))
1869 /* Find, clear, then process each source of interrupt */
1871 gt_iir
= I915_READ(GTIIR
);
1873 I915_WRITE(GTIIR
, gt_iir
);
1875 pm_iir
= I915_READ(GEN6_PMIIR
);
1877 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1879 iir
= I915_READ(VLV_IIR
);
1881 /* Consume port before clearing IIR or we'll miss events */
1882 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1883 i9xx_hpd_irq_handler(dev
);
1884 I915_WRITE(VLV_IIR
, iir
);
1887 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1893 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1895 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1896 /* Call regardless, as some status bits might not be
1897 * signalled in iir */
1898 valleyview_pipestat_irq_handler(dev
, iir
);
1905 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1907 struct drm_device
*dev
= arg
;
1908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1909 u32 master_ctl
, iir
;
1910 irqreturn_t ret
= IRQ_NONE
;
1912 if (!intel_irqs_enabled(dev_priv
))
1916 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1917 iir
= I915_READ(VLV_IIR
);
1919 if (master_ctl
== 0 && iir
== 0)
1924 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1926 /* Find, clear, then process each source of interrupt */
1929 /* Consume port before clearing IIR or we'll miss events */
1930 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1931 i9xx_hpd_irq_handler(dev
);
1932 I915_WRITE(VLV_IIR
, iir
);
1935 gen8_gt_irq_handler(dev_priv
, master_ctl
);
1937 /* Call regardless, as some status bits might not be
1938 * signalled in iir */
1939 valleyview_pipestat_irq_handler(dev
, iir
);
1941 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1942 POSTING_READ(GEN8_MASTER_IRQ
);
1948 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1952 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1953 u32 dig_hotplug_reg
;
1954 u32 pin_mask
, long_mask
;
1956 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1957 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1959 pch_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
, dig_hotplug_reg
, hpd_ibx
);
1960 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1962 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1963 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1964 SDE_AUDIO_POWER_SHIFT
);
1965 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1969 if (pch_iir
& SDE_AUX_MASK
)
1970 dp_aux_irq_handler(dev
);
1972 if (pch_iir
& SDE_GMBUS
)
1973 gmbus_irq_handler(dev
);
1975 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1976 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1978 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1979 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1981 if (pch_iir
& SDE_POISON
)
1982 DRM_ERROR("PCH poison interrupt\n");
1984 if (pch_iir
& SDE_FDI_MASK
)
1985 for_each_pipe(dev_priv
, pipe
)
1986 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1988 I915_READ(FDI_RX_IIR(pipe
)));
1990 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1991 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1993 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1994 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1996 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1997 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1999 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
2000 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2003 static void ivb_err_int_handler(struct drm_device
*dev
)
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2009 if (err_int
& ERR_INT_POISON
)
2010 DRM_ERROR("Poison interrupt\n");
2012 for_each_pipe(dev_priv
, pipe
) {
2013 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2014 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2016 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2017 if (IS_IVYBRIDGE(dev
))
2018 ivb_pipe_crc_irq_handler(dev
, pipe
);
2020 hsw_pipe_crc_irq_handler(dev
, pipe
);
2024 I915_WRITE(GEN7_ERR_INT
, err_int
);
2027 static void cpt_serr_int_handler(struct drm_device
*dev
)
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2030 u32 serr_int
= I915_READ(SERR_INT
);
2032 if (serr_int
& SERR_INT_POISON
)
2033 DRM_ERROR("PCH poison interrupt\n");
2035 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2036 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2038 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2039 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2041 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2042 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2044 I915_WRITE(SERR_INT
, serr_int
);
2047 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2051 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2052 u32 dig_hotplug_reg
;
2053 u32 pin_mask
, long_mask
;
2055 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2056 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2058 pch_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
, dig_hotplug_reg
, hpd_cpt
);
2059 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2061 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2062 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2063 SDE_AUDIO_POWER_SHIFT_CPT
);
2064 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2068 if (pch_iir
& SDE_AUX_MASK_CPT
)
2069 dp_aux_irq_handler(dev
);
2071 if (pch_iir
& SDE_GMBUS_CPT
)
2072 gmbus_irq_handler(dev
);
2074 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2075 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2077 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2078 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2080 if (pch_iir
& SDE_FDI_MASK_CPT
)
2081 for_each_pipe(dev_priv
, pipe
)
2082 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2084 I915_READ(FDI_RX_IIR(pipe
)));
2086 if (pch_iir
& SDE_ERROR_CPT
)
2087 cpt_serr_int_handler(dev
);
2090 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2095 if (de_iir
& DE_AUX_CHANNEL_A
)
2096 dp_aux_irq_handler(dev
);
2098 if (de_iir
& DE_GSE
)
2099 intel_opregion_asle_intr(dev
);
2101 if (de_iir
& DE_POISON
)
2102 DRM_ERROR("Poison interrupt\n");
2104 for_each_pipe(dev_priv
, pipe
) {
2105 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2106 intel_pipe_handle_vblank(dev
, pipe
))
2107 intel_check_page_flip(dev
, pipe
);
2109 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2110 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2112 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2113 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2115 /* plane/pipes map 1:1 on ilk+ */
2116 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2117 intel_prepare_page_flip(dev
, pipe
);
2118 intel_finish_page_flip_plane(dev
, pipe
);
2122 /* check event from PCH */
2123 if (de_iir
& DE_PCH_EVENT
) {
2124 u32 pch_iir
= I915_READ(SDEIIR
);
2126 if (HAS_PCH_CPT(dev
))
2127 cpt_irq_handler(dev
, pch_iir
);
2129 ibx_irq_handler(dev
, pch_iir
);
2131 /* should clear PCH hotplug event before clear CPU irq */
2132 I915_WRITE(SDEIIR
, pch_iir
);
2135 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2136 ironlake_rps_change_irq_handler(dev
);
2139 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 if (de_iir
& DE_ERR_INT_IVB
)
2145 ivb_err_int_handler(dev
);
2147 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2148 dp_aux_irq_handler(dev
);
2150 if (de_iir
& DE_GSE_IVB
)
2151 intel_opregion_asle_intr(dev
);
2153 for_each_pipe(dev_priv
, pipe
) {
2154 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2155 intel_pipe_handle_vblank(dev
, pipe
))
2156 intel_check_page_flip(dev
, pipe
);
2158 /* plane/pipes map 1:1 on ilk+ */
2159 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2160 intel_prepare_page_flip(dev
, pipe
);
2161 intel_finish_page_flip_plane(dev
, pipe
);
2165 /* check event from PCH */
2166 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2167 u32 pch_iir
= I915_READ(SDEIIR
);
2169 cpt_irq_handler(dev
, pch_iir
);
2171 /* clear PCH hotplug event before clear CPU irq */
2172 I915_WRITE(SDEIIR
, pch_iir
);
2177 * To handle irqs with the minimum potential races with fresh interrupts, we:
2178 * 1 - Disable Master Interrupt Control.
2179 * 2 - Find the source(s) of the interrupt.
2180 * 3 - Clear the Interrupt Identity bits (IIR).
2181 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2182 * 5 - Re-enable Master Interrupt Control.
2184 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2186 struct drm_device
*dev
= arg
;
2187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2188 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2189 irqreturn_t ret
= IRQ_NONE
;
2191 if (!intel_irqs_enabled(dev_priv
))
2194 /* We get interrupts on unclaimed registers, so check for this before we
2195 * do any I915_{READ,WRITE}. */
2196 intel_uncore_check_errors(dev
);
2198 /* disable master interrupt before clearing iir */
2199 de_ier
= I915_READ(DEIER
);
2200 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2201 POSTING_READ(DEIER
);
2203 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2204 * interrupts will will be stored on its back queue, and then we'll be
2205 * able to process them after we restore SDEIER (as soon as we restore
2206 * it, we'll get an interrupt if SDEIIR still has something to process
2207 * due to its back queue). */
2208 if (!HAS_PCH_NOP(dev
)) {
2209 sde_ier
= I915_READ(SDEIER
);
2210 I915_WRITE(SDEIER
, 0);
2211 POSTING_READ(SDEIER
);
2214 /* Find, clear, then process each source of interrupt */
2216 gt_iir
= I915_READ(GTIIR
);
2218 I915_WRITE(GTIIR
, gt_iir
);
2220 if (INTEL_INFO(dev
)->gen
>= 6)
2221 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2223 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2226 de_iir
= I915_READ(DEIIR
);
2228 I915_WRITE(DEIIR
, de_iir
);
2230 if (INTEL_INFO(dev
)->gen
>= 7)
2231 ivb_display_irq_handler(dev
, de_iir
);
2233 ilk_display_irq_handler(dev
, de_iir
);
2236 if (INTEL_INFO(dev
)->gen
>= 6) {
2237 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2239 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2241 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2245 I915_WRITE(DEIER
, de_ier
);
2246 POSTING_READ(DEIER
);
2247 if (!HAS_PCH_NOP(dev
)) {
2248 I915_WRITE(SDEIER
, sde_ier
);
2249 POSTING_READ(SDEIER
);
2255 static void bxt_hpd_handler(struct drm_device
*dev
, uint32_t iir_status
)
2257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2258 u32 hp_control
, hp_trigger
;
2259 u32 pin_mask
, long_mask
;
2261 /* Get the status */
2262 hp_trigger
= iir_status
& BXT_DE_PORT_HOTPLUG_MASK
;
2263 hp_control
= I915_READ(BXT_HOTPLUG_CTL
);
2265 /* Hotplug not enabled ? */
2266 if (!(hp_control
& BXT_HOTPLUG_CTL_MASK
)) {
2267 DRM_ERROR("Interrupt when HPD disabled\n");
2271 /* Clear sticky bits in hpd status */
2272 I915_WRITE(BXT_HOTPLUG_CTL
, hp_control
);
2274 pch_get_hpd_pins(&pin_mask
, &long_mask
, hp_trigger
, hp_control
, hpd_bxt
);
2275 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2278 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2280 struct drm_device
*dev
= arg
;
2281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 irqreturn_t ret
= IRQ_NONE
;
2286 u32 aux_mask
= GEN8_AUX_CHANNEL_A
;
2288 if (!intel_irqs_enabled(dev_priv
))
2292 aux_mask
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
2295 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2296 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2300 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2302 /* Find, clear, then process each source of interrupt */
2304 ret
= gen8_gt_irq_handler(dev_priv
, master_ctl
);
2306 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2307 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2309 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2311 if (tmp
& GEN8_DE_MISC_GSE
)
2312 intel_opregion_asle_intr(dev
);
2314 DRM_ERROR("Unexpected DE Misc interrupt\n");
2317 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2320 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2321 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2325 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2328 if (tmp
& aux_mask
) {
2329 dp_aux_irq_handler(dev
);
2333 if (IS_BROXTON(dev
) && tmp
& BXT_DE_PORT_HOTPLUG_MASK
) {
2334 bxt_hpd_handler(dev
, tmp
);
2338 if (IS_BROXTON(dev
) && (tmp
& BXT_DE_PORT_GMBUS
)) {
2339 gmbus_irq_handler(dev
);
2344 DRM_ERROR("Unexpected DE Port interrupt\n");
2347 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2350 for_each_pipe(dev_priv
, pipe
) {
2351 uint32_t pipe_iir
, flip_done
= 0, fault_errors
= 0;
2353 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2356 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2359 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2361 if (pipe_iir
& GEN8_PIPE_VBLANK
&&
2362 intel_pipe_handle_vblank(dev
, pipe
))
2363 intel_check_page_flip(dev
, pipe
);
2366 flip_done
= pipe_iir
& GEN9_PIPE_PLANE1_FLIP_DONE
;
2368 flip_done
= pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
;
2371 intel_prepare_page_flip(dev
, pipe
);
2372 intel_finish_page_flip_plane(dev
, pipe
);
2375 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2376 hsw_pipe_crc_irq_handler(dev
, pipe
);
2378 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2379 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
2384 fault_errors
= pipe_iir
& GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2386 fault_errors
= pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2389 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2391 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2393 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2396 if (HAS_PCH_SPLIT(dev
) && !HAS_PCH_NOP(dev
) &&
2397 master_ctl
& GEN8_DE_PCH_IRQ
) {
2399 * FIXME(BDW): Assume for now that the new interrupt handling
2400 * scheme also closed the SDE interrupt handling race we've seen
2401 * on older pch-split platforms. But this needs testing.
2403 u32 pch_iir
= I915_READ(SDEIIR
);
2405 I915_WRITE(SDEIIR
, pch_iir
);
2407 cpt_irq_handler(dev
, pch_iir
);
2409 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2413 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2414 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2419 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2420 bool reset_completed
)
2422 struct intel_engine_cs
*ring
;
2426 * Notify all waiters for GPU completion events that reset state has
2427 * been changed, and that they need to restart their wait after
2428 * checking for potential errors (and bail out to drop locks if there is
2429 * a gpu reset pending so that i915_error_work_func can acquire them).
2432 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2433 for_each_ring(ring
, dev_priv
, i
)
2434 wake_up_all(&ring
->irq_queue
);
2436 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2437 wake_up_all(&dev_priv
->pending_flip_queue
);
2440 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2441 * reset state is cleared.
2443 if (reset_completed
)
2444 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2448 * i915_reset_and_wakeup - do process context error handling work
2450 * Fire an error uevent so userspace can see that a hang or error
2453 static void i915_reset_and_wakeup(struct drm_device
*dev
)
2455 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2456 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
2457 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2458 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2459 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2462 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2465 * Note that there's only one work item which does gpu resets, so we
2466 * need not worry about concurrent gpu resets potentially incrementing
2467 * error->reset_counter twice. We only need to take care of another
2468 * racing irq/hangcheck declaring the gpu dead for a second time. A
2469 * quick check for that is good enough: schedule_work ensures the
2470 * correct ordering between hang detection and this work item, and since
2471 * the reset in-progress bit is only ever set by code outside of this
2472 * work we don't need to worry about any other races.
2474 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2475 DRM_DEBUG_DRIVER("resetting chip\n");
2476 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2480 * In most cases it's guaranteed that we get here with an RPM
2481 * reference held, for example because there is a pending GPU
2482 * request that won't finish until the reset is done. This
2483 * isn't the case at least when we get here by doing a
2484 * simulated reset via debugs, so get an RPM reference.
2486 intel_runtime_pm_get(dev_priv
);
2488 intel_prepare_reset(dev
);
2491 * All state reset _must_ be completed before we update the
2492 * reset counter, for otherwise waiters might miss the reset
2493 * pending state and not properly drop locks, resulting in
2494 * deadlocks with the reset work.
2496 ret
= i915_reset(dev
);
2498 intel_finish_reset(dev
);
2500 intel_runtime_pm_put(dev_priv
);
2504 * After all the gem state is reset, increment the reset
2505 * counter and wake up everyone waiting for the reset to
2508 * Since unlock operations are a one-sided barrier only,
2509 * we need to insert a barrier here to order any seqno
2511 * the counter increment.
2513 smp_mb__before_atomic();
2514 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2516 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2517 KOBJ_CHANGE
, reset_done_event
);
2519 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2523 * Note: The wake_up also serves as a memory barrier so that
2524 * waiters see the update value of the reset counter atomic_t.
2526 i915_error_wake_up(dev_priv
, true);
2530 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2533 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2534 u32 eir
= I915_READ(EIR
);
2540 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2542 i915_get_extra_instdone(dev
, instdone
);
2545 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2546 u32 ipeir
= I915_READ(IPEIR_I965
);
2548 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2549 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2550 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2551 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2552 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2553 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2554 I915_WRITE(IPEIR_I965
, ipeir
);
2555 POSTING_READ(IPEIR_I965
);
2557 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2558 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2559 pr_err("page table error\n");
2560 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2561 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2562 POSTING_READ(PGTBL_ER
);
2566 if (!IS_GEN2(dev
)) {
2567 if (eir
& I915_ERROR_PAGE_TABLE
) {
2568 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2569 pr_err("page table error\n");
2570 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2571 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2572 POSTING_READ(PGTBL_ER
);
2576 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2577 pr_err("memory refresh error:\n");
2578 for_each_pipe(dev_priv
, pipe
)
2579 pr_err("pipe %c stat: 0x%08x\n",
2580 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2581 /* pipestat has already been acked */
2583 if (eir
& I915_ERROR_INSTRUCTION
) {
2584 pr_err("instruction error\n");
2585 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2586 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2587 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2588 if (INTEL_INFO(dev
)->gen
< 4) {
2589 u32 ipeir
= I915_READ(IPEIR
);
2591 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2592 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2593 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2594 I915_WRITE(IPEIR
, ipeir
);
2595 POSTING_READ(IPEIR
);
2597 u32 ipeir
= I915_READ(IPEIR_I965
);
2599 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2600 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2601 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2602 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2603 I915_WRITE(IPEIR_I965
, ipeir
);
2604 POSTING_READ(IPEIR_I965
);
2608 I915_WRITE(EIR
, eir
);
2610 eir
= I915_READ(EIR
);
2613 * some errors might have become stuck,
2616 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2617 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2618 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2623 * i915_handle_error - handle a gpu error
2626 * Do some basic checking of regsiter state at error time and
2627 * dump it to the syslog. Also call i915_capture_error_state() to make
2628 * sure we get a record and make it available in debugfs. Fire a uevent
2629 * so userspace knows something bad happened (should trigger collection
2630 * of a ring dump etc.).
2632 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2633 const char *fmt
, ...)
2635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2639 va_start(args
, fmt
);
2640 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2643 i915_capture_error_state(dev
, wedged
, error_msg
);
2644 i915_report_and_clear_eir(dev
);
2647 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2648 &dev_priv
->gpu_error
.reset_counter
);
2651 * Wakeup waiting processes so that the reset function
2652 * i915_reset_and_wakeup doesn't deadlock trying to grab
2653 * various locks. By bumping the reset counter first, the woken
2654 * processes will see a reset in progress and back off,
2655 * releasing their locks and then wait for the reset completion.
2656 * We must do this for _all_ gpu waiters that might hold locks
2657 * that the reset work needs to acquire.
2659 * Note: The wake_up serves as the required memory barrier to
2660 * ensure that the waiters see the updated value of the reset
2663 i915_error_wake_up(dev_priv
, false);
2666 i915_reset_and_wakeup(dev
);
2669 /* Called from drm generic code, passed 'crtc' which
2670 * we use as a pipe index
2672 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2675 unsigned long irqflags
;
2677 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2678 if (INTEL_INFO(dev
)->gen
>= 4)
2679 i915_enable_pipestat(dev_priv
, pipe
,
2680 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2682 i915_enable_pipestat(dev_priv
, pipe
,
2683 PIPE_VBLANK_INTERRUPT_STATUS
);
2684 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2689 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 unsigned long irqflags
;
2693 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2694 DE_PIPE_VBLANK(pipe
);
2696 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2697 ironlake_enable_display_irq(dev_priv
, bit
);
2698 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2703 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2706 unsigned long irqflags
;
2708 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2709 i915_enable_pipestat(dev_priv
, pipe
,
2710 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2711 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2716 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2719 unsigned long irqflags
;
2721 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2722 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2723 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2724 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2725 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2729 /* Called from drm generic code, passed 'crtc' which
2730 * we use as a pipe index
2732 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2735 unsigned long irqflags
;
2737 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2738 i915_disable_pipestat(dev_priv
, pipe
,
2739 PIPE_VBLANK_INTERRUPT_STATUS
|
2740 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2741 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2744 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2747 unsigned long irqflags
;
2748 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2749 DE_PIPE_VBLANK(pipe
);
2751 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2752 ironlake_disable_display_irq(dev_priv
, bit
);
2753 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2756 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2759 unsigned long irqflags
;
2761 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2762 i915_disable_pipestat(dev_priv
, pipe
,
2763 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2764 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2767 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2770 unsigned long irqflags
;
2772 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2773 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2774 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2775 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2776 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2779 static struct drm_i915_gem_request
*
2780 ring_last_request(struct intel_engine_cs
*ring
)
2782 return list_entry(ring
->request_list
.prev
,
2783 struct drm_i915_gem_request
, list
);
2787 ring_idle(struct intel_engine_cs
*ring
)
2789 return (list_empty(&ring
->request_list
) ||
2790 i915_gem_request_completed(ring_last_request(ring
), false));
2794 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2796 if (INTEL_INFO(dev
)->gen
>= 8) {
2797 return (ipehr
>> 23) == 0x1c;
2799 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2800 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2801 MI_SEMAPHORE_REGISTER
);
2805 static struct intel_engine_cs
*
2806 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*ring
, u32 ipehr
, u64 offset
)
2808 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2809 struct intel_engine_cs
*signaller
;
2812 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2813 for_each_ring(signaller
, dev_priv
, i
) {
2814 if (ring
== signaller
)
2817 if (offset
== signaller
->semaphore
.signal_ggtt
[ring
->id
])
2821 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2823 for_each_ring(signaller
, dev_priv
, i
) {
2824 if(ring
== signaller
)
2827 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2832 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2833 ring
->id
, ipehr
, offset
);
2838 static struct intel_engine_cs
*
2839 semaphore_waits_for(struct intel_engine_cs
*ring
, u32
*seqno
)
2841 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2842 u32 cmd
, ipehr
, head
;
2846 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2847 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2851 * HEAD is likely pointing to the dword after the actual command,
2852 * so scan backwards until we find the MBOX. But limit it to just 3
2853 * or 4 dwords depending on the semaphore wait command size.
2854 * Note that we don't care about ACTHD here since that might
2855 * point at at batch, and semaphores are always emitted into the
2856 * ringbuffer itself.
2858 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2859 backwards
= (INTEL_INFO(ring
->dev
)->gen
>= 8) ? 5 : 4;
2861 for (i
= backwards
; i
; --i
) {
2863 * Be paranoid and presume the hw has gone off into the wild -
2864 * our ring is smaller than what the hardware (and hence
2865 * HEAD_ADDR) allows. Also handles wrap-around.
2867 head
&= ring
->buffer
->size
- 1;
2869 /* This here seems to blow up */
2870 cmd
= ioread32(ring
->buffer
->virtual_start
+ head
);
2880 *seqno
= ioread32(ring
->buffer
->virtual_start
+ head
+ 4) + 1;
2881 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2882 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 12);
2884 offset
= ioread32(ring
->buffer
->virtual_start
+ head
+ 8);
2886 return semaphore_wait_to_signaller_ring(ring
, ipehr
, offset
);
2889 static int semaphore_passed(struct intel_engine_cs
*ring
)
2891 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2892 struct intel_engine_cs
*signaller
;
2895 ring
->hangcheck
.deadlock
++;
2897 signaller
= semaphore_waits_for(ring
, &seqno
);
2898 if (signaller
== NULL
)
2901 /* Prevent pathological recursion due to driver bugs */
2902 if (signaller
->hangcheck
.deadlock
>= I915_NUM_RINGS
)
2905 if (i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
))
2908 /* cursory check for an unkickable deadlock */
2909 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2910 semaphore_passed(signaller
) < 0)
2916 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2918 struct intel_engine_cs
*ring
;
2921 for_each_ring(ring
, dev_priv
, i
)
2922 ring
->hangcheck
.deadlock
= 0;
2925 static enum intel_ring_hangcheck_action
2926 ring_stuck(struct intel_engine_cs
*ring
, u64 acthd
)
2928 struct drm_device
*dev
= ring
->dev
;
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2932 if (acthd
!= ring
->hangcheck
.acthd
) {
2933 if (acthd
> ring
->hangcheck
.max_acthd
) {
2934 ring
->hangcheck
.max_acthd
= acthd
;
2935 return HANGCHECK_ACTIVE
;
2938 return HANGCHECK_ACTIVE_LOOP
;
2942 return HANGCHECK_HUNG
;
2944 /* Is the chip hanging on a WAIT_FOR_EVENT?
2945 * If so we can simply poke the RB_WAIT bit
2946 * and break the hang. This should work on
2947 * all but the second generation chipsets.
2949 tmp
= I915_READ_CTL(ring
);
2950 if (tmp
& RING_WAIT
) {
2951 i915_handle_error(dev
, false,
2952 "Kicking stuck wait on %s",
2954 I915_WRITE_CTL(ring
, tmp
);
2955 return HANGCHECK_KICK
;
2958 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2959 switch (semaphore_passed(ring
)) {
2961 return HANGCHECK_HUNG
;
2963 i915_handle_error(dev
, false,
2964 "Kicking stuck semaphore on %s",
2966 I915_WRITE_CTL(ring
, tmp
);
2967 return HANGCHECK_KICK
;
2969 return HANGCHECK_WAIT
;
2973 return HANGCHECK_HUNG
;
2977 * This is called when the chip hasn't reported back with completed
2978 * batchbuffers in a long time. We keep track per ring seqno progress and
2979 * if there are no progress, hangcheck score for that ring is increased.
2980 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2981 * we kick the ring. If we see no progress on three subsequent calls
2982 * we assume chip is wedged and try to fix it by resetting the chip.
2984 static void i915_hangcheck_elapsed(struct work_struct
*work
)
2986 struct drm_i915_private
*dev_priv
=
2987 container_of(work
, typeof(*dev_priv
),
2988 gpu_error
.hangcheck_work
.work
);
2989 struct drm_device
*dev
= dev_priv
->dev
;
2990 struct intel_engine_cs
*ring
;
2992 int busy_count
= 0, rings_hung
= 0;
2993 bool stuck
[I915_NUM_RINGS
] = { 0 };
2998 if (!i915
.enable_hangcheck
)
3001 for_each_ring(ring
, dev_priv
, i
) {
3006 semaphore_clear_deadlocks(dev_priv
);
3008 seqno
= ring
->get_seqno(ring
, false);
3009 acthd
= intel_ring_get_active_head(ring
);
3011 if (ring
->hangcheck
.seqno
== seqno
) {
3012 if (ring_idle(ring
)) {
3013 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
3015 if (waitqueue_active(&ring
->irq_queue
)) {
3016 /* Issue a wake-up to catch stuck h/w. */
3017 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
3018 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
3019 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3022 DRM_INFO("Fake missed irq on %s\n",
3024 wake_up_all(&ring
->irq_queue
);
3026 /* Safeguard against driver failure */
3027 ring
->hangcheck
.score
+= BUSY
;
3031 /* We always increment the hangcheck score
3032 * if the ring is busy and still processing
3033 * the same request, so that no single request
3034 * can run indefinitely (such as a chain of
3035 * batches). The only time we do not increment
3036 * the hangcheck score on this ring, if this
3037 * ring is in a legitimate wait for another
3038 * ring. In that case the waiting ring is a
3039 * victim and we want to be sure we catch the
3040 * right culprit. Then every time we do kick
3041 * the ring, add a small increment to the
3042 * score so that we can catch a batch that is
3043 * being repeatedly kicked and so responsible
3044 * for stalling the machine.
3046 ring
->hangcheck
.action
= ring_stuck(ring
,
3049 switch (ring
->hangcheck
.action
) {
3050 case HANGCHECK_IDLE
:
3051 case HANGCHECK_WAIT
:
3052 case HANGCHECK_ACTIVE
:
3054 case HANGCHECK_ACTIVE_LOOP
:
3055 ring
->hangcheck
.score
+= BUSY
;
3057 case HANGCHECK_KICK
:
3058 ring
->hangcheck
.score
+= KICK
;
3060 case HANGCHECK_HUNG
:
3061 ring
->hangcheck
.score
+= HUNG
;
3067 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3069 /* Gradually reduce the count so that we catch DoS
3070 * attempts across multiple batches.
3072 if (ring
->hangcheck
.score
> 0)
3073 ring
->hangcheck
.score
--;
3075 ring
->hangcheck
.acthd
= ring
->hangcheck
.max_acthd
= 0;
3078 ring
->hangcheck
.seqno
= seqno
;
3079 ring
->hangcheck
.acthd
= acthd
;
3083 for_each_ring(ring
, dev_priv
, i
) {
3084 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3085 DRM_INFO("%s on %s\n",
3086 stuck
[i
] ? "stuck" : "no progress",
3093 return i915_handle_error(dev
, true, "Ring hung");
3096 /* Reset timer case chip hangs without another request
3098 i915_queue_hangcheck(dev
);
3101 void i915_queue_hangcheck(struct drm_device
*dev
)
3103 struct i915_gpu_error
*e
= &to_i915(dev
)->gpu_error
;
3105 if (!i915
.enable_hangcheck
)
3108 /* Don't continually defer the hangcheck so that it is always run at
3109 * least once after work has been scheduled on any ring. Otherwise,
3110 * we will ignore a hung ring if a second ring is kept busy.
3113 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3114 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3117 static void ibx_irq_reset(struct drm_device
*dev
)
3119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3121 if (HAS_PCH_NOP(dev
))
3124 GEN5_IRQ_RESET(SDE
);
3126 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3127 I915_WRITE(SERR_INT
, 0xffffffff);
3131 * SDEIER is also touched by the interrupt handler to work around missed PCH
3132 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3133 * instead we unconditionally enable all PCH interrupt sources here, but then
3134 * only unmask them as needed with SDEIMR.
3136 * This function needs to be called before interrupts are enabled.
3138 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3142 if (HAS_PCH_NOP(dev
))
3145 WARN_ON(I915_READ(SDEIER
) != 0);
3146 I915_WRITE(SDEIER
, 0xffffffff);
3147 POSTING_READ(SDEIER
);
3150 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3155 if (INTEL_INFO(dev
)->gen
>= 6)
3156 GEN5_IRQ_RESET(GEN6_PM
);
3161 static void ironlake_irq_reset(struct drm_device
*dev
)
3163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3165 I915_WRITE(HWSTAM
, 0xffffffff);
3169 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3171 gen5_gt_irq_reset(dev
);
3176 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3180 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3181 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3183 for_each_pipe(dev_priv
, pipe
)
3184 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3186 GEN5_IRQ_RESET(VLV_
);
3189 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 I915_WRITE(VLV_IMR
, 0);
3195 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3196 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3197 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3199 gen5_gt_irq_reset(dev
);
3201 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3203 vlv_display_irq_reset(dev_priv
);
3206 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3208 GEN8_IRQ_RESET_NDX(GT
, 0);
3209 GEN8_IRQ_RESET_NDX(GT
, 1);
3210 GEN8_IRQ_RESET_NDX(GT
, 2);
3211 GEN8_IRQ_RESET_NDX(GT
, 3);
3214 static void gen8_irq_reset(struct drm_device
*dev
)
3216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3219 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3220 POSTING_READ(GEN8_MASTER_IRQ
);
3222 gen8_gt_irq_reset(dev_priv
);
3224 for_each_pipe(dev_priv
, pipe
)
3225 if (intel_display_power_is_enabled(dev_priv
,
3226 POWER_DOMAIN_PIPE(pipe
)))
3227 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3229 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3230 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3231 GEN5_IRQ_RESET(GEN8_PCU_
);
3233 if (HAS_PCH_SPLIT(dev
))
3237 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3238 unsigned int pipe_mask
)
3240 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3242 spin_lock_irq(&dev_priv
->irq_lock
);
3243 if (pipe_mask
& 1 << PIPE_A
)
3244 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_A
,
3245 dev_priv
->de_irq_mask
[PIPE_A
],
3246 ~dev_priv
->de_irq_mask
[PIPE_A
] | extra_ier
);
3247 if (pipe_mask
& 1 << PIPE_B
)
3248 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_B
,
3249 dev_priv
->de_irq_mask
[PIPE_B
],
3250 ~dev_priv
->de_irq_mask
[PIPE_B
] | extra_ier
);
3251 if (pipe_mask
& 1 << PIPE_C
)
3252 GEN8_IRQ_INIT_NDX(DE_PIPE
, PIPE_C
,
3253 dev_priv
->de_irq_mask
[PIPE_C
],
3254 ~dev_priv
->de_irq_mask
[PIPE_C
] | extra_ier
);
3255 spin_unlock_irq(&dev_priv
->irq_lock
);
3258 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3262 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3263 POSTING_READ(GEN8_MASTER_IRQ
);
3265 gen8_gt_irq_reset(dev_priv
);
3267 GEN5_IRQ_RESET(GEN8_PCU_
);
3269 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3271 vlv_display_irq_reset(dev_priv
);
3274 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3277 struct intel_encoder
*intel_encoder
;
3278 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
3280 if (HAS_PCH_IBX(dev
)) {
3281 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3282 for_each_intel_encoder(dev
, intel_encoder
)
3283 if (dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
== HPD_ENABLED
)
3284 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3286 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3287 for_each_intel_encoder(dev
, intel_encoder
)
3288 if (dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
== HPD_ENABLED
)
3289 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3292 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3295 * Enable digital hotplug on the PCH, and configure the DP short pulse
3296 * duration to 2ms (which is the minimum in the Display Port spec)
3298 * This register is the same on all known PCH chips.
3300 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3301 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3302 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3303 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3304 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3305 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3308 static void bxt_hpd_irq_setup(struct drm_device
*dev
)
3310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3311 struct intel_encoder
*intel_encoder
;
3312 u32 hotplug_port
= 0;
3315 /* Now, enable HPD */
3316 for_each_intel_encoder(dev
, intel_encoder
) {
3317 if (dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
3319 hotplug_port
|= hpd_bxt
[intel_encoder
->hpd_pin
];
3322 /* Mask all HPD control bits */
3323 hotplug_ctrl
= I915_READ(BXT_HOTPLUG_CTL
) & ~BXT_HOTPLUG_CTL_MASK
;
3325 /* Enable requested port in hotplug control */
3326 /* TODO: implement (short) HPD support on port A */
3327 WARN_ON_ONCE(hotplug_port
& BXT_DE_PORT_HP_DDIA
);
3328 if (hotplug_port
& BXT_DE_PORT_HP_DDIB
)
3329 hotplug_ctrl
|= BXT_DDIB_HPD_ENABLE
;
3330 if (hotplug_port
& BXT_DE_PORT_HP_DDIC
)
3331 hotplug_ctrl
|= BXT_DDIC_HPD_ENABLE
;
3332 I915_WRITE(BXT_HOTPLUG_CTL
, hotplug_ctrl
);
3334 /* Unmask DDI hotplug in IMR */
3335 hotplug_ctrl
= I915_READ(GEN8_DE_PORT_IMR
) & ~hotplug_port
;
3336 I915_WRITE(GEN8_DE_PORT_IMR
, hotplug_ctrl
);
3338 /* Enable DDI hotplug in IER */
3339 hotplug_ctrl
= I915_READ(GEN8_DE_PORT_IER
) | hotplug_port
;
3340 I915_WRITE(GEN8_DE_PORT_IER
, hotplug_ctrl
);
3341 POSTING_READ(GEN8_DE_PORT_IER
);
3344 static void ibx_irq_postinstall(struct drm_device
*dev
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3349 if (HAS_PCH_NOP(dev
))
3352 if (HAS_PCH_IBX(dev
))
3353 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3355 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3357 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3358 I915_WRITE(SDEIMR
, ~mask
);
3361 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 u32 pm_irqs
, gt_irqs
;
3366 pm_irqs
= gt_irqs
= 0;
3368 dev_priv
->gt_irq_mask
= ~0;
3369 if (HAS_L3_DPF(dev
)) {
3370 /* L3 parity interrupt is always unmasked. */
3371 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3372 gt_irqs
|= GT_PARITY_ERROR(dev
);
3375 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3377 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3378 ILK_BSD_USER_INTERRUPT
;
3380 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3383 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3385 if (INTEL_INFO(dev
)->gen
>= 6) {
3387 * RPS interrupts will get enabled/disabled on demand when RPS
3388 * itself is enabled/disabled.
3391 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3393 dev_priv
->pm_irq_mask
= 0xffffffff;
3394 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3398 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3401 u32 display_mask
, extra_mask
;
3403 if (INTEL_INFO(dev
)->gen
>= 7) {
3404 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3405 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3406 DE_PLANEB_FLIP_DONE_IVB
|
3407 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3408 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3409 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3411 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3412 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3414 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3416 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3417 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3420 dev_priv
->irq_mask
= ~display_mask
;
3422 I915_WRITE(HWSTAM
, 0xeffe);
3424 ibx_irq_pre_postinstall(dev
);
3426 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3428 gen5_gt_irq_postinstall(dev
);
3430 ibx_irq_postinstall(dev
);
3432 if (IS_IRONLAKE_M(dev
)) {
3433 /* Enable PCU event interrupts
3435 * spinlocking not required here for correctness since interrupt
3436 * setup is guaranteed to run in single-threaded context. But we
3437 * need it to make the assert_spin_locked happy. */
3438 spin_lock_irq(&dev_priv
->irq_lock
);
3439 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3440 spin_unlock_irq(&dev_priv
->irq_lock
);
3446 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3452 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3453 PIPE_FIFO_UNDERRUN_STATUS
;
3455 for_each_pipe(dev_priv
, pipe
)
3456 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3457 POSTING_READ(PIPESTAT(PIPE_A
));
3459 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3460 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3462 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3463 for_each_pipe(dev_priv
, pipe
)
3464 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3466 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3467 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3468 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3469 if (IS_CHERRYVIEW(dev_priv
))
3470 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3471 dev_priv
->irq_mask
&= ~iir_mask
;
3473 I915_WRITE(VLV_IIR
, iir_mask
);
3474 I915_WRITE(VLV_IIR
, iir_mask
);
3475 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3476 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3477 POSTING_READ(VLV_IMR
);
3480 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3486 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3487 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3488 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3489 if (IS_CHERRYVIEW(dev_priv
))
3490 iir_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3492 dev_priv
->irq_mask
|= iir_mask
;
3493 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3494 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3495 I915_WRITE(VLV_IIR
, iir_mask
);
3496 I915_WRITE(VLV_IIR
, iir_mask
);
3497 POSTING_READ(VLV_IIR
);
3499 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3500 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3502 i915_disable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3503 for_each_pipe(dev_priv
, pipe
)
3504 i915_disable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3506 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3507 PIPE_FIFO_UNDERRUN_STATUS
;
3509 for_each_pipe(dev_priv
, pipe
)
3510 I915_WRITE(PIPESTAT(pipe
), pipestat_mask
);
3511 POSTING_READ(PIPESTAT(PIPE_A
));
3514 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3516 assert_spin_locked(&dev_priv
->irq_lock
);
3518 if (dev_priv
->display_irqs_enabled
)
3521 dev_priv
->display_irqs_enabled
= true;
3523 if (intel_irqs_enabled(dev_priv
))
3524 valleyview_display_irqs_install(dev_priv
);
3527 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3529 assert_spin_locked(&dev_priv
->irq_lock
);
3531 if (!dev_priv
->display_irqs_enabled
)
3534 dev_priv
->display_irqs_enabled
= false;
3536 if (intel_irqs_enabled(dev_priv
))
3537 valleyview_display_irqs_uninstall(dev_priv
);
3540 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3542 dev_priv
->irq_mask
= ~0;
3544 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3545 POSTING_READ(PORT_HOTPLUG_EN
);
3547 I915_WRITE(VLV_IIR
, 0xffffffff);
3548 I915_WRITE(VLV_IIR
, 0xffffffff);
3549 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3550 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3551 POSTING_READ(VLV_IMR
);
3553 /* Interrupt setup is already guaranteed to be single-threaded, this is
3554 * just to make the assert_spin_locked check happy. */
3555 spin_lock_irq(&dev_priv
->irq_lock
);
3556 if (dev_priv
->display_irqs_enabled
)
3557 valleyview_display_irqs_install(dev_priv
);
3558 spin_unlock_irq(&dev_priv
->irq_lock
);
3561 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3565 vlv_display_irq_postinstall(dev_priv
);
3567 gen5_gt_irq_postinstall(dev
);
3569 /* ack & enable invalid PTE error interrupts */
3570 #if 0 /* FIXME: add support to irq handler for checking these bits */
3571 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3572 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3575 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3580 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3582 /* These are interrupts we'll toggle with the ring mask register */
3583 uint32_t gt_interrupts
[] = {
3584 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3585 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3586 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3587 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3588 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3589 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3590 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3591 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3592 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3594 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3595 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3598 dev_priv
->pm_irq_mask
= 0xffffffff;
3599 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3600 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3602 * RPS interrupts will get enabled/disabled on demand when RPS itself
3603 * is enabled/disabled.
3605 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3606 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3609 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3611 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3612 uint32_t de_pipe_enables
;
3614 u32 de_port_en
= GEN8_AUX_CHANNEL_A
;
3616 if (IS_GEN9(dev_priv
)) {
3617 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3618 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3619 de_port_en
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3622 if (IS_BROXTON(dev_priv
))
3623 de_port_en
|= BXT_DE_PORT_GMBUS
;
3625 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3626 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3628 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3629 GEN8_PIPE_FIFO_UNDERRUN
;
3631 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3632 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3633 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3635 for_each_pipe(dev_priv
, pipe
)
3636 if (intel_display_power_is_enabled(dev_priv
,
3637 POWER_DOMAIN_PIPE(pipe
)))
3638 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3639 dev_priv
->de_irq_mask
[pipe
],
3642 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_en
, de_port_en
);
3645 static int gen8_irq_postinstall(struct drm_device
*dev
)
3647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3649 if (HAS_PCH_SPLIT(dev
))
3650 ibx_irq_pre_postinstall(dev
);
3652 gen8_gt_irq_postinstall(dev_priv
);
3653 gen8_de_irq_postinstall(dev_priv
);
3655 if (HAS_PCH_SPLIT(dev
))
3656 ibx_irq_postinstall(dev
);
3658 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3659 POSTING_READ(GEN8_MASTER_IRQ
);
3664 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 vlv_display_irq_postinstall(dev_priv
);
3670 gen8_gt_irq_postinstall(dev_priv
);
3672 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3673 POSTING_READ(GEN8_MASTER_IRQ
);
3678 static void gen8_irq_uninstall(struct drm_device
*dev
)
3680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3685 gen8_irq_reset(dev
);
3688 static void vlv_display_irq_uninstall(struct drm_i915_private
*dev_priv
)
3690 /* Interrupt setup is already guaranteed to be single-threaded, this is
3691 * just to make the assert_spin_locked check happy. */
3692 spin_lock_irq(&dev_priv
->irq_lock
);
3693 if (dev_priv
->display_irqs_enabled
)
3694 valleyview_display_irqs_uninstall(dev_priv
);
3695 spin_unlock_irq(&dev_priv
->irq_lock
);
3697 vlv_display_irq_reset(dev_priv
);
3699 dev_priv
->irq_mask
= ~0;
3702 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 I915_WRITE(VLV_MASTER_IER
, 0);
3711 gen5_gt_irq_reset(dev
);
3713 I915_WRITE(HWSTAM
, 0xffffffff);
3715 vlv_display_irq_uninstall(dev_priv
);
3718 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3725 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3726 POSTING_READ(GEN8_MASTER_IRQ
);
3728 gen8_gt_irq_reset(dev_priv
);
3730 GEN5_IRQ_RESET(GEN8_PCU_
);
3732 vlv_display_irq_uninstall(dev_priv
);
3735 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 ironlake_irq_reset(dev
);
3745 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3750 for_each_pipe(dev_priv
, pipe
)
3751 I915_WRITE(PIPESTAT(pipe
), 0);
3752 I915_WRITE16(IMR
, 0xffff);
3753 I915_WRITE16(IER
, 0x0);
3754 POSTING_READ16(IER
);
3757 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3762 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3764 /* Unmask the interrupts that we always want on. */
3765 dev_priv
->irq_mask
=
3766 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3767 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3768 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3769 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3770 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3773 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3774 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3775 I915_USER_INTERRUPT
);
3776 POSTING_READ16(IER
);
3778 /* Interrupt setup is already guaranteed to be single-threaded, this is
3779 * just to make the assert_spin_locked check happy. */
3780 spin_lock_irq(&dev_priv
->irq_lock
);
3781 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3782 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3783 spin_unlock_irq(&dev_priv
->irq_lock
);
3789 * Returns true when a page flip has completed.
3791 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3792 int plane
, int pipe
, u32 iir
)
3794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3795 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3797 if (!intel_pipe_handle_vblank(dev
, pipe
))
3800 if ((iir
& flip_pending
) == 0)
3801 goto check_page_flip
;
3803 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3804 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3805 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3806 * the flip is completed (no longer pending). Since this doesn't raise
3807 * an interrupt per se, we watch for the change at vblank.
3809 if (I915_READ16(ISR
) & flip_pending
)
3810 goto check_page_flip
;
3812 intel_prepare_page_flip(dev
, plane
);
3813 intel_finish_page_flip(dev
, pipe
);
3817 intel_check_page_flip(dev
, pipe
);
3821 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3823 struct drm_device
*dev
= arg
;
3824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3830 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3832 if (!intel_irqs_enabled(dev_priv
))
3835 iir
= I915_READ16(IIR
);
3839 while (iir
& ~flip_mask
) {
3840 /* Can't rely on pipestat interrupt bit in iir as it might
3841 * have been cleared after the pipestat interrupt was received.
3842 * It doesn't set the bit in iir again, but it still produces
3843 * interrupts (for non-MSI).
3845 spin_lock(&dev_priv
->irq_lock
);
3846 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3847 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3849 for_each_pipe(dev_priv
, pipe
) {
3850 int reg
= PIPESTAT(pipe
);
3851 pipe_stats
[pipe
] = I915_READ(reg
);
3854 * Clear the PIPE*STAT regs before the IIR
3856 if (pipe_stats
[pipe
] & 0x8000ffff)
3857 I915_WRITE(reg
, pipe_stats
[pipe
]);
3859 spin_unlock(&dev_priv
->irq_lock
);
3861 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3862 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3864 if (iir
& I915_USER_INTERRUPT
)
3865 notify_ring(&dev_priv
->ring
[RCS
]);
3867 for_each_pipe(dev_priv
, pipe
) {
3872 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3873 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3874 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3876 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3877 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3879 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3880 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3890 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3895 for_each_pipe(dev_priv
, pipe
) {
3896 /* Clear enable bits; then clear status bits */
3897 I915_WRITE(PIPESTAT(pipe
), 0);
3898 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3900 I915_WRITE16(IMR
, 0xffff);
3901 I915_WRITE16(IER
, 0x0);
3902 I915_WRITE16(IIR
, I915_READ16(IIR
));
3905 static void i915_irq_preinstall(struct drm_device
* dev
)
3907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3910 if (I915_HAS_HOTPLUG(dev
)) {
3911 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3912 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3915 I915_WRITE16(HWSTAM
, 0xeffe);
3916 for_each_pipe(dev_priv
, pipe
)
3917 I915_WRITE(PIPESTAT(pipe
), 0);
3918 I915_WRITE(IMR
, 0xffffffff);
3919 I915_WRITE(IER
, 0x0);
3923 static int i915_irq_postinstall(struct drm_device
*dev
)
3925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3928 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3930 /* Unmask the interrupts that we always want on. */
3931 dev_priv
->irq_mask
=
3932 ~(I915_ASLE_INTERRUPT
|
3933 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3934 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3935 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3936 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3939 I915_ASLE_INTERRUPT
|
3940 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3941 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3942 I915_USER_INTERRUPT
;
3944 if (I915_HAS_HOTPLUG(dev
)) {
3945 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3946 POSTING_READ(PORT_HOTPLUG_EN
);
3948 /* Enable in IER... */
3949 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3950 /* and unmask in IMR */
3951 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3954 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3955 I915_WRITE(IER
, enable_mask
);
3958 i915_enable_asle_pipestat(dev
);
3960 /* Interrupt setup is already guaranteed to be single-threaded, this is
3961 * just to make the assert_spin_locked check happy. */
3962 spin_lock_irq(&dev_priv
->irq_lock
);
3963 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3964 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3965 spin_unlock_irq(&dev_priv
->irq_lock
);
3971 * Returns true when a page flip has completed.
3973 static bool i915_handle_vblank(struct drm_device
*dev
,
3974 int plane
, int pipe
, u32 iir
)
3976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3977 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3979 if (!intel_pipe_handle_vblank(dev
, pipe
))
3982 if ((iir
& flip_pending
) == 0)
3983 goto check_page_flip
;
3985 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3986 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3987 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3988 * the flip is completed (no longer pending). Since this doesn't raise
3989 * an interrupt per se, we watch for the change at vblank.
3991 if (I915_READ(ISR
) & flip_pending
)
3992 goto check_page_flip
;
3994 intel_prepare_page_flip(dev
, plane
);
3995 intel_finish_page_flip(dev
, pipe
);
3999 intel_check_page_flip(dev
, pipe
);
4003 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4005 struct drm_device
*dev
= arg
;
4006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4007 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4009 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4010 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4011 int pipe
, ret
= IRQ_NONE
;
4013 if (!intel_irqs_enabled(dev_priv
))
4016 iir
= I915_READ(IIR
);
4018 bool irq_received
= (iir
& ~flip_mask
) != 0;
4019 bool blc_event
= false;
4021 /* Can't rely on pipestat interrupt bit in iir as it might
4022 * have been cleared after the pipestat interrupt was received.
4023 * It doesn't set the bit in iir again, but it still produces
4024 * interrupts (for non-MSI).
4026 spin_lock(&dev_priv
->irq_lock
);
4027 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4028 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4030 for_each_pipe(dev_priv
, pipe
) {
4031 int reg
= PIPESTAT(pipe
);
4032 pipe_stats
[pipe
] = I915_READ(reg
);
4034 /* Clear the PIPE*STAT regs before the IIR */
4035 if (pipe_stats
[pipe
] & 0x8000ffff) {
4036 I915_WRITE(reg
, pipe_stats
[pipe
]);
4037 irq_received
= true;
4040 spin_unlock(&dev_priv
->irq_lock
);
4045 /* Consume port. Then clear IIR or we'll miss events */
4046 if (I915_HAS_HOTPLUG(dev
) &&
4047 iir
& I915_DISPLAY_PORT_INTERRUPT
)
4048 i9xx_hpd_irq_handler(dev
);
4050 I915_WRITE(IIR
, iir
& ~flip_mask
);
4051 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4053 if (iir
& I915_USER_INTERRUPT
)
4054 notify_ring(&dev_priv
->ring
[RCS
]);
4056 for_each_pipe(dev_priv
, pipe
) {
4061 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4062 i915_handle_vblank(dev
, plane
, pipe
, iir
))
4063 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4065 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4068 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4069 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4071 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4072 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4076 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4077 intel_opregion_asle_intr(dev
);
4079 /* With MSI, interrupts are only generated when iir
4080 * transitions from zero to nonzero. If another bit got
4081 * set while we were handling the existing iir bits, then
4082 * we would never get another interrupt.
4084 * This is fine on non-MSI as well, as if we hit this path
4085 * we avoid exiting the interrupt handler only to generate
4088 * Note that for MSI this could cause a stray interrupt report
4089 * if an interrupt landed in the time between writing IIR and
4090 * the posting read. This should be rare enough to never
4091 * trigger the 99% of 100,000 interrupts test for disabling
4096 } while (iir
& ~flip_mask
);
4101 static void i915_irq_uninstall(struct drm_device
* dev
)
4103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4106 if (I915_HAS_HOTPLUG(dev
)) {
4107 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4108 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4111 I915_WRITE16(HWSTAM
, 0xffff);
4112 for_each_pipe(dev_priv
, pipe
) {
4113 /* Clear enable bits; then clear status bits */
4114 I915_WRITE(PIPESTAT(pipe
), 0);
4115 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4117 I915_WRITE(IMR
, 0xffffffff);
4118 I915_WRITE(IER
, 0x0);
4120 I915_WRITE(IIR
, I915_READ(IIR
));
4123 static void i965_irq_preinstall(struct drm_device
* dev
)
4125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4128 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4129 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4131 I915_WRITE(HWSTAM
, 0xeffe);
4132 for_each_pipe(dev_priv
, pipe
)
4133 I915_WRITE(PIPESTAT(pipe
), 0);
4134 I915_WRITE(IMR
, 0xffffffff);
4135 I915_WRITE(IER
, 0x0);
4139 static int i965_irq_postinstall(struct drm_device
*dev
)
4141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4145 /* Unmask the interrupts that we always want on. */
4146 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4147 I915_DISPLAY_PORT_INTERRUPT
|
4148 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4149 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4150 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4151 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4152 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4154 enable_mask
= ~dev_priv
->irq_mask
;
4155 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4156 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4157 enable_mask
|= I915_USER_INTERRUPT
;
4160 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4162 /* Interrupt setup is already guaranteed to be single-threaded, this is
4163 * just to make the assert_spin_locked check happy. */
4164 spin_lock_irq(&dev_priv
->irq_lock
);
4165 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4166 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4167 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4168 spin_unlock_irq(&dev_priv
->irq_lock
);
4171 * Enable some error detection, note the instruction error mask
4172 * bit is reserved, so we leave it masked.
4175 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4176 GM45_ERROR_MEM_PRIV
|
4177 GM45_ERROR_CP_PRIV
|
4178 I915_ERROR_MEMORY_REFRESH
);
4180 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4181 I915_ERROR_MEMORY_REFRESH
);
4183 I915_WRITE(EMR
, error_mask
);
4185 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4186 I915_WRITE(IER
, enable_mask
);
4189 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4190 POSTING_READ(PORT_HOTPLUG_EN
);
4192 i915_enable_asle_pipestat(dev
);
4197 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 struct intel_encoder
*intel_encoder
;
4203 assert_spin_locked(&dev_priv
->irq_lock
);
4205 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
4206 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
4207 /* Note HDMI and DP share hotplug bits */
4208 /* enable bits are the same for all generations */
4209 for_each_intel_encoder(dev
, intel_encoder
)
4210 if (dev_priv
->hotplug
.stats
[intel_encoder
->hpd_pin
].state
== HPD_ENABLED
)
4211 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
4212 /* Programming the CRT detection parameters tends
4213 to generate a spurious hotplug event about three
4214 seconds later. So just do it once.
4217 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4218 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
4219 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4221 /* Ignore TV since it's buggy */
4222 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
4225 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4227 struct drm_device
*dev
= arg
;
4228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4230 u32 pipe_stats
[I915_MAX_PIPES
];
4231 int ret
= IRQ_NONE
, pipe
;
4233 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4234 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4236 if (!intel_irqs_enabled(dev_priv
))
4239 iir
= I915_READ(IIR
);
4242 bool irq_received
= (iir
& ~flip_mask
) != 0;
4243 bool blc_event
= false;
4245 /* Can't rely on pipestat interrupt bit in iir as it might
4246 * have been cleared after the pipestat interrupt was received.
4247 * It doesn't set the bit in iir again, but it still produces
4248 * interrupts (for non-MSI).
4250 spin_lock(&dev_priv
->irq_lock
);
4251 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4252 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4254 for_each_pipe(dev_priv
, pipe
) {
4255 int reg
= PIPESTAT(pipe
);
4256 pipe_stats
[pipe
] = I915_READ(reg
);
4259 * Clear the PIPE*STAT regs before the IIR
4261 if (pipe_stats
[pipe
] & 0x8000ffff) {
4262 I915_WRITE(reg
, pipe_stats
[pipe
]);
4263 irq_received
= true;
4266 spin_unlock(&dev_priv
->irq_lock
);
4273 /* Consume port. Then clear IIR or we'll miss events */
4274 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4275 i9xx_hpd_irq_handler(dev
);
4277 I915_WRITE(IIR
, iir
& ~flip_mask
);
4278 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4280 if (iir
& I915_USER_INTERRUPT
)
4281 notify_ring(&dev_priv
->ring
[RCS
]);
4282 if (iir
& I915_BSD_USER_INTERRUPT
)
4283 notify_ring(&dev_priv
->ring
[VCS
]);
4285 for_each_pipe(dev_priv
, pipe
) {
4286 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4287 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4288 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4290 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4293 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4294 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4296 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4297 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4300 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4301 intel_opregion_asle_intr(dev
);
4303 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4304 gmbus_irq_handler(dev
);
4306 /* With MSI, interrupts are only generated when iir
4307 * transitions from zero to nonzero. If another bit got
4308 * set while we were handling the existing iir bits, then
4309 * we would never get another interrupt.
4311 * This is fine on non-MSI as well, as if we hit this path
4312 * we avoid exiting the interrupt handler only to generate
4315 * Note that for MSI this could cause a stray interrupt report
4316 * if an interrupt landed in the time between writing IIR and
4317 * the posting read. This should be rare enough to never
4318 * trigger the 99% of 100,000 interrupts test for disabling
4327 static void i965_irq_uninstall(struct drm_device
* dev
)
4329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4335 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4336 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4338 I915_WRITE(HWSTAM
, 0xffffffff);
4339 for_each_pipe(dev_priv
, pipe
)
4340 I915_WRITE(PIPESTAT(pipe
), 0);
4341 I915_WRITE(IMR
, 0xffffffff);
4342 I915_WRITE(IER
, 0x0);
4344 for_each_pipe(dev_priv
, pipe
)
4345 I915_WRITE(PIPESTAT(pipe
),
4346 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4347 I915_WRITE(IIR
, I915_READ(IIR
));
4350 static void intel_hpd_irq_reenable_work(struct work_struct
*work
)
4352 struct drm_i915_private
*dev_priv
=
4353 container_of(work
, typeof(*dev_priv
),
4354 hotplug
.reenable_work
.work
);
4355 struct drm_device
*dev
= dev_priv
->dev
;
4356 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4359 intel_runtime_pm_get(dev_priv
);
4361 spin_lock_irq(&dev_priv
->irq_lock
);
4362 for_each_hpd_pin(i
) {
4363 struct drm_connector
*connector
;
4365 if (dev_priv
->hotplug
.stats
[i
].state
!= HPD_DISABLED
)
4368 dev_priv
->hotplug
.stats
[i
].state
= HPD_ENABLED
;
4370 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4371 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4373 if (intel_connector
->encoder
->hpd_pin
== i
) {
4374 if (connector
->polled
!= intel_connector
->polled
)
4375 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4377 connector
->polled
= intel_connector
->polled
;
4378 if (!connector
->polled
)
4379 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4383 if (dev_priv
->display
.hpd_irq_setup
)
4384 dev_priv
->display
.hpd_irq_setup(dev
);
4385 spin_unlock_irq(&dev_priv
->irq_lock
);
4387 intel_runtime_pm_put(dev_priv
);
4391 * intel_irq_init - initializes irq support
4392 * @dev_priv: i915 device instance
4394 * This function initializes all the irq support including work items, timers
4395 * and all the vtables. It does not setup the interrupt itself though.
4397 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4399 struct drm_device
*dev
= dev_priv
->dev
;
4401 INIT_WORK(&dev_priv
->hotplug
.hotplug_work
, i915_hotplug_work_func
);
4402 INIT_WORK(&dev_priv
->hotplug
.dig_port_work
, i915_digport_work_func
);
4403 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4404 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4406 /* Let's track the enabled rps events */
4407 if (IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
4408 /* WaGsvRC0ResidencyMethod:vlv */
4409 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4411 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4413 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4414 i915_hangcheck_elapsed
);
4415 INIT_DELAYED_WORK(&dev_priv
->hotplug
.reenable_work
,
4416 intel_hpd_irq_reenable_work
);
4418 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4420 if (IS_GEN2(dev_priv
)) {
4421 dev
->max_vblank_count
= 0;
4422 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4423 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4424 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4425 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4427 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4428 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4432 * Opt out of the vblank disable timer on everything except gen2.
4433 * Gen2 doesn't have a hardware frame counter and so depends on
4434 * vblank interrupts to produce sane vblank seuquence numbers.
4436 if (!IS_GEN2(dev_priv
))
4437 dev
->vblank_disable_immediate
= true;
4439 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4440 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4442 if (IS_CHERRYVIEW(dev_priv
)) {
4443 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4444 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4445 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4446 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4447 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4448 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4449 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4450 } else if (IS_VALLEYVIEW(dev_priv
)) {
4451 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4452 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4453 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4454 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4455 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4456 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4457 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4458 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4459 dev
->driver
->irq_handler
= gen8_irq_handler
;
4460 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4461 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4462 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4463 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4464 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4465 if (HAS_PCH_SPLIT(dev
))
4466 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4468 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4469 } else if (HAS_PCH_SPLIT(dev
)) {
4470 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4471 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4472 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4473 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4474 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4475 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4476 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4478 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4479 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4480 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4481 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4482 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4483 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4484 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4485 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4486 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4487 dev
->driver
->irq_handler
= i915_irq_handler
;
4489 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4490 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4491 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4492 dev
->driver
->irq_handler
= i965_irq_handler
;
4494 if (I915_HAS_HOTPLUG(dev_priv
))
4495 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4496 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4497 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4502 * intel_hpd_init - initializes and enables hpd support
4503 * @dev_priv: i915 device instance
4505 * This function enables the hotplug support. It requires that interrupts have
4506 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4507 * poll request can run concurrently to other code, so locking rules must be
4510 * This is a separate step from interrupt enabling to simplify the locking rules
4511 * in the driver load and resume code.
4513 void intel_hpd_init(struct drm_i915_private
*dev_priv
)
4515 struct drm_device
*dev
= dev_priv
->dev
;
4516 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4517 struct drm_connector
*connector
;
4520 for_each_hpd_pin(i
) {
4521 dev_priv
->hotplug
.stats
[i
].count
= 0;
4522 dev_priv
->hotplug
.stats
[i
].state
= HPD_ENABLED
;
4524 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4525 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4526 connector
->polled
= intel_connector
->polled
;
4527 if (connector
->encoder
&& !connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4528 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4529 if (intel_connector
->mst_port
)
4530 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4533 /* Interrupt setup is already guaranteed to be single-threaded, this is
4534 * just to make the assert_spin_locked checks happy. */
4535 spin_lock_irq(&dev_priv
->irq_lock
);
4536 if (dev_priv
->display
.hpd_irq_setup
)
4537 dev_priv
->display
.hpd_irq_setup(dev
);
4538 spin_unlock_irq(&dev_priv
->irq_lock
);
4542 * intel_irq_install - enables the hardware interrupt
4543 * @dev_priv: i915 device instance
4545 * This function enables the hardware interrupt handling, but leaves the hotplug
4546 * handling still disabled. It is called after intel_irq_init().
4548 * In the driver load and resume code we need working interrupts in a few places
4549 * but don't want to deal with the hassle of concurrent probe and hotplug
4550 * workers. Hence the split into this two-stage approach.
4552 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4555 * We enable some interrupt sources in our postinstall hooks, so mark
4556 * interrupts as enabled _before_ actually enabling them to avoid
4557 * special cases in our ordering checks.
4559 dev_priv
->pm
.irqs_enabled
= true;
4561 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4565 * intel_irq_uninstall - finilizes all irq handling
4566 * @dev_priv: i915 device instance
4568 * This stops interrupt and hotplug handling and unregisters and frees all
4569 * resources acquired in the init functions.
4571 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4573 drm_irq_uninstall(dev_priv
->dev
);
4574 intel_hpd_cancel_work(dev_priv
);
4575 dev_priv
->pm
.irqs_enabled
= false;
4579 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4580 * @dev_priv: i915 device instance
4582 * This function is used to disable interrupts at runtime, both in the runtime
4583 * pm and the system suspend/resume code.
4585 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4587 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4588 dev_priv
->pm
.irqs_enabled
= false;
4589 synchronize_irq(dev_priv
->dev
->irq
);
4593 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4594 * @dev_priv: i915 device instance
4596 * This function is used to enable interrupts at runtime, both in the runtime
4597 * pm and the system suspend/resume code.
4599 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4601 dev_priv
->pm
.irqs_enabled
= true;
4602 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4603 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);