1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_gen4
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* For display hotplug interrupt */
85 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
87 assert_spin_locked(&dev_priv
->irq_lock
);
89 if (dev_priv
->pc8
.irqs_disabled
) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
95 if ((dev_priv
->irq_mask
& mask
) != 0) {
96 dev_priv
->irq_mask
&= ~mask
;
97 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
103 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
105 assert_spin_locked(&dev_priv
->irq_lock
);
107 if (dev_priv
->pc8
.irqs_disabled
) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv
->pc8
.regsave
.deimr
|= mask
;
113 if ((dev_priv
->irq_mask
& mask
) != mask
) {
114 dev_priv
->irq_mask
|= mask
;
115 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
126 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
127 uint32_t interrupt_mask
,
128 uint32_t enabled_irq_mask
)
130 assert_spin_locked(&dev_priv
->irq_lock
);
132 if (dev_priv
->pc8
.irqs_disabled
) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
135 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
140 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
141 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
142 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
146 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
148 ilk_update_gt_irq(dev_priv
, mask
, mask
);
151 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
153 ilk_update_gt_irq(dev_priv
, mask
, 0);
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
162 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
163 uint32_t interrupt_mask
,
164 uint32_t enabled_irq_mask
)
168 assert_spin_locked(&dev_priv
->irq_lock
);
170 if (dev_priv
->pc8
.irqs_disabled
) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
173 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
178 new_val
= dev_priv
->pm_irq_mask
;
179 new_val
&= ~interrupt_mask
;
180 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
182 if (new_val
!= dev_priv
->pm_irq_mask
) {
183 dev_priv
->pm_irq_mask
= new_val
;
184 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
185 POSTING_READ(GEN6_PMIMR
);
189 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
191 snb_update_pm_irq(dev_priv
, mask
, mask
);
194 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
196 snb_update_pm_irq(dev_priv
, mask
, 0);
199 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
202 struct intel_crtc
*crtc
;
205 assert_spin_locked(&dev_priv
->irq_lock
);
207 for_each_pipe(pipe
) {
208 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
210 if (crtc
->cpu_fifo_underrun_disabled
)
217 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
221 struct intel_crtc
*crtc
;
223 assert_spin_locked(&dev_priv
->irq_lock
);
225 for_each_pipe(pipe
) {
226 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
228 if (crtc
->pch_fifo_underrun_disabled
)
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
236 enum pipe pipe
, bool enable
)
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
240 DE_PIPEB_FIFO_UNDERRUN
;
243 ironlake_enable_display_irq(dev_priv
, bit
);
245 ironlake_disable_display_irq(dev_priv
, bit
);
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
249 enum pipe pipe
, bool enable
)
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
255 if (!ivb_can_enable_err_int(dev
))
258 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
260 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
266 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
274 enum pipe pipe
, bool enable
)
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
278 assert_spin_locked(&dev_priv
->irq_lock
);
281 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_FIFO_UNDERRUN
;
283 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_FIFO_UNDERRUN
;
284 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
285 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
289 * ibx_display_interrupt_update - update SDEIMR
290 * @dev_priv: driver private
291 * @interrupt_mask: mask of interrupt bits to update
292 * @enabled_irq_mask: mask of interrupt bits to enable
294 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
295 uint32_t interrupt_mask
,
296 uint32_t enabled_irq_mask
)
298 uint32_t sdeimr
= I915_READ(SDEIMR
);
299 sdeimr
&= ~interrupt_mask
;
300 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
302 assert_spin_locked(&dev_priv
->irq_lock
);
304 if (dev_priv
->pc8
.irqs_disabled
&&
305 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
306 WARN(1, "IRQs disabled\n");
307 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
308 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
313 I915_WRITE(SDEIMR
, sdeimr
);
314 POSTING_READ(SDEIMR
);
316 #define ibx_enable_display_interrupt(dev_priv, bits) \
317 ibx_display_interrupt_update((dev_priv), (bits), (bits))
318 #define ibx_disable_display_interrupt(dev_priv, bits) \
319 ibx_display_interrupt_update((dev_priv), (bits), 0)
321 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
322 enum transcoder pch_transcoder
,
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
326 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
327 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
330 ibx_enable_display_interrupt(dev_priv
, bit
);
332 ibx_disable_display_interrupt(dev_priv
, bit
);
335 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
336 enum transcoder pch_transcoder
,
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
345 if (!cpt_can_enable_serr_int(dev
))
348 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
350 uint32_t tmp
= I915_READ(SERR_INT
);
351 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
353 /* Change the state _after_ we've read out the current one. */
354 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
357 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
358 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
359 transcoder_name(pch_transcoder
));
365 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
368 * @enable: true if we want to report FIFO underrun errors, false otherwise
370 * This function makes us disable or enable CPU fifo underruns for a specific
371 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
372 * reporting for one pipe may also disable all the other CPU error interruts for
373 * the other pipes, due to the fact that there's just one interrupt mask/enable
374 * bit for all the pipes.
376 * Returns the previous state of underrun reporting.
378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
379 enum pipe pipe
, bool enable
)
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
382 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
383 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
387 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
389 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
394 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
396 if (IS_GEN5(dev
) || IS_GEN6(dev
))
397 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
398 else if (IS_GEN7(dev
))
399 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
400 else if (IS_GEN8(dev
))
401 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
404 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
409 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
411 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
412 * @enable: true if we want to report FIFO underrun errors, false otherwise
414 * This function makes us disable or enable PCH fifo underruns for a specific
415 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
416 * underrun reporting for one transcoder may also disable all the other PCH
417 * error interruts for the other transcoders, due to the fact that there's just
418 * one interrupt mask/enable bit for all the transcoders.
420 * Returns the previous state of underrun reporting.
422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
423 enum transcoder pch_transcoder
,
426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
427 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
428 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
433 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
434 * has only one pch transcoder A that all pipes can use. To avoid racy
435 * pch transcoder -> pipe lookups from interrupt code simply store the
436 * underrun statistics in crtc A. Since we never expose this anywhere
437 * nor use it outside of the fifo underrun code here using the "wrong"
438 * crtc on LPT won't cause issues.
441 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
443 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
448 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
450 if (HAS_PCH_IBX(dev
))
451 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
453 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
456 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
462 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
)
464 u32 reg
= PIPESTAT(pipe
);
465 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
467 assert_spin_locked(&dev_priv
->irq_lock
);
469 if ((pipestat
& mask
) == mask
)
472 /* Enable the interrupt, clear any pending status */
473 pipestat
|= mask
| (mask
>> 16);
474 I915_WRITE(reg
, pipestat
);
479 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
)
481 u32 reg
= PIPESTAT(pipe
);
482 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
484 assert_spin_locked(&dev_priv
->irq_lock
);
486 if ((pipestat
& mask
) == 0)
490 I915_WRITE(reg
, pipestat
);
495 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
497 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
500 unsigned long irqflags
;
502 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
505 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
507 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_ENABLE
);
508 if (INTEL_INFO(dev
)->gen
>= 4)
509 i915_enable_pipestat(dev_priv
, PIPE_A
,
510 PIPE_LEGACY_BLC_EVENT_ENABLE
);
512 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
516 * i915_pipe_enabled - check if a pipe is enabled
518 * @pipe: pipe to check
520 * Reading certain registers when the pipe is disabled can hang the chip.
521 * Use this routine to make sure the PLL is running and the pipe is active
522 * before reading such registers if unsure.
525 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
527 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
529 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
530 /* Locking is horribly broken here, but whatever. */
531 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
532 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
534 return intel_crtc
->active
;
536 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
540 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
542 /* Gen2 doesn't have a hardware frame counter */
546 /* Called from drm generic code, passed a 'crtc', which
547 * we use as a pipe index
549 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
551 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
552 unsigned long high_frame
;
553 unsigned long low_frame
;
554 u32 high1
, high2
, low
, pixel
, vbl_start
;
556 if (!i915_pipe_enabled(dev
, pipe
)) {
557 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
558 "pipe %c\n", pipe_name(pipe
));
562 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
563 struct intel_crtc
*intel_crtc
=
564 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
565 const struct drm_display_mode
*mode
=
566 &intel_crtc
->config
.adjusted_mode
;
568 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
570 enum transcoder cpu_transcoder
=
571 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
574 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
575 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
580 high_frame
= PIPEFRAME(pipe
);
581 low_frame
= PIPEFRAMEPIXEL(pipe
);
584 * High & low register fields aren't synchronized, so make sure
585 * we get a low value that's stable across two reads of the high
589 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
590 low
= I915_READ(low_frame
);
591 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
592 } while (high1
!= high2
);
594 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
595 pixel
= low
& PIPE_PIXEL_MASK
;
596 low
>>= PIPE_FRAME_LOW_SHIFT
;
599 * The frame counter increments at beginning of active.
600 * Cook up a vblank counter by also checking the pixel
601 * counter against vblank start.
603 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
606 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
608 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
609 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
611 if (!i915_pipe_enabled(dev
, pipe
)) {
612 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
613 "pipe %c\n", pipe_name(pipe
));
617 return I915_READ(reg
);
620 static bool intel_pipe_in_vblank(struct drm_device
*dev
, enum pipe pipe
)
622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
625 if (IS_VALLEYVIEW(dev
)) {
626 status
= pipe
== PIPE_A
?
627 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
628 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
630 return I915_READ(VLV_ISR
) & status
;
631 } else if (IS_GEN2(dev
)) {
632 status
= pipe
== PIPE_A
?
633 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
634 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
636 return I915_READ16(ISR
) & status
;
637 } else if (INTEL_INFO(dev
)->gen
< 5) {
638 status
= pipe
== PIPE_A
?
639 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
640 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
642 return I915_READ(ISR
) & status
;
643 } else if (INTEL_INFO(dev
)->gen
< 7) {
644 status
= pipe
== PIPE_A
?
648 return I915_READ(DEISR
) & status
;
653 status
= DE_PIPEA_VBLANK_IVB
;
656 status
= DE_PIPEB_VBLANK_IVB
;
659 status
= DE_PIPEC_VBLANK_IVB
;
663 return I915_READ(DEISR
) & status
;
667 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
668 int *vpos
, int *hpos
)
670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
671 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
673 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
675 int vbl_start
, vbl_end
, htotal
, vtotal
;
679 if (!intel_crtc
->active
) {
680 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
681 "pipe %c\n", pipe_name(pipe
));
685 htotal
= mode
->crtc_htotal
;
686 vtotal
= mode
->crtc_vtotal
;
687 vbl_start
= mode
->crtc_vblank_start
;
688 vbl_end
= mode
->crtc_vblank_end
;
690 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
692 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
693 /* No obvious pixelcount register. Only query vertical
694 * scanout position from Display scan line register.
697 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
699 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
702 * The scanline counter increments at the leading edge
703 * of hsync, ie. it completely misses the active portion
704 * of the line. Fix up the counter at both edges of vblank
705 * to get a more accurate picture whether we're in vblank
708 in_vbl
= intel_pipe_in_vblank(dev
, pipe
);
709 if ((in_vbl
&& position
== vbl_start
- 1) ||
710 (!in_vbl
&& position
== vbl_end
- 1))
711 position
= (position
+ 1) % vtotal
;
713 /* Have access to pixelcount since start of frame.
714 * We can split this into vertical and horizontal
717 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
719 /* convert to pixel counts */
725 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
728 * While in vblank, position will be negative
729 * counting up towards 0 at vbl_end. And outside
730 * vblank, position will be positive counting
733 if (position
>= vbl_start
)
736 position
+= vtotal
- vbl_end
;
738 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
742 *vpos
= position
/ htotal
;
743 *hpos
= position
- (*vpos
* htotal
);
748 ret
|= DRM_SCANOUTPOS_INVBL
;
753 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
755 struct timeval
*vblank_time
,
758 struct drm_crtc
*crtc
;
760 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
761 DRM_ERROR("Invalid crtc %d\n", pipe
);
765 /* Get drm_crtc to timestamp: */
766 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
768 DRM_ERROR("Invalid crtc %d\n", pipe
);
772 if (!crtc
->enabled
) {
773 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
777 /* Helper routine in DRM core does all the work: */
778 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
783 static bool intel_hpd_irq_event(struct drm_device
*dev
,
784 struct drm_connector
*connector
)
786 enum drm_connector_status old_status
;
788 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
789 old_status
= connector
->status
;
791 connector
->status
= connector
->funcs
->detect(connector
, false);
792 if (old_status
== connector
->status
)
795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
797 drm_get_connector_name(connector
),
798 drm_get_connector_status_name(old_status
),
799 drm_get_connector_status_name(connector
->status
));
805 * Handle hotplug events outside the interrupt handler proper.
807 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
809 static void i915_hotplug_work_func(struct work_struct
*work
)
811 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
813 struct drm_device
*dev
= dev_priv
->dev
;
814 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
815 struct intel_connector
*intel_connector
;
816 struct intel_encoder
*intel_encoder
;
817 struct drm_connector
*connector
;
818 unsigned long irqflags
;
819 bool hpd_disabled
= false;
820 bool changed
= false;
823 /* HPD irq before everything is fully set up. */
824 if (!dev_priv
->enable_hotplug_processing
)
827 mutex_lock(&mode_config
->mutex
);
828 DRM_DEBUG_KMS("running encoder hotplug functions\n");
830 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
832 hpd_event_bits
= dev_priv
->hpd_event_bits
;
833 dev_priv
->hpd_event_bits
= 0;
834 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
835 intel_connector
= to_intel_connector(connector
);
836 intel_encoder
= intel_connector
->encoder
;
837 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
838 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
839 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
840 DRM_INFO("HPD interrupt storm detected on connector %s: "
841 "switching from hotplug detection to polling\n",
842 drm_get_connector_name(connector
));
843 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
844 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
845 | DRM_CONNECTOR_POLL_DISCONNECT
;
848 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
849 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
850 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
853 /* if there were no outputs to poll, poll was disabled,
854 * therefore make sure it's enabled when disabling HPD on
857 drm_kms_helper_poll_enable(dev
);
858 mod_timer(&dev_priv
->hotplug_reenable_timer
,
859 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
862 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
864 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
865 intel_connector
= to_intel_connector(connector
);
866 intel_encoder
= intel_connector
->encoder
;
867 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
868 if (intel_encoder
->hot_plug
)
869 intel_encoder
->hot_plug(intel_encoder
);
870 if (intel_hpd_irq_event(dev
, connector
))
874 mutex_unlock(&mode_config
->mutex
);
877 drm_kms_helper_hotplug_event(dev
);
880 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
882 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
883 u32 busy_up
, busy_down
, max_avg
, min_avg
;
886 spin_lock(&mchdev_lock
);
888 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
890 new_delay
= dev_priv
->ips
.cur_delay
;
892 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
893 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
894 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
895 max_avg
= I915_READ(RCBMAXAVG
);
896 min_avg
= I915_READ(RCBMINAVG
);
898 /* Handle RCS change request from hw */
899 if (busy_up
> max_avg
) {
900 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
901 new_delay
= dev_priv
->ips
.cur_delay
- 1;
902 if (new_delay
< dev_priv
->ips
.max_delay
)
903 new_delay
= dev_priv
->ips
.max_delay
;
904 } else if (busy_down
< min_avg
) {
905 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
906 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
907 if (new_delay
> dev_priv
->ips
.min_delay
)
908 new_delay
= dev_priv
->ips
.min_delay
;
911 if (ironlake_set_drps(dev
, new_delay
))
912 dev_priv
->ips
.cur_delay
= new_delay
;
914 spin_unlock(&mchdev_lock
);
919 static void notify_ring(struct drm_device
*dev
,
920 struct intel_ring_buffer
*ring
)
922 if (ring
->obj
== NULL
)
925 trace_i915_gem_request_complete(ring
);
927 wake_up_all(&ring
->irq_queue
);
928 i915_queue_hangcheck(dev
);
931 static void gen6_pm_rps_work(struct work_struct
*work
)
933 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
938 spin_lock_irq(&dev_priv
->irq_lock
);
939 pm_iir
= dev_priv
->rps
.pm_iir
;
940 dev_priv
->rps
.pm_iir
= 0;
941 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
942 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
943 spin_unlock_irq(&dev_priv
->irq_lock
);
945 /* Make sure we didn't queue anything we're not going to process. */
946 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
948 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
951 mutex_lock(&dev_priv
->rps
.hw_lock
);
953 adj
= dev_priv
->rps
.last_adj
;
954 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
959 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
962 * For better performance, jump directly
963 * to RPe if we're below it.
965 if (new_delay
< dev_priv
->rps
.rpe_delay
)
966 new_delay
= dev_priv
->rps
.rpe_delay
;
967 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
968 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
969 new_delay
= dev_priv
->rps
.rpe_delay
;
971 new_delay
= dev_priv
->rps
.min_delay
;
973 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
978 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
979 } else { /* unknown event */
980 new_delay
= dev_priv
->rps
.cur_delay
;
983 /* sysfs frequency interfaces may have snuck in while servicing the
986 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
987 new_delay
= dev_priv
->rps
.min_delay
;
988 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
989 new_delay
= dev_priv
->rps
.max_delay
;
990 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
992 if (IS_VALLEYVIEW(dev_priv
->dev
))
993 valleyview_set_rps(dev_priv
->dev
, new_delay
);
995 gen6_set_rps(dev_priv
->dev
, new_delay
);
997 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1002 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1004 * @work: workqueue struct
1006 * Doesn't actually do anything except notify userspace. As a consequence of
1007 * this event, userspace should try to remap the bad rows since statistically
1008 * it is likely the same row is more likely to go bad again.
1010 static void ivybridge_parity_work(struct work_struct
*work
)
1012 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
1013 l3_parity
.error_work
);
1014 u32 error_status
, row
, bank
, subbank
;
1015 char *parity_event
[6];
1017 unsigned long flags
;
1020 /* We must turn off DOP level clock gating to access the L3 registers.
1021 * In order to prevent a get/put style interface, acquire struct mutex
1022 * any time we access those registers.
1024 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1026 /* If we've screwed up tracking, just let the interrupt fire again */
1027 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1030 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1031 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1032 POSTING_READ(GEN7_MISCCPCTL
);
1034 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1038 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1041 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1043 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1045 error_status
= I915_READ(reg
);
1046 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1047 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1048 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1050 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1053 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1054 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1055 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1056 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1057 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1058 parity_event
[5] = NULL
;
1060 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
1061 KOBJ_CHANGE
, parity_event
);
1063 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1064 slice
, row
, bank
, subbank
);
1066 kfree(parity_event
[4]);
1067 kfree(parity_event
[3]);
1068 kfree(parity_event
[2]);
1069 kfree(parity_event
[1]);
1072 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1075 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1076 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1077 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1078 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1080 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1083 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1085 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1087 if (!HAS_L3_DPF(dev
))
1090 spin_lock(&dev_priv
->irq_lock
);
1091 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1092 spin_unlock(&dev_priv
->irq_lock
);
1094 iir
&= GT_PARITY_ERROR(dev
);
1095 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1096 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1098 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1099 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1101 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1104 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1105 struct drm_i915_private
*dev_priv
,
1109 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1110 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1111 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1112 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1115 static void snb_gt_irq_handler(struct drm_device
*dev
,
1116 struct drm_i915_private
*dev_priv
,
1121 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1122 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1123 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1124 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1125 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1126 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1128 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1129 GT_BSD_CS_ERROR_INTERRUPT
|
1130 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1131 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1132 i915_handle_error(dev
, false);
1135 if (gt_iir
& GT_PARITY_ERROR(dev
))
1136 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1139 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1140 struct drm_i915_private
*dev_priv
,
1145 irqreturn_t ret
= IRQ_NONE
;
1147 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1148 tmp
= I915_READ(GEN8_GT_IIR(0));
1151 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1152 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1153 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1154 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1155 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1156 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1157 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1159 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1162 if (master_ctl
& GEN8_GT_VCS1_IRQ
) {
1163 tmp
= I915_READ(GEN8_GT_IIR(1));
1166 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1167 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1168 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1169 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1171 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1174 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1175 tmp
= I915_READ(GEN8_GT_IIR(3));
1178 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1179 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1180 notify_ring(dev
, &dev_priv
->ring
[VECS
]);
1181 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1183 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1189 #define HPD_STORM_DETECT_PERIOD 1000
1190 #define HPD_STORM_THRESHOLD 5
1192 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1193 u32 hotplug_trigger
,
1196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1198 bool storm_detected
= false;
1200 if (!hotplug_trigger
)
1203 spin_lock(&dev_priv
->irq_lock
);
1204 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1206 WARN(((hpd
[i
] & hotplug_trigger
) &&
1207 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1208 "Received HPD interrupt although disabled\n");
1210 if (!(hpd
[i
] & hotplug_trigger
) ||
1211 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1214 dev_priv
->hpd_event_bits
|= (1 << i
);
1215 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1216 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1217 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1218 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1219 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1220 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1221 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1222 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1223 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1224 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1225 storm_detected
= true;
1227 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1228 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1229 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1234 dev_priv
->display
.hpd_irq_setup(dev
);
1235 spin_unlock(&dev_priv
->irq_lock
);
1238 * Our hotplug handler can grab modeset locks (by calling down into the
1239 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1240 * queue for otherwise the flush_work in the pageflip code will
1243 schedule_work(&dev_priv
->hotplug_work
);
1246 static void gmbus_irq_handler(struct drm_device
*dev
)
1248 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1250 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1253 static void dp_aux_irq_handler(struct drm_device
*dev
)
1255 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1257 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1260 #if defined(CONFIG_DEBUG_FS)
1261 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1262 uint32_t crc0
, uint32_t crc1
,
1263 uint32_t crc2
, uint32_t crc3
,
1266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1267 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1268 struct intel_pipe_crc_entry
*entry
;
1271 spin_lock(&pipe_crc
->lock
);
1273 if (!pipe_crc
->entries
) {
1274 spin_unlock(&pipe_crc
->lock
);
1275 DRM_ERROR("spurious interrupt\n");
1279 head
= pipe_crc
->head
;
1280 tail
= pipe_crc
->tail
;
1282 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1283 spin_unlock(&pipe_crc
->lock
);
1284 DRM_ERROR("CRC buffer overflowing\n");
1288 entry
= &pipe_crc
->entries
[head
];
1290 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1291 entry
->crc
[0] = crc0
;
1292 entry
->crc
[1] = crc1
;
1293 entry
->crc
[2] = crc2
;
1294 entry
->crc
[3] = crc3
;
1295 entry
->crc
[4] = crc4
;
1297 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1298 pipe_crc
->head
= head
;
1300 spin_unlock(&pipe_crc
->lock
);
1302 wake_up_interruptible(&pipe_crc
->wq
);
1306 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1307 uint32_t crc0
, uint32_t crc1
,
1308 uint32_t crc2
, uint32_t crc3
,
1313 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1317 display_pipe_crc_irq_handler(dev
, pipe
,
1318 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1322 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1326 display_pipe_crc_irq_handler(dev
, pipe
,
1327 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1328 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1329 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1330 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1331 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1334 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1337 uint32_t res1
, res2
;
1339 if (INTEL_INFO(dev
)->gen
>= 3)
1340 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1344 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1345 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1349 display_pipe_crc_irq_handler(dev
, pipe
,
1350 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1351 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1352 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1356 /* The RPS events need forcewake, so we add them to a work queue and mask their
1357 * IMR bits until the work is done. Other interrupts can be processed without
1358 * the work queue. */
1359 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1361 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1362 spin_lock(&dev_priv
->irq_lock
);
1363 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1364 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1365 spin_unlock(&dev_priv
->irq_lock
);
1367 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1370 if (HAS_VEBOX(dev_priv
->dev
)) {
1371 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1372 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1374 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1375 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1376 i915_handle_error(dev_priv
->dev
, false);
1381 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1383 struct drm_device
*dev
= (struct drm_device
*) arg
;
1384 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1385 u32 iir
, gt_iir
, pm_iir
;
1386 irqreturn_t ret
= IRQ_NONE
;
1387 unsigned long irqflags
;
1389 u32 pipe_stats
[I915_MAX_PIPES
];
1391 atomic_inc(&dev_priv
->irq_received
);
1394 iir
= I915_READ(VLV_IIR
);
1395 gt_iir
= I915_READ(GTIIR
);
1396 pm_iir
= I915_READ(GEN6_PMIIR
);
1398 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1403 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1405 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1406 for_each_pipe(pipe
) {
1407 int reg
= PIPESTAT(pipe
);
1408 pipe_stats
[pipe
] = I915_READ(reg
);
1411 * Clear the PIPE*STAT regs before the IIR
1413 if (pipe_stats
[pipe
] & 0x8000ffff) {
1414 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1415 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1417 I915_WRITE(reg
, pipe_stats
[pipe
]);
1420 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1422 for_each_pipe(pipe
) {
1423 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1424 drm_handle_vblank(dev
, pipe
);
1426 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1427 intel_prepare_page_flip(dev
, pipe
);
1428 intel_finish_page_flip(dev
, pipe
);
1431 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1432 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1435 /* Consume port. Then clear IIR or we'll miss events */
1436 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1437 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1438 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1440 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1443 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1445 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1446 I915_READ(PORT_HOTPLUG_STAT
);
1449 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1450 gmbus_irq_handler(dev
);
1453 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1455 I915_WRITE(GTIIR
, gt_iir
);
1456 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1457 I915_WRITE(VLV_IIR
, iir
);
1464 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1466 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1468 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1470 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1472 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1473 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1474 SDE_AUDIO_POWER_SHIFT
);
1475 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1479 if (pch_iir
& SDE_AUX_MASK
)
1480 dp_aux_irq_handler(dev
);
1482 if (pch_iir
& SDE_GMBUS
)
1483 gmbus_irq_handler(dev
);
1485 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1486 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1488 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1489 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1491 if (pch_iir
& SDE_POISON
)
1492 DRM_ERROR("PCH poison interrupt\n");
1494 if (pch_iir
& SDE_FDI_MASK
)
1496 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1498 I915_READ(FDI_RX_IIR(pipe
)));
1500 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1501 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1503 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1504 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1506 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1507 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1509 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1511 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1512 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1514 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1517 static void ivb_err_int_handler(struct drm_device
*dev
)
1519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1523 if (err_int
& ERR_INT_POISON
)
1524 DRM_ERROR("Poison interrupt\n");
1526 for_each_pipe(pipe
) {
1527 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) {
1528 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1530 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1534 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1535 if (IS_IVYBRIDGE(dev
))
1536 ivb_pipe_crc_irq_handler(dev
, pipe
);
1538 hsw_pipe_crc_irq_handler(dev
, pipe
);
1542 I915_WRITE(GEN7_ERR_INT
, err_int
);
1545 static void cpt_serr_int_handler(struct drm_device
*dev
)
1547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1548 u32 serr_int
= I915_READ(SERR_INT
);
1550 if (serr_int
& SERR_INT_POISON
)
1551 DRM_ERROR("PCH poison interrupt\n");
1553 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1554 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1556 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1558 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1559 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1561 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1563 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1564 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1566 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1568 I915_WRITE(SERR_INT
, serr_int
);
1571 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1573 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1575 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1577 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1579 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1580 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1581 SDE_AUDIO_POWER_SHIFT_CPT
);
1582 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1586 if (pch_iir
& SDE_AUX_MASK_CPT
)
1587 dp_aux_irq_handler(dev
);
1589 if (pch_iir
& SDE_GMBUS_CPT
)
1590 gmbus_irq_handler(dev
);
1592 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1593 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1595 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1596 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1598 if (pch_iir
& SDE_FDI_MASK_CPT
)
1600 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1602 I915_READ(FDI_RX_IIR(pipe
)));
1604 if (pch_iir
& SDE_ERROR_CPT
)
1605 cpt_serr_int_handler(dev
);
1608 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 if (de_iir
& DE_AUX_CHANNEL_A
)
1614 dp_aux_irq_handler(dev
);
1616 if (de_iir
& DE_GSE
)
1617 intel_opregion_asle_intr(dev
);
1619 if (de_iir
& DE_POISON
)
1620 DRM_ERROR("Poison interrupt\n");
1622 for_each_pipe(pipe
) {
1623 if (de_iir
& DE_PIPE_VBLANK(pipe
))
1624 drm_handle_vblank(dev
, pipe
);
1626 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
1627 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1628 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1631 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
1632 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1634 /* plane/pipes map 1:1 on ilk+ */
1635 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
1636 intel_prepare_page_flip(dev
, pipe
);
1637 intel_finish_page_flip_plane(dev
, pipe
);
1641 /* check event from PCH */
1642 if (de_iir
& DE_PCH_EVENT
) {
1643 u32 pch_iir
= I915_READ(SDEIIR
);
1645 if (HAS_PCH_CPT(dev
))
1646 cpt_irq_handler(dev
, pch_iir
);
1648 ibx_irq_handler(dev
, pch_iir
);
1650 /* should clear PCH hotplug event before clear CPU irq */
1651 I915_WRITE(SDEIIR
, pch_iir
);
1654 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1655 ironlake_rps_change_irq_handler(dev
);
1658 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1663 if (de_iir
& DE_ERR_INT_IVB
)
1664 ivb_err_int_handler(dev
);
1666 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1667 dp_aux_irq_handler(dev
);
1669 if (de_iir
& DE_GSE_IVB
)
1670 intel_opregion_asle_intr(dev
);
1673 if (de_iir
& (DE_PIPE_VBLANK_IVB(i
)))
1674 drm_handle_vblank(dev
, i
);
1676 /* plane/pipes map 1:1 on ilk+ */
1677 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(i
)) {
1678 intel_prepare_page_flip(dev
, i
);
1679 intel_finish_page_flip_plane(dev
, i
);
1683 /* check event from PCH */
1684 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1685 u32 pch_iir
= I915_READ(SDEIIR
);
1687 cpt_irq_handler(dev
, pch_iir
);
1689 /* clear PCH hotplug event before clear CPU irq */
1690 I915_WRITE(SDEIIR
, pch_iir
);
1694 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1696 struct drm_device
*dev
= (struct drm_device
*) arg
;
1697 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1698 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1699 irqreturn_t ret
= IRQ_NONE
;
1701 atomic_inc(&dev_priv
->irq_received
);
1703 /* We get interrupts on unclaimed registers, so check for this before we
1704 * do any I915_{READ,WRITE}. */
1705 intel_uncore_check_errors(dev
);
1707 /* disable master interrupt before clearing iir */
1708 de_ier
= I915_READ(DEIER
);
1709 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1710 POSTING_READ(DEIER
);
1712 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1713 * interrupts will will be stored on its back queue, and then we'll be
1714 * able to process them after we restore SDEIER (as soon as we restore
1715 * it, we'll get an interrupt if SDEIIR still has something to process
1716 * due to its back queue). */
1717 if (!HAS_PCH_NOP(dev
)) {
1718 sde_ier
= I915_READ(SDEIER
);
1719 I915_WRITE(SDEIER
, 0);
1720 POSTING_READ(SDEIER
);
1723 gt_iir
= I915_READ(GTIIR
);
1725 if (INTEL_INFO(dev
)->gen
>= 6)
1726 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1728 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1729 I915_WRITE(GTIIR
, gt_iir
);
1733 de_iir
= I915_READ(DEIIR
);
1735 if (INTEL_INFO(dev
)->gen
>= 7)
1736 ivb_display_irq_handler(dev
, de_iir
);
1738 ilk_display_irq_handler(dev
, de_iir
);
1739 I915_WRITE(DEIIR
, de_iir
);
1743 if (INTEL_INFO(dev
)->gen
>= 6) {
1744 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1746 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1747 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1752 I915_WRITE(DEIER
, de_ier
);
1753 POSTING_READ(DEIER
);
1754 if (!HAS_PCH_NOP(dev
)) {
1755 I915_WRITE(SDEIER
, sde_ier
);
1756 POSTING_READ(SDEIER
);
1762 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
1764 struct drm_device
*dev
= arg
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1767 irqreturn_t ret
= IRQ_NONE
;
1771 atomic_inc(&dev_priv
->irq_received
);
1773 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
1774 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
1778 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1779 POSTING_READ(GEN8_MASTER_IRQ
);
1781 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1783 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
1784 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
1785 if (tmp
& GEN8_DE_MISC_GSE
)
1786 intel_opregion_asle_intr(dev
);
1788 DRM_ERROR("Unexpected DE Misc interrupt\n");
1790 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1793 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
1798 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
1799 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
1800 if (tmp
& GEN8_AUX_CHANNEL_A
)
1801 dp_aux_irq_handler(dev
);
1803 DRM_ERROR("Unexpected DE Port interrupt\n");
1805 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1808 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
1813 for_each_pipe(pipe
) {
1816 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
1819 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
1820 if (pipe_iir
& GEN8_PIPE_VBLANK
)
1821 drm_handle_vblank(dev
, pipe
);
1823 if (pipe_iir
& GEN8_PIPE_FLIP_DONE
) {
1824 intel_prepare_page_flip(dev
, pipe
);
1825 intel_finish_page_flip_plane(dev
, pipe
);
1828 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
1829 hsw_pipe_crc_irq_handler(dev
, pipe
);
1831 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
) {
1832 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1834 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1838 if (pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
) {
1839 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1841 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
1846 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
1848 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1851 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
1853 * FIXME(BDW): Assume for now that the new interrupt handling
1854 * scheme also closed the SDE interrupt handling race we've seen
1855 * on older pch-split platforms. But this needs testing.
1857 u32 pch_iir
= I915_READ(SDEIIR
);
1859 cpt_irq_handler(dev
, pch_iir
);
1862 I915_WRITE(SDEIIR
, pch_iir
);
1867 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1868 POSTING_READ(GEN8_MASTER_IRQ
);
1873 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1874 bool reset_completed
)
1876 struct intel_ring_buffer
*ring
;
1880 * Notify all waiters for GPU completion events that reset state has
1881 * been changed, and that they need to restart their wait after
1882 * checking for potential errors (and bail out to drop locks if there is
1883 * a gpu reset pending so that i915_error_work_func can acquire them).
1886 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1887 for_each_ring(ring
, dev_priv
, i
)
1888 wake_up_all(&ring
->irq_queue
);
1890 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1891 wake_up_all(&dev_priv
->pending_flip_queue
);
1894 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1895 * reset state is cleared.
1897 if (reset_completed
)
1898 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1902 * i915_error_work_func - do process context error handling work
1903 * @work: work struct
1905 * Fire an error uevent so userspace can see that a hang or error
1908 static void i915_error_work_func(struct work_struct
*work
)
1910 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1912 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1914 struct drm_device
*dev
= dev_priv
->dev
;
1915 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1916 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1917 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1920 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1923 * Note that there's only one work item which does gpu resets, so we
1924 * need not worry about concurrent gpu resets potentially incrementing
1925 * error->reset_counter twice. We only need to take care of another
1926 * racing irq/hangcheck declaring the gpu dead for a second time. A
1927 * quick check for that is good enough: schedule_work ensures the
1928 * correct ordering between hang detection and this work item, and since
1929 * the reset in-progress bit is only ever set by code outside of this
1930 * work we don't need to worry about any other races.
1932 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1933 DRM_DEBUG_DRIVER("resetting chip\n");
1934 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1938 * All state reset _must_ be completed before we update the
1939 * reset counter, for otherwise waiters might miss the reset
1940 * pending state and not properly drop locks, resulting in
1941 * deadlocks with the reset work.
1943 ret
= i915_reset(dev
);
1945 intel_display_handle_reset(dev
);
1949 * After all the gem state is reset, increment the reset
1950 * counter and wake up everyone waiting for the reset to
1953 * Since unlock operations are a one-sided barrier only,
1954 * we need to insert a barrier here to order any seqno
1956 * the counter increment.
1958 smp_mb__before_atomic_inc();
1959 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1961 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1962 KOBJ_CHANGE
, reset_done_event
);
1964 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1968 * Note: The wake_up also serves as a memory barrier so that
1969 * waiters see the update value of the reset counter atomic_t.
1971 i915_error_wake_up(dev_priv
, true);
1975 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1978 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1979 u32 eir
= I915_READ(EIR
);
1985 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1987 i915_get_extra_instdone(dev
, instdone
);
1990 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1991 u32 ipeir
= I915_READ(IPEIR_I965
);
1993 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1994 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1995 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1996 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1997 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1998 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1999 I915_WRITE(IPEIR_I965
, ipeir
);
2000 POSTING_READ(IPEIR_I965
);
2002 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2003 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2004 pr_err("page table error\n");
2005 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2006 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2007 POSTING_READ(PGTBL_ER
);
2011 if (!IS_GEN2(dev
)) {
2012 if (eir
& I915_ERROR_PAGE_TABLE
) {
2013 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2014 pr_err("page table error\n");
2015 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2016 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2017 POSTING_READ(PGTBL_ER
);
2021 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2022 pr_err("memory refresh error:\n");
2024 pr_err("pipe %c stat: 0x%08x\n",
2025 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2026 /* pipestat has already been acked */
2028 if (eir
& I915_ERROR_INSTRUCTION
) {
2029 pr_err("instruction error\n");
2030 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2031 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2032 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2033 if (INTEL_INFO(dev
)->gen
< 4) {
2034 u32 ipeir
= I915_READ(IPEIR
);
2036 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2037 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2038 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2039 I915_WRITE(IPEIR
, ipeir
);
2040 POSTING_READ(IPEIR
);
2042 u32 ipeir
= I915_READ(IPEIR_I965
);
2044 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2045 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2046 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2047 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2048 I915_WRITE(IPEIR_I965
, ipeir
);
2049 POSTING_READ(IPEIR_I965
);
2053 I915_WRITE(EIR
, eir
);
2055 eir
= I915_READ(EIR
);
2058 * some errors might have become stuck,
2061 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2062 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2063 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2068 * i915_handle_error - handle an error interrupt
2071 * Do some basic checking of regsiter state at error interrupt time and
2072 * dump it to the syslog. Also call i915_capture_error_state() to make
2073 * sure we get a record and make it available in debugfs. Fire a uevent
2074 * so userspace knows something bad happened (should trigger collection
2075 * of a ring dump etc.).
2077 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
2079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2081 i915_capture_error_state(dev
);
2082 i915_report_and_clear_eir(dev
);
2085 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2086 &dev_priv
->gpu_error
.reset_counter
);
2089 * Wakeup waiting processes so that the reset work function
2090 * i915_error_work_func doesn't deadlock trying to grab various
2091 * locks. By bumping the reset counter first, the woken
2092 * processes will see a reset in progress and back off,
2093 * releasing their locks and then wait for the reset completion.
2094 * We must do this for _all_ gpu waiters that might hold locks
2095 * that the reset work needs to acquire.
2097 * Note: The wake_up serves as the required memory barrier to
2098 * ensure that the waiters see the updated value of the reset
2101 i915_error_wake_up(dev_priv
, false);
2105 * Our reset work can grab modeset locks (since it needs to reset the
2106 * state of outstanding pagelips). Hence it must not be run on our own
2107 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2108 * code will deadlock.
2110 schedule_work(&dev_priv
->gpu_error
.work
);
2113 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2115 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2116 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2118 struct drm_i915_gem_object
*obj
;
2119 struct intel_unpin_work
*work
;
2120 unsigned long flags
;
2121 bool stall_detected
;
2123 /* Ignore early vblank irqs */
2124 if (intel_crtc
== NULL
)
2127 spin_lock_irqsave(&dev
->event_lock
, flags
);
2128 work
= intel_crtc
->unpin_work
;
2131 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2132 !work
->enable_stall_check
) {
2133 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2134 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2138 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2139 obj
= work
->pending_flip_obj
;
2140 if (INTEL_INFO(dev
)->gen
>= 4) {
2141 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2142 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2143 i915_gem_obj_ggtt_offset(obj
);
2145 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2146 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2147 crtc
->y
* crtc
->fb
->pitches
[0] +
2148 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2151 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2153 if (stall_detected
) {
2154 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2155 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2159 /* Called from drm generic code, passed 'crtc' which
2160 * we use as a pipe index
2162 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2164 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2165 unsigned long irqflags
;
2167 if (!i915_pipe_enabled(dev
, pipe
))
2170 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2171 if (INTEL_INFO(dev
)->gen
>= 4)
2172 i915_enable_pipestat(dev_priv
, pipe
,
2173 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2175 i915_enable_pipestat(dev_priv
, pipe
,
2176 PIPE_VBLANK_INTERRUPT_ENABLE
);
2178 /* maintain vblank delivery even in deep C-states */
2179 if (dev_priv
->info
->gen
== 3)
2180 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2181 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2186 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2188 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2189 unsigned long irqflags
;
2190 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2191 DE_PIPE_VBLANK(pipe
);
2193 if (!i915_pipe_enabled(dev
, pipe
))
2196 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2197 ironlake_enable_display_irq(dev_priv
, bit
);
2198 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2203 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2205 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2206 unsigned long irqflags
;
2209 if (!i915_pipe_enabled(dev
, pipe
))
2212 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2213 imr
= I915_READ(VLV_IMR
);
2215 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2217 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2218 I915_WRITE(VLV_IMR
, imr
);
2219 i915_enable_pipestat(dev_priv
, pipe
,
2220 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2221 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2226 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 unsigned long irqflags
;
2231 if (!i915_pipe_enabled(dev
, pipe
))
2234 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2235 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2236 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2237 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2238 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2242 /* Called from drm generic code, passed 'crtc' which
2243 * we use as a pipe index
2245 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2247 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2248 unsigned long irqflags
;
2250 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2251 if (dev_priv
->info
->gen
== 3)
2252 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2254 i915_disable_pipestat(dev_priv
, pipe
,
2255 PIPE_VBLANK_INTERRUPT_ENABLE
|
2256 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2257 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2260 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2262 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2263 unsigned long irqflags
;
2264 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2265 DE_PIPE_VBLANK(pipe
);
2267 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2268 ironlake_disable_display_irq(dev_priv
, bit
);
2269 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2272 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2274 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2275 unsigned long irqflags
;
2278 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2279 i915_disable_pipestat(dev_priv
, pipe
,
2280 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2281 imr
= I915_READ(VLV_IMR
);
2283 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2285 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2286 I915_WRITE(VLV_IMR
, imr
);
2287 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2290 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2293 unsigned long irqflags
;
2295 if (!i915_pipe_enabled(dev
, pipe
))
2298 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2299 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2300 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2301 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2302 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2306 ring_last_seqno(struct intel_ring_buffer
*ring
)
2308 return list_entry(ring
->request_list
.prev
,
2309 struct drm_i915_gem_request
, list
)->seqno
;
2313 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2315 return (list_empty(&ring
->request_list
) ||
2316 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2319 static struct intel_ring_buffer
*
2320 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2322 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2323 u32 cmd
, ipehr
, acthd
, acthd_min
;
2325 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2326 if ((ipehr
& ~(0x3 << 16)) !=
2327 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2330 /* ACTHD is likely pointing to the dword after the actual command,
2331 * so scan backwards until we find the MBOX.
2333 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2334 acthd_min
= max((int)acthd
- 3 * 4, 0);
2336 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2341 if (acthd
< acthd_min
)
2345 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2346 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2349 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2351 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2352 struct intel_ring_buffer
*signaller
;
2355 ring
->hangcheck
.deadlock
= true;
2357 signaller
= semaphore_waits_for(ring
, &seqno
);
2358 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2361 /* cursory check for an unkickable deadlock */
2362 ctl
= I915_READ_CTL(signaller
);
2363 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2366 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2369 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2371 struct intel_ring_buffer
*ring
;
2374 for_each_ring(ring
, dev_priv
, i
)
2375 ring
->hangcheck
.deadlock
= false;
2378 static enum intel_ring_hangcheck_action
2379 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2381 struct drm_device
*dev
= ring
->dev
;
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2385 if (ring
->hangcheck
.acthd
!= acthd
)
2386 return HANGCHECK_ACTIVE
;
2389 return HANGCHECK_HUNG
;
2391 /* Is the chip hanging on a WAIT_FOR_EVENT?
2392 * If so we can simply poke the RB_WAIT bit
2393 * and break the hang. This should work on
2394 * all but the second generation chipsets.
2396 tmp
= I915_READ_CTL(ring
);
2397 if (tmp
& RING_WAIT
) {
2398 DRM_ERROR("Kicking stuck wait on %s\n",
2400 i915_handle_error(dev
, false);
2401 I915_WRITE_CTL(ring
, tmp
);
2402 return HANGCHECK_KICK
;
2405 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2406 switch (semaphore_passed(ring
)) {
2408 return HANGCHECK_HUNG
;
2410 DRM_ERROR("Kicking stuck semaphore on %s\n",
2412 i915_handle_error(dev
, false);
2413 I915_WRITE_CTL(ring
, tmp
);
2414 return HANGCHECK_KICK
;
2416 return HANGCHECK_WAIT
;
2420 return HANGCHECK_HUNG
;
2424 * This is called when the chip hasn't reported back with completed
2425 * batchbuffers in a long time. We keep track per ring seqno progress and
2426 * if there are no progress, hangcheck score for that ring is increased.
2427 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2428 * we kick the ring. If we see no progress on three subsequent calls
2429 * we assume chip is wedged and try to fix it by resetting the chip.
2431 static void i915_hangcheck_elapsed(unsigned long data
)
2433 struct drm_device
*dev
= (struct drm_device
*)data
;
2434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2435 struct intel_ring_buffer
*ring
;
2437 int busy_count
= 0, rings_hung
= 0;
2438 bool stuck
[I915_NUM_RINGS
] = { 0 };
2444 if (!i915_enable_hangcheck
)
2447 for_each_ring(ring
, dev_priv
, i
) {
2451 semaphore_clear_deadlocks(dev_priv
);
2453 seqno
= ring
->get_seqno(ring
, false);
2454 acthd
= intel_ring_get_active_head(ring
);
2456 if (ring
->hangcheck
.seqno
== seqno
) {
2457 if (ring_idle(ring
, seqno
)) {
2458 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2460 if (waitqueue_active(&ring
->irq_queue
)) {
2461 /* Issue a wake-up to catch stuck h/w. */
2462 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2463 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2464 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2467 DRM_INFO("Fake missed irq on %s\n",
2469 wake_up_all(&ring
->irq_queue
);
2471 /* Safeguard against driver failure */
2472 ring
->hangcheck
.score
+= BUSY
;
2476 /* We always increment the hangcheck score
2477 * if the ring is busy and still processing
2478 * the same request, so that no single request
2479 * can run indefinitely (such as a chain of
2480 * batches). The only time we do not increment
2481 * the hangcheck score on this ring, if this
2482 * ring is in a legitimate wait for another
2483 * ring. In that case the waiting ring is a
2484 * victim and we want to be sure we catch the
2485 * right culprit. Then every time we do kick
2486 * the ring, add a small increment to the
2487 * score so that we can catch a batch that is
2488 * being repeatedly kicked and so responsible
2489 * for stalling the machine.
2491 ring
->hangcheck
.action
= ring_stuck(ring
,
2494 switch (ring
->hangcheck
.action
) {
2495 case HANGCHECK_IDLE
:
2496 case HANGCHECK_WAIT
:
2498 case HANGCHECK_ACTIVE
:
2499 ring
->hangcheck
.score
+= BUSY
;
2501 case HANGCHECK_KICK
:
2502 ring
->hangcheck
.score
+= KICK
;
2504 case HANGCHECK_HUNG
:
2505 ring
->hangcheck
.score
+= HUNG
;
2511 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2513 /* Gradually reduce the count so that we catch DoS
2514 * attempts across multiple batches.
2516 if (ring
->hangcheck
.score
> 0)
2517 ring
->hangcheck
.score
--;
2520 ring
->hangcheck
.seqno
= seqno
;
2521 ring
->hangcheck
.acthd
= acthd
;
2525 for_each_ring(ring
, dev_priv
, i
) {
2526 if (ring
->hangcheck
.score
> FIRE
) {
2527 DRM_INFO("%s on %s\n",
2528 stuck
[i
] ? "stuck" : "no progress",
2535 return i915_handle_error(dev
, true);
2538 /* Reset timer case chip hangs without another request
2540 i915_queue_hangcheck(dev
);
2543 void i915_queue_hangcheck(struct drm_device
*dev
)
2545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2546 if (!i915_enable_hangcheck
)
2549 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2550 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2553 static void ibx_irq_preinstall(struct drm_device
*dev
)
2555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2557 if (HAS_PCH_NOP(dev
))
2560 /* south display irq */
2561 I915_WRITE(SDEIMR
, 0xffffffff);
2563 * SDEIER is also touched by the interrupt handler to work around missed
2564 * PCH interrupts. Hence we can't update it after the interrupt handler
2565 * is enabled - instead we unconditionally enable all PCH interrupt
2566 * sources here, but then only unmask them as needed with SDEIMR.
2568 I915_WRITE(SDEIER
, 0xffffffff);
2569 POSTING_READ(SDEIER
);
2572 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 I915_WRITE(GTIMR
, 0xffffffff);
2578 I915_WRITE(GTIER
, 0x0);
2579 POSTING_READ(GTIER
);
2581 if (INTEL_INFO(dev
)->gen
>= 6) {
2583 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2584 I915_WRITE(GEN6_PMIER
, 0x0);
2585 POSTING_READ(GEN6_PMIER
);
2591 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2593 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2595 atomic_set(&dev_priv
->irq_received
, 0);
2597 I915_WRITE(HWSTAM
, 0xeffe);
2599 I915_WRITE(DEIMR
, 0xffffffff);
2600 I915_WRITE(DEIER
, 0x0);
2601 POSTING_READ(DEIER
);
2603 gen5_gt_irq_preinstall(dev
);
2605 ibx_irq_preinstall(dev
);
2608 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2610 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2613 atomic_set(&dev_priv
->irq_received
, 0);
2616 I915_WRITE(VLV_IMR
, 0);
2617 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2618 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2619 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2622 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2623 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2625 gen5_gt_irq_preinstall(dev
);
2627 I915_WRITE(DPINVGTT
, 0xff);
2629 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2630 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2632 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2633 I915_WRITE(VLV_IIR
, 0xffffffff);
2634 I915_WRITE(VLV_IMR
, 0xffffffff);
2635 I915_WRITE(VLV_IER
, 0x0);
2636 POSTING_READ(VLV_IER
);
2639 static void gen8_irq_preinstall(struct drm_device
*dev
)
2641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2644 atomic_set(&dev_priv
->irq_received
, 0);
2646 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2647 POSTING_READ(GEN8_MASTER_IRQ
);
2649 /* IIR can theoretically queue up two events. Be paranoid */
2650 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2651 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2652 POSTING_READ(GEN8_##type##_IMR(which)); \
2653 I915_WRITE(GEN8_##type##_IER(which), 0); \
2654 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2655 POSTING_READ(GEN8_##type##_IIR(which)); \
2656 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2659 #define GEN8_IRQ_INIT(type) do { \
2660 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2661 POSTING_READ(GEN8_##type##_IMR); \
2662 I915_WRITE(GEN8_##type##_IER, 0); \
2663 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2664 POSTING_READ(GEN8_##type##_IIR); \
2665 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2668 GEN8_IRQ_INIT_NDX(GT
, 0);
2669 GEN8_IRQ_INIT_NDX(GT
, 1);
2670 GEN8_IRQ_INIT_NDX(GT
, 2);
2671 GEN8_IRQ_INIT_NDX(GT
, 3);
2673 for_each_pipe(pipe
) {
2674 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
);
2677 GEN8_IRQ_INIT(DE_PORT
);
2678 GEN8_IRQ_INIT(DE_MISC
);
2680 #undef GEN8_IRQ_INIT
2681 #undef GEN8_IRQ_INIT_NDX
2683 POSTING_READ(GEN8_PCU_IIR
);
2686 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2688 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2689 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2690 struct intel_encoder
*intel_encoder
;
2691 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2693 if (HAS_PCH_IBX(dev
)) {
2694 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2695 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2696 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2697 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2699 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2700 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2701 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2702 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2705 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2708 * Enable digital hotplug on the PCH, and configure the DP short pulse
2709 * duration to 2ms (which is the minimum in the Display Port spec)
2711 * This register is the same on all known PCH chips.
2713 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2714 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2715 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2716 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2717 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2718 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2721 static void ibx_irq_postinstall(struct drm_device
*dev
)
2723 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2726 if (HAS_PCH_NOP(dev
))
2729 if (HAS_PCH_IBX(dev
)) {
2730 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2731 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2733 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2735 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2738 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2739 I915_WRITE(SDEIMR
, ~mask
);
2742 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2745 u32 pm_irqs
, gt_irqs
;
2747 pm_irqs
= gt_irqs
= 0;
2749 dev_priv
->gt_irq_mask
= ~0;
2750 if (HAS_L3_DPF(dev
)) {
2751 /* L3 parity interrupt is always unmasked. */
2752 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2753 gt_irqs
|= GT_PARITY_ERROR(dev
);
2756 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2758 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2759 ILK_BSD_USER_INTERRUPT
;
2761 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2764 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2765 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2766 I915_WRITE(GTIER
, gt_irqs
);
2767 POSTING_READ(GTIER
);
2769 if (INTEL_INFO(dev
)->gen
>= 6) {
2770 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2773 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2775 dev_priv
->pm_irq_mask
= 0xffffffff;
2776 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2777 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2778 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2779 POSTING_READ(GEN6_PMIER
);
2783 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2785 unsigned long irqflags
;
2786 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2787 u32 display_mask
, extra_mask
;
2789 if (INTEL_INFO(dev
)->gen
>= 7) {
2790 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2791 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2792 DE_PLANEB_FLIP_DONE_IVB
|
2793 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2795 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2796 DE_PIPEA_VBLANK_IVB
);
2798 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2800 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2801 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2803 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
2804 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
2806 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2809 dev_priv
->irq_mask
= ~display_mask
;
2811 /* should always can generate irq */
2812 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2813 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2814 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2815 POSTING_READ(DEIER
);
2817 gen5_gt_irq_postinstall(dev
);
2819 ibx_irq_postinstall(dev
);
2821 if (IS_IRONLAKE_M(dev
)) {
2822 /* Enable PCU event interrupts
2824 * spinlocking not required here for correctness since interrupt
2825 * setup is guaranteed to run in single-threaded context. But we
2826 * need it to make the assert_spin_locked happy. */
2827 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2828 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2829 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2835 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2837 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2839 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
|
2840 PIPE_CRC_DONE_ENABLE
;
2841 unsigned long irqflags
;
2843 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2844 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2845 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2846 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2847 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2850 *Leave vblank interrupts masked initially. enable/disable will
2851 * toggle them based on usage.
2853 dev_priv
->irq_mask
= (~enable_mask
) |
2854 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2855 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2857 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2858 POSTING_READ(PORT_HOTPLUG_EN
);
2860 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2861 I915_WRITE(VLV_IER
, enable_mask
);
2862 I915_WRITE(VLV_IIR
, 0xffffffff);
2863 I915_WRITE(PIPESTAT(0), 0xffff);
2864 I915_WRITE(PIPESTAT(1), 0xffff);
2865 POSTING_READ(VLV_IER
);
2867 /* Interrupt setup is already guaranteed to be single-threaded, this is
2868 * just to make the assert_spin_locked check happy. */
2869 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2870 i915_enable_pipestat(dev_priv
, PIPE_A
, pipestat_enable
);
2871 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_EVENT_ENABLE
);
2872 i915_enable_pipestat(dev_priv
, PIPE_B
, pipestat_enable
);
2873 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2875 I915_WRITE(VLV_IIR
, 0xffffffff);
2876 I915_WRITE(VLV_IIR
, 0xffffffff);
2878 gen5_gt_irq_postinstall(dev
);
2880 /* ack & enable invalid PTE error interrupts */
2881 #if 0 /* FIXME: add support to irq handler for checking these bits */
2882 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2883 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2886 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2891 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
2895 /* These are interrupts we'll toggle with the ring mask register */
2896 uint32_t gt_interrupts
[] = {
2897 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
2898 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
2899 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
2900 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
2901 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
2903 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
2906 for (i
= 0; i
< ARRAY_SIZE(gt_interrupts
); i
++) {
2907 u32 tmp
= I915_READ(GEN8_GT_IIR(i
));
2909 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2911 I915_WRITE(GEN8_GT_IMR(i
), ~gt_interrupts
[i
]);
2912 I915_WRITE(GEN8_GT_IER(i
), gt_interrupts
[i
]);
2914 POSTING_READ(GEN8_GT_IER(0));
2917 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
2919 struct drm_device
*dev
= dev_priv
->dev
;
2920 uint32_t de_pipe_masked
= GEN8_PIPE_FLIP_DONE
|
2921 GEN8_PIPE_CDCLK_CRC_DONE
|
2922 GEN8_PIPE_FIFO_UNDERRUN
|
2923 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2924 uint32_t de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
;
2926 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
2927 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
2928 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
2930 for_each_pipe(pipe
) {
2931 u32 tmp
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2933 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2935 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2936 I915_WRITE(GEN8_DE_PIPE_IER(pipe
), de_pipe_enables
);
2938 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2940 I915_WRITE(GEN8_DE_PORT_IMR
, ~GEN8_AUX_CHANNEL_A
);
2941 I915_WRITE(GEN8_DE_PORT_IER
, GEN8_AUX_CHANNEL_A
);
2942 POSTING_READ(GEN8_DE_PORT_IER
);
2945 static int gen8_irq_postinstall(struct drm_device
*dev
)
2947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2949 gen8_gt_irq_postinstall(dev_priv
);
2950 gen8_de_irq_postinstall(dev_priv
);
2952 ibx_irq_postinstall(dev
);
2954 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
2955 POSTING_READ(GEN8_MASTER_IRQ
);
2960 static void gen8_irq_uninstall(struct drm_device
*dev
)
2962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2968 atomic_set(&dev_priv
->irq_received
, 0);
2970 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2972 #define GEN8_IRQ_FINI_NDX(type, which) do { \
2973 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2974 I915_WRITE(GEN8_##type##_IER(which), 0); \
2975 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2978 #define GEN8_IRQ_FINI(type) do { \
2979 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2980 I915_WRITE(GEN8_##type##_IER, 0); \
2981 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2984 GEN8_IRQ_FINI_NDX(GT
, 0);
2985 GEN8_IRQ_FINI_NDX(GT
, 1);
2986 GEN8_IRQ_FINI_NDX(GT
, 2);
2987 GEN8_IRQ_FINI_NDX(GT
, 3);
2989 for_each_pipe(pipe
) {
2990 GEN8_IRQ_FINI_NDX(DE_PIPE
, pipe
);
2993 GEN8_IRQ_FINI(DE_PORT
);
2994 GEN8_IRQ_FINI(DE_MISC
);
2996 #undef GEN8_IRQ_FINI
2997 #undef GEN8_IRQ_FINI_NDX
2999 POSTING_READ(GEN8_PCU_IIR
);
3002 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3004 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3010 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3013 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3015 I915_WRITE(HWSTAM
, 0xffffffff);
3016 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3017 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3019 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3020 I915_WRITE(VLV_IIR
, 0xffffffff);
3021 I915_WRITE(VLV_IMR
, 0xffffffff);
3022 I915_WRITE(VLV_IER
, 0x0);
3023 POSTING_READ(VLV_IER
);
3026 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3028 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3033 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3035 I915_WRITE(HWSTAM
, 0xffffffff);
3037 I915_WRITE(DEIMR
, 0xffffffff);
3038 I915_WRITE(DEIER
, 0x0);
3039 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
3041 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
3043 I915_WRITE(GTIMR
, 0xffffffff);
3044 I915_WRITE(GTIER
, 0x0);
3045 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
3047 if (HAS_PCH_NOP(dev
))
3050 I915_WRITE(SDEIMR
, 0xffffffff);
3051 I915_WRITE(SDEIER
, 0x0);
3052 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
3053 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3054 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
3057 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3059 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3062 atomic_set(&dev_priv
->irq_received
, 0);
3065 I915_WRITE(PIPESTAT(pipe
), 0);
3066 I915_WRITE16(IMR
, 0xffff);
3067 I915_WRITE16(IER
, 0x0);
3068 POSTING_READ16(IER
);
3071 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3073 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3074 unsigned long irqflags
;
3077 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3079 /* Unmask the interrupts that we always want on. */
3080 dev_priv
->irq_mask
=
3081 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3082 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3083 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3084 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3085 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3086 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3089 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3090 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3091 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3092 I915_USER_INTERRUPT
);
3093 POSTING_READ16(IER
);
3095 /* Interrupt setup is already guaranteed to be single-threaded, this is
3096 * just to make the assert_spin_locked check happy. */
3097 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3098 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
3099 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
3100 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3106 * Returns true when a page flip has completed.
3108 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3111 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3112 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
3114 if (!drm_handle_vblank(dev
, pipe
))
3117 if ((iir
& flip_pending
) == 0)
3120 intel_prepare_page_flip(dev
, pipe
);
3122 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3123 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3124 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3125 * the flip is completed (no longer pending). Since this doesn't raise
3126 * an interrupt per se, we watch for the change at vblank.
3128 if (I915_READ16(ISR
) & flip_pending
)
3131 intel_finish_page_flip(dev
, pipe
);
3136 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3138 struct drm_device
*dev
= (struct drm_device
*) arg
;
3139 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3142 unsigned long irqflags
;
3145 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3146 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3148 atomic_inc(&dev_priv
->irq_received
);
3150 iir
= I915_READ16(IIR
);
3154 while (iir
& ~flip_mask
) {
3155 /* Can't rely on pipestat interrupt bit in iir as it might
3156 * have been cleared after the pipestat interrupt was received.
3157 * It doesn't set the bit in iir again, but it still produces
3158 * interrupts (for non-MSI).
3160 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3161 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3162 i915_handle_error(dev
, false);
3164 for_each_pipe(pipe
) {
3165 int reg
= PIPESTAT(pipe
);
3166 pipe_stats
[pipe
] = I915_READ(reg
);
3169 * Clear the PIPE*STAT regs before the IIR
3171 if (pipe_stats
[pipe
] & 0x8000ffff) {
3172 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3173 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3175 I915_WRITE(reg
, pipe_stats
[pipe
]);
3178 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3180 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3181 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3183 i915_update_dri1_breadcrumb(dev
);
3185 if (iir
& I915_USER_INTERRUPT
)
3186 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3188 for_each_pipe(pipe
) {
3189 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3190 i8xx_handle_vblank(dev
, pipe
, iir
))
3191 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3193 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3194 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3203 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3205 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3208 for_each_pipe(pipe
) {
3209 /* Clear enable bits; then clear status bits */
3210 I915_WRITE(PIPESTAT(pipe
), 0);
3211 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3213 I915_WRITE16(IMR
, 0xffff);
3214 I915_WRITE16(IER
, 0x0);
3215 I915_WRITE16(IIR
, I915_READ16(IIR
));
3218 static void i915_irq_preinstall(struct drm_device
* dev
)
3220 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3223 atomic_set(&dev_priv
->irq_received
, 0);
3225 if (I915_HAS_HOTPLUG(dev
)) {
3226 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3227 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3230 I915_WRITE16(HWSTAM
, 0xeffe);
3232 I915_WRITE(PIPESTAT(pipe
), 0);
3233 I915_WRITE(IMR
, 0xffffffff);
3234 I915_WRITE(IER
, 0x0);
3238 static int i915_irq_postinstall(struct drm_device
*dev
)
3240 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3242 unsigned long irqflags
;
3244 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3246 /* Unmask the interrupts that we always want on. */
3247 dev_priv
->irq_mask
=
3248 ~(I915_ASLE_INTERRUPT
|
3249 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3250 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3251 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3252 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3253 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3256 I915_ASLE_INTERRUPT
|
3257 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3258 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3259 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3260 I915_USER_INTERRUPT
;
3262 if (I915_HAS_HOTPLUG(dev
)) {
3263 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3264 POSTING_READ(PORT_HOTPLUG_EN
);
3266 /* Enable in IER... */
3267 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3268 /* and unmask in IMR */
3269 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3272 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3273 I915_WRITE(IER
, enable_mask
);
3276 i915_enable_asle_pipestat(dev
);
3278 /* Interrupt setup is already guaranteed to be single-threaded, this is
3279 * just to make the assert_spin_locked check happy. */
3280 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3281 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
3282 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
3283 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3289 * Returns true when a page flip has completed.
3291 static bool i915_handle_vblank(struct drm_device
*dev
,
3292 int plane
, int pipe
, u32 iir
)
3294 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3295 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3297 if (!drm_handle_vblank(dev
, pipe
))
3300 if ((iir
& flip_pending
) == 0)
3303 intel_prepare_page_flip(dev
, plane
);
3305 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3306 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3307 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3308 * the flip is completed (no longer pending). Since this doesn't raise
3309 * an interrupt per se, we watch for the change at vblank.
3311 if (I915_READ(ISR
) & flip_pending
)
3314 intel_finish_page_flip(dev
, pipe
);
3319 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3321 struct drm_device
*dev
= (struct drm_device
*) arg
;
3322 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3323 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3324 unsigned long irqflags
;
3326 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3327 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3328 int pipe
, ret
= IRQ_NONE
;
3330 atomic_inc(&dev_priv
->irq_received
);
3332 iir
= I915_READ(IIR
);
3334 bool irq_received
= (iir
& ~flip_mask
) != 0;
3335 bool blc_event
= false;
3337 /* Can't rely on pipestat interrupt bit in iir as it might
3338 * have been cleared after the pipestat interrupt was received.
3339 * It doesn't set the bit in iir again, but it still produces
3340 * interrupts (for non-MSI).
3342 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3343 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3344 i915_handle_error(dev
, false);
3346 for_each_pipe(pipe
) {
3347 int reg
= PIPESTAT(pipe
);
3348 pipe_stats
[pipe
] = I915_READ(reg
);
3350 /* Clear the PIPE*STAT regs before the IIR */
3351 if (pipe_stats
[pipe
] & 0x8000ffff) {
3352 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3353 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3355 I915_WRITE(reg
, pipe_stats
[pipe
]);
3356 irq_received
= true;
3359 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3364 /* Consume port. Then clear IIR or we'll miss events */
3365 if ((I915_HAS_HOTPLUG(dev
)) &&
3366 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3367 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3368 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3370 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3373 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
3375 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3376 POSTING_READ(PORT_HOTPLUG_STAT
);
3379 I915_WRITE(IIR
, iir
& ~flip_mask
);
3380 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3382 if (iir
& I915_USER_INTERRUPT
)
3383 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3385 for_each_pipe(pipe
) {
3390 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3391 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3392 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3394 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3397 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3398 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3401 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3402 intel_opregion_asle_intr(dev
);
3404 /* With MSI, interrupts are only generated when iir
3405 * transitions from zero to nonzero. If another bit got
3406 * set while we were handling the existing iir bits, then
3407 * we would never get another interrupt.
3409 * This is fine on non-MSI as well, as if we hit this path
3410 * we avoid exiting the interrupt handler only to generate
3413 * Note that for MSI this could cause a stray interrupt report
3414 * if an interrupt landed in the time between writing IIR and
3415 * the posting read. This should be rare enough to never
3416 * trigger the 99% of 100,000 interrupts test for disabling
3421 } while (iir
& ~flip_mask
);
3423 i915_update_dri1_breadcrumb(dev
);
3428 static void i915_irq_uninstall(struct drm_device
* dev
)
3430 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3433 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3435 if (I915_HAS_HOTPLUG(dev
)) {
3436 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3437 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3440 I915_WRITE16(HWSTAM
, 0xffff);
3441 for_each_pipe(pipe
) {
3442 /* Clear enable bits; then clear status bits */
3443 I915_WRITE(PIPESTAT(pipe
), 0);
3444 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3446 I915_WRITE(IMR
, 0xffffffff);
3447 I915_WRITE(IER
, 0x0);
3449 I915_WRITE(IIR
, I915_READ(IIR
));
3452 static void i965_irq_preinstall(struct drm_device
* dev
)
3454 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3457 atomic_set(&dev_priv
->irq_received
, 0);
3459 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3460 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3462 I915_WRITE(HWSTAM
, 0xeffe);
3464 I915_WRITE(PIPESTAT(pipe
), 0);
3465 I915_WRITE(IMR
, 0xffffffff);
3466 I915_WRITE(IER
, 0x0);
3470 static int i965_irq_postinstall(struct drm_device
*dev
)
3472 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3475 unsigned long irqflags
;
3477 /* Unmask the interrupts that we always want on. */
3478 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3479 I915_DISPLAY_PORT_INTERRUPT
|
3480 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3481 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3482 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3483 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3484 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3486 enable_mask
= ~dev_priv
->irq_mask
;
3487 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3488 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3489 enable_mask
|= I915_USER_INTERRUPT
;
3492 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3494 /* Interrupt setup is already guaranteed to be single-threaded, this is
3495 * just to make the assert_spin_locked check happy. */
3496 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3497 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_EVENT_ENABLE
);
3498 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_ENABLE
);
3499 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_ENABLE
);
3500 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3503 * Enable some error detection, note the instruction error mask
3504 * bit is reserved, so we leave it masked.
3507 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3508 GM45_ERROR_MEM_PRIV
|
3509 GM45_ERROR_CP_PRIV
|
3510 I915_ERROR_MEMORY_REFRESH
);
3512 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3513 I915_ERROR_MEMORY_REFRESH
);
3515 I915_WRITE(EMR
, error_mask
);
3517 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3518 I915_WRITE(IER
, enable_mask
);
3521 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3522 POSTING_READ(PORT_HOTPLUG_EN
);
3524 i915_enable_asle_pipestat(dev
);
3529 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3531 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3532 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3533 struct intel_encoder
*intel_encoder
;
3536 assert_spin_locked(&dev_priv
->irq_lock
);
3538 if (I915_HAS_HOTPLUG(dev
)) {
3539 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3540 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3541 /* Note HDMI and DP share hotplug bits */
3542 /* enable bits are the same for all generations */
3543 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3544 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3545 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3546 /* Programming the CRT detection parameters tends
3547 to generate a spurious hotplug event about three
3548 seconds later. So just do it once.
3551 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3552 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3553 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3555 /* Ignore TV since it's buggy */
3556 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3560 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3562 struct drm_device
*dev
= (struct drm_device
*) arg
;
3563 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3565 u32 pipe_stats
[I915_MAX_PIPES
];
3566 unsigned long irqflags
;
3568 int ret
= IRQ_NONE
, pipe
;
3570 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3571 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3573 atomic_inc(&dev_priv
->irq_received
);
3575 iir
= I915_READ(IIR
);
3578 bool blc_event
= false;
3580 irq_received
= (iir
& ~flip_mask
) != 0;
3582 /* Can't rely on pipestat interrupt bit in iir as it might
3583 * have been cleared after the pipestat interrupt was received.
3584 * It doesn't set the bit in iir again, but it still produces
3585 * interrupts (for non-MSI).
3587 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3588 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3589 i915_handle_error(dev
, false);
3591 for_each_pipe(pipe
) {
3592 int reg
= PIPESTAT(pipe
);
3593 pipe_stats
[pipe
] = I915_READ(reg
);
3596 * Clear the PIPE*STAT regs before the IIR
3598 if (pipe_stats
[pipe
] & 0x8000ffff) {
3599 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3600 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3602 I915_WRITE(reg
, pipe_stats
[pipe
]);
3606 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3613 /* Consume port. Then clear IIR or we'll miss events */
3614 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3615 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3616 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3617 HOTPLUG_INT_STATUS_G4X
:
3618 HOTPLUG_INT_STATUS_I915
);
3620 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3623 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3624 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3626 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3627 I915_READ(PORT_HOTPLUG_STAT
);
3630 I915_WRITE(IIR
, iir
& ~flip_mask
);
3631 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3633 if (iir
& I915_USER_INTERRUPT
)
3634 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3635 if (iir
& I915_BSD_USER_INTERRUPT
)
3636 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3638 for_each_pipe(pipe
) {
3639 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3640 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3641 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3643 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3646 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3647 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3651 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3652 intel_opregion_asle_intr(dev
);
3654 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3655 gmbus_irq_handler(dev
);
3657 /* With MSI, interrupts are only generated when iir
3658 * transitions from zero to nonzero. If another bit got
3659 * set while we were handling the existing iir bits, then
3660 * we would never get another interrupt.
3662 * This is fine on non-MSI as well, as if we hit this path
3663 * we avoid exiting the interrupt handler only to generate
3666 * Note that for MSI this could cause a stray interrupt report
3667 * if an interrupt landed in the time between writing IIR and
3668 * the posting read. This should be rare enough to never
3669 * trigger the 99% of 100,000 interrupts test for disabling
3675 i915_update_dri1_breadcrumb(dev
);
3680 static void i965_irq_uninstall(struct drm_device
* dev
)
3682 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3688 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3690 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3691 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3693 I915_WRITE(HWSTAM
, 0xffffffff);
3695 I915_WRITE(PIPESTAT(pipe
), 0);
3696 I915_WRITE(IMR
, 0xffffffff);
3697 I915_WRITE(IER
, 0x0);
3700 I915_WRITE(PIPESTAT(pipe
),
3701 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3702 I915_WRITE(IIR
, I915_READ(IIR
));
3705 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3707 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3708 struct drm_device
*dev
= dev_priv
->dev
;
3709 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3710 unsigned long irqflags
;
3713 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3714 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3715 struct drm_connector
*connector
;
3717 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3720 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3722 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3723 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3725 if (intel_connector
->encoder
->hpd_pin
== i
) {
3726 if (connector
->polled
!= intel_connector
->polled
)
3727 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3728 drm_get_connector_name(connector
));
3729 connector
->polled
= intel_connector
->polled
;
3730 if (!connector
->polled
)
3731 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3735 if (dev_priv
->display
.hpd_irq_setup
)
3736 dev_priv
->display
.hpd_irq_setup(dev
);
3737 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3740 void intel_irq_init(struct drm_device
*dev
)
3742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3744 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3745 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3746 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3747 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3749 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3750 i915_hangcheck_elapsed
,
3751 (unsigned long) dev
);
3752 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3753 (unsigned long) dev_priv
);
3755 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3758 dev
->max_vblank_count
= 0;
3759 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
3760 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3761 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3762 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3764 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3765 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3768 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3769 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3770 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3773 if (IS_VALLEYVIEW(dev
)) {
3774 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3775 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3776 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3777 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3778 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3779 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3780 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3781 } else if (IS_GEN8(dev
)) {
3782 dev
->driver
->irq_handler
= gen8_irq_handler
;
3783 dev
->driver
->irq_preinstall
= gen8_irq_preinstall
;
3784 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
3785 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
3786 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
3787 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
3788 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3789 } else if (HAS_PCH_SPLIT(dev
)) {
3790 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3791 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3792 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3793 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3794 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3795 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3796 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3798 if (INTEL_INFO(dev
)->gen
== 2) {
3799 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3800 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3801 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3802 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3803 } else if (INTEL_INFO(dev
)->gen
== 3) {
3804 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3805 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3806 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3807 dev
->driver
->irq_handler
= i915_irq_handler
;
3808 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3810 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3811 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3812 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3813 dev
->driver
->irq_handler
= i965_irq_handler
;
3814 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3816 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3817 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3821 void intel_hpd_init(struct drm_device
*dev
)
3823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3825 struct drm_connector
*connector
;
3826 unsigned long irqflags
;
3829 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3830 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3831 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3833 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3834 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3835 connector
->polled
= intel_connector
->polled
;
3836 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3837 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3840 /* Interrupt setup is already guaranteed to be single-threaded, this is
3841 * just to make the assert_spin_locked checks happy. */
3842 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3843 if (dev_priv
->display
.hpd_irq_setup
)
3844 dev_priv
->display
.hpd_irq_setup(dev
);
3845 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3848 /* Disable interrupts so we can allow Package C8+. */
3849 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3852 unsigned long irqflags
;
3854 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3856 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3857 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3858 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3859 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3860 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3862 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3863 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3864 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3865 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3867 dev_priv
->pc8
.irqs_disabled
= true;
3869 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3872 /* Restore interrupts so we can recover from Package C8+. */
3873 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3876 unsigned long irqflags
;
3877 uint32_t val
, expected
;
3879 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3881 val
= I915_READ(DEIMR
);
3882 expected
= ~DE_PCH_EVENT_IVB
;
3883 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3885 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3886 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3887 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3890 val
= I915_READ(GTIMR
);
3891 expected
= 0xffffffff;
3892 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3894 val
= I915_READ(GEN6_PMIMR
);
3895 expected
= 0xffffffff;
3896 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3899 dev_priv
->pc8
.irqs_disabled
= false;
3901 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3902 ibx_enable_display_interrupt(dev_priv
,
3903 ~dev_priv
->pc8
.regsave
.sdeimr
&
3904 ~SDE_HOTPLUG_MASK_CPT
);
3905 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3906 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3907 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3909 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);