1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
108 * ilk_update_gt_irq - update GTIMR
109 * @dev_priv: driver private
110 * @interrupt_mask: mask of interrupt bits to update
111 * @enabled_irq_mask: mask of interrupt bits to enable
113 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
114 uint32_t interrupt_mask
,
115 uint32_t enabled_irq_mask
)
117 assert_spin_locked(&dev_priv
->irq_lock
);
119 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
120 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
121 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
125 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
127 ilk_update_gt_irq(dev_priv
, mask
, mask
);
130 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
132 ilk_update_gt_irq(dev_priv
, mask
, 0);
136 * snb_update_pm_irq - update GEN6_PMIMR
137 * @dev_priv: driver private
138 * @interrupt_mask: mask of interrupt bits to update
139 * @enabled_irq_mask: mask of interrupt bits to enable
141 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
142 uint32_t interrupt_mask
,
143 uint32_t enabled_irq_mask
)
147 assert_spin_locked(&dev_priv
->irq_lock
);
149 new_val
= dev_priv
->pm_irq_mask
;
150 new_val
&= ~interrupt_mask
;
151 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
153 if (new_val
!= dev_priv
->pm_irq_mask
) {
154 dev_priv
->pm_irq_mask
= new_val
;
155 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
156 POSTING_READ(GEN6_PMIMR
);
160 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
162 snb_update_pm_irq(dev_priv
, mask
, mask
);
165 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
167 snb_update_pm_irq(dev_priv
, mask
, 0);
170 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct intel_crtc
*crtc
;
176 assert_spin_locked(&dev_priv
->irq_lock
);
178 for_each_pipe(pipe
) {
179 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
181 if (crtc
->cpu_fifo_underrun_disabled
)
188 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct intel_crtc
*crtc
;
194 assert_spin_locked(&dev_priv
->irq_lock
);
196 for_each_pipe(pipe
) {
197 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
199 if (crtc
->pch_fifo_underrun_disabled
)
206 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
207 enum pipe pipe
, bool enable
)
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
211 DE_PIPEB_FIFO_UNDERRUN
;
214 ironlake_enable_display_irq(dev_priv
, bit
);
216 ironlake_disable_display_irq(dev_priv
, bit
);
219 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum pipe pipe
, bool enable
)
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
224 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
226 if (!ivb_can_enable_err_int(dev
))
229 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
231 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
233 /* Change the state _after_ we've read out the current one. */
234 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
237 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
238 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
245 * ibx_display_interrupt_update - update SDEIMR
246 * @dev_priv: driver private
247 * @interrupt_mask: mask of interrupt bits to update
248 * @enabled_irq_mask: mask of interrupt bits to enable
250 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
251 uint32_t interrupt_mask
,
252 uint32_t enabled_irq_mask
)
254 uint32_t sdeimr
= I915_READ(SDEIMR
);
255 sdeimr
&= ~interrupt_mask
;
256 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
258 assert_spin_locked(&dev_priv
->irq_lock
);
260 I915_WRITE(SDEIMR
, sdeimr
);
261 POSTING_READ(SDEIMR
);
263 #define ibx_enable_display_interrupt(dev_priv, bits) \
264 ibx_display_interrupt_update((dev_priv), (bits), (bits))
265 #define ibx_disable_display_interrupt(dev_priv, bits) \
266 ibx_display_interrupt_update((dev_priv), (bits), 0)
268 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
269 enum transcoder pch_transcoder
,
272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
273 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
274 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
277 ibx_enable_display_interrupt(dev_priv
, bit
);
279 ibx_disable_display_interrupt(dev_priv
, bit
);
282 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
283 enum transcoder pch_transcoder
,
286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
292 if (!cpt_can_enable_serr_int(dev
))
295 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
297 uint32_t tmp
= I915_READ(SERR_INT
);
298 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
300 /* Change the state _after_ we've read out the current one. */
301 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
304 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
305 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
306 transcoder_name(pch_transcoder
));
312 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
315 * @enable: true if we want to report FIFO underrun errors, false otherwise
317 * This function makes us disable or enable CPU fifo underruns for a specific
318 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
319 * reporting for one pipe may also disable all the other CPU error interruts for
320 * the other pipes, due to the fact that there's just one interrupt mask/enable
321 * bit for all the pipes.
323 * Returns the previous state of underrun reporting.
325 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
326 enum pipe pipe
, bool enable
)
328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
329 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
334 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
336 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
341 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
343 if (IS_GEN5(dev
) || IS_GEN6(dev
))
344 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
345 else if (IS_GEN7(dev
))
346 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
349 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
354 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
356 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
357 * @enable: true if we want to report FIFO underrun errors, false otherwise
359 * This function makes us disable or enable PCH fifo underruns for a specific
360 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
361 * underrun reporting for one transcoder may also disable all the other PCH
362 * error interruts for the other transcoders, due to the fact that there's just
363 * one interrupt mask/enable bit for all the transcoders.
365 * Returns the previous state of underrun reporting.
367 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
368 enum transcoder pch_transcoder
,
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
378 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
379 * has only one pch transcoder A that all pipes can use. To avoid racy
380 * pch transcoder -> pipe lookups from interrupt code simply store the
381 * underrun statistics in crtc A. Since we never expose this anywhere
382 * nor use it outside of the fifo underrun code here using the "wrong"
383 * crtc on LPT won't cause issues.
386 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
388 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
393 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
395 if (HAS_PCH_IBX(dev
))
396 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
398 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
401 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
407 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
409 u32 reg
= PIPESTAT(pipe
);
410 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
412 assert_spin_locked(&dev_priv
->irq_lock
);
414 if ((pipestat
& mask
) == mask
)
417 /* Enable the interrupt, clear any pending status */
418 pipestat
|= mask
| (mask
>> 16);
419 I915_WRITE(reg
, pipestat
);
424 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
426 u32 reg
= PIPESTAT(pipe
);
427 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
429 assert_spin_locked(&dev_priv
->irq_lock
);
431 if ((pipestat
& mask
) == 0)
435 I915_WRITE(reg
, pipestat
);
440 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
442 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
445 unsigned long irqflags
;
447 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
450 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
452 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
453 if (INTEL_INFO(dev
)->gen
>= 4)
454 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
456 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
460 * i915_pipe_enabled - check if a pipe is enabled
462 * @pipe: pipe to check
464 * Reading certain registers when the pipe is disabled can hang the chip.
465 * Use this routine to make sure the PLL is running and the pipe is active
466 * before reading such registers if unsure.
469 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
471 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
473 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
474 /* Locking is horribly broken here, but whatever. */
475 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
476 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
478 return intel_crtc
->active
;
480 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
484 /* Called from drm generic code, passed a 'crtc', which
485 * we use as a pipe index
487 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
489 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
490 unsigned long high_frame
;
491 unsigned long low_frame
;
492 u32 high1
, high2
, low
;
494 if (!i915_pipe_enabled(dev
, pipe
)) {
495 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
496 "pipe %c\n", pipe_name(pipe
));
500 high_frame
= PIPEFRAME(pipe
);
501 low_frame
= PIPEFRAMEPIXEL(pipe
);
504 * High & low register fields aren't synchronized, so make sure
505 * we get a low value that's stable across two reads of the high
509 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
510 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
511 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
512 } while (high1
!= high2
);
514 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
515 low
>>= PIPE_FRAME_LOW_SHIFT
;
516 return (high1
<< 8) | low
;
519 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
521 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
522 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
524 if (!i915_pipe_enabled(dev
, pipe
)) {
525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
526 "pipe %c\n", pipe_name(pipe
));
530 return I915_READ(reg
);
533 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
534 int *vpos
, int *hpos
)
536 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
537 u32 vbl
= 0, position
= 0;
538 int vbl_start
, vbl_end
, htotal
, vtotal
;
541 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
544 if (!i915_pipe_enabled(dev
, pipe
)) {
545 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
546 "pipe %c\n", pipe_name(pipe
));
551 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
553 if (INTEL_INFO(dev
)->gen
>= 4) {
554 /* No obvious pixelcount register. Only query vertical
555 * scanout position from Display scan line register.
557 position
= I915_READ(PIPEDSL(pipe
));
559 /* Decode into vertical scanout position. Don't have
560 * horizontal scanout position.
562 *vpos
= position
& 0x1fff;
565 /* Have access to pixelcount since start of frame.
566 * We can split this into vertical and horizontal
569 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
571 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
572 *vpos
= position
/ htotal
;
573 *hpos
= position
- (*vpos
* htotal
);
576 /* Query vblank area. */
577 vbl
= I915_READ(VBLANK(cpu_transcoder
));
579 /* Test position against vblank region. */
580 vbl_start
= vbl
& 0x1fff;
581 vbl_end
= (vbl
>> 16) & 0x1fff;
583 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
586 /* Inside "upper part" of vblank area? Apply corrective offset: */
587 if (in_vbl
&& (*vpos
>= vbl_start
))
588 *vpos
= *vpos
- vtotal
;
590 /* Readouts valid? */
592 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
596 ret
|= DRM_SCANOUTPOS_INVBL
;
601 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
603 struct timeval
*vblank_time
,
606 struct drm_crtc
*crtc
;
608 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
609 DRM_ERROR("Invalid crtc %d\n", pipe
);
613 /* Get drm_crtc to timestamp: */
614 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
616 DRM_ERROR("Invalid crtc %d\n", pipe
);
620 if (!crtc
->enabled
) {
621 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
625 /* Helper routine in DRM core does all the work: */
626 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
631 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
633 enum drm_connector_status old_status
;
635 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
636 old_status
= connector
->status
;
638 connector
->status
= connector
->funcs
->detect(connector
, false);
639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
641 drm_get_connector_name(connector
),
642 old_status
, connector
->status
);
643 return (old_status
!= connector
->status
);
647 * Handle hotplug events outside the interrupt handler proper.
649 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
651 static void i915_hotplug_work_func(struct work_struct
*work
)
653 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
655 struct drm_device
*dev
= dev_priv
->dev
;
656 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
657 struct intel_connector
*intel_connector
;
658 struct intel_encoder
*intel_encoder
;
659 struct drm_connector
*connector
;
660 unsigned long irqflags
;
661 bool hpd_disabled
= false;
662 bool changed
= false;
665 /* HPD irq before everything is fully set up. */
666 if (!dev_priv
->enable_hotplug_processing
)
669 mutex_lock(&mode_config
->mutex
);
670 DRM_DEBUG_KMS("running encoder hotplug functions\n");
672 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
674 hpd_event_bits
= dev_priv
->hpd_event_bits
;
675 dev_priv
->hpd_event_bits
= 0;
676 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
677 intel_connector
= to_intel_connector(connector
);
678 intel_encoder
= intel_connector
->encoder
;
679 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
680 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
681 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
682 DRM_INFO("HPD interrupt storm detected on connector %s: "
683 "switching from hotplug detection to polling\n",
684 drm_get_connector_name(connector
));
685 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
686 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
687 | DRM_CONNECTOR_POLL_DISCONNECT
;
690 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
691 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
692 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
695 /* if there were no outputs to poll, poll was disabled,
696 * therefore make sure it's enabled when disabling HPD on
699 drm_kms_helper_poll_enable(dev
);
700 mod_timer(&dev_priv
->hotplug_reenable_timer
,
701 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
704 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
706 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
707 intel_connector
= to_intel_connector(connector
);
708 intel_encoder
= intel_connector
->encoder
;
709 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
710 if (intel_encoder
->hot_plug
)
711 intel_encoder
->hot_plug(intel_encoder
);
712 if (intel_hpd_irq_event(dev
, connector
))
716 mutex_unlock(&mode_config
->mutex
);
719 drm_kms_helper_hotplug_event(dev
);
722 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
724 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
725 u32 busy_up
, busy_down
, max_avg
, min_avg
;
728 spin_lock(&mchdev_lock
);
730 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
732 new_delay
= dev_priv
->ips
.cur_delay
;
734 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
735 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
736 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
737 max_avg
= I915_READ(RCBMAXAVG
);
738 min_avg
= I915_READ(RCBMINAVG
);
740 /* Handle RCS change request from hw */
741 if (busy_up
> max_avg
) {
742 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
743 new_delay
= dev_priv
->ips
.cur_delay
- 1;
744 if (new_delay
< dev_priv
->ips
.max_delay
)
745 new_delay
= dev_priv
->ips
.max_delay
;
746 } else if (busy_down
< min_avg
) {
747 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
748 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
749 if (new_delay
> dev_priv
->ips
.min_delay
)
750 new_delay
= dev_priv
->ips
.min_delay
;
753 if (ironlake_set_drps(dev
, new_delay
))
754 dev_priv
->ips
.cur_delay
= new_delay
;
756 spin_unlock(&mchdev_lock
);
761 static void notify_ring(struct drm_device
*dev
,
762 struct intel_ring_buffer
*ring
)
764 if (ring
->obj
== NULL
)
767 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
769 wake_up_all(&ring
->irq_queue
);
770 i915_queue_hangcheck(dev
);
773 static void gen6_pm_rps_work(struct work_struct
*work
)
775 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
780 spin_lock_irq(&dev_priv
->irq_lock
);
781 pm_iir
= dev_priv
->rps
.pm_iir
;
782 dev_priv
->rps
.pm_iir
= 0;
783 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
784 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
785 spin_unlock_irq(&dev_priv
->irq_lock
);
787 /* Make sure we didn't queue anything we're not going to process. */
788 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
790 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
793 mutex_lock(&dev_priv
->rps
.hw_lock
);
795 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
796 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
799 * For better performance, jump directly
800 * to RPe if we're below it.
802 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
803 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
804 new_delay
= dev_priv
->rps
.rpe_delay
;
806 new_delay
= dev_priv
->rps
.cur_delay
- 1;
808 /* sysfs frequency interfaces may have snuck in while servicing the
811 if (new_delay
>= dev_priv
->rps
.min_delay
&&
812 new_delay
<= dev_priv
->rps
.max_delay
) {
813 if (IS_VALLEYVIEW(dev_priv
->dev
))
814 valleyview_set_rps(dev_priv
->dev
, new_delay
);
816 gen6_set_rps(dev_priv
->dev
, new_delay
);
819 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
821 * On VLV, when we enter RC6 we may not be at the minimum
822 * voltage level, so arm a timer to check. It should only
823 * fire when there's activity or once after we've entered
824 * RC6, and then won't be re-armed until the next RPS interrupt.
826 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
827 msecs_to_jiffies(100));
830 mutex_unlock(&dev_priv
->rps
.hw_lock
);
835 * ivybridge_parity_work - Workqueue called when a parity error interrupt
837 * @work: workqueue struct
839 * Doesn't actually do anything except notify userspace. As a consequence of
840 * this event, userspace should try to remap the bad rows since statistically
841 * it is likely the same row is more likely to go bad again.
843 static void ivybridge_parity_work(struct work_struct
*work
)
845 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
846 l3_parity
.error_work
);
847 u32 error_status
, row
, bank
, subbank
;
848 char *parity_event
[5];
852 /* We must turn off DOP level clock gating to access the L3 registers.
853 * In order to prevent a get/put style interface, acquire struct mutex
854 * any time we access those registers.
856 mutex_lock(&dev_priv
->dev
->struct_mutex
);
858 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
859 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
860 POSTING_READ(GEN7_MISCCPCTL
);
862 error_status
= I915_READ(GEN7_L3CDERRST1
);
863 row
= GEN7_PARITY_ERROR_ROW(error_status
);
864 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
865 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
867 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
868 GEN7_L3CDERRST1_ENABLE
);
869 POSTING_READ(GEN7_L3CDERRST1
);
871 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
873 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
874 ilk_enable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
875 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
877 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
879 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
880 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
881 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
882 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
883 parity_event
[4] = NULL
;
885 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
886 KOBJ_CHANGE
, parity_event
);
888 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
891 kfree(parity_event
[3]);
892 kfree(parity_event
[2]);
893 kfree(parity_event
[1]);
896 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
898 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
900 if (!HAS_L3_GPU_CACHE(dev
))
903 spin_lock(&dev_priv
->irq_lock
);
904 ilk_disable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
905 spin_unlock(&dev_priv
->irq_lock
);
907 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
910 static void ilk_gt_irq_handler(struct drm_device
*dev
,
911 struct drm_i915_private
*dev_priv
,
915 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
916 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
917 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
918 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
921 static void snb_gt_irq_handler(struct drm_device
*dev
,
922 struct drm_i915_private
*dev_priv
,
927 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
928 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
929 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
930 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
931 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
932 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
934 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
935 GT_BSD_CS_ERROR_INTERRUPT
|
936 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
937 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
938 i915_handle_error(dev
, false);
941 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
942 ivybridge_parity_error_irq_handler(dev
);
945 #define HPD_STORM_DETECT_PERIOD 1000
946 #define HPD_STORM_THRESHOLD 5
948 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
952 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
954 bool storm_detected
= false;
956 if (!hotplug_trigger
)
959 spin_lock(&dev_priv
->irq_lock
);
960 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
962 WARN(((hpd
[i
] & hotplug_trigger
) &&
963 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
964 "Received HPD interrupt although disabled\n");
966 if (!(hpd
[i
] & hotplug_trigger
) ||
967 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
970 dev_priv
->hpd_event_bits
|= (1 << i
);
971 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
972 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
973 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
974 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
975 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
976 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
977 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
978 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
979 dev_priv
->hpd_event_bits
&= ~(1 << i
);
980 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
981 storm_detected
= true;
983 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
984 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
985 dev_priv
->hpd_stats
[i
].hpd_cnt
);
990 dev_priv
->display
.hpd_irq_setup(dev
);
991 spin_unlock(&dev_priv
->irq_lock
);
993 queue_work(dev_priv
->wq
,
994 &dev_priv
->hotplug_work
);
997 static void gmbus_irq_handler(struct drm_device
*dev
)
999 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1001 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1004 static void dp_aux_irq_handler(struct drm_device
*dev
)
1006 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1008 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1011 /* The RPS events need forcewake, so we add them to a work queue and mask their
1012 * IMR bits until the work is done. Other interrupts can be processed without
1013 * the work queue. */
1014 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1016 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1017 spin_lock(&dev_priv
->irq_lock
);
1018 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1019 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1020 spin_unlock(&dev_priv
->irq_lock
);
1022 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1025 if (HAS_VEBOX(dev_priv
->dev
)) {
1026 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1027 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1029 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1030 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1031 i915_handle_error(dev_priv
->dev
, false);
1036 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1038 struct drm_device
*dev
= (struct drm_device
*) arg
;
1039 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1040 u32 iir
, gt_iir
, pm_iir
;
1041 irqreturn_t ret
= IRQ_NONE
;
1042 unsigned long irqflags
;
1044 u32 pipe_stats
[I915_MAX_PIPES
];
1046 atomic_inc(&dev_priv
->irq_received
);
1049 iir
= I915_READ(VLV_IIR
);
1050 gt_iir
= I915_READ(GTIIR
);
1051 pm_iir
= I915_READ(GEN6_PMIIR
);
1053 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1058 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1060 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1061 for_each_pipe(pipe
) {
1062 int reg
= PIPESTAT(pipe
);
1063 pipe_stats
[pipe
] = I915_READ(reg
);
1066 * Clear the PIPE*STAT regs before the IIR
1068 if (pipe_stats
[pipe
] & 0x8000ffff) {
1069 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1070 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1072 I915_WRITE(reg
, pipe_stats
[pipe
]);
1075 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1077 for_each_pipe(pipe
) {
1078 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1079 drm_handle_vblank(dev
, pipe
);
1081 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1082 intel_prepare_page_flip(dev
, pipe
);
1083 intel_finish_page_flip(dev
, pipe
);
1087 /* Consume port. Then clear IIR or we'll miss events */
1088 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1089 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1090 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1092 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1095 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1097 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1098 I915_READ(PORT_HOTPLUG_STAT
);
1101 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1102 gmbus_irq_handler(dev
);
1105 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1107 I915_WRITE(GTIIR
, gt_iir
);
1108 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1109 I915_WRITE(VLV_IIR
, iir
);
1116 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1118 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1120 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1122 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1124 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1125 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1126 SDE_AUDIO_POWER_SHIFT
);
1127 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1131 if (pch_iir
& SDE_AUX_MASK
)
1132 dp_aux_irq_handler(dev
);
1134 if (pch_iir
& SDE_GMBUS
)
1135 gmbus_irq_handler(dev
);
1137 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1138 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1140 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1141 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1143 if (pch_iir
& SDE_POISON
)
1144 DRM_ERROR("PCH poison interrupt\n");
1146 if (pch_iir
& SDE_FDI_MASK
)
1148 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1150 I915_READ(FDI_RX_IIR(pipe
)));
1152 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1153 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1155 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1156 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1158 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1159 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1161 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1163 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1164 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1166 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1169 static void ivb_err_int_handler(struct drm_device
*dev
)
1171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1172 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1174 if (err_int
& ERR_INT_POISON
)
1175 DRM_ERROR("Poison interrupt\n");
1177 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1178 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1179 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1181 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1182 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1183 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1185 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1186 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1187 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1189 I915_WRITE(GEN7_ERR_INT
, err_int
);
1192 static void cpt_serr_int_handler(struct drm_device
*dev
)
1194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1195 u32 serr_int
= I915_READ(SERR_INT
);
1197 if (serr_int
& SERR_INT_POISON
)
1198 DRM_ERROR("PCH poison interrupt\n");
1200 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1201 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1203 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1205 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1206 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1208 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1210 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1211 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1213 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1215 I915_WRITE(SERR_INT
, serr_int
);
1218 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1220 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1222 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1224 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1226 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1227 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1228 SDE_AUDIO_POWER_SHIFT_CPT
);
1229 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1233 if (pch_iir
& SDE_AUX_MASK_CPT
)
1234 dp_aux_irq_handler(dev
);
1236 if (pch_iir
& SDE_GMBUS_CPT
)
1237 gmbus_irq_handler(dev
);
1239 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1240 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1242 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1243 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1245 if (pch_iir
& SDE_FDI_MASK_CPT
)
1247 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1249 I915_READ(FDI_RX_IIR(pipe
)));
1251 if (pch_iir
& SDE_ERROR_CPT
)
1252 cpt_serr_int_handler(dev
);
1255 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 if (de_iir
& DE_AUX_CHANNEL_A
)
1260 dp_aux_irq_handler(dev
);
1262 if (de_iir
& DE_GSE
)
1263 intel_opregion_asle_intr(dev
);
1265 if (de_iir
& DE_PIPEA_VBLANK
)
1266 drm_handle_vblank(dev
, 0);
1268 if (de_iir
& DE_PIPEB_VBLANK
)
1269 drm_handle_vblank(dev
, 1);
1271 if (de_iir
& DE_POISON
)
1272 DRM_ERROR("Poison interrupt\n");
1274 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1275 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1276 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1278 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1279 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1280 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1282 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1283 intel_prepare_page_flip(dev
, 0);
1284 intel_finish_page_flip_plane(dev
, 0);
1287 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1288 intel_prepare_page_flip(dev
, 1);
1289 intel_finish_page_flip_plane(dev
, 1);
1292 /* check event from PCH */
1293 if (de_iir
& DE_PCH_EVENT
) {
1294 u32 pch_iir
= I915_READ(SDEIIR
);
1296 if (HAS_PCH_CPT(dev
))
1297 cpt_irq_handler(dev
, pch_iir
);
1299 ibx_irq_handler(dev
, pch_iir
);
1301 /* should clear PCH hotplug event before clear CPU irq */
1302 I915_WRITE(SDEIIR
, pch_iir
);
1305 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1306 ironlake_rps_change_irq_handler(dev
);
1309 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1314 if (de_iir
& DE_ERR_INT_IVB
)
1315 ivb_err_int_handler(dev
);
1317 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1318 dp_aux_irq_handler(dev
);
1320 if (de_iir
& DE_GSE_IVB
)
1321 intel_opregion_asle_intr(dev
);
1323 for (i
= 0; i
< 3; i
++) {
1324 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1325 drm_handle_vblank(dev
, i
);
1326 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1327 intel_prepare_page_flip(dev
, i
);
1328 intel_finish_page_flip_plane(dev
, i
);
1332 /* check event from PCH */
1333 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1334 u32 pch_iir
= I915_READ(SDEIIR
);
1336 cpt_irq_handler(dev
, pch_iir
);
1338 /* clear PCH hotplug event before clear CPU irq */
1339 I915_WRITE(SDEIIR
, pch_iir
);
1343 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1345 struct drm_device
*dev
= (struct drm_device
*) arg
;
1346 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1347 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1348 irqreturn_t ret
= IRQ_NONE
;
1349 bool err_int_reenable
= false;
1351 atomic_inc(&dev_priv
->irq_received
);
1353 /* We get interrupts on unclaimed registers, so check for this before we
1354 * do any I915_{READ,WRITE}. */
1355 intel_uncore_check_errors(dev
);
1357 /* disable master interrupt before clearing iir */
1358 de_ier
= I915_READ(DEIER
);
1359 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1360 POSTING_READ(DEIER
);
1362 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1363 * interrupts will will be stored on its back queue, and then we'll be
1364 * able to process them after we restore SDEIER (as soon as we restore
1365 * it, we'll get an interrupt if SDEIIR still has something to process
1366 * due to its back queue). */
1367 if (!HAS_PCH_NOP(dev
)) {
1368 sde_ier
= I915_READ(SDEIER
);
1369 I915_WRITE(SDEIER
, 0);
1370 POSTING_READ(SDEIER
);
1373 /* On Haswell, also mask ERR_INT because we don't want to risk
1374 * generating "unclaimed register" interrupts from inside the interrupt
1376 if (IS_HASWELL(dev
)) {
1377 spin_lock(&dev_priv
->irq_lock
);
1378 err_int_reenable
= ~dev_priv
->irq_mask
& DE_ERR_INT_IVB
;
1379 if (err_int_reenable
)
1380 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1381 spin_unlock(&dev_priv
->irq_lock
);
1384 gt_iir
= I915_READ(GTIIR
);
1386 if (INTEL_INFO(dev
)->gen
>= 6)
1387 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1389 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1390 I915_WRITE(GTIIR
, gt_iir
);
1394 de_iir
= I915_READ(DEIIR
);
1396 if (INTEL_INFO(dev
)->gen
>= 7)
1397 ivb_display_irq_handler(dev
, de_iir
);
1399 ilk_display_irq_handler(dev
, de_iir
);
1400 I915_WRITE(DEIIR
, de_iir
);
1404 if (INTEL_INFO(dev
)->gen
>= 6) {
1405 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1407 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1408 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1413 if (err_int_reenable
) {
1414 spin_lock(&dev_priv
->irq_lock
);
1415 if (ivb_can_enable_err_int(dev
))
1416 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1417 spin_unlock(&dev_priv
->irq_lock
);
1420 I915_WRITE(DEIER
, de_ier
);
1421 POSTING_READ(DEIER
);
1422 if (!HAS_PCH_NOP(dev
)) {
1423 I915_WRITE(SDEIER
, sde_ier
);
1424 POSTING_READ(SDEIER
);
1431 * i915_error_work_func - do process context error handling work
1432 * @work: work struct
1434 * Fire an error uevent so userspace can see that a hang or error
1437 static void i915_error_work_func(struct work_struct
*work
)
1439 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1441 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1443 struct drm_device
*dev
= dev_priv
->dev
;
1444 struct intel_ring_buffer
*ring
;
1445 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1446 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1447 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1450 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1453 * Note that there's only one work item which does gpu resets, so we
1454 * need not worry about concurrent gpu resets potentially incrementing
1455 * error->reset_counter twice. We only need to take care of another
1456 * racing irq/hangcheck declaring the gpu dead for a second time. A
1457 * quick check for that is good enough: schedule_work ensures the
1458 * correct ordering between hang detection and this work item, and since
1459 * the reset in-progress bit is only ever set by code outside of this
1460 * work we don't need to worry about any other races.
1462 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1463 DRM_DEBUG_DRIVER("resetting chip\n");
1464 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1467 ret
= i915_reset(dev
);
1471 * After all the gem state is reset, increment the reset
1472 * counter and wake up everyone waiting for the reset to
1475 * Since unlock operations are a one-sided barrier only,
1476 * we need to insert a barrier here to order any seqno
1478 * the counter increment.
1480 smp_mb__before_atomic_inc();
1481 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1483 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1484 KOBJ_CHANGE
, reset_done_event
);
1486 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1489 for_each_ring(ring
, dev_priv
, i
)
1490 wake_up_all(&ring
->irq_queue
);
1492 intel_display_handle_reset(dev
);
1494 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1498 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1502 u32 eir
= I915_READ(EIR
);
1508 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1510 i915_get_extra_instdone(dev
, instdone
);
1513 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1514 u32 ipeir
= I915_READ(IPEIR_I965
);
1516 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1517 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1518 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1519 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1520 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1521 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1522 I915_WRITE(IPEIR_I965
, ipeir
);
1523 POSTING_READ(IPEIR_I965
);
1525 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1526 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1527 pr_err("page table error\n");
1528 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1529 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1530 POSTING_READ(PGTBL_ER
);
1534 if (!IS_GEN2(dev
)) {
1535 if (eir
& I915_ERROR_PAGE_TABLE
) {
1536 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1537 pr_err("page table error\n");
1538 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1539 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1540 POSTING_READ(PGTBL_ER
);
1544 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1545 pr_err("memory refresh error:\n");
1547 pr_err("pipe %c stat: 0x%08x\n",
1548 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1549 /* pipestat has already been acked */
1551 if (eir
& I915_ERROR_INSTRUCTION
) {
1552 pr_err("instruction error\n");
1553 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1554 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1555 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1556 if (INTEL_INFO(dev
)->gen
< 4) {
1557 u32 ipeir
= I915_READ(IPEIR
);
1559 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1560 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1561 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1562 I915_WRITE(IPEIR
, ipeir
);
1563 POSTING_READ(IPEIR
);
1565 u32 ipeir
= I915_READ(IPEIR_I965
);
1567 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1568 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1569 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1570 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1571 I915_WRITE(IPEIR_I965
, ipeir
);
1572 POSTING_READ(IPEIR_I965
);
1576 I915_WRITE(EIR
, eir
);
1578 eir
= I915_READ(EIR
);
1581 * some errors might have become stuck,
1584 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1585 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1586 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1591 * i915_handle_error - handle an error interrupt
1594 * Do some basic checking of regsiter state at error interrupt time and
1595 * dump it to the syslog. Also call i915_capture_error_state() to make
1596 * sure we get a record and make it available in debugfs. Fire a uevent
1597 * so userspace knows something bad happened (should trigger collection
1598 * of a ring dump etc.).
1600 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 struct intel_ring_buffer
*ring
;
1606 i915_capture_error_state(dev
);
1607 i915_report_and_clear_eir(dev
);
1610 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1611 &dev_priv
->gpu_error
.reset_counter
);
1614 * Wakeup waiting processes so that the reset work item
1615 * doesn't deadlock trying to grab various locks.
1617 for_each_ring(ring
, dev_priv
, i
)
1618 wake_up_all(&ring
->irq_queue
);
1621 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1624 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1626 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1627 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1629 struct drm_i915_gem_object
*obj
;
1630 struct intel_unpin_work
*work
;
1631 unsigned long flags
;
1632 bool stall_detected
;
1634 /* Ignore early vblank irqs */
1635 if (intel_crtc
== NULL
)
1638 spin_lock_irqsave(&dev
->event_lock
, flags
);
1639 work
= intel_crtc
->unpin_work
;
1642 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1643 !work
->enable_stall_check
) {
1644 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1645 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1649 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1650 obj
= work
->pending_flip_obj
;
1651 if (INTEL_INFO(dev
)->gen
>= 4) {
1652 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1653 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1654 i915_gem_obj_ggtt_offset(obj
);
1656 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1657 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1658 crtc
->y
* crtc
->fb
->pitches
[0] +
1659 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1662 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1664 if (stall_detected
) {
1665 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1666 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1670 /* Called from drm generic code, passed 'crtc' which
1671 * we use as a pipe index
1673 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1675 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1676 unsigned long irqflags
;
1678 if (!i915_pipe_enabled(dev
, pipe
))
1681 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1682 if (INTEL_INFO(dev
)->gen
>= 4)
1683 i915_enable_pipestat(dev_priv
, pipe
,
1684 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1686 i915_enable_pipestat(dev_priv
, pipe
,
1687 PIPE_VBLANK_INTERRUPT_ENABLE
);
1689 /* maintain vblank delivery even in deep C-states */
1690 if (dev_priv
->info
->gen
== 3)
1691 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1692 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1697 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1699 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1700 unsigned long irqflags
;
1701 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1702 DE_PIPE_VBLANK_ILK(pipe
);
1704 if (!i915_pipe_enabled(dev
, pipe
))
1707 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1708 ironlake_enable_display_irq(dev_priv
, bit
);
1709 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1714 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1716 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1717 unsigned long irqflags
;
1720 if (!i915_pipe_enabled(dev
, pipe
))
1723 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1724 imr
= I915_READ(VLV_IMR
);
1726 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1728 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1729 I915_WRITE(VLV_IMR
, imr
);
1730 i915_enable_pipestat(dev_priv
, pipe
,
1731 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1732 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1737 /* Called from drm generic code, passed 'crtc' which
1738 * we use as a pipe index
1740 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1742 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1743 unsigned long irqflags
;
1745 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1746 if (dev_priv
->info
->gen
== 3)
1747 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1749 i915_disable_pipestat(dev_priv
, pipe
,
1750 PIPE_VBLANK_INTERRUPT_ENABLE
|
1751 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1752 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1755 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1757 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1758 unsigned long irqflags
;
1759 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1760 DE_PIPE_VBLANK_ILK(pipe
);
1762 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1763 ironlake_disable_display_irq(dev_priv
, bit
);
1764 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1767 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1769 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1770 unsigned long irqflags
;
1773 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1774 i915_disable_pipestat(dev_priv
, pipe
,
1775 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1776 imr
= I915_READ(VLV_IMR
);
1778 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1780 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1781 I915_WRITE(VLV_IMR
, imr
);
1782 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1786 ring_last_seqno(struct intel_ring_buffer
*ring
)
1788 return list_entry(ring
->request_list
.prev
,
1789 struct drm_i915_gem_request
, list
)->seqno
;
1793 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1795 return (list_empty(&ring
->request_list
) ||
1796 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1799 static struct intel_ring_buffer
*
1800 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1802 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1803 u32 cmd
, ipehr
, acthd
, acthd_min
;
1805 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1806 if ((ipehr
& ~(0x3 << 16)) !=
1807 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1810 /* ACTHD is likely pointing to the dword after the actual command,
1811 * so scan backwards until we find the MBOX.
1813 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1814 acthd_min
= max((int)acthd
- 3 * 4, 0);
1816 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1821 if (acthd
< acthd_min
)
1825 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1826 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1829 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1831 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1832 struct intel_ring_buffer
*signaller
;
1835 ring
->hangcheck
.deadlock
= true;
1837 signaller
= semaphore_waits_for(ring
, &seqno
);
1838 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1841 /* cursory check for an unkickable deadlock */
1842 ctl
= I915_READ_CTL(signaller
);
1843 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1846 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1849 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1851 struct intel_ring_buffer
*ring
;
1854 for_each_ring(ring
, dev_priv
, i
)
1855 ring
->hangcheck
.deadlock
= false;
1858 static enum intel_ring_hangcheck_action
1859 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1861 struct drm_device
*dev
= ring
->dev
;
1862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1865 if (ring
->hangcheck
.acthd
!= acthd
)
1866 return HANGCHECK_ACTIVE
;
1869 return HANGCHECK_HUNG
;
1871 /* Is the chip hanging on a WAIT_FOR_EVENT?
1872 * If so we can simply poke the RB_WAIT bit
1873 * and break the hang. This should work on
1874 * all but the second generation chipsets.
1876 tmp
= I915_READ_CTL(ring
);
1877 if (tmp
& RING_WAIT
) {
1878 DRM_ERROR("Kicking stuck wait on %s\n",
1880 I915_WRITE_CTL(ring
, tmp
);
1881 return HANGCHECK_KICK
;
1884 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1885 switch (semaphore_passed(ring
)) {
1887 return HANGCHECK_HUNG
;
1889 DRM_ERROR("Kicking stuck semaphore on %s\n",
1891 I915_WRITE_CTL(ring
, tmp
);
1892 return HANGCHECK_KICK
;
1894 return HANGCHECK_WAIT
;
1898 return HANGCHECK_HUNG
;
1902 * This is called when the chip hasn't reported back with completed
1903 * batchbuffers in a long time. We keep track per ring seqno progress and
1904 * if there are no progress, hangcheck score for that ring is increased.
1905 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1906 * we kick the ring. If we see no progress on three subsequent calls
1907 * we assume chip is wedged and try to fix it by resetting the chip.
1909 static void i915_hangcheck_elapsed(unsigned long data
)
1911 struct drm_device
*dev
= (struct drm_device
*)data
;
1912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1913 struct intel_ring_buffer
*ring
;
1915 int busy_count
= 0, rings_hung
= 0;
1916 bool stuck
[I915_NUM_RINGS
] = { 0 };
1922 if (!i915_enable_hangcheck
)
1925 for_each_ring(ring
, dev_priv
, i
) {
1929 semaphore_clear_deadlocks(dev_priv
);
1931 seqno
= ring
->get_seqno(ring
, false);
1932 acthd
= intel_ring_get_active_head(ring
);
1934 if (ring
->hangcheck
.seqno
== seqno
) {
1935 if (ring_idle(ring
, seqno
)) {
1936 if (waitqueue_active(&ring
->irq_queue
)) {
1937 /* Issue a wake-up to catch stuck h/w. */
1938 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1940 wake_up_all(&ring
->irq_queue
);
1941 ring
->hangcheck
.score
+= HUNG
;
1945 /* We always increment the hangcheck score
1946 * if the ring is busy and still processing
1947 * the same request, so that no single request
1948 * can run indefinitely (such as a chain of
1949 * batches). The only time we do not increment
1950 * the hangcheck score on this ring, if this
1951 * ring is in a legitimate wait for another
1952 * ring. In that case the waiting ring is a
1953 * victim and we want to be sure we catch the
1954 * right culprit. Then every time we do kick
1955 * the ring, add a small increment to the
1956 * score so that we can catch a batch that is
1957 * being repeatedly kicked and so responsible
1958 * for stalling the machine.
1960 ring
->hangcheck
.action
= ring_stuck(ring
,
1963 switch (ring
->hangcheck
.action
) {
1964 case HANGCHECK_WAIT
:
1966 case HANGCHECK_ACTIVE
:
1967 ring
->hangcheck
.score
+= BUSY
;
1969 case HANGCHECK_KICK
:
1970 ring
->hangcheck
.score
+= KICK
;
1972 case HANGCHECK_HUNG
:
1973 ring
->hangcheck
.score
+= HUNG
;
1979 /* Gradually reduce the count so that we catch DoS
1980 * attempts across multiple batches.
1982 if (ring
->hangcheck
.score
> 0)
1983 ring
->hangcheck
.score
--;
1986 ring
->hangcheck
.seqno
= seqno
;
1987 ring
->hangcheck
.acthd
= acthd
;
1991 for_each_ring(ring
, dev_priv
, i
) {
1992 if (ring
->hangcheck
.score
> FIRE
) {
1993 DRM_ERROR("%s on %s\n",
1994 stuck
[i
] ? "stuck" : "no progress",
2001 return i915_handle_error(dev
, true);
2004 /* Reset timer case chip hangs without another request
2006 i915_queue_hangcheck(dev
);
2009 void i915_queue_hangcheck(struct drm_device
*dev
)
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 if (!i915_enable_hangcheck
)
2015 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2016 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2019 static void ibx_irq_preinstall(struct drm_device
*dev
)
2021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2023 if (HAS_PCH_NOP(dev
))
2026 /* south display irq */
2027 I915_WRITE(SDEIMR
, 0xffffffff);
2029 * SDEIER is also touched by the interrupt handler to work around missed
2030 * PCH interrupts. Hence we can't update it after the interrupt handler
2031 * is enabled - instead we unconditionally enable all PCH interrupt
2032 * sources here, but then only unmask them as needed with SDEIMR.
2034 I915_WRITE(SDEIER
, 0xffffffff);
2035 POSTING_READ(SDEIER
);
2038 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2043 I915_WRITE(GTIMR
, 0xffffffff);
2044 I915_WRITE(GTIER
, 0x0);
2045 POSTING_READ(GTIER
);
2047 if (INTEL_INFO(dev
)->gen
>= 6) {
2049 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2050 I915_WRITE(GEN6_PMIER
, 0x0);
2051 POSTING_READ(GEN6_PMIER
);
2057 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2059 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2061 atomic_set(&dev_priv
->irq_received
, 0);
2063 I915_WRITE(HWSTAM
, 0xeffe);
2065 I915_WRITE(DEIMR
, 0xffffffff);
2066 I915_WRITE(DEIER
, 0x0);
2067 POSTING_READ(DEIER
);
2069 gen5_gt_irq_preinstall(dev
);
2071 ibx_irq_preinstall(dev
);
2074 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2076 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2079 atomic_set(&dev_priv
->irq_received
, 0);
2082 I915_WRITE(VLV_IMR
, 0);
2083 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2084 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2085 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2088 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2089 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2091 gen5_gt_irq_preinstall(dev
);
2093 I915_WRITE(DPINVGTT
, 0xff);
2095 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2096 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2098 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2099 I915_WRITE(VLV_IIR
, 0xffffffff);
2100 I915_WRITE(VLV_IMR
, 0xffffffff);
2101 I915_WRITE(VLV_IER
, 0x0);
2102 POSTING_READ(VLV_IER
);
2105 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2107 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2108 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2109 struct intel_encoder
*intel_encoder
;
2110 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2112 if (HAS_PCH_IBX(dev
)) {
2113 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2114 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2115 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2116 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2118 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2119 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2120 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2121 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2124 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2127 * Enable digital hotplug on the PCH, and configure the DP short pulse
2128 * duration to 2ms (which is the minimum in the Display Port spec)
2130 * This register is the same on all known PCH chips.
2132 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2133 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2134 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2135 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2136 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2137 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2140 static void ibx_irq_postinstall(struct drm_device
*dev
)
2142 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2145 if (HAS_PCH_NOP(dev
))
2148 if (HAS_PCH_IBX(dev
)) {
2149 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2150 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2152 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2154 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2157 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2158 I915_WRITE(SDEIMR
, ~mask
);
2161 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2164 u32 pm_irqs
, gt_irqs
;
2166 pm_irqs
= gt_irqs
= 0;
2168 dev_priv
->gt_irq_mask
= ~0;
2169 if (HAS_L3_GPU_CACHE(dev
)) {
2170 /* L3 parity interrupt is always unmasked. */
2171 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2172 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2175 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2177 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2178 ILK_BSD_USER_INTERRUPT
;
2180 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2183 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2184 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2185 I915_WRITE(GTIER
, gt_irqs
);
2186 POSTING_READ(GTIER
);
2188 if (INTEL_INFO(dev
)->gen
>= 6) {
2189 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2192 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2194 dev_priv
->pm_irq_mask
= 0xffffffff;
2195 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2196 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2197 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2198 POSTING_READ(GEN6_PMIER
);
2202 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2204 unsigned long irqflags
;
2205 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2206 u32 display_mask
, extra_mask
;
2208 if (INTEL_INFO(dev
)->gen
>= 7) {
2209 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2210 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2211 DE_PLANEB_FLIP_DONE_IVB
|
2212 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2214 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2215 DE_PIPEA_VBLANK_IVB
);
2217 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2219 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2220 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2221 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2222 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2223 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2226 dev_priv
->irq_mask
= ~display_mask
;
2228 /* should always can generate irq */
2229 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2230 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2231 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2232 POSTING_READ(DEIER
);
2234 gen5_gt_irq_postinstall(dev
);
2236 ibx_irq_postinstall(dev
);
2238 if (IS_IRONLAKE_M(dev
)) {
2239 /* Enable PCU event interrupts
2241 * spinlocking not required here for correctness since interrupt
2242 * setup is guaranteed to run in single-threaded context. But we
2243 * need it to make the assert_spin_locked happy. */
2244 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2245 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2246 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2252 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2256 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2257 unsigned long irqflags
;
2259 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2260 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2261 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2262 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2263 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2266 *Leave vblank interrupts masked initially. enable/disable will
2267 * toggle them based on usage.
2269 dev_priv
->irq_mask
= (~enable_mask
) |
2270 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2271 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2273 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2274 POSTING_READ(PORT_HOTPLUG_EN
);
2276 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2277 I915_WRITE(VLV_IER
, enable_mask
);
2278 I915_WRITE(VLV_IIR
, 0xffffffff);
2279 I915_WRITE(PIPESTAT(0), 0xffff);
2280 I915_WRITE(PIPESTAT(1), 0xffff);
2281 POSTING_READ(VLV_IER
);
2283 /* Interrupt setup is already guaranteed to be single-threaded, this is
2284 * just to make the assert_spin_locked check happy. */
2285 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2286 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2287 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2288 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2289 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2291 I915_WRITE(VLV_IIR
, 0xffffffff);
2292 I915_WRITE(VLV_IIR
, 0xffffffff);
2294 gen5_gt_irq_postinstall(dev
);
2296 /* ack & enable invalid PTE error interrupts */
2297 #if 0 /* FIXME: add support to irq handler for checking these bits */
2298 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2299 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2302 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2307 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2309 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2315 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2318 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2320 I915_WRITE(HWSTAM
, 0xffffffff);
2321 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2322 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2324 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2325 I915_WRITE(VLV_IIR
, 0xffffffff);
2326 I915_WRITE(VLV_IMR
, 0xffffffff);
2327 I915_WRITE(VLV_IER
, 0x0);
2328 POSTING_READ(VLV_IER
);
2331 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2333 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2338 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2340 I915_WRITE(HWSTAM
, 0xffffffff);
2342 I915_WRITE(DEIMR
, 0xffffffff);
2343 I915_WRITE(DEIER
, 0x0);
2344 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2346 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2348 I915_WRITE(GTIMR
, 0xffffffff);
2349 I915_WRITE(GTIER
, 0x0);
2350 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2352 if (HAS_PCH_NOP(dev
))
2355 I915_WRITE(SDEIMR
, 0xffffffff);
2356 I915_WRITE(SDEIER
, 0x0);
2357 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2358 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2359 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2362 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2364 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2367 atomic_set(&dev_priv
->irq_received
, 0);
2370 I915_WRITE(PIPESTAT(pipe
), 0);
2371 I915_WRITE16(IMR
, 0xffff);
2372 I915_WRITE16(IER
, 0x0);
2373 POSTING_READ16(IER
);
2376 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2378 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2381 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2383 /* Unmask the interrupts that we always want on. */
2384 dev_priv
->irq_mask
=
2385 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2386 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2387 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2388 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2389 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2390 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2393 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2394 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2395 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2396 I915_USER_INTERRUPT
);
2397 POSTING_READ16(IER
);
2403 * Returns true when a page flip has completed.
2405 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2408 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2409 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2411 if (!drm_handle_vblank(dev
, pipe
))
2414 if ((iir
& flip_pending
) == 0)
2417 intel_prepare_page_flip(dev
, pipe
);
2419 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2420 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2421 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2422 * the flip is completed (no longer pending). Since this doesn't raise
2423 * an interrupt per se, we watch for the change at vblank.
2425 if (I915_READ16(ISR
) & flip_pending
)
2428 intel_finish_page_flip(dev
, pipe
);
2433 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2435 struct drm_device
*dev
= (struct drm_device
*) arg
;
2436 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2439 unsigned long irqflags
;
2442 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2443 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2445 atomic_inc(&dev_priv
->irq_received
);
2447 iir
= I915_READ16(IIR
);
2451 while (iir
& ~flip_mask
) {
2452 /* Can't rely on pipestat interrupt bit in iir as it might
2453 * have been cleared after the pipestat interrupt was received.
2454 * It doesn't set the bit in iir again, but it still produces
2455 * interrupts (for non-MSI).
2457 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2458 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2459 i915_handle_error(dev
, false);
2461 for_each_pipe(pipe
) {
2462 int reg
= PIPESTAT(pipe
);
2463 pipe_stats
[pipe
] = I915_READ(reg
);
2466 * Clear the PIPE*STAT regs before the IIR
2468 if (pipe_stats
[pipe
] & 0x8000ffff) {
2469 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2470 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2472 I915_WRITE(reg
, pipe_stats
[pipe
]);
2475 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2477 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2478 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2480 i915_update_dri1_breadcrumb(dev
);
2482 if (iir
& I915_USER_INTERRUPT
)
2483 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2485 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2486 i8xx_handle_vblank(dev
, 0, iir
))
2487 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2489 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2490 i8xx_handle_vblank(dev
, 1, iir
))
2491 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2499 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2501 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2504 for_each_pipe(pipe
) {
2505 /* Clear enable bits; then clear status bits */
2506 I915_WRITE(PIPESTAT(pipe
), 0);
2507 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2509 I915_WRITE16(IMR
, 0xffff);
2510 I915_WRITE16(IER
, 0x0);
2511 I915_WRITE16(IIR
, I915_READ16(IIR
));
2514 static void i915_irq_preinstall(struct drm_device
* dev
)
2516 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2519 atomic_set(&dev_priv
->irq_received
, 0);
2521 if (I915_HAS_HOTPLUG(dev
)) {
2522 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2523 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2526 I915_WRITE16(HWSTAM
, 0xeffe);
2528 I915_WRITE(PIPESTAT(pipe
), 0);
2529 I915_WRITE(IMR
, 0xffffffff);
2530 I915_WRITE(IER
, 0x0);
2534 static int i915_irq_postinstall(struct drm_device
*dev
)
2536 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2539 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2541 /* Unmask the interrupts that we always want on. */
2542 dev_priv
->irq_mask
=
2543 ~(I915_ASLE_INTERRUPT
|
2544 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2545 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2546 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2547 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2548 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2551 I915_ASLE_INTERRUPT
|
2552 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2553 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2554 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2555 I915_USER_INTERRUPT
;
2557 if (I915_HAS_HOTPLUG(dev
)) {
2558 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2559 POSTING_READ(PORT_HOTPLUG_EN
);
2561 /* Enable in IER... */
2562 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2563 /* and unmask in IMR */
2564 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2567 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2568 I915_WRITE(IER
, enable_mask
);
2571 i915_enable_asle_pipestat(dev
);
2577 * Returns true when a page flip has completed.
2579 static bool i915_handle_vblank(struct drm_device
*dev
,
2580 int plane
, int pipe
, u32 iir
)
2582 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2583 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2585 if (!drm_handle_vblank(dev
, pipe
))
2588 if ((iir
& flip_pending
) == 0)
2591 intel_prepare_page_flip(dev
, plane
);
2593 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2594 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2595 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2596 * the flip is completed (no longer pending). Since this doesn't raise
2597 * an interrupt per se, we watch for the change at vblank.
2599 if (I915_READ(ISR
) & flip_pending
)
2602 intel_finish_page_flip(dev
, pipe
);
2607 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2609 struct drm_device
*dev
= (struct drm_device
*) arg
;
2610 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2611 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2612 unsigned long irqflags
;
2614 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2615 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2616 int pipe
, ret
= IRQ_NONE
;
2618 atomic_inc(&dev_priv
->irq_received
);
2620 iir
= I915_READ(IIR
);
2622 bool irq_received
= (iir
& ~flip_mask
) != 0;
2623 bool blc_event
= false;
2625 /* Can't rely on pipestat interrupt bit in iir as it might
2626 * have been cleared after the pipestat interrupt was received.
2627 * It doesn't set the bit in iir again, but it still produces
2628 * interrupts (for non-MSI).
2630 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2631 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2632 i915_handle_error(dev
, false);
2634 for_each_pipe(pipe
) {
2635 int reg
= PIPESTAT(pipe
);
2636 pipe_stats
[pipe
] = I915_READ(reg
);
2638 /* Clear the PIPE*STAT regs before the IIR */
2639 if (pipe_stats
[pipe
] & 0x8000ffff) {
2640 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2641 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2643 I915_WRITE(reg
, pipe_stats
[pipe
]);
2644 irq_received
= true;
2647 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2652 /* Consume port. Then clear IIR or we'll miss events */
2653 if ((I915_HAS_HOTPLUG(dev
)) &&
2654 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2655 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2656 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2658 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2661 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2663 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2664 POSTING_READ(PORT_HOTPLUG_STAT
);
2667 I915_WRITE(IIR
, iir
& ~flip_mask
);
2668 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2670 if (iir
& I915_USER_INTERRUPT
)
2671 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2673 for_each_pipe(pipe
) {
2678 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2679 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2680 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2682 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2686 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2687 intel_opregion_asle_intr(dev
);
2689 /* With MSI, interrupts are only generated when iir
2690 * transitions from zero to nonzero. If another bit got
2691 * set while we were handling the existing iir bits, then
2692 * we would never get another interrupt.
2694 * This is fine on non-MSI as well, as if we hit this path
2695 * we avoid exiting the interrupt handler only to generate
2698 * Note that for MSI this could cause a stray interrupt report
2699 * if an interrupt landed in the time between writing IIR and
2700 * the posting read. This should be rare enough to never
2701 * trigger the 99% of 100,000 interrupts test for disabling
2706 } while (iir
& ~flip_mask
);
2708 i915_update_dri1_breadcrumb(dev
);
2713 static void i915_irq_uninstall(struct drm_device
* dev
)
2715 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2718 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2720 if (I915_HAS_HOTPLUG(dev
)) {
2721 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2722 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2725 I915_WRITE16(HWSTAM
, 0xffff);
2726 for_each_pipe(pipe
) {
2727 /* Clear enable bits; then clear status bits */
2728 I915_WRITE(PIPESTAT(pipe
), 0);
2729 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2731 I915_WRITE(IMR
, 0xffffffff);
2732 I915_WRITE(IER
, 0x0);
2734 I915_WRITE(IIR
, I915_READ(IIR
));
2737 static void i965_irq_preinstall(struct drm_device
* dev
)
2739 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2742 atomic_set(&dev_priv
->irq_received
, 0);
2744 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2745 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2747 I915_WRITE(HWSTAM
, 0xeffe);
2749 I915_WRITE(PIPESTAT(pipe
), 0);
2750 I915_WRITE(IMR
, 0xffffffff);
2751 I915_WRITE(IER
, 0x0);
2755 static int i965_irq_postinstall(struct drm_device
*dev
)
2757 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2760 unsigned long irqflags
;
2762 /* Unmask the interrupts that we always want on. */
2763 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2764 I915_DISPLAY_PORT_INTERRUPT
|
2765 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2766 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2767 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2768 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2769 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2771 enable_mask
= ~dev_priv
->irq_mask
;
2772 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2773 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2774 enable_mask
|= I915_USER_INTERRUPT
;
2777 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2779 /* Interrupt setup is already guaranteed to be single-threaded, this is
2780 * just to make the assert_spin_locked check happy. */
2781 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2782 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2783 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2786 * Enable some error detection, note the instruction error mask
2787 * bit is reserved, so we leave it masked.
2790 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2791 GM45_ERROR_MEM_PRIV
|
2792 GM45_ERROR_CP_PRIV
|
2793 I915_ERROR_MEMORY_REFRESH
);
2795 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2796 I915_ERROR_MEMORY_REFRESH
);
2798 I915_WRITE(EMR
, error_mask
);
2800 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2801 I915_WRITE(IER
, enable_mask
);
2804 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2805 POSTING_READ(PORT_HOTPLUG_EN
);
2807 i915_enable_asle_pipestat(dev
);
2812 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2814 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2815 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2816 struct intel_encoder
*intel_encoder
;
2819 assert_spin_locked(&dev_priv
->irq_lock
);
2821 if (I915_HAS_HOTPLUG(dev
)) {
2822 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2823 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2824 /* Note HDMI and DP share hotplug bits */
2825 /* enable bits are the same for all generations */
2826 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2827 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2828 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2829 /* Programming the CRT detection parameters tends
2830 to generate a spurious hotplug event about three
2831 seconds later. So just do it once.
2834 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2835 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2836 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2838 /* Ignore TV since it's buggy */
2839 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2843 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2845 struct drm_device
*dev
= (struct drm_device
*) arg
;
2846 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2848 u32 pipe_stats
[I915_MAX_PIPES
];
2849 unsigned long irqflags
;
2851 int ret
= IRQ_NONE
, pipe
;
2853 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2854 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2856 atomic_inc(&dev_priv
->irq_received
);
2858 iir
= I915_READ(IIR
);
2861 bool blc_event
= false;
2863 irq_received
= (iir
& ~flip_mask
) != 0;
2865 /* Can't rely on pipestat interrupt bit in iir as it might
2866 * have been cleared after the pipestat interrupt was received.
2867 * It doesn't set the bit in iir again, but it still produces
2868 * interrupts (for non-MSI).
2870 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2871 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2872 i915_handle_error(dev
, false);
2874 for_each_pipe(pipe
) {
2875 int reg
= PIPESTAT(pipe
);
2876 pipe_stats
[pipe
] = I915_READ(reg
);
2879 * Clear the PIPE*STAT regs before the IIR
2881 if (pipe_stats
[pipe
] & 0x8000ffff) {
2882 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2883 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2885 I915_WRITE(reg
, pipe_stats
[pipe
]);
2889 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2896 /* Consume port. Then clear IIR or we'll miss events */
2897 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2898 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2899 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2900 HOTPLUG_INT_STATUS_G4X
:
2901 HOTPLUG_INT_STATUS_I915
);
2903 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2906 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2907 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2909 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2910 I915_READ(PORT_HOTPLUG_STAT
);
2913 I915_WRITE(IIR
, iir
& ~flip_mask
);
2914 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2916 if (iir
& I915_USER_INTERRUPT
)
2917 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2918 if (iir
& I915_BSD_USER_INTERRUPT
)
2919 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2921 for_each_pipe(pipe
) {
2922 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2923 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2924 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2926 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2931 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2932 intel_opregion_asle_intr(dev
);
2934 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2935 gmbus_irq_handler(dev
);
2937 /* With MSI, interrupts are only generated when iir
2938 * transitions from zero to nonzero. If another bit got
2939 * set while we were handling the existing iir bits, then
2940 * we would never get another interrupt.
2942 * This is fine on non-MSI as well, as if we hit this path
2943 * we avoid exiting the interrupt handler only to generate
2946 * Note that for MSI this could cause a stray interrupt report
2947 * if an interrupt landed in the time between writing IIR and
2948 * the posting read. This should be rare enough to never
2949 * trigger the 99% of 100,000 interrupts test for disabling
2955 i915_update_dri1_breadcrumb(dev
);
2960 static void i965_irq_uninstall(struct drm_device
* dev
)
2962 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2968 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2970 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2971 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2973 I915_WRITE(HWSTAM
, 0xffffffff);
2975 I915_WRITE(PIPESTAT(pipe
), 0);
2976 I915_WRITE(IMR
, 0xffffffff);
2977 I915_WRITE(IER
, 0x0);
2980 I915_WRITE(PIPESTAT(pipe
),
2981 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2982 I915_WRITE(IIR
, I915_READ(IIR
));
2985 static void i915_reenable_hotplug_timer_func(unsigned long data
)
2987 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
2988 struct drm_device
*dev
= dev_priv
->dev
;
2989 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2990 unsigned long irqflags
;
2993 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2994 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
2995 struct drm_connector
*connector
;
2997 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3000 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3002 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3003 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3005 if (intel_connector
->encoder
->hpd_pin
== i
) {
3006 if (connector
->polled
!= intel_connector
->polled
)
3007 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3008 drm_get_connector_name(connector
));
3009 connector
->polled
= intel_connector
->polled
;
3010 if (!connector
->polled
)
3011 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3015 if (dev_priv
->display
.hpd_irq_setup
)
3016 dev_priv
->display
.hpd_irq_setup(dev
);
3017 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3020 void intel_irq_init(struct drm_device
*dev
)
3022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3024 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3025 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3026 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3027 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3029 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3030 i915_hangcheck_elapsed
,
3031 (unsigned long) dev
);
3032 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3033 (unsigned long) dev_priv
);
3035 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3037 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3038 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3039 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3040 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3041 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3044 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3045 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3047 dev
->driver
->get_vblank_timestamp
= NULL
;
3048 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3050 if (IS_VALLEYVIEW(dev
)) {
3051 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3052 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3053 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3054 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3055 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3056 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3057 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3058 } else if (HAS_PCH_SPLIT(dev
)) {
3059 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3060 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3061 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3062 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3063 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3064 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3065 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3067 if (INTEL_INFO(dev
)->gen
== 2) {
3068 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3069 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3070 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3071 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3072 } else if (INTEL_INFO(dev
)->gen
== 3) {
3073 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3074 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3075 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3076 dev
->driver
->irq_handler
= i915_irq_handler
;
3077 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3079 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3080 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3081 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3082 dev
->driver
->irq_handler
= i965_irq_handler
;
3083 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3085 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3086 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3090 void intel_hpd_init(struct drm_device
*dev
)
3092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3093 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3094 struct drm_connector
*connector
;
3095 unsigned long irqflags
;
3098 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3099 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3100 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3102 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3103 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3104 connector
->polled
= intel_connector
->polled
;
3105 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3106 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3109 /* Interrupt setup is already guaranteed to be single-threaded, this is
3110 * just to make the assert_spin_locked checks happy. */
3111 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3112 if (dev_priv
->display
.hpd_irq_setup
)
3113 dev_priv
->display
.hpd_irq_setup(dev
);
3114 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);