1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
264 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
266 ilk_update_gt_irq(dev_priv
, mask
, mask
);
267 POSTING_READ_FW(GTIMR
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
)
341 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
343 spin_lock_irq(&dev_priv
->irq_lock
);
344 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
347 dev_priv
->rps
.pm_iir
= 0;
348 spin_unlock_irq(&dev_priv
->irq_lock
);
351 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
353 spin_lock_irq(&dev_priv
->irq_lock
);
354 WARN_ON_ONCE(dev_priv
->rps
.pm_iir
);
355 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
356 dev_priv
->rps
.interrupts_enabled
= true;
357 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
358 dev_priv
->pm_rps_events
);
359 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
361 spin_unlock_irq(&dev_priv
->irq_lock
);
364 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
366 return (mask
& ~dev_priv
->rps
.pm_intr_keep
);
369 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
371 spin_lock_irq(&dev_priv
->irq_lock
);
372 dev_priv
->rps
.interrupts_enabled
= false;
374 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
376 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
377 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
378 ~dev_priv
->pm_rps_events
);
380 spin_unlock_irq(&dev_priv
->irq_lock
);
381 synchronize_irq(dev_priv
->drm
.irq
);
383 /* Now that we will not be generating any more work, flush any
384 * outsanding tasks. As we are called on the RPS idle path,
385 * we will reset the GPU to minimum frequencies, so the current
386 * state of the worker can be discarded.
388 cancel_work_sync(&dev_priv
->rps
.work
);
389 gen6_reset_rps_interrupts(dev_priv
);
393 * bdw_update_port_irq - update DE port interrupt
394 * @dev_priv: driver private
395 * @interrupt_mask: mask of interrupt bits to update
396 * @enabled_irq_mask: mask of interrupt bits to enable
398 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
399 uint32_t interrupt_mask
,
400 uint32_t enabled_irq_mask
)
405 assert_spin_locked(&dev_priv
->irq_lock
);
407 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
409 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
412 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
415 new_val
&= ~interrupt_mask
;
416 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
418 if (new_val
!= old_val
) {
419 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
420 POSTING_READ(GEN8_DE_PORT_IMR
);
425 * bdw_update_pipe_irq - update DE pipe interrupt
426 * @dev_priv: driver private
427 * @pipe: pipe whose interrupt to update
428 * @interrupt_mask: mask of interrupt bits to update
429 * @enabled_irq_mask: mask of interrupt bits to enable
431 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
433 uint32_t interrupt_mask
,
434 uint32_t enabled_irq_mask
)
438 assert_spin_locked(&dev_priv
->irq_lock
);
440 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
442 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
445 new_val
= dev_priv
->de_irq_mask
[pipe
];
446 new_val
&= ~interrupt_mask
;
447 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
449 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
450 dev_priv
->de_irq_mask
[pipe
] = new_val
;
451 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
452 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
457 * ibx_display_interrupt_update - update SDEIMR
458 * @dev_priv: driver private
459 * @interrupt_mask: mask of interrupt bits to update
460 * @enabled_irq_mask: mask of interrupt bits to enable
462 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
463 uint32_t interrupt_mask
,
464 uint32_t enabled_irq_mask
)
466 uint32_t sdeimr
= I915_READ(SDEIMR
);
467 sdeimr
&= ~interrupt_mask
;
468 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
470 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
472 assert_spin_locked(&dev_priv
->irq_lock
);
474 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
477 I915_WRITE(SDEIMR
, sdeimr
);
478 POSTING_READ(SDEIMR
);
482 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
483 u32 enable_mask
, u32 status_mask
)
485 i915_reg_t reg
= PIPESTAT(pipe
);
486 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
488 assert_spin_locked(&dev_priv
->irq_lock
);
489 WARN_ON(!intel_irqs_enabled(dev_priv
));
491 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
492 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
493 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
494 pipe_name(pipe
), enable_mask
, status_mask
))
497 if ((pipestat
& enable_mask
) == enable_mask
)
500 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
502 /* Enable the interrupt, clear any pending status */
503 pipestat
|= enable_mask
| status_mask
;
504 I915_WRITE(reg
, pipestat
);
509 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
510 u32 enable_mask
, u32 status_mask
)
512 i915_reg_t reg
= PIPESTAT(pipe
);
513 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
515 assert_spin_locked(&dev_priv
->irq_lock
);
516 WARN_ON(!intel_irqs_enabled(dev_priv
));
518 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
519 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
520 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
521 pipe_name(pipe
), enable_mask
, status_mask
))
524 if ((pipestat
& enable_mask
) == 0)
527 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
529 pipestat
&= ~enable_mask
;
530 I915_WRITE(reg
, pipestat
);
534 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
536 u32 enable_mask
= status_mask
<< 16;
539 * On pipe A we don't support the PSR interrupt yet,
540 * on pipe B and C the same bit MBZ.
542 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
545 * On pipe B and C we don't support the PSR interrupt yet, on pipe
546 * A the same bit is for perf counters which we don't use either.
548 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
551 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
552 SPRITE0_FLIP_DONE_INT_EN_VLV
|
553 SPRITE1_FLIP_DONE_INT_EN_VLV
);
554 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
555 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
556 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
557 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
563 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
568 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
569 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
572 enable_mask
= status_mask
<< 16;
573 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
577 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
582 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
583 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
586 enable_mask
= status_mask
<< 16;
587 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
591 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
592 * @dev_priv: i915 device private
594 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
596 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
599 spin_lock_irq(&dev_priv
->irq_lock
);
601 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
602 if (INTEL_GEN(dev_priv
) >= 4)
603 i915_enable_pipestat(dev_priv
, PIPE_A
,
604 PIPE_LEGACY_BLC_EVENT_STATUS
);
606 spin_unlock_irq(&dev_priv
->irq_lock
);
610 * This timing diagram depicts the video signal in and
611 * around the vertical blanking period.
613 * Assumptions about the fictitious mode used in this example:
615 * vsync_start = vblank_start + 1
616 * vsync_end = vblank_start + 2
617 * vtotal = vblank_start + 3
620 * latch double buffered registers
621 * increment frame counter (ctg+)
622 * generate start of vblank interrupt (gen4+)
625 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
626 * | may be shifted forward 1-3 extra lines via PIPECONF
628 * | | start of vsync:
629 * | | generate vsync interrupt
631 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
632 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
633 * ----va---> <-----------------vb--------------------> <--------va-------------
634 * | | <----vs-----> |
635 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
636 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
637 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
639 * last visible pixel first visible pixel
640 * | increment frame counter (gen3/4)
641 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
643 * x = horizontal active
644 * _ = horizontal blanking
645 * hs = horizontal sync
646 * va = vertical active
647 * vb = vertical blanking
649 * vbs = vblank_start (number)
652 * - most events happen at the start of horizontal sync
653 * - frame start happens at the start of horizontal blank, 1-4 lines
654 * (depending on PIPECONF settings) after the start of vblank
655 * - gen3/4 pixel and frame counter are synchronized with the start
656 * of horizontal active on the first line of vertical active
659 /* Called from drm generic code, passed a 'crtc', which
660 * we use as a pipe index
662 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
664 struct drm_i915_private
*dev_priv
= to_i915(dev
);
665 i915_reg_t high_frame
, low_frame
;
666 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
667 struct intel_crtc
*intel_crtc
=
668 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
669 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
671 htotal
= mode
->crtc_htotal
;
672 hsync_start
= mode
->crtc_hsync_start
;
673 vbl_start
= mode
->crtc_vblank_start
;
674 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
675 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
677 /* Convert to pixel count */
680 /* Start of vblank event occurs at start of hsync */
681 vbl_start
-= htotal
- hsync_start
;
683 high_frame
= PIPEFRAME(pipe
);
684 low_frame
= PIPEFRAMEPIXEL(pipe
);
687 * High & low register fields aren't synchronized, so make sure
688 * we get a low value that's stable across two reads of the high
692 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
693 low
= I915_READ(low_frame
);
694 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
695 } while (high1
!= high2
);
697 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
698 pixel
= low
& PIPE_PIXEL_MASK
;
699 low
>>= PIPE_FRAME_LOW_SHIFT
;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
709 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
711 struct drm_i915_private
*dev_priv
= to_i915(dev
);
713 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
716 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
717 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
719 struct drm_device
*dev
= crtc
->base
.dev
;
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
721 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
722 enum pipe pipe
= crtc
->pipe
;
723 int position
, vtotal
;
725 vtotal
= mode
->crtc_vtotal
;
726 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
729 if (IS_GEN2(dev_priv
))
730 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
732 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
735 * On HSW, the DSL reg (0x70000) appears to return 0 if we
736 * read it just before the start of vblank. So try it again
737 * so we don't accidentally end up spanning a vblank frame
738 * increment, causing the pipe_update_end() code to squak at us.
740 * The nature of this problem means we can't simply check the ISR
741 * bit and return the vblank start value; nor can we use the scanline
742 * debug register in the transcoder as it appears to have the same
743 * problem. We may need to extend this to include other platforms,
744 * but so far testing only shows the problem on HSW.
746 if (HAS_DDI(dev_priv
) && !position
) {
749 for (i
= 0; i
< 100; i
++) {
751 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
753 if (temp
!= position
) {
761 * See update_scanline_offset() for the details on the
762 * scanline_offset adjustment.
764 return (position
+ crtc
->scanline_offset
) % vtotal
;
767 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
768 unsigned int flags
, int *vpos
, int *hpos
,
769 ktime_t
*stime
, ktime_t
*etime
,
770 const struct drm_display_mode
*mode
)
772 struct drm_i915_private
*dev_priv
= to_i915(dev
);
773 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
776 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
779 unsigned long irqflags
;
781 if (WARN_ON(!mode
->crtc_clock
)) {
782 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
783 "pipe %c\n", pipe_name(pipe
));
787 htotal
= mode
->crtc_htotal
;
788 hsync_start
= mode
->crtc_hsync_start
;
789 vtotal
= mode
->crtc_vtotal
;
790 vbl_start
= mode
->crtc_vblank_start
;
791 vbl_end
= mode
->crtc_vblank_end
;
793 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
794 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
799 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
802 * Lock uncore.lock, as we will do multiple timing critical raw
803 * register reads, potentially with preemption disabled, so the
804 * following code must not block on uncore.lock.
806 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
808 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
810 /* Get optional system timestamp before query. */
812 *stime
= ktime_get();
814 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
815 /* No obvious pixelcount register. Only query vertical
816 * scanout position from Display scan line register.
818 position
= __intel_get_crtc_scanline(intel_crtc
);
820 /* Have access to pixelcount since start of frame.
821 * We can split this into vertical and horizontal
824 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
826 /* convert to pixel counts */
832 * In interlaced modes, the pixel counter counts all pixels,
833 * so one field will have htotal more pixels. In order to avoid
834 * the reported position from jumping backwards when the pixel
835 * counter is beyond the length of the shorter field, just
836 * clamp the position the length of the shorter field. This
837 * matches how the scanline counter based position works since
838 * the scanline counter doesn't count the two half lines.
840 if (position
>= vtotal
)
841 position
= vtotal
- 1;
844 * Start of vblank interrupt is triggered at start of hsync,
845 * just prior to the first active line of vblank. However we
846 * consider lines to start at the leading edge of horizontal
847 * active. So, should we get here before we've crossed into
848 * the horizontal active of the first line in vblank, we would
849 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
850 * always add htotal-hsync_start to the current pixel position.
852 position
= (position
+ htotal
- hsync_start
) % vtotal
;
855 /* Get optional system timestamp after query. */
857 *etime
= ktime_get();
859 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
861 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
863 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
866 * While in vblank, position will be negative
867 * counting up towards 0 at vbl_end. And outside
868 * vblank, position will be positive counting
871 if (position
>= vbl_start
)
874 position
+= vtotal
- vbl_end
;
876 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
880 *vpos
= position
/ htotal
;
881 *hpos
= position
- (*vpos
* htotal
);
886 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
891 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
893 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
894 unsigned long irqflags
;
897 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
898 position
= __intel_get_crtc_scanline(crtc
);
899 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
904 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
906 struct timeval
*vblank_time
,
909 struct drm_crtc
*crtc
;
911 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
912 DRM_ERROR("Invalid crtc %u\n", pipe
);
916 /* Get drm_crtc to timestamp: */
917 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
919 DRM_ERROR("Invalid crtc %u\n", pipe
);
923 if (!crtc
->hwmode
.crtc_clock
) {
924 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
928 /* Helper routine in DRM core does all the work: */
929 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
934 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
936 u32 busy_up
, busy_down
, max_avg
, min_avg
;
939 spin_lock(&mchdev_lock
);
941 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
943 new_delay
= dev_priv
->ips
.cur_delay
;
945 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
946 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
947 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
948 max_avg
= I915_READ(RCBMAXAVG
);
949 min_avg
= I915_READ(RCBMINAVG
);
951 /* Handle RCS change request from hw */
952 if (busy_up
> max_avg
) {
953 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
954 new_delay
= dev_priv
->ips
.cur_delay
- 1;
955 if (new_delay
< dev_priv
->ips
.max_delay
)
956 new_delay
= dev_priv
->ips
.max_delay
;
957 } else if (busy_down
< min_avg
) {
958 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
959 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
960 if (new_delay
> dev_priv
->ips
.min_delay
)
961 new_delay
= dev_priv
->ips
.min_delay
;
964 if (ironlake_set_drps(dev_priv
, new_delay
))
965 dev_priv
->ips
.cur_delay
= new_delay
;
967 spin_unlock(&mchdev_lock
);
972 static void notify_ring(struct intel_engine_cs
*engine
)
974 smp_store_mb(engine
->breadcrumbs
.irq_posted
, true);
975 if (intel_engine_wakeup(engine
)) {
976 trace_i915_gem_request_notify(engine
);
977 engine
->breadcrumbs
.irq_wakeups
++;
981 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
982 struct intel_rps_ei
*ei
)
984 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
985 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
986 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
989 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
990 const struct intel_rps_ei
*old
,
991 const struct intel_rps_ei
*now
,
995 unsigned int mul
= 100;
997 if (old
->cz_clock
== 0)
1000 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1003 time
= now
->cz_clock
- old
->cz_clock
;
1004 time
*= threshold
* dev_priv
->czclk_freq
;
1006 /* Workload can be split between render + media, e.g. SwapBuffers
1007 * being blitted in X after being rendered in mesa. To account for
1008 * this we need to combine both engines into our activity counter.
1010 c0
= now
->render_c0
- old
->render_c0
;
1011 c0
+= now
->media_c0
- old
->media_c0
;
1012 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1017 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1019 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1020 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1023 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1025 struct intel_rps_ei now
;
1028 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1031 vlv_c0_read(dev_priv
, &now
);
1032 if (now
.cz_clock
== 0)
1035 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1036 if (!vlv_c0_above(dev_priv
,
1037 &dev_priv
->rps
.down_ei
, &now
,
1038 dev_priv
->rps
.down_threshold
))
1039 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1040 dev_priv
->rps
.down_ei
= now
;
1043 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1044 if (vlv_c0_above(dev_priv
,
1045 &dev_priv
->rps
.up_ei
, &now
,
1046 dev_priv
->rps
.up_threshold
))
1047 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1048 dev_priv
->rps
.up_ei
= now
;
1054 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1056 struct intel_engine_cs
*engine
;
1058 for_each_engine(engine
, dev_priv
)
1059 if (intel_engine_has_waiter(engine
))
1065 static void gen6_pm_rps_work(struct work_struct
*work
)
1067 struct drm_i915_private
*dev_priv
=
1068 container_of(work
, struct drm_i915_private
, rps
.work
);
1070 int new_delay
, adj
, min
, max
;
1073 spin_lock_irq(&dev_priv
->irq_lock
);
1074 /* Speed up work cancelation during disabling rps interrupts. */
1075 if (!dev_priv
->rps
.interrupts_enabled
) {
1076 spin_unlock_irq(&dev_priv
->irq_lock
);
1080 pm_iir
= dev_priv
->rps
.pm_iir
;
1081 dev_priv
->rps
.pm_iir
= 0;
1082 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1083 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1084 client_boost
= dev_priv
->rps
.client_boost
;
1085 dev_priv
->rps
.client_boost
= false;
1086 spin_unlock_irq(&dev_priv
->irq_lock
);
1088 /* Make sure we didn't queue anything we're not going to process. */
1089 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1091 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1094 mutex_lock(&dev_priv
->rps
.hw_lock
);
1096 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1098 adj
= dev_priv
->rps
.last_adj
;
1099 new_delay
= dev_priv
->rps
.cur_freq
;
1100 min
= dev_priv
->rps
.min_freq_softlimit
;
1101 max
= dev_priv
->rps
.max_freq_softlimit
;
1102 if (client_boost
|| any_waiters(dev_priv
))
1103 max
= dev_priv
->rps
.max_freq
;
1104 if (client_boost
&& new_delay
< dev_priv
->rps
.boost_freq
) {
1105 new_delay
= dev_priv
->rps
.boost_freq
;
1107 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1110 else /* CHV needs even encode values */
1111 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1113 * For better performance, jump directly
1114 * to RPe if we're below it.
1116 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1117 new_delay
= dev_priv
->rps
.efficient_freq
;
1120 } else if (client_boost
|| any_waiters(dev_priv
)) {
1122 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1123 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1124 new_delay
= dev_priv
->rps
.efficient_freq
;
1126 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1128 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1131 else /* CHV needs even encode values */
1132 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1133 } else { /* unknown event */
1137 dev_priv
->rps
.last_adj
= adj
;
1139 /* sysfs frequency interfaces may have snuck in while servicing the
1143 new_delay
= clamp_t(int, new_delay
, min
, max
);
1145 intel_set_rps(dev_priv
, new_delay
);
1147 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1152 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1154 * @work: workqueue struct
1156 * Doesn't actually do anything except notify userspace. As a consequence of
1157 * this event, userspace should try to remap the bad rows since statistically
1158 * it is likely the same row is more likely to go bad again.
1160 static void ivybridge_parity_work(struct work_struct
*work
)
1162 struct drm_i915_private
*dev_priv
=
1163 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1164 u32 error_status
, row
, bank
, subbank
;
1165 char *parity_event
[6];
1169 /* We must turn off DOP level clock gating to access the L3 registers.
1170 * In order to prevent a get/put style interface, acquire struct mutex
1171 * any time we access those registers.
1173 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1175 /* If we've screwed up tracking, just let the interrupt fire again */
1176 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1179 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1180 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1181 POSTING_READ(GEN7_MISCCPCTL
);
1183 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1187 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1190 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1192 reg
= GEN7_L3CDERRST1(slice
);
1194 error_status
= I915_READ(reg
);
1195 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1196 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1197 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1199 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1202 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1203 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1204 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1205 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1206 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1207 parity_event
[5] = NULL
;
1209 kobject_uevent_env(&dev_priv
->drm
.primary
->kdev
->kobj
,
1210 KOBJ_CHANGE
, parity_event
);
1212 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1213 slice
, row
, bank
, subbank
);
1215 kfree(parity_event
[4]);
1216 kfree(parity_event
[3]);
1217 kfree(parity_event
[2]);
1218 kfree(parity_event
[1]);
1221 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1224 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1225 spin_lock_irq(&dev_priv
->irq_lock
);
1226 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1227 spin_unlock_irq(&dev_priv
->irq_lock
);
1229 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1232 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1235 if (!HAS_L3_DPF(dev_priv
))
1238 spin_lock(&dev_priv
->irq_lock
);
1239 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1240 spin_unlock(&dev_priv
->irq_lock
);
1242 iir
&= GT_PARITY_ERROR(dev_priv
);
1243 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1244 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1246 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1247 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1249 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1252 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1255 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1256 notify_ring(&dev_priv
->engine
[RCS
]);
1257 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1258 notify_ring(&dev_priv
->engine
[VCS
]);
1261 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1264 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1265 notify_ring(&dev_priv
->engine
[RCS
]);
1266 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1267 notify_ring(&dev_priv
->engine
[VCS
]);
1268 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1269 notify_ring(&dev_priv
->engine
[BCS
]);
1271 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1272 GT_BSD_CS_ERROR_INTERRUPT
|
1273 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1274 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1276 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1277 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1280 static __always_inline
void
1281 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1283 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1284 notify_ring(engine
);
1285 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1286 tasklet_schedule(&engine
->irq_tasklet
);
1289 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1293 irqreturn_t ret
= IRQ_NONE
;
1295 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1296 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1298 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1301 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1304 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1305 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1307 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1310 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1313 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1314 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1316 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1319 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1322 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1323 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1324 if (gt_iir
[2] & dev_priv
->pm_rps_events
) {
1325 I915_WRITE_FW(GEN8_GT_IIR(2),
1326 gt_iir
[2] & dev_priv
->pm_rps_events
);
1329 DRM_ERROR("The master control interrupt lied (PM)!\n");
1335 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1339 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1340 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1341 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1342 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1346 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1347 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1348 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1349 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1353 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1354 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1356 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1357 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1360 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1364 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1366 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1368 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1374 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1378 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1384 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1388 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1390 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1392 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1394 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1400 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1404 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1410 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1414 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1416 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1418 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1424 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1428 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1430 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1432 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1439 * Get a bit mask of pins that have triggered, and which ones may be long.
1440 * This can be called multiple times with the same masks to accumulate
1441 * hotplug detection results from several registers.
1443 * Note that the caller is expected to zero out the masks initially.
1445 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1446 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1447 const u32 hpd
[HPD_NUM_PINS
],
1448 bool long_pulse_detect(enum port port
, u32 val
))
1453 for_each_hpd_pin(i
) {
1454 if ((hpd
[i
] & hotplug_trigger
) == 0)
1457 *pin_mask
|= BIT(i
);
1459 if (!intel_hpd_pin_to_port(i
, &port
))
1462 if (long_pulse_detect(port
, dig_hotplug_reg
))
1463 *long_mask
|= BIT(i
);
1466 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1467 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1471 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1473 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1476 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1478 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1481 #if defined(CONFIG_DEBUG_FS)
1482 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1484 uint32_t crc0
, uint32_t crc1
,
1485 uint32_t crc2
, uint32_t crc3
,
1488 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1489 struct intel_pipe_crc_entry
*entry
;
1492 spin_lock(&pipe_crc
->lock
);
1494 if (!pipe_crc
->entries
) {
1495 spin_unlock(&pipe_crc
->lock
);
1496 DRM_DEBUG_KMS("spurious interrupt\n");
1500 head
= pipe_crc
->head
;
1501 tail
= pipe_crc
->tail
;
1503 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1504 spin_unlock(&pipe_crc
->lock
);
1505 DRM_ERROR("CRC buffer overflowing\n");
1509 entry
= &pipe_crc
->entries
[head
];
1511 entry
->frame
= dev_priv
->drm
.driver
->get_vblank_counter(&dev_priv
->drm
,
1513 entry
->crc
[0] = crc0
;
1514 entry
->crc
[1] = crc1
;
1515 entry
->crc
[2] = crc2
;
1516 entry
->crc
[3] = crc3
;
1517 entry
->crc
[4] = crc4
;
1519 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1520 pipe_crc
->head
= head
;
1522 spin_unlock(&pipe_crc
->lock
);
1524 wake_up_interruptible(&pipe_crc
->wq
);
1528 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1530 uint32_t crc0
, uint32_t crc1
,
1531 uint32_t crc2
, uint32_t crc3
,
1536 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1539 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1540 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1544 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1547 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1548 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1549 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1550 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1551 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1552 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1555 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1558 uint32_t res1
, res2
;
1560 if (INTEL_GEN(dev_priv
) >= 3)
1561 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1565 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1566 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1570 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1571 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1572 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1573 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1577 /* The RPS events need forcewake, so we add them to a work queue and mask their
1578 * IMR bits until the work is done. Other interrupts can be processed without
1579 * the work queue. */
1580 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1582 if (pm_iir
& dev_priv
->pm_rps_events
) {
1583 spin_lock(&dev_priv
->irq_lock
);
1584 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1585 if (dev_priv
->rps
.interrupts_enabled
) {
1586 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1587 schedule_work(&dev_priv
->rps
.work
);
1589 spin_unlock(&dev_priv
->irq_lock
);
1592 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1595 if (HAS_VEBOX(dev_priv
)) {
1596 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1597 notify_ring(&dev_priv
->engine
[VECS
]);
1599 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1600 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1604 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1609 ret
= drm_handle_vblank(&dev_priv
->drm
, pipe
);
1611 intel_finish_page_flip_mmio(dev_priv
, pipe
);
1616 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1617 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1621 spin_lock(&dev_priv
->irq_lock
);
1623 if (!dev_priv
->display_irqs_enabled
) {
1624 spin_unlock(&dev_priv
->irq_lock
);
1628 for_each_pipe(dev_priv
, pipe
) {
1630 u32 mask
, iir_bit
= 0;
1633 * PIPESTAT bits get signalled even when the interrupt is
1634 * disabled with the mask bits, and some of the status bits do
1635 * not generate interrupts at all (like the underrun bit). Hence
1636 * we need to be careful that we only handle what we want to
1640 /* fifo underruns are filterered in the underrun handler. */
1641 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1645 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1648 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1651 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1655 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1660 reg
= PIPESTAT(pipe
);
1661 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1662 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1665 * Clear the PIPE*STAT regs before the IIR
1667 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1668 PIPESTAT_INT_STATUS_MASK
))
1669 I915_WRITE(reg
, pipe_stats
[pipe
]);
1671 spin_unlock(&dev_priv
->irq_lock
);
1674 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1675 u32 pipe_stats
[I915_MAX_PIPES
])
1679 for_each_pipe(dev_priv
, pipe
) {
1680 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1681 intel_pipe_handle_vblank(dev_priv
, pipe
))
1682 intel_check_page_flip(dev_priv
, pipe
);
1684 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
)
1685 intel_finish_page_flip_cs(dev_priv
, pipe
);
1687 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1688 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1690 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1691 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1694 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1695 gmbus_irq_handler(dev_priv
);
1698 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1700 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1703 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1705 return hotplug_status
;
1708 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1711 u32 pin_mask
= 0, long_mask
= 0;
1713 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1714 IS_CHERRYVIEW(dev_priv
)) {
1715 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1717 if (hotplug_trigger
) {
1718 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1719 hotplug_trigger
, hpd_status_g4x
,
1720 i9xx_port_hotplug_long_detect
);
1722 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1725 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1726 dp_aux_irq_handler(dev_priv
);
1728 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1730 if (hotplug_trigger
) {
1731 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1732 hotplug_trigger
, hpd_status_i915
,
1733 i9xx_port_hotplug_long_detect
);
1734 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1739 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1741 struct drm_device
*dev
= arg
;
1742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1743 irqreturn_t ret
= IRQ_NONE
;
1745 if (!intel_irqs_enabled(dev_priv
))
1748 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1749 disable_rpm_wakeref_asserts(dev_priv
);
1752 u32 iir
, gt_iir
, pm_iir
;
1753 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1754 u32 hotplug_status
= 0;
1757 gt_iir
= I915_READ(GTIIR
);
1758 pm_iir
= I915_READ(GEN6_PMIIR
);
1759 iir
= I915_READ(VLV_IIR
);
1761 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1767 * Theory on interrupt generation, based on empirical evidence:
1769 * x = ((VLV_IIR & VLV_IER) ||
1770 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1771 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1773 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1774 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1775 * guarantee the CPU interrupt will be raised again even if we
1776 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1777 * bits this time around.
1779 I915_WRITE(VLV_MASTER_IER
, 0);
1780 ier
= I915_READ(VLV_IER
);
1781 I915_WRITE(VLV_IER
, 0);
1784 I915_WRITE(GTIIR
, gt_iir
);
1786 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1788 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1789 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1791 /* Call regardless, as some status bits might not be
1792 * signalled in iir */
1793 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1796 * VLV_IIR is single buffered, and reflects the level
1797 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1800 I915_WRITE(VLV_IIR
, iir
);
1802 I915_WRITE(VLV_IER
, ier
);
1803 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1804 POSTING_READ(VLV_MASTER_IER
);
1807 snb_gt_irq_handler(dev_priv
, gt_iir
);
1809 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1812 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1814 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1817 enable_rpm_wakeref_asserts(dev_priv
);
1822 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1824 struct drm_device
*dev
= arg
;
1825 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1826 irqreturn_t ret
= IRQ_NONE
;
1828 if (!intel_irqs_enabled(dev_priv
))
1831 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1832 disable_rpm_wakeref_asserts(dev_priv
);
1835 u32 master_ctl
, iir
;
1837 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1838 u32 hotplug_status
= 0;
1841 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1842 iir
= I915_READ(VLV_IIR
);
1844 if (master_ctl
== 0 && iir
== 0)
1850 * Theory on interrupt generation, based on empirical evidence:
1852 * x = ((VLV_IIR & VLV_IER) ||
1853 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1854 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1856 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1857 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1858 * guarantee the CPU interrupt will be raised again even if we
1859 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1860 * bits this time around.
1862 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1863 ier
= I915_READ(VLV_IER
);
1864 I915_WRITE(VLV_IER
, 0);
1866 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1868 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1869 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1871 /* Call regardless, as some status bits might not be
1872 * signalled in iir */
1873 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1876 * VLV_IIR is single buffered, and reflects the level
1877 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1880 I915_WRITE(VLV_IIR
, iir
);
1882 I915_WRITE(VLV_IER
, ier
);
1883 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1884 POSTING_READ(GEN8_MASTER_IRQ
);
1886 gen8_gt_irq_handler(dev_priv
, gt_iir
);
1889 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1891 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1894 enable_rpm_wakeref_asserts(dev_priv
);
1899 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1900 u32 hotplug_trigger
,
1901 const u32 hpd
[HPD_NUM_PINS
])
1903 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1906 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1907 * unless we touch the hotplug register, even if hotplug_trigger is
1908 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1911 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1912 if (!hotplug_trigger
) {
1913 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1914 PORTD_HOTPLUG_STATUS_MASK
|
1915 PORTC_HOTPLUG_STATUS_MASK
|
1916 PORTB_HOTPLUG_STATUS_MASK
;
1917 dig_hotplug_reg
&= ~mask
;
1920 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1921 if (!hotplug_trigger
)
1924 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1925 dig_hotplug_reg
, hpd
,
1926 pch_port_hotplug_long_detect
);
1928 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1931 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1934 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1936 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
1938 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1939 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1940 SDE_AUDIO_POWER_SHIFT
);
1941 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1945 if (pch_iir
& SDE_AUX_MASK
)
1946 dp_aux_irq_handler(dev_priv
);
1948 if (pch_iir
& SDE_GMBUS
)
1949 gmbus_irq_handler(dev_priv
);
1951 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1952 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1954 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1955 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1957 if (pch_iir
& SDE_POISON
)
1958 DRM_ERROR("PCH poison interrupt\n");
1960 if (pch_iir
& SDE_FDI_MASK
)
1961 for_each_pipe(dev_priv
, pipe
)
1962 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1964 I915_READ(FDI_RX_IIR(pipe
)));
1966 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1967 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1969 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1970 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1972 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1973 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1975 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1976 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1979 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
1981 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1984 if (err_int
& ERR_INT_POISON
)
1985 DRM_ERROR("Poison interrupt\n");
1987 for_each_pipe(dev_priv
, pipe
) {
1988 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1989 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1991 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1992 if (IS_IVYBRIDGE(dev_priv
))
1993 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
1995 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
1999 I915_WRITE(GEN7_ERR_INT
, err_int
);
2002 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2004 u32 serr_int
= I915_READ(SERR_INT
);
2006 if (serr_int
& SERR_INT_POISON
)
2007 DRM_ERROR("PCH poison interrupt\n");
2009 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2010 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2012 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2013 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2015 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2016 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2018 I915_WRITE(SERR_INT
, serr_int
);
2021 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2024 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2026 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2028 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2029 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2030 SDE_AUDIO_POWER_SHIFT_CPT
);
2031 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2035 if (pch_iir
& SDE_AUX_MASK_CPT
)
2036 dp_aux_irq_handler(dev_priv
);
2038 if (pch_iir
& SDE_GMBUS_CPT
)
2039 gmbus_irq_handler(dev_priv
);
2041 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2042 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2044 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2045 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2047 if (pch_iir
& SDE_FDI_MASK_CPT
)
2048 for_each_pipe(dev_priv
, pipe
)
2049 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2051 I915_READ(FDI_RX_IIR(pipe
)));
2053 if (pch_iir
& SDE_ERROR_CPT
)
2054 cpt_serr_int_handler(dev_priv
);
2057 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2059 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2060 ~SDE_PORTE_HOTPLUG_SPT
;
2061 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2062 u32 pin_mask
= 0, long_mask
= 0;
2064 if (hotplug_trigger
) {
2065 u32 dig_hotplug_reg
;
2067 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2068 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2070 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2071 dig_hotplug_reg
, hpd_spt
,
2072 spt_port_hotplug_long_detect
);
2075 if (hotplug2_trigger
) {
2076 u32 dig_hotplug_reg
;
2078 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2079 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2081 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2082 dig_hotplug_reg
, hpd_spt
,
2083 spt_port_hotplug2_long_detect
);
2087 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2089 if (pch_iir
& SDE_GMBUS_CPT
)
2090 gmbus_irq_handler(dev_priv
);
2093 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2094 u32 hotplug_trigger
,
2095 const u32 hpd
[HPD_NUM_PINS
])
2097 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2099 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2100 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2102 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2103 dig_hotplug_reg
, hpd
,
2104 ilk_port_hotplug_long_detect
);
2106 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2109 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2113 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2115 if (hotplug_trigger
)
2116 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2118 if (de_iir
& DE_AUX_CHANNEL_A
)
2119 dp_aux_irq_handler(dev_priv
);
2121 if (de_iir
& DE_GSE
)
2122 intel_opregion_asle_intr(dev_priv
);
2124 if (de_iir
& DE_POISON
)
2125 DRM_ERROR("Poison interrupt\n");
2127 for_each_pipe(dev_priv
, pipe
) {
2128 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2129 intel_pipe_handle_vblank(dev_priv
, pipe
))
2130 intel_check_page_flip(dev_priv
, pipe
);
2132 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2133 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2135 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2136 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2138 /* plane/pipes map 1:1 on ilk+ */
2139 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
))
2140 intel_finish_page_flip_cs(dev_priv
, pipe
);
2143 /* check event from PCH */
2144 if (de_iir
& DE_PCH_EVENT
) {
2145 u32 pch_iir
= I915_READ(SDEIIR
);
2147 if (HAS_PCH_CPT(dev_priv
))
2148 cpt_irq_handler(dev_priv
, pch_iir
);
2150 ibx_irq_handler(dev_priv
, pch_iir
);
2152 /* should clear PCH hotplug event before clear CPU irq */
2153 I915_WRITE(SDEIIR
, pch_iir
);
2156 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2157 ironlake_rps_change_irq_handler(dev_priv
);
2160 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2164 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2166 if (hotplug_trigger
)
2167 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2169 if (de_iir
& DE_ERR_INT_IVB
)
2170 ivb_err_int_handler(dev_priv
);
2172 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2173 dp_aux_irq_handler(dev_priv
);
2175 if (de_iir
& DE_GSE_IVB
)
2176 intel_opregion_asle_intr(dev_priv
);
2178 for_each_pipe(dev_priv
, pipe
) {
2179 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2180 intel_pipe_handle_vblank(dev_priv
, pipe
))
2181 intel_check_page_flip(dev_priv
, pipe
);
2183 /* plane/pipes map 1:1 on ilk+ */
2184 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
))
2185 intel_finish_page_flip_cs(dev_priv
, pipe
);
2188 /* check event from PCH */
2189 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2190 u32 pch_iir
= I915_READ(SDEIIR
);
2192 cpt_irq_handler(dev_priv
, pch_iir
);
2194 /* clear PCH hotplug event before clear CPU irq */
2195 I915_WRITE(SDEIIR
, pch_iir
);
2200 * To handle irqs with the minimum potential races with fresh interrupts, we:
2201 * 1 - Disable Master Interrupt Control.
2202 * 2 - Find the source(s) of the interrupt.
2203 * 3 - Clear the Interrupt Identity bits (IIR).
2204 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2205 * 5 - Re-enable Master Interrupt Control.
2207 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2209 struct drm_device
*dev
= arg
;
2210 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2211 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2212 irqreturn_t ret
= IRQ_NONE
;
2214 if (!intel_irqs_enabled(dev_priv
))
2217 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2218 disable_rpm_wakeref_asserts(dev_priv
);
2220 /* disable master interrupt before clearing iir */
2221 de_ier
= I915_READ(DEIER
);
2222 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2223 POSTING_READ(DEIER
);
2225 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2226 * interrupts will will be stored on its back queue, and then we'll be
2227 * able to process them after we restore SDEIER (as soon as we restore
2228 * it, we'll get an interrupt if SDEIIR still has something to process
2229 * due to its back queue). */
2230 if (!HAS_PCH_NOP(dev_priv
)) {
2231 sde_ier
= I915_READ(SDEIER
);
2232 I915_WRITE(SDEIER
, 0);
2233 POSTING_READ(SDEIER
);
2236 /* Find, clear, then process each source of interrupt */
2238 gt_iir
= I915_READ(GTIIR
);
2240 I915_WRITE(GTIIR
, gt_iir
);
2242 if (INTEL_GEN(dev_priv
) >= 6)
2243 snb_gt_irq_handler(dev_priv
, gt_iir
);
2245 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2248 de_iir
= I915_READ(DEIIR
);
2250 I915_WRITE(DEIIR
, de_iir
);
2252 if (INTEL_GEN(dev_priv
) >= 7)
2253 ivb_display_irq_handler(dev_priv
, de_iir
);
2255 ilk_display_irq_handler(dev_priv
, de_iir
);
2258 if (INTEL_GEN(dev_priv
) >= 6) {
2259 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2261 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2263 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2267 I915_WRITE(DEIER
, de_ier
);
2268 POSTING_READ(DEIER
);
2269 if (!HAS_PCH_NOP(dev_priv
)) {
2270 I915_WRITE(SDEIER
, sde_ier
);
2271 POSTING_READ(SDEIER
);
2274 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2275 enable_rpm_wakeref_asserts(dev_priv
);
2280 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2281 u32 hotplug_trigger
,
2282 const u32 hpd
[HPD_NUM_PINS
])
2284 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2286 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2287 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2289 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2290 dig_hotplug_reg
, hpd
,
2291 bxt_port_hotplug_long_detect
);
2293 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2297 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2299 irqreturn_t ret
= IRQ_NONE
;
2303 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2304 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2306 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2308 if (iir
& GEN8_DE_MISC_GSE
)
2309 intel_opregion_asle_intr(dev_priv
);
2311 DRM_ERROR("Unexpected DE Misc interrupt\n");
2314 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2317 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2318 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2323 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2326 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2327 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2328 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2329 GEN9_AUX_CHANNEL_C
|
2332 if (iir
& tmp_mask
) {
2333 dp_aux_irq_handler(dev_priv
);
2337 if (IS_BROXTON(dev_priv
)) {
2338 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2340 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2344 } else if (IS_BROADWELL(dev_priv
)) {
2345 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2347 ilk_hpd_irq_handler(dev_priv
,
2353 if (IS_BROXTON(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2354 gmbus_irq_handler(dev_priv
);
2359 DRM_ERROR("Unexpected DE Port interrupt\n");
2362 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2365 for_each_pipe(dev_priv
, pipe
) {
2366 u32 flip_done
, fault_errors
;
2368 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2371 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2373 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2378 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2380 if (iir
& GEN8_PIPE_VBLANK
&&
2381 intel_pipe_handle_vblank(dev_priv
, pipe
))
2382 intel_check_page_flip(dev_priv
, pipe
);
2385 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2386 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2388 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2391 intel_finish_page_flip_cs(dev_priv
, pipe
);
2393 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2394 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2396 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2397 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2400 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2401 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2403 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2406 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2411 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2412 master_ctl
& GEN8_DE_PCH_IRQ
) {
2414 * FIXME(BDW): Assume for now that the new interrupt handling
2415 * scheme also closed the SDE interrupt handling race we've seen
2416 * on older pch-split platforms. But this needs testing.
2418 iir
= I915_READ(SDEIIR
);
2420 I915_WRITE(SDEIIR
, iir
);
2423 if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
))
2424 spt_irq_handler(dev_priv
, iir
);
2426 cpt_irq_handler(dev_priv
, iir
);
2429 * Like on previous PCH there seems to be something
2430 * fishy going on with forwarding PCH interrupts.
2432 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2439 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2441 struct drm_device
*dev
= arg
;
2442 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2447 if (!intel_irqs_enabled(dev_priv
))
2450 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2451 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2455 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2457 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2458 disable_rpm_wakeref_asserts(dev_priv
);
2460 /* Find, clear, then process each source of interrupt */
2461 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2462 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2463 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2465 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2466 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2468 enable_rpm_wakeref_asserts(dev_priv
);
2473 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
)
2476 * Notify all waiters for GPU completion events that reset state has
2477 * been changed, and that they need to restart their wait after
2478 * checking for potential errors (and bail out to drop locks if there is
2479 * a gpu reset pending so that i915_error_work_func can acquire them).
2482 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2483 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
2485 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2486 wake_up_all(&dev_priv
->pending_flip_queue
);
2490 * i915_reset_and_wakeup - do process context error handling work
2491 * @dev_priv: i915 device private
2493 * Fire an error uevent so userspace can see that a hang or error
2496 static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv
)
2498 struct kobject
*kobj
= &dev_priv
->drm
.primary
->kdev
->kobj
;
2499 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2500 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2501 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2504 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2507 * Note that there's only one work item which does gpu resets, so we
2508 * need not worry about concurrent gpu resets potentially incrementing
2509 * error->reset_counter twice. We only need to take care of another
2510 * racing irq/hangcheck declaring the gpu dead for a second time. A
2511 * quick check for that is good enough: schedule_work ensures the
2512 * correct ordering between hang detection and this work item, and since
2513 * the reset in-progress bit is only ever set by code outside of this
2514 * work we don't need to worry about any other races.
2516 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
2517 DRM_DEBUG_DRIVER("resetting chip\n");
2518 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2521 * In most cases it's guaranteed that we get here with an RPM
2522 * reference held, for example because there is a pending GPU
2523 * request that won't finish until the reset is done. This
2524 * isn't the case at least when we get here by doing a
2525 * simulated reset via debugs, so get an RPM reference.
2527 intel_runtime_pm_get(dev_priv
);
2529 intel_prepare_reset(dev_priv
);
2532 * All state reset _must_ be completed before we update the
2533 * reset counter, for otherwise waiters might miss the reset
2534 * pending state and not properly drop locks, resulting in
2535 * deadlocks with the reset work.
2537 ret
= i915_reset(dev_priv
);
2539 intel_finish_reset(dev_priv
);
2541 intel_runtime_pm_put(dev_priv
);
2544 kobject_uevent_env(kobj
,
2545 KOBJ_CHANGE
, reset_done_event
);
2548 * Note: The wake_up also serves as a memory barrier so that
2549 * waiters see the update value of the reset counter atomic_t.
2551 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2555 static void i915_report_and_clear_eir(struct drm_i915_private
*dev_priv
)
2557 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2558 u32 eir
= I915_READ(EIR
);
2564 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2566 i915_get_extra_instdone(dev_priv
, instdone
);
2568 if (IS_G4X(dev_priv
)) {
2569 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2570 u32 ipeir
= I915_READ(IPEIR_I965
);
2572 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2573 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2574 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2575 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2576 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2577 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2578 I915_WRITE(IPEIR_I965
, ipeir
);
2579 POSTING_READ(IPEIR_I965
);
2581 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2582 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2583 pr_err("page table error\n");
2584 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2585 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2586 POSTING_READ(PGTBL_ER
);
2590 if (!IS_GEN2(dev_priv
)) {
2591 if (eir
& I915_ERROR_PAGE_TABLE
) {
2592 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2593 pr_err("page table error\n");
2594 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2595 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2596 POSTING_READ(PGTBL_ER
);
2600 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2601 pr_err("memory refresh error:\n");
2602 for_each_pipe(dev_priv
, pipe
)
2603 pr_err("pipe %c stat: 0x%08x\n",
2604 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2605 /* pipestat has already been acked */
2607 if (eir
& I915_ERROR_INSTRUCTION
) {
2608 pr_err("instruction error\n");
2609 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2610 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2611 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2612 if (INTEL_GEN(dev_priv
) < 4) {
2613 u32 ipeir
= I915_READ(IPEIR
);
2615 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2616 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2617 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2618 I915_WRITE(IPEIR
, ipeir
);
2619 POSTING_READ(IPEIR
);
2621 u32 ipeir
= I915_READ(IPEIR_I965
);
2623 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2624 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2625 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2626 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2627 I915_WRITE(IPEIR_I965
, ipeir
);
2628 POSTING_READ(IPEIR_I965
);
2632 I915_WRITE(EIR
, eir
);
2634 eir
= I915_READ(EIR
);
2637 * some errors might have become stuck,
2640 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2641 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2642 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2647 * i915_handle_error - handle a gpu error
2648 * @dev_priv: i915 device private
2649 * @engine_mask: mask representing engines that are hung
2650 * Do some basic checking of register state at error time and
2651 * dump it to the syslog. Also call i915_capture_error_state() to make
2652 * sure we get a record and make it available in debugfs. Fire a uevent
2653 * so userspace knows something bad happened (should trigger collection
2654 * of a ring dump etc.).
2655 * @fmt: Error message format string
2657 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2659 const char *fmt
, ...)
2664 va_start(args
, fmt
);
2665 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2668 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2669 i915_report_and_clear_eir(dev_priv
);
2672 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2673 &dev_priv
->gpu_error
.reset_counter
);
2676 * Wakeup waiting processes so that the reset function
2677 * i915_reset_and_wakeup doesn't deadlock trying to grab
2678 * various locks. By bumping the reset counter first, the woken
2679 * processes will see a reset in progress and back off,
2680 * releasing their locks and then wait for the reset completion.
2681 * We must do this for _all_ gpu waiters that might hold locks
2682 * that the reset work needs to acquire.
2684 * Note: The wake_up serves as the required memory barrier to
2685 * ensure that the waiters see the updated value of the reset
2688 i915_error_wake_up(dev_priv
);
2691 i915_reset_and_wakeup(dev_priv
);
2694 /* Called from drm generic code, passed 'crtc' which
2695 * we use as a pipe index
2697 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2699 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2700 unsigned long irqflags
;
2702 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2703 if (INTEL_INFO(dev
)->gen
>= 4)
2704 i915_enable_pipestat(dev_priv
, pipe
,
2705 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2707 i915_enable_pipestat(dev_priv
, pipe
,
2708 PIPE_VBLANK_INTERRUPT_STATUS
);
2709 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2714 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2716 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2717 unsigned long irqflags
;
2718 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2719 DE_PIPE_VBLANK(pipe
);
2721 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2722 ilk_enable_display_irq(dev_priv
, bit
);
2723 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2728 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2730 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2731 unsigned long irqflags
;
2733 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2734 i915_enable_pipestat(dev_priv
, pipe
,
2735 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2736 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2741 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2743 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2744 unsigned long irqflags
;
2746 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2747 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2748 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2753 /* Called from drm generic code, passed 'crtc' which
2754 * we use as a pipe index
2756 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2758 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2759 unsigned long irqflags
;
2761 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2762 i915_disable_pipestat(dev_priv
, pipe
,
2763 PIPE_VBLANK_INTERRUPT_STATUS
|
2764 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2765 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2768 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2771 unsigned long irqflags
;
2772 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2773 DE_PIPE_VBLANK(pipe
);
2775 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2776 ilk_disable_display_irq(dev_priv
, bit
);
2777 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2780 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2782 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2783 unsigned long irqflags
;
2785 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2786 i915_disable_pipestat(dev_priv
, pipe
,
2787 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2788 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2791 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2793 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2794 unsigned long irqflags
;
2796 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2797 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2798 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2802 ipehr_is_semaphore_wait(struct intel_engine_cs
*engine
, u32 ipehr
)
2804 if (INTEL_GEN(engine
->i915
) >= 8) {
2805 return (ipehr
>> 23) == 0x1c;
2807 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2808 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2809 MI_SEMAPHORE_REGISTER
);
2813 static struct intel_engine_cs
*
2814 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2817 struct drm_i915_private
*dev_priv
= engine
->i915
;
2818 struct intel_engine_cs
*signaller
;
2820 if (INTEL_GEN(dev_priv
) >= 8) {
2821 for_each_engine(signaller
, dev_priv
) {
2822 if (engine
== signaller
)
2825 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2829 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2831 for_each_engine(signaller
, dev_priv
) {
2832 if(engine
== signaller
)
2835 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2840 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2841 engine
->id
, ipehr
, offset
);
2846 static struct intel_engine_cs
*
2847 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2849 struct drm_i915_private
*dev_priv
= engine
->i915
;
2850 void __iomem
*vaddr
;
2851 u32 cmd
, ipehr
, head
;
2856 * This function does not support execlist mode - any attempt to
2857 * proceed further into this function will result in a kernel panic
2858 * when dereferencing ring->buffer, which is not set up in execlist
2861 * The correct way of doing it would be to derive the currently
2862 * executing ring buffer from the current context, which is derived
2863 * from the currently running request. Unfortunately, to get the
2864 * current request we would have to grab the struct_mutex before doing
2865 * anything else, which would be ill-advised since some other thread
2866 * might have grabbed it already and managed to hang itself, causing
2867 * the hang checker to deadlock.
2869 * Therefore, this function does not support execlist mode in its
2870 * current form. Just return NULL and move on.
2872 if (engine
->buffer
== NULL
)
2875 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2876 if (!ipehr_is_semaphore_wait(engine
, ipehr
))
2880 * HEAD is likely pointing to the dword after the actual command,
2881 * so scan backwards until we find the MBOX. But limit it to just 3
2882 * or 4 dwords depending on the semaphore wait command size.
2883 * Note that we don't care about ACTHD here since that might
2884 * point at at batch, and semaphores are always emitted into the
2885 * ringbuffer itself.
2887 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2888 backwards
= (INTEL_GEN(dev_priv
) >= 8) ? 5 : 4;
2889 vaddr
= (void __iomem
*)engine
->buffer
->vaddr
;
2891 for (i
= backwards
; i
; --i
) {
2893 * Be paranoid and presume the hw has gone off into the wild -
2894 * our ring is smaller than what the hardware (and hence
2895 * HEAD_ADDR) allows. Also handles wrap-around.
2897 head
&= engine
->buffer
->size
- 1;
2899 /* This here seems to blow up */
2900 cmd
= ioread32(vaddr
+ head
);
2910 *seqno
= ioread32(vaddr
+ head
+ 4) + 1;
2911 if (INTEL_GEN(dev_priv
) >= 8) {
2912 offset
= ioread32(vaddr
+ head
+ 12);
2914 offset
|= ioread32(vaddr
+ head
+ 8);
2916 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2919 static int semaphore_passed(struct intel_engine_cs
*engine
)
2921 struct drm_i915_private
*dev_priv
= engine
->i915
;
2922 struct intel_engine_cs
*signaller
;
2925 engine
->hangcheck
.deadlock
++;
2927 signaller
= semaphore_waits_for(engine
, &seqno
);
2928 if (signaller
== NULL
)
2931 /* Prevent pathological recursion due to driver bugs */
2932 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2935 if (i915_seqno_passed(intel_engine_get_seqno(signaller
), seqno
))
2938 /* cursory check for an unkickable deadlock */
2939 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2940 semaphore_passed(signaller
) < 0)
2946 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2948 struct intel_engine_cs
*engine
;
2950 for_each_engine(engine
, dev_priv
)
2951 engine
->hangcheck
.deadlock
= 0;
2954 static bool subunits_stuck(struct intel_engine_cs
*engine
)
2956 u32 instdone
[I915_NUM_INSTDONE_REG
];
2960 if (engine
->id
!= RCS
)
2963 i915_get_extra_instdone(engine
->i915
, instdone
);
2965 /* There might be unstable subunit states even when
2966 * actual head is not moving. Filter out the unstable ones by
2967 * accumulating the undone -> done transitions and only
2968 * consider those as progress.
2971 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
2972 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
2974 if (tmp
!= engine
->hangcheck
.instdone
[i
])
2977 engine
->hangcheck
.instdone
[i
] |= tmp
;
2983 static enum intel_engine_hangcheck_action
2984 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
2986 if (acthd
!= engine
->hangcheck
.acthd
) {
2988 /* Clear subunit states on head movement */
2989 memset(engine
->hangcheck
.instdone
, 0,
2990 sizeof(engine
->hangcheck
.instdone
));
2992 return HANGCHECK_ACTIVE
;
2995 if (!subunits_stuck(engine
))
2996 return HANGCHECK_ACTIVE
;
2998 return HANGCHECK_HUNG
;
3001 static enum intel_engine_hangcheck_action
3002 engine_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3004 struct drm_i915_private
*dev_priv
= engine
->i915
;
3005 enum intel_engine_hangcheck_action ha
;
3008 ha
= head_stuck(engine
, acthd
);
3009 if (ha
!= HANGCHECK_HUNG
)
3012 if (IS_GEN2(dev_priv
))
3013 return HANGCHECK_HUNG
;
3015 /* Is the chip hanging on a WAIT_FOR_EVENT?
3016 * If so we can simply poke the RB_WAIT bit
3017 * and break the hang. This should work on
3018 * all but the second generation chipsets.
3020 tmp
= I915_READ_CTL(engine
);
3021 if (tmp
& RING_WAIT
) {
3022 i915_handle_error(dev_priv
, 0,
3023 "Kicking stuck wait on %s",
3025 I915_WRITE_CTL(engine
, tmp
);
3026 return HANGCHECK_KICK
;
3029 if (INTEL_GEN(dev_priv
) >= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3030 switch (semaphore_passed(engine
)) {
3032 return HANGCHECK_HUNG
;
3034 i915_handle_error(dev_priv
, 0,
3035 "Kicking stuck semaphore on %s",
3037 I915_WRITE_CTL(engine
, tmp
);
3038 return HANGCHECK_KICK
;
3040 return HANGCHECK_WAIT
;
3044 return HANGCHECK_HUNG
;
3047 static unsigned long kick_waiters(struct intel_engine_cs
*engine
)
3049 struct drm_i915_private
*i915
= engine
->i915
;
3050 unsigned long irq_count
= READ_ONCE(engine
->breadcrumbs
.irq_wakeups
);
3052 if (engine
->hangcheck
.user_interrupts
== irq_count
&&
3053 !test_and_set_bit(engine
->id
, &i915
->gpu_error
.missed_irq_rings
)) {
3054 if (!test_bit(engine
->id
, &i915
->gpu_error
.test_irq_rings
))
3055 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3058 intel_engine_enable_fake_irq(engine
);
3064 * This is called when the chip hasn't reported back with completed
3065 * batchbuffers in a long time. We keep track per ring seqno progress and
3066 * if there are no progress, hangcheck score for that ring is increased.
3067 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3068 * we kick the ring. If we see no progress on three subsequent calls
3069 * we assume chip is wedged and try to fix it by resetting the chip.
3071 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3073 struct drm_i915_private
*dev_priv
=
3074 container_of(work
, typeof(*dev_priv
),
3075 gpu_error
.hangcheck_work
.work
);
3076 struct intel_engine_cs
*engine
;
3077 unsigned int hung
= 0, stuck
= 0;
3082 #define ACTIVE_DECAY 15
3084 if (!i915
.enable_hangcheck
)
3087 if (!READ_ONCE(dev_priv
->gt
.awake
))
3090 /* As enabling the GPU requires fairly extensive mmio access,
3091 * periodically arm the mmio checker to see if we are triggering
3092 * any invalid access.
3094 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3096 for_each_engine(engine
, dev_priv
) {
3097 bool busy
= intel_engine_has_waiter(engine
);
3100 unsigned user_interrupts
;
3102 semaphore_clear_deadlocks(dev_priv
);
3104 /* We don't strictly need an irq-barrier here, as we are not
3105 * serving an interrupt request, be paranoid in case the
3106 * barrier has side-effects (such as preventing a broken
3107 * cacheline snoop) and so be sure that we can see the seqno
3108 * advance. If the seqno should stick, due to a stale
3109 * cacheline, we would erroneously declare the GPU hung.
3111 if (engine
->irq_seqno_barrier
)
3112 engine
->irq_seqno_barrier(engine
);
3114 acthd
= intel_engine_get_active_head(engine
);
3115 seqno
= intel_engine_get_seqno(engine
);
3117 /* Reset stuck interrupts between batch advances */
3118 user_interrupts
= 0;
3120 if (engine
->hangcheck
.seqno
== seqno
) {
3121 if (!intel_engine_is_active(engine
)) {
3122 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3124 /* Safeguard against driver failure */
3125 user_interrupts
= kick_waiters(engine
);
3126 engine
->hangcheck
.score
+= BUSY
;
3129 /* We always increment the hangcheck score
3130 * if the engine is busy and still processing
3131 * the same request, so that no single request
3132 * can run indefinitely (such as a chain of
3133 * batches). The only time we do not increment
3134 * the hangcheck score on this ring, if this
3135 * engine is in a legitimate wait for another
3136 * engine. In that case the waiting engine is a
3137 * victim and we want to be sure we catch the
3138 * right culprit. Then every time we do kick
3139 * the ring, add a small increment to the
3140 * score so that we can catch a batch that is
3141 * being repeatedly kicked and so responsible
3142 * for stalling the machine.
3144 engine
->hangcheck
.action
=
3145 engine_stuck(engine
, acthd
);
3147 switch (engine
->hangcheck
.action
) {
3148 case HANGCHECK_IDLE
:
3149 case HANGCHECK_WAIT
:
3151 case HANGCHECK_ACTIVE
:
3152 engine
->hangcheck
.score
+= BUSY
;
3154 case HANGCHECK_KICK
:
3155 engine
->hangcheck
.score
+= KICK
;
3157 case HANGCHECK_HUNG
:
3158 engine
->hangcheck
.score
+= HUNG
;
3163 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3164 hung
|= intel_engine_flag(engine
);
3165 if (engine
->hangcheck
.action
!= HANGCHECK_HUNG
)
3166 stuck
|= intel_engine_flag(engine
);
3169 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3171 /* Gradually reduce the count so that we catch DoS
3172 * attempts across multiple batches.
3174 if (engine
->hangcheck
.score
> 0)
3175 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3176 if (engine
->hangcheck
.score
< 0)
3177 engine
->hangcheck
.score
= 0;
3179 /* Clear head and subunit states on seqno movement */
3182 memset(engine
->hangcheck
.instdone
, 0,
3183 sizeof(engine
->hangcheck
.instdone
));
3186 engine
->hangcheck
.seqno
= seqno
;
3187 engine
->hangcheck
.acthd
= acthd
;
3188 engine
->hangcheck
.user_interrupts
= user_interrupts
;
3196 /* If some rings hung but others were still busy, only
3197 * blame the hanging rings in the synopsis.
3201 len
= scnprintf(msg
, sizeof(msg
),
3202 "%s on ", stuck
== hung
? "No progress" : "Hang");
3203 for_each_engine_masked(engine
, dev_priv
, hung
)
3204 len
+= scnprintf(msg
+ len
, sizeof(msg
) - len
,
3205 "%s, ", engine
->name
);
3208 return i915_handle_error(dev_priv
, hung
, msg
);
3211 /* Reset timer in case GPU hangs without another request being added */
3213 i915_queue_hangcheck(dev_priv
);
3216 static void ibx_irq_reset(struct drm_device
*dev
)
3218 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3220 if (HAS_PCH_NOP(dev
))
3223 GEN5_IRQ_RESET(SDE
);
3225 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3226 I915_WRITE(SERR_INT
, 0xffffffff);
3230 * SDEIER is also touched by the interrupt handler to work around missed PCH
3231 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3232 * instead we unconditionally enable all PCH interrupt sources here, but then
3233 * only unmask them as needed with SDEIMR.
3235 * This function needs to be called before interrupts are enabled.
3237 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3239 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3241 if (HAS_PCH_NOP(dev
))
3244 WARN_ON(I915_READ(SDEIER
) != 0);
3245 I915_WRITE(SDEIER
, 0xffffffff);
3246 POSTING_READ(SDEIER
);
3249 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3251 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3254 if (INTEL_INFO(dev
)->gen
>= 6)
3255 GEN5_IRQ_RESET(GEN6_PM
);
3258 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3262 if (IS_CHERRYVIEW(dev_priv
))
3263 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3265 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3267 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
3268 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3270 for_each_pipe(dev_priv
, pipe
) {
3271 I915_WRITE(PIPESTAT(pipe
),
3272 PIPE_FIFO_UNDERRUN_STATUS
|
3273 PIPESTAT_INT_STATUS_MASK
);
3274 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
3277 GEN5_IRQ_RESET(VLV_
);
3278 dev_priv
->irq_mask
= ~0;
3281 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3287 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3288 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3290 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3291 for_each_pipe(dev_priv
, pipe
)
3292 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3294 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3295 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3296 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3297 if (IS_CHERRYVIEW(dev_priv
))
3298 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3300 WARN_ON(dev_priv
->irq_mask
!= ~0);
3302 dev_priv
->irq_mask
= ~enable_mask
;
3304 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3309 static void ironlake_irq_reset(struct drm_device
*dev
)
3311 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3313 I915_WRITE(HWSTAM
, 0xffffffff);
3317 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3319 gen5_gt_irq_reset(dev
);
3324 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3326 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3328 I915_WRITE(VLV_MASTER_IER
, 0);
3329 POSTING_READ(VLV_MASTER_IER
);
3331 gen5_gt_irq_reset(dev
);
3333 spin_lock_irq(&dev_priv
->irq_lock
);
3334 if (dev_priv
->display_irqs_enabled
)
3335 vlv_display_irq_reset(dev_priv
);
3336 spin_unlock_irq(&dev_priv
->irq_lock
);
3339 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3341 GEN8_IRQ_RESET_NDX(GT
, 0);
3342 GEN8_IRQ_RESET_NDX(GT
, 1);
3343 GEN8_IRQ_RESET_NDX(GT
, 2);
3344 GEN8_IRQ_RESET_NDX(GT
, 3);
3347 static void gen8_irq_reset(struct drm_device
*dev
)
3349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3352 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3353 POSTING_READ(GEN8_MASTER_IRQ
);
3355 gen8_gt_irq_reset(dev_priv
);
3357 for_each_pipe(dev_priv
, pipe
)
3358 if (intel_display_power_is_enabled(dev_priv
,
3359 POWER_DOMAIN_PIPE(pipe
)))
3360 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3362 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3363 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3364 GEN5_IRQ_RESET(GEN8_PCU_
);
3366 if (HAS_PCH_SPLIT(dev
))
3370 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3371 unsigned int pipe_mask
)
3373 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3376 spin_lock_irq(&dev_priv
->irq_lock
);
3377 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3378 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3379 dev_priv
->de_irq_mask
[pipe
],
3380 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3381 spin_unlock_irq(&dev_priv
->irq_lock
);
3384 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3385 unsigned int pipe_mask
)
3389 spin_lock_irq(&dev_priv
->irq_lock
);
3390 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3391 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3392 spin_unlock_irq(&dev_priv
->irq_lock
);
3394 /* make sure we're done processing display irqs */
3395 synchronize_irq(dev_priv
->drm
.irq
);
3398 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3400 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3402 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3403 POSTING_READ(GEN8_MASTER_IRQ
);
3405 gen8_gt_irq_reset(dev_priv
);
3407 GEN5_IRQ_RESET(GEN8_PCU_
);
3409 spin_lock_irq(&dev_priv
->irq_lock
);
3410 if (dev_priv
->display_irqs_enabled
)
3411 vlv_display_irq_reset(dev_priv
);
3412 spin_unlock_irq(&dev_priv
->irq_lock
);
3415 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3416 const u32 hpd
[HPD_NUM_PINS
])
3418 struct intel_encoder
*encoder
;
3419 u32 enabled_irqs
= 0;
3421 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
3422 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3423 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3425 return enabled_irqs
;
3428 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3430 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3432 if (HAS_PCH_IBX(dev_priv
)) {
3433 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3434 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3436 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3437 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3440 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3443 * Enable digital hotplug on the PCH, and configure the DP short pulse
3444 * duration to 2ms (which is the minimum in the Display Port spec).
3445 * The pulse duration bits are reserved on LPT+.
3447 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3448 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3449 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3450 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3451 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3453 * When CPU and PCH are on the same package, port A
3454 * HPD must be enabled in both north and south.
3456 if (HAS_PCH_LPT_LP(dev_priv
))
3457 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3458 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3461 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3463 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3465 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3466 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3468 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3470 /* Enable digital hotplug on the PCH */
3471 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3472 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3473 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3474 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3476 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3477 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3478 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3481 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3483 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3485 if (INTEL_GEN(dev_priv
) >= 8) {
3486 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3487 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3489 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3490 } else if (INTEL_GEN(dev_priv
) >= 7) {
3491 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3492 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3494 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3496 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3497 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3499 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3503 * Enable digital hotplug on the CPU, and configure the DP short pulse
3504 * duration to 2ms (which is the minimum in the Display Port spec)
3505 * The pulse duration bits are reserved on HSW+.
3507 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3508 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3509 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3510 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3512 ibx_hpd_irq_setup(dev_priv
);
3515 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3517 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3519 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3520 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3522 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3524 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3525 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3526 PORTA_HOTPLUG_ENABLE
;
3528 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3529 hotplug
, enabled_irqs
);
3530 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3533 * For BXT invert bit has to be set based on AOB design
3534 * for HPD detection logic, update it based on VBT fields.
3537 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3538 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3539 hotplug
|= BXT_DDIA_HPD_INVERT
;
3540 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3541 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3542 hotplug
|= BXT_DDIB_HPD_INVERT
;
3543 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3544 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3545 hotplug
|= BXT_DDIC_HPD_INVERT
;
3547 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3550 static void ibx_irq_postinstall(struct drm_device
*dev
)
3552 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3555 if (HAS_PCH_NOP(dev
))
3558 if (HAS_PCH_IBX(dev
))
3559 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3561 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3563 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3564 I915_WRITE(SDEIMR
, ~mask
);
3567 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3569 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3570 u32 pm_irqs
, gt_irqs
;
3572 pm_irqs
= gt_irqs
= 0;
3574 dev_priv
->gt_irq_mask
= ~0;
3575 if (HAS_L3_DPF(dev
)) {
3576 /* L3 parity interrupt is always unmasked. */
3577 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3578 gt_irqs
|= GT_PARITY_ERROR(dev
);
3581 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3583 gt_irqs
|= ILK_BSD_USER_INTERRUPT
;
3585 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3588 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3590 if (INTEL_INFO(dev
)->gen
>= 6) {
3592 * RPS interrupts will get enabled/disabled on demand when RPS
3593 * itself is enabled/disabled.
3596 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3598 dev_priv
->pm_irq_mask
= 0xffffffff;
3599 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3603 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3606 u32 display_mask
, extra_mask
;
3608 if (INTEL_INFO(dev
)->gen
>= 7) {
3609 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3610 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3611 DE_PLANEB_FLIP_DONE_IVB
|
3612 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3613 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3614 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3615 DE_DP_A_HOTPLUG_IVB
);
3617 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3618 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3620 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3622 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3623 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3627 dev_priv
->irq_mask
= ~display_mask
;
3629 I915_WRITE(HWSTAM
, 0xeffe);
3631 ibx_irq_pre_postinstall(dev
);
3633 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3635 gen5_gt_irq_postinstall(dev
);
3637 ibx_irq_postinstall(dev
);
3639 if (IS_IRONLAKE_M(dev
)) {
3640 /* Enable PCU event interrupts
3642 * spinlocking not required here for correctness since interrupt
3643 * setup is guaranteed to run in single-threaded context. But we
3644 * need it to make the assert_spin_locked happy. */
3645 spin_lock_irq(&dev_priv
->irq_lock
);
3646 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3647 spin_unlock_irq(&dev_priv
->irq_lock
);
3653 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3655 assert_spin_locked(&dev_priv
->irq_lock
);
3657 if (dev_priv
->display_irqs_enabled
)
3660 dev_priv
->display_irqs_enabled
= true;
3662 if (intel_irqs_enabled(dev_priv
)) {
3663 vlv_display_irq_reset(dev_priv
);
3664 vlv_display_irq_postinstall(dev_priv
);
3668 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3670 assert_spin_locked(&dev_priv
->irq_lock
);
3672 if (!dev_priv
->display_irqs_enabled
)
3675 dev_priv
->display_irqs_enabled
= false;
3677 if (intel_irqs_enabled(dev_priv
))
3678 vlv_display_irq_reset(dev_priv
);
3682 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3684 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3686 gen5_gt_irq_postinstall(dev
);
3688 spin_lock_irq(&dev_priv
->irq_lock
);
3689 if (dev_priv
->display_irqs_enabled
)
3690 vlv_display_irq_postinstall(dev_priv
);
3691 spin_unlock_irq(&dev_priv
->irq_lock
);
3693 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3694 POSTING_READ(VLV_MASTER_IER
);
3699 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3701 /* These are interrupts we'll toggle with the ring mask register */
3702 uint32_t gt_interrupts
[] = {
3703 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3704 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3705 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3706 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3707 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3708 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3709 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3710 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3712 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3713 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3716 if (HAS_L3_DPF(dev_priv
))
3717 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3719 dev_priv
->pm_irq_mask
= 0xffffffff;
3720 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3721 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3723 * RPS interrupts will get enabled/disabled on demand when RPS itself
3724 * is enabled/disabled.
3726 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3727 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3730 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3732 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3733 uint32_t de_pipe_enables
;
3734 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3735 u32 de_port_enables
;
3736 u32 de_misc_masked
= GEN8_DE_MISC_GSE
;
3739 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3740 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3741 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3742 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3744 if (IS_BROXTON(dev_priv
))
3745 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3747 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3748 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3751 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3752 GEN8_PIPE_FIFO_UNDERRUN
;
3754 de_port_enables
= de_port_masked
;
3755 if (IS_BROXTON(dev_priv
))
3756 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3757 else if (IS_BROADWELL(dev_priv
))
3758 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3760 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3761 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3762 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3764 for_each_pipe(dev_priv
, pipe
)
3765 if (intel_display_power_is_enabled(dev_priv
,
3766 POWER_DOMAIN_PIPE(pipe
)))
3767 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3768 dev_priv
->de_irq_mask
[pipe
],
3771 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3772 GEN5_IRQ_INIT(GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3775 static int gen8_irq_postinstall(struct drm_device
*dev
)
3777 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3779 if (HAS_PCH_SPLIT(dev
))
3780 ibx_irq_pre_postinstall(dev
);
3782 gen8_gt_irq_postinstall(dev_priv
);
3783 gen8_de_irq_postinstall(dev_priv
);
3785 if (HAS_PCH_SPLIT(dev
))
3786 ibx_irq_postinstall(dev
);
3788 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3789 POSTING_READ(GEN8_MASTER_IRQ
);
3794 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3796 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3798 gen8_gt_irq_postinstall(dev_priv
);
3800 spin_lock_irq(&dev_priv
->irq_lock
);
3801 if (dev_priv
->display_irqs_enabled
)
3802 vlv_display_irq_postinstall(dev_priv
);
3803 spin_unlock_irq(&dev_priv
->irq_lock
);
3805 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3806 POSTING_READ(GEN8_MASTER_IRQ
);
3811 static void gen8_irq_uninstall(struct drm_device
*dev
)
3813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3818 gen8_irq_reset(dev
);
3821 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3828 I915_WRITE(VLV_MASTER_IER
, 0);
3829 POSTING_READ(VLV_MASTER_IER
);
3831 gen5_gt_irq_reset(dev
);
3833 I915_WRITE(HWSTAM
, 0xffffffff);
3835 spin_lock_irq(&dev_priv
->irq_lock
);
3836 if (dev_priv
->display_irqs_enabled
)
3837 vlv_display_irq_reset(dev_priv
);
3838 spin_unlock_irq(&dev_priv
->irq_lock
);
3841 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3848 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3849 POSTING_READ(GEN8_MASTER_IRQ
);
3851 gen8_gt_irq_reset(dev_priv
);
3853 GEN5_IRQ_RESET(GEN8_PCU_
);
3855 spin_lock_irq(&dev_priv
->irq_lock
);
3856 if (dev_priv
->display_irqs_enabled
)
3857 vlv_display_irq_reset(dev_priv
);
3858 spin_unlock_irq(&dev_priv
->irq_lock
);
3861 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3863 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3868 ironlake_irq_reset(dev
);
3871 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3873 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3876 for_each_pipe(dev_priv
, pipe
)
3877 I915_WRITE(PIPESTAT(pipe
), 0);
3878 I915_WRITE16(IMR
, 0xffff);
3879 I915_WRITE16(IER
, 0x0);
3880 POSTING_READ16(IER
);
3883 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3885 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3888 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3890 /* Unmask the interrupts that we always want on. */
3891 dev_priv
->irq_mask
=
3892 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3893 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3894 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3895 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3896 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3899 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3900 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3901 I915_USER_INTERRUPT
);
3902 POSTING_READ16(IER
);
3904 /* Interrupt setup is already guaranteed to be single-threaded, this is
3905 * just to make the assert_spin_locked check happy. */
3906 spin_lock_irq(&dev_priv
->irq_lock
);
3907 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3908 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3909 spin_unlock_irq(&dev_priv
->irq_lock
);
3915 * Returns true when a page flip has completed.
3917 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3918 int plane
, int pipe
, u32 iir
)
3920 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3922 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3925 if ((iir
& flip_pending
) == 0)
3926 goto check_page_flip
;
3928 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3929 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3930 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3931 * the flip is completed (no longer pending). Since this doesn't raise
3932 * an interrupt per se, we watch for the change at vblank.
3934 if (I915_READ16(ISR
) & flip_pending
)
3935 goto check_page_flip
;
3937 intel_finish_page_flip_cs(dev_priv
, pipe
);
3941 intel_check_page_flip(dev_priv
, pipe
);
3945 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3947 struct drm_device
*dev
= arg
;
3948 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3953 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3954 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3957 if (!intel_irqs_enabled(dev_priv
))
3960 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3961 disable_rpm_wakeref_asserts(dev_priv
);
3964 iir
= I915_READ16(IIR
);
3968 while (iir
& ~flip_mask
) {
3969 /* Can't rely on pipestat interrupt bit in iir as it might
3970 * have been cleared after the pipestat interrupt was received.
3971 * It doesn't set the bit in iir again, but it still produces
3972 * interrupts (for non-MSI).
3974 spin_lock(&dev_priv
->irq_lock
);
3975 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3976 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3978 for_each_pipe(dev_priv
, pipe
) {
3979 i915_reg_t reg
= PIPESTAT(pipe
);
3980 pipe_stats
[pipe
] = I915_READ(reg
);
3983 * Clear the PIPE*STAT regs before the IIR
3985 if (pipe_stats
[pipe
] & 0x8000ffff)
3986 I915_WRITE(reg
, pipe_stats
[pipe
]);
3988 spin_unlock(&dev_priv
->irq_lock
);
3990 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3991 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3993 if (iir
& I915_USER_INTERRUPT
)
3994 notify_ring(&dev_priv
->engine
[RCS
]);
3996 for_each_pipe(dev_priv
, pipe
) {
3998 if (HAS_FBC(dev_priv
))
4001 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4002 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4003 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4005 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4006 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4008 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4009 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4018 enable_rpm_wakeref_asserts(dev_priv
);
4023 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4028 for_each_pipe(dev_priv
, pipe
) {
4029 /* Clear enable bits; then clear status bits */
4030 I915_WRITE(PIPESTAT(pipe
), 0);
4031 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4033 I915_WRITE16(IMR
, 0xffff);
4034 I915_WRITE16(IER
, 0x0);
4035 I915_WRITE16(IIR
, I915_READ16(IIR
));
4038 static void i915_irq_preinstall(struct drm_device
* dev
)
4040 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4043 if (I915_HAS_HOTPLUG(dev
)) {
4044 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4045 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4048 I915_WRITE16(HWSTAM
, 0xeffe);
4049 for_each_pipe(dev_priv
, pipe
)
4050 I915_WRITE(PIPESTAT(pipe
), 0);
4051 I915_WRITE(IMR
, 0xffffffff);
4052 I915_WRITE(IER
, 0x0);
4056 static int i915_irq_postinstall(struct drm_device
*dev
)
4058 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4061 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4063 /* Unmask the interrupts that we always want on. */
4064 dev_priv
->irq_mask
=
4065 ~(I915_ASLE_INTERRUPT
|
4066 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4067 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4068 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4069 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4072 I915_ASLE_INTERRUPT
|
4073 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4074 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4075 I915_USER_INTERRUPT
;
4077 if (I915_HAS_HOTPLUG(dev
)) {
4078 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4079 POSTING_READ(PORT_HOTPLUG_EN
);
4081 /* Enable in IER... */
4082 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4083 /* and unmask in IMR */
4084 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4087 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4088 I915_WRITE(IER
, enable_mask
);
4091 i915_enable_asle_pipestat(dev_priv
);
4093 /* Interrupt setup is already guaranteed to be single-threaded, this is
4094 * just to make the assert_spin_locked check happy. */
4095 spin_lock_irq(&dev_priv
->irq_lock
);
4096 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4097 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4098 spin_unlock_irq(&dev_priv
->irq_lock
);
4104 * Returns true when a page flip has completed.
4106 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
4107 int plane
, int pipe
, u32 iir
)
4109 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4111 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
4114 if ((iir
& flip_pending
) == 0)
4115 goto check_page_flip
;
4117 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4118 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4119 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4120 * the flip is completed (no longer pending). Since this doesn't raise
4121 * an interrupt per se, we watch for the change at vblank.
4123 if (I915_READ(ISR
) & flip_pending
)
4124 goto check_page_flip
;
4126 intel_finish_page_flip_cs(dev_priv
, pipe
);
4130 intel_check_page_flip(dev_priv
, pipe
);
4134 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4136 struct drm_device
*dev
= arg
;
4137 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4138 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4140 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4141 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4142 int pipe
, ret
= IRQ_NONE
;
4144 if (!intel_irqs_enabled(dev_priv
))
4147 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4148 disable_rpm_wakeref_asserts(dev_priv
);
4150 iir
= I915_READ(IIR
);
4152 bool irq_received
= (iir
& ~flip_mask
) != 0;
4153 bool blc_event
= false;
4155 /* Can't rely on pipestat interrupt bit in iir as it might
4156 * have been cleared after the pipestat interrupt was received.
4157 * It doesn't set the bit in iir again, but it still produces
4158 * interrupts (for non-MSI).
4160 spin_lock(&dev_priv
->irq_lock
);
4161 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4162 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4164 for_each_pipe(dev_priv
, pipe
) {
4165 i915_reg_t reg
= PIPESTAT(pipe
);
4166 pipe_stats
[pipe
] = I915_READ(reg
);
4168 /* Clear the PIPE*STAT regs before the IIR */
4169 if (pipe_stats
[pipe
] & 0x8000ffff) {
4170 I915_WRITE(reg
, pipe_stats
[pipe
]);
4171 irq_received
= true;
4174 spin_unlock(&dev_priv
->irq_lock
);
4179 /* Consume port. Then clear IIR or we'll miss events */
4180 if (I915_HAS_HOTPLUG(dev_priv
) &&
4181 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4182 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4184 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4187 I915_WRITE(IIR
, iir
& ~flip_mask
);
4188 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4190 if (iir
& I915_USER_INTERRUPT
)
4191 notify_ring(&dev_priv
->engine
[RCS
]);
4193 for_each_pipe(dev_priv
, pipe
) {
4195 if (HAS_FBC(dev_priv
))
4198 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4199 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4200 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4202 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4205 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4206 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4208 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4209 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4213 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4214 intel_opregion_asle_intr(dev_priv
);
4216 /* With MSI, interrupts are only generated when iir
4217 * transitions from zero to nonzero. If another bit got
4218 * set while we were handling the existing iir bits, then
4219 * we would never get another interrupt.
4221 * This is fine on non-MSI as well, as if we hit this path
4222 * we avoid exiting the interrupt handler only to generate
4225 * Note that for MSI this could cause a stray interrupt report
4226 * if an interrupt landed in the time between writing IIR and
4227 * the posting read. This should be rare enough to never
4228 * trigger the 99% of 100,000 interrupts test for disabling
4233 } while (iir
& ~flip_mask
);
4235 enable_rpm_wakeref_asserts(dev_priv
);
4240 static void i915_irq_uninstall(struct drm_device
* dev
)
4242 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4245 if (I915_HAS_HOTPLUG(dev
)) {
4246 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4247 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4250 I915_WRITE16(HWSTAM
, 0xffff);
4251 for_each_pipe(dev_priv
, pipe
) {
4252 /* Clear enable bits; then clear status bits */
4253 I915_WRITE(PIPESTAT(pipe
), 0);
4254 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4256 I915_WRITE(IMR
, 0xffffffff);
4257 I915_WRITE(IER
, 0x0);
4259 I915_WRITE(IIR
, I915_READ(IIR
));
4262 static void i965_irq_preinstall(struct drm_device
* dev
)
4264 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4267 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4268 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4270 I915_WRITE(HWSTAM
, 0xeffe);
4271 for_each_pipe(dev_priv
, pipe
)
4272 I915_WRITE(PIPESTAT(pipe
), 0);
4273 I915_WRITE(IMR
, 0xffffffff);
4274 I915_WRITE(IER
, 0x0);
4278 static int i965_irq_postinstall(struct drm_device
*dev
)
4280 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4284 /* Unmask the interrupts that we always want on. */
4285 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4286 I915_DISPLAY_PORT_INTERRUPT
|
4287 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4288 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4289 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4290 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4291 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4293 enable_mask
= ~dev_priv
->irq_mask
;
4294 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4295 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4296 enable_mask
|= I915_USER_INTERRUPT
;
4298 if (IS_G4X(dev_priv
))
4299 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4301 /* Interrupt setup is already guaranteed to be single-threaded, this is
4302 * just to make the assert_spin_locked check happy. */
4303 spin_lock_irq(&dev_priv
->irq_lock
);
4304 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4305 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4306 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4307 spin_unlock_irq(&dev_priv
->irq_lock
);
4310 * Enable some error detection, note the instruction error mask
4311 * bit is reserved, so we leave it masked.
4313 if (IS_G4X(dev_priv
)) {
4314 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4315 GM45_ERROR_MEM_PRIV
|
4316 GM45_ERROR_CP_PRIV
|
4317 I915_ERROR_MEMORY_REFRESH
);
4319 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4320 I915_ERROR_MEMORY_REFRESH
);
4322 I915_WRITE(EMR
, error_mask
);
4324 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4325 I915_WRITE(IER
, enable_mask
);
4328 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4329 POSTING_READ(PORT_HOTPLUG_EN
);
4331 i915_enable_asle_pipestat(dev_priv
);
4336 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
4340 assert_spin_locked(&dev_priv
->irq_lock
);
4342 /* Note HDMI and DP share hotplug bits */
4343 /* enable bits are the same for all generations */
4344 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
4345 /* Programming the CRT detection parameters tends
4346 to generate a spurious hotplug event about three
4347 seconds later. So just do it once.
4349 if (IS_G4X(dev_priv
))
4350 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4351 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4353 /* Ignore TV since it's buggy */
4354 i915_hotplug_interrupt_update_locked(dev_priv
,
4355 HOTPLUG_INT_EN_MASK
|
4356 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4357 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4361 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4363 struct drm_device
*dev
= arg
;
4364 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4366 u32 pipe_stats
[I915_MAX_PIPES
];
4367 int ret
= IRQ_NONE
, pipe
;
4369 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4370 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4372 if (!intel_irqs_enabled(dev_priv
))
4375 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4376 disable_rpm_wakeref_asserts(dev_priv
);
4378 iir
= I915_READ(IIR
);
4381 bool irq_received
= (iir
& ~flip_mask
) != 0;
4382 bool blc_event
= false;
4384 /* Can't rely on pipestat interrupt bit in iir as it might
4385 * have been cleared after the pipestat interrupt was received.
4386 * It doesn't set the bit in iir again, but it still produces
4387 * interrupts (for non-MSI).
4389 spin_lock(&dev_priv
->irq_lock
);
4390 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4391 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4393 for_each_pipe(dev_priv
, pipe
) {
4394 i915_reg_t reg
= PIPESTAT(pipe
);
4395 pipe_stats
[pipe
] = I915_READ(reg
);
4398 * Clear the PIPE*STAT regs before the IIR
4400 if (pipe_stats
[pipe
] & 0x8000ffff) {
4401 I915_WRITE(reg
, pipe_stats
[pipe
]);
4402 irq_received
= true;
4405 spin_unlock(&dev_priv
->irq_lock
);
4412 /* Consume port. Then clear IIR or we'll miss events */
4413 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4414 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4416 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4419 I915_WRITE(IIR
, iir
& ~flip_mask
);
4420 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4422 if (iir
& I915_USER_INTERRUPT
)
4423 notify_ring(&dev_priv
->engine
[RCS
]);
4424 if (iir
& I915_BSD_USER_INTERRUPT
)
4425 notify_ring(&dev_priv
->engine
[VCS
]);
4427 for_each_pipe(dev_priv
, pipe
) {
4428 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4429 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4430 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4432 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4435 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4436 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4438 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4439 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4442 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4443 intel_opregion_asle_intr(dev_priv
);
4445 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4446 gmbus_irq_handler(dev_priv
);
4448 /* With MSI, interrupts are only generated when iir
4449 * transitions from zero to nonzero. If another bit got
4450 * set while we were handling the existing iir bits, then
4451 * we would never get another interrupt.
4453 * This is fine on non-MSI as well, as if we hit this path
4454 * we avoid exiting the interrupt handler only to generate
4457 * Note that for MSI this could cause a stray interrupt report
4458 * if an interrupt landed in the time between writing IIR and
4459 * the posting read. This should be rare enough to never
4460 * trigger the 99% of 100,000 interrupts test for disabling
4466 enable_rpm_wakeref_asserts(dev_priv
);
4471 static void i965_irq_uninstall(struct drm_device
* dev
)
4473 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4479 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4480 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4482 I915_WRITE(HWSTAM
, 0xffffffff);
4483 for_each_pipe(dev_priv
, pipe
)
4484 I915_WRITE(PIPESTAT(pipe
), 0);
4485 I915_WRITE(IMR
, 0xffffffff);
4486 I915_WRITE(IER
, 0x0);
4488 for_each_pipe(dev_priv
, pipe
)
4489 I915_WRITE(PIPESTAT(pipe
),
4490 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4491 I915_WRITE(IIR
, I915_READ(IIR
));
4495 * intel_irq_init - initializes irq support
4496 * @dev_priv: i915 device instance
4498 * This function initializes all the irq support including work items, timers
4499 * and all the vtables. It does not setup the interrupt itself though.
4501 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4503 struct drm_device
*dev
= &dev_priv
->drm
;
4505 intel_hpd_init_work(dev_priv
);
4507 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4508 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4510 /* Let's track the enabled rps events */
4511 if (IS_VALLEYVIEW(dev_priv
))
4512 /* WaGsvRC0ResidencyMethod:vlv */
4513 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4515 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4517 dev_priv
->rps
.pm_intr_keep
= 0;
4520 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4521 * if GEN6_PM_UP_EI_EXPIRED is masked.
4523 * TODO: verify if this can be reproduced on VLV,CHV.
4525 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
4526 dev_priv
->rps
.pm_intr_keep
|= GEN6_PM_RP_UP_EI_EXPIRED
;
4528 if (INTEL_INFO(dev_priv
)->gen
>= 8)
4529 dev_priv
->rps
.pm_intr_keep
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
4531 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4532 i915_hangcheck_elapsed
);
4534 if (IS_GEN2(dev_priv
)) {
4535 /* Gen2 doesn't have a hardware frame counter */
4536 dev
->max_vblank_count
= 0;
4537 dev
->driver
->get_vblank_counter
= drm_vblank_no_hw_counter
;
4538 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4539 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4540 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4542 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4543 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4547 * Opt out of the vblank disable timer on everything except gen2.
4548 * Gen2 doesn't have a hardware frame counter and so depends on
4549 * vblank interrupts to produce sane vblank seuquence numbers.
4551 if (!IS_GEN2(dev_priv
))
4552 dev
->vblank_disable_immediate
= true;
4554 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4555 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4557 if (IS_CHERRYVIEW(dev_priv
)) {
4558 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4559 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4560 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4561 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4562 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4563 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4564 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4565 } else if (IS_VALLEYVIEW(dev_priv
)) {
4566 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4567 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4568 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4569 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4570 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4571 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4572 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4573 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4574 dev
->driver
->irq_handler
= gen8_irq_handler
;
4575 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4576 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4577 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4578 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4579 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4580 if (IS_BROXTON(dev
))
4581 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4582 else if (HAS_PCH_SPT(dev
) || HAS_PCH_KBP(dev
))
4583 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4585 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4586 } else if (HAS_PCH_SPLIT(dev
)) {
4587 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4588 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4589 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4590 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4591 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4592 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4593 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4595 if (IS_GEN2(dev_priv
)) {
4596 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4597 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4598 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4599 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4600 } else if (IS_GEN3(dev_priv
)) {
4601 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4602 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4603 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4604 dev
->driver
->irq_handler
= i915_irq_handler
;
4606 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4607 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4608 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4609 dev
->driver
->irq_handler
= i965_irq_handler
;
4611 if (I915_HAS_HOTPLUG(dev_priv
))
4612 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4613 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4614 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4619 * intel_irq_install - enables the hardware interrupt
4620 * @dev_priv: i915 device instance
4622 * This function enables the hardware interrupt handling, but leaves the hotplug
4623 * handling still disabled. It is called after intel_irq_init().
4625 * In the driver load and resume code we need working interrupts in a few places
4626 * but don't want to deal with the hassle of concurrent probe and hotplug
4627 * workers. Hence the split into this two-stage approach.
4629 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4632 * We enable some interrupt sources in our postinstall hooks, so mark
4633 * interrupts as enabled _before_ actually enabling them to avoid
4634 * special cases in our ordering checks.
4636 dev_priv
->pm
.irqs_enabled
= true;
4638 return drm_irq_install(&dev_priv
->drm
, dev_priv
->drm
.pdev
->irq
);
4642 * intel_irq_uninstall - finilizes all irq handling
4643 * @dev_priv: i915 device instance
4645 * This stops interrupt and hotplug handling and unregisters and frees all
4646 * resources acquired in the init functions.
4648 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4650 drm_irq_uninstall(&dev_priv
->drm
);
4651 intel_hpd_cancel_work(dev_priv
);
4652 dev_priv
->pm
.irqs_enabled
= false;
4656 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4657 * @dev_priv: i915 device instance
4659 * This function is used to disable interrupts at runtime, both in the runtime
4660 * pm and the system suspend/resume code.
4662 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4664 dev_priv
->drm
.driver
->irq_uninstall(&dev_priv
->drm
);
4665 dev_priv
->pm
.irqs_enabled
= false;
4666 synchronize_irq(dev_priv
->drm
.irq
);
4670 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4671 * @dev_priv: i915 device instance
4673 * This function is used to enable interrupts at runtime, both in the runtime
4674 * pm and the system suspend/resume code.
4676 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4678 dev_priv
->pm
.irqs_enabled
= true;
4679 dev_priv
->drm
.driver
->irq_preinstall(&dev_priv
->drm
);
4680 dev_priv
->drm
.driver
->irq_postinstall(&dev_priv
->drm
);