1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 static void ibx_hpd_irq_setup(struct drm_device
*dev
);
83 static void i915_hpd_irq_setup(struct drm_device
*dev
);
85 /* For display hotplug interrupt */
87 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
89 if ((dev_priv
->irq_mask
& mask
) != 0) {
90 dev_priv
->irq_mask
&= ~mask
;
91 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
97 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
99 if ((dev_priv
->irq_mask
& mask
) != mask
) {
100 dev_priv
->irq_mask
|= mask
;
101 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
106 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
109 struct intel_crtc
*crtc
;
112 for_each_pipe(pipe
) {
113 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
115 if (crtc
->cpu_fifo_underrun_disabled
)
122 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
126 struct intel_crtc
*crtc
;
128 for_each_pipe(pipe
) {
129 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
131 if (crtc
->pch_fifo_underrun_disabled
)
138 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
139 enum pipe pipe
, bool enable
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
142 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
143 DE_PIPEB_FIFO_UNDERRUN
;
146 ironlake_enable_display_irq(dev_priv
, bit
);
148 ironlake_disable_display_irq(dev_priv
, bit
);
151 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
157 if (!ivb_can_enable_err_int(dev
))
160 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN_A
|
161 ERR_INT_FIFO_UNDERRUN_B
|
162 ERR_INT_FIFO_UNDERRUN_C
);
164 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
166 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
170 static void ibx_set_fifo_underrun_reporting(struct intel_crtc
*crtc
,
173 struct drm_device
*dev
= crtc
->base
.dev
;
174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
175 uint32_t bit
= (crtc
->pipe
== PIPE_A
) ? SDE_TRANSA_FIFO_UNDER
:
176 SDE_TRANSB_FIFO_UNDER
;
179 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) & ~bit
);
181 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) | bit
);
183 POSTING_READ(SDEIMR
);
186 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
187 enum transcoder pch_transcoder
,
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 if (!cpt_can_enable_serr_int(dev
))
196 I915_WRITE(SERR_INT
, SERR_INT_TRANS_A_FIFO_UNDERRUN
|
197 SERR_INT_TRANS_B_FIFO_UNDERRUN
|
198 SERR_INT_TRANS_C_FIFO_UNDERRUN
);
200 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) & ~SDE_ERROR_CPT
);
202 I915_WRITE(SDEIMR
, I915_READ(SDEIMR
) | SDE_ERROR_CPT
);
205 POSTING_READ(SDEIMR
);
209 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
212 * @enable: true if we want to report FIFO underrun errors, false otherwise
214 * This function makes us disable or enable CPU fifo underruns for a specific
215 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
216 * reporting for one pipe may also disable all the other CPU error interruts for
217 * the other pipes, due to the fact that there's just one interrupt mask/enable
218 * bit for all the pipes.
220 * Returns the previous state of underrun reporting.
222 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
223 enum pipe pipe
, bool enable
)
225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
226 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
231 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
233 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
238 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
240 if (IS_GEN5(dev
) || IS_GEN6(dev
))
241 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
242 else if (IS_GEN7(dev
))
243 ivybridge_set_fifo_underrun_reporting(dev
, enable
);
246 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
251 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
253 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
254 * @enable: true if we want to report FIFO underrun errors, false otherwise
256 * This function makes us disable or enable PCH fifo underruns for a specific
257 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
258 * underrun reporting for one transcoder may also disable all the other PCH
259 * error interruts for the other transcoders, due to the fact that there's just
260 * one interrupt mask/enable bit for all the transcoders.
262 * Returns the previous state of underrun reporting.
264 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
265 enum transcoder pch_transcoder
,
268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
270 struct drm_crtc
*crtc
;
271 struct intel_crtc
*intel_crtc
;
275 if (HAS_PCH_LPT(dev
)) {
278 struct drm_crtc
*c
= dev_priv
->pipe_to_crtc_mapping
[p
];
279 if (intel_pipe_has_type(c
, INTEL_OUTPUT_ANALOG
)) {
285 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
289 crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
291 intel_crtc
= to_intel_crtc(crtc
);
293 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
295 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
300 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
302 if (HAS_PCH_IBX(dev
))
303 ibx_set_fifo_underrun_reporting(intel_crtc
, enable
);
305 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
308 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
314 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
316 u32 reg
= PIPESTAT(pipe
);
317 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
319 if ((pipestat
& mask
) == mask
)
322 /* Enable the interrupt, clear any pending status */
323 pipestat
|= mask
| (mask
>> 16);
324 I915_WRITE(reg
, pipestat
);
329 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
331 u32 reg
= PIPESTAT(pipe
);
332 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
334 if ((pipestat
& mask
) == 0)
338 I915_WRITE(reg
, pipestat
);
343 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
345 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
347 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
348 unsigned long irqflags
;
350 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
353 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
355 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
356 if (INTEL_INFO(dev
)->gen
>= 4)
357 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
359 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
363 * i915_pipe_enabled - check if a pipe is enabled
365 * @pipe: pipe to check
367 * Reading certain registers when the pipe is disabled can hang the chip.
368 * Use this routine to make sure the PLL is running and the pipe is active
369 * before reading such registers if unsure.
372 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
374 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
376 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
377 /* Locking is horribly broken here, but whatever. */
378 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
379 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
381 return intel_crtc
->active
;
383 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
387 /* Called from drm generic code, passed a 'crtc', which
388 * we use as a pipe index
390 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
392 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
393 unsigned long high_frame
;
394 unsigned long low_frame
;
395 u32 high1
, high2
, low
;
397 if (!i915_pipe_enabled(dev
, pipe
)) {
398 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
399 "pipe %c\n", pipe_name(pipe
));
403 high_frame
= PIPEFRAME(pipe
);
404 low_frame
= PIPEFRAMEPIXEL(pipe
);
407 * High & low register fields aren't synchronized, so make sure
408 * we get a low value that's stable across two reads of the high
412 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
413 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
414 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
415 } while (high1
!= high2
);
417 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
418 low
>>= PIPE_FRAME_LOW_SHIFT
;
419 return (high1
<< 8) | low
;
422 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
424 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
425 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
427 if (!i915_pipe_enabled(dev
, pipe
)) {
428 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
429 "pipe %c\n", pipe_name(pipe
));
433 return I915_READ(reg
);
436 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
437 int *vpos
, int *hpos
)
439 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
440 u32 vbl
= 0, position
= 0;
441 int vbl_start
, vbl_end
, htotal
, vtotal
;
444 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
447 if (!i915_pipe_enabled(dev
, pipe
)) {
448 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
449 "pipe %c\n", pipe_name(pipe
));
454 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
456 if (INTEL_INFO(dev
)->gen
>= 4) {
457 /* No obvious pixelcount register. Only query vertical
458 * scanout position from Display scan line register.
460 position
= I915_READ(PIPEDSL(pipe
));
462 /* Decode into vertical scanout position. Don't have
463 * horizontal scanout position.
465 *vpos
= position
& 0x1fff;
468 /* Have access to pixelcount since start of frame.
469 * We can split this into vertical and horizontal
472 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
474 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
475 *vpos
= position
/ htotal
;
476 *hpos
= position
- (*vpos
* htotal
);
479 /* Query vblank area. */
480 vbl
= I915_READ(VBLANK(cpu_transcoder
));
482 /* Test position against vblank region. */
483 vbl_start
= vbl
& 0x1fff;
484 vbl_end
= (vbl
>> 16) & 0x1fff;
486 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
489 /* Inside "upper part" of vblank area? Apply corrective offset: */
490 if (in_vbl
&& (*vpos
>= vbl_start
))
491 *vpos
= *vpos
- vtotal
;
493 /* Readouts valid? */
495 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
499 ret
|= DRM_SCANOUTPOS_INVBL
;
504 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
506 struct timeval
*vblank_time
,
509 struct drm_crtc
*crtc
;
511 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
512 DRM_ERROR("Invalid crtc %d\n", pipe
);
516 /* Get drm_crtc to timestamp: */
517 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
519 DRM_ERROR("Invalid crtc %d\n", pipe
);
523 if (!crtc
->enabled
) {
524 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
528 /* Helper routine in DRM core does all the work: */
529 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
534 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
536 enum drm_connector_status old_status
;
538 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
539 old_status
= connector
->status
;
541 connector
->status
= connector
->funcs
->detect(connector
, false);
542 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
544 drm_get_connector_name(connector
),
545 old_status
, connector
->status
);
546 return (old_status
!= connector
->status
);
550 * Handle hotplug events outside the interrupt handler proper.
552 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
554 static void i915_hotplug_work_func(struct work_struct
*work
)
556 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
558 struct drm_device
*dev
= dev_priv
->dev
;
559 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
560 struct intel_connector
*intel_connector
;
561 struct intel_encoder
*intel_encoder
;
562 struct drm_connector
*connector
;
563 unsigned long irqflags
;
564 bool hpd_disabled
= false;
565 bool changed
= false;
568 /* HPD irq before everything is fully set up. */
569 if (!dev_priv
->enable_hotplug_processing
)
572 mutex_lock(&mode_config
->mutex
);
573 DRM_DEBUG_KMS("running encoder hotplug functions\n");
575 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
577 hpd_event_bits
= dev_priv
->hpd_event_bits
;
578 dev_priv
->hpd_event_bits
= 0;
579 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
580 intel_connector
= to_intel_connector(connector
);
581 intel_encoder
= intel_connector
->encoder
;
582 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
583 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
584 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
585 DRM_INFO("HPD interrupt storm detected on connector %s: "
586 "switching from hotplug detection to polling\n",
587 drm_get_connector_name(connector
));
588 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
589 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
590 | DRM_CONNECTOR_POLL_DISCONNECT
;
593 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
594 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
595 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
598 /* if there were no outputs to poll, poll was disabled,
599 * therefore make sure it's enabled when disabling HPD on
602 drm_kms_helper_poll_enable(dev
);
603 mod_timer(&dev_priv
->hotplug_reenable_timer
,
604 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
607 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
609 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
610 intel_connector
= to_intel_connector(connector
);
611 intel_encoder
= intel_connector
->encoder
;
612 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
613 if (intel_encoder
->hot_plug
)
614 intel_encoder
->hot_plug(intel_encoder
);
615 if (intel_hpd_irq_event(dev
, connector
))
619 mutex_unlock(&mode_config
->mutex
);
622 drm_kms_helper_hotplug_event(dev
);
625 static void ironlake_handle_rps_change(struct drm_device
*dev
)
627 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
628 u32 busy_up
, busy_down
, max_avg
, min_avg
;
632 spin_lock_irqsave(&mchdev_lock
, flags
);
634 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
636 new_delay
= dev_priv
->ips
.cur_delay
;
638 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
639 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
640 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
641 max_avg
= I915_READ(RCBMAXAVG
);
642 min_avg
= I915_READ(RCBMINAVG
);
644 /* Handle RCS change request from hw */
645 if (busy_up
> max_avg
) {
646 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
647 new_delay
= dev_priv
->ips
.cur_delay
- 1;
648 if (new_delay
< dev_priv
->ips
.max_delay
)
649 new_delay
= dev_priv
->ips
.max_delay
;
650 } else if (busy_down
< min_avg
) {
651 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
652 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
653 if (new_delay
> dev_priv
->ips
.min_delay
)
654 new_delay
= dev_priv
->ips
.min_delay
;
657 if (ironlake_set_drps(dev
, new_delay
))
658 dev_priv
->ips
.cur_delay
= new_delay
;
660 spin_unlock_irqrestore(&mchdev_lock
, flags
);
665 static void notify_ring(struct drm_device
*dev
,
666 struct intel_ring_buffer
*ring
)
668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
670 if (ring
->obj
== NULL
)
673 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
675 wake_up_all(&ring
->irq_queue
);
676 if (i915_enable_hangcheck
) {
677 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
678 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
682 static void gen6_pm_rps_work(struct work_struct
*work
)
684 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
689 spin_lock_irq(&dev_priv
->rps
.lock
);
690 pm_iir
= dev_priv
->rps
.pm_iir
;
691 dev_priv
->rps
.pm_iir
= 0;
692 pm_imr
= I915_READ(GEN6_PMIMR
);
693 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
694 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
695 spin_unlock_irq(&dev_priv
->rps
.lock
);
697 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
700 mutex_lock(&dev_priv
->rps
.hw_lock
);
702 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
)
703 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
705 new_delay
= dev_priv
->rps
.cur_delay
- 1;
707 /* sysfs frequency interfaces may have snuck in while servicing the
710 if (!(new_delay
> dev_priv
->rps
.max_delay
||
711 new_delay
< dev_priv
->rps
.min_delay
)) {
712 if (IS_VALLEYVIEW(dev_priv
->dev
))
713 valleyview_set_rps(dev_priv
->dev
, new_delay
);
715 gen6_set_rps(dev_priv
->dev
, new_delay
);
718 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
720 * On VLV, when we enter RC6 we may not be at the minimum
721 * voltage level, so arm a timer to check. It should only
722 * fire when there's activity or once after we've entered
723 * RC6, and then won't be re-armed until the next RPS interrupt.
725 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
726 msecs_to_jiffies(100));
729 mutex_unlock(&dev_priv
->rps
.hw_lock
);
734 * ivybridge_parity_work - Workqueue called when a parity error interrupt
736 * @work: workqueue struct
738 * Doesn't actually do anything except notify userspace. As a consequence of
739 * this event, userspace should try to remap the bad rows since statistically
740 * it is likely the same row is more likely to go bad again.
742 static void ivybridge_parity_work(struct work_struct
*work
)
744 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
745 l3_parity
.error_work
);
746 u32 error_status
, row
, bank
, subbank
;
747 char *parity_event
[5];
751 /* We must turn off DOP level clock gating to access the L3 registers.
752 * In order to prevent a get/put style interface, acquire struct mutex
753 * any time we access those registers.
755 mutex_lock(&dev_priv
->dev
->struct_mutex
);
757 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
758 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
759 POSTING_READ(GEN7_MISCCPCTL
);
761 error_status
= I915_READ(GEN7_L3CDERRST1
);
762 row
= GEN7_PARITY_ERROR_ROW(error_status
);
763 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
764 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
766 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
767 GEN7_L3CDERRST1_ENABLE
);
768 POSTING_READ(GEN7_L3CDERRST1
);
770 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
772 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
773 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
774 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
775 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
777 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
779 parity_event
[0] = "L3_PARITY_ERROR=1";
780 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
781 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
782 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
783 parity_event
[4] = NULL
;
785 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
786 KOBJ_CHANGE
, parity_event
);
788 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
791 kfree(parity_event
[3]);
792 kfree(parity_event
[2]);
793 kfree(parity_event
[1]);
796 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
798 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
801 if (!HAS_L3_GPU_CACHE(dev
))
804 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
805 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
806 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
807 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
809 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
812 static void snb_gt_irq_handler(struct drm_device
*dev
,
813 struct drm_i915_private
*dev_priv
,
818 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
819 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
820 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
821 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
822 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
823 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
825 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
826 GT_BSD_CS_ERROR_INTERRUPT
|
827 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
828 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
829 i915_handle_error(dev
, false);
832 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
833 ivybridge_handle_parity_error(dev
);
836 /* Legacy way of handling PM interrupts */
837 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
843 * IIR bits should never already be set because IMR should
844 * prevent an interrupt from being shown in IIR. The warning
845 * displays a case where we've unsafely cleared
846 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
847 * type is not a problem, it displays a problem in the logic.
849 * The mask bit in IMR is cleared by dev_priv->rps.work.
852 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
853 dev_priv
->rps
.pm_iir
|= pm_iir
;
854 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
855 POSTING_READ(GEN6_PMIMR
);
856 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
858 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
861 #define HPD_STORM_DETECT_PERIOD 1000
862 #define HPD_STORM_THRESHOLD 5
864 static inline bool hotplug_irq_storm_detect(struct drm_device
*dev
,
868 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
869 unsigned long irqflags
;
873 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
875 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
877 if (!(hpd
[i
] & hotplug_trigger
) ||
878 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
881 dev_priv
->hpd_event_bits
|= (1 << i
);
882 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
883 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
884 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
885 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
886 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
887 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
888 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
889 dev_priv
->hpd_event_bits
&= ~(1 << i
);
890 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
893 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
897 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
902 static void gmbus_irq_handler(struct drm_device
*dev
)
904 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
906 wake_up_all(&dev_priv
->gmbus_wait_queue
);
909 static void dp_aux_irq_handler(struct drm_device
*dev
)
911 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
913 wake_up_all(&dev_priv
->gmbus_wait_queue
);
916 /* Unlike gen6_queue_rps_work() from which this function is originally derived,
917 * we must be able to deal with other PM interrupts. This is complicated because
918 * of the way in which we use the masks to defer the RPS work (which for
919 * posterity is necessary because of forcewake).
921 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
926 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
927 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
928 if (dev_priv
->rps
.pm_iir
) {
929 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
930 /* never want to mask useful interrupts. (also posting read) */
931 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
932 /* TODO: if queue_work is slow, move it out of the spinlock */
933 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
935 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
937 if (pm_iir
& ~GEN6_PM_RPS_EVENTS
) {
938 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
939 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
941 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
942 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
943 i915_handle_error(dev_priv
->dev
, false);
948 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
950 struct drm_device
*dev
= (struct drm_device
*) arg
;
951 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
952 u32 iir
, gt_iir
, pm_iir
;
953 irqreturn_t ret
= IRQ_NONE
;
954 unsigned long irqflags
;
956 u32 pipe_stats
[I915_MAX_PIPES
];
958 atomic_inc(&dev_priv
->irq_received
);
961 iir
= I915_READ(VLV_IIR
);
962 gt_iir
= I915_READ(GTIIR
);
963 pm_iir
= I915_READ(GEN6_PMIIR
);
965 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
970 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
972 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
973 for_each_pipe(pipe
) {
974 int reg
= PIPESTAT(pipe
);
975 pipe_stats
[pipe
] = I915_READ(reg
);
978 * Clear the PIPE*STAT regs before the IIR
980 if (pipe_stats
[pipe
] & 0x8000ffff) {
981 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
982 DRM_DEBUG_DRIVER("pipe %c underrun\n",
984 I915_WRITE(reg
, pipe_stats
[pipe
]);
987 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
989 for_each_pipe(pipe
) {
990 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
991 drm_handle_vblank(dev
, pipe
);
993 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
994 intel_prepare_page_flip(dev
, pipe
);
995 intel_finish_page_flip(dev
, pipe
);
999 /* Consume port. Then clear IIR or we'll miss events */
1000 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1001 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1002 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1004 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1006 if (hotplug_trigger
) {
1007 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_status_i915
))
1008 i915_hpd_irq_setup(dev
);
1009 queue_work(dev_priv
->wq
,
1010 &dev_priv
->hotplug_work
);
1012 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1013 I915_READ(PORT_HOTPLUG_STAT
);
1016 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1017 gmbus_irq_handler(dev
);
1019 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1020 gen6_queue_rps_work(dev_priv
, pm_iir
);
1022 I915_WRITE(GTIIR
, gt_iir
);
1023 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1024 I915_WRITE(VLV_IIR
, iir
);
1031 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1033 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1035 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1037 if (hotplug_trigger
) {
1038 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_ibx
))
1039 ibx_hpd_irq_setup(dev
);
1040 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
1042 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1043 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1044 SDE_AUDIO_POWER_SHIFT
);
1045 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1049 if (pch_iir
& SDE_AUX_MASK
)
1050 dp_aux_irq_handler(dev
);
1052 if (pch_iir
& SDE_GMBUS
)
1053 gmbus_irq_handler(dev
);
1055 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1056 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1058 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1059 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1061 if (pch_iir
& SDE_POISON
)
1062 DRM_ERROR("PCH poison interrupt\n");
1064 if (pch_iir
& SDE_FDI_MASK
)
1066 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1068 I915_READ(FDI_RX_IIR(pipe
)));
1070 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1071 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1073 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1074 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1076 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1077 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1079 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1081 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1082 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1084 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1087 static void ivb_err_int_handler(struct drm_device
*dev
)
1089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1090 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1092 if (err_int
& ERR_INT_POISON
)
1093 DRM_ERROR("Poison interrupt\n");
1095 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1096 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1097 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1099 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1100 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1101 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1103 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1104 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1105 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1107 I915_WRITE(GEN7_ERR_INT
, err_int
);
1110 static void cpt_serr_int_handler(struct drm_device
*dev
)
1112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 u32 serr_int
= I915_READ(SERR_INT
);
1115 if (serr_int
& SERR_INT_POISON
)
1116 DRM_ERROR("PCH poison interrupt\n");
1118 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1119 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1121 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1123 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1124 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1126 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1128 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1129 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1131 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1133 I915_WRITE(SERR_INT
, serr_int
);
1136 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1138 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1140 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1142 if (hotplug_trigger
) {
1143 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_cpt
))
1144 ibx_hpd_irq_setup(dev
);
1145 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
1147 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1148 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1149 SDE_AUDIO_POWER_SHIFT_CPT
);
1150 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1154 if (pch_iir
& SDE_AUX_MASK_CPT
)
1155 dp_aux_irq_handler(dev
);
1157 if (pch_iir
& SDE_GMBUS_CPT
)
1158 gmbus_irq_handler(dev
);
1160 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1161 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1163 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1164 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1166 if (pch_iir
& SDE_FDI_MASK_CPT
)
1168 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1170 I915_READ(FDI_RX_IIR(pipe
)));
1172 if (pch_iir
& SDE_ERROR_CPT
)
1173 cpt_serr_int_handler(dev
);
1176 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1178 struct drm_device
*dev
= (struct drm_device
*) arg
;
1179 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1180 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1181 irqreturn_t ret
= IRQ_NONE
;
1184 atomic_inc(&dev_priv
->irq_received
);
1186 /* We get interrupts on unclaimed registers, so check for this before we
1187 * do any I915_{READ,WRITE}. */
1188 if (IS_HASWELL(dev
) &&
1189 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1190 DRM_ERROR("Unclaimed register before interrupt\n");
1191 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1194 /* disable master interrupt before clearing iir */
1195 de_ier
= I915_READ(DEIER
);
1196 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1198 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1199 * interrupts will will be stored on its back queue, and then we'll be
1200 * able to process them after we restore SDEIER (as soon as we restore
1201 * it, we'll get an interrupt if SDEIIR still has something to process
1202 * due to its back queue). */
1203 if (!HAS_PCH_NOP(dev
)) {
1204 sde_ier
= I915_READ(SDEIER
);
1205 I915_WRITE(SDEIER
, 0);
1206 POSTING_READ(SDEIER
);
1209 /* On Haswell, also mask ERR_INT because we don't want to risk
1210 * generating "unclaimed register" interrupts from inside the interrupt
1212 if (IS_HASWELL(dev
))
1213 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1215 gt_iir
= I915_READ(GTIIR
);
1217 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1218 I915_WRITE(GTIIR
, gt_iir
);
1222 de_iir
= I915_READ(DEIIR
);
1224 if (de_iir
& DE_ERR_INT_IVB
)
1225 ivb_err_int_handler(dev
);
1227 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1228 dp_aux_irq_handler(dev
);
1230 if (de_iir
& DE_GSE_IVB
)
1231 intel_opregion_asle_intr(dev
);
1233 for (i
= 0; i
< 3; i
++) {
1234 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1235 drm_handle_vblank(dev
, i
);
1236 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1237 intel_prepare_page_flip(dev
, i
);
1238 intel_finish_page_flip_plane(dev
, i
);
1242 /* check event from PCH */
1243 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1244 u32 pch_iir
= I915_READ(SDEIIR
);
1246 cpt_irq_handler(dev
, pch_iir
);
1248 /* clear PCH hotplug event before clear CPU irq */
1249 I915_WRITE(SDEIIR
, pch_iir
);
1252 I915_WRITE(DEIIR
, de_iir
);
1256 pm_iir
= I915_READ(GEN6_PMIIR
);
1258 if (IS_HASWELL(dev
))
1259 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1260 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1261 gen6_queue_rps_work(dev_priv
, pm_iir
);
1262 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1266 if (IS_HASWELL(dev
) && ivb_can_enable_err_int(dev
))
1267 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1269 I915_WRITE(DEIER
, de_ier
);
1270 POSTING_READ(DEIER
);
1271 if (!HAS_PCH_NOP(dev
)) {
1272 I915_WRITE(SDEIER
, sde_ier
);
1273 POSTING_READ(SDEIER
);
1279 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1280 struct drm_i915_private
*dev_priv
,
1284 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1285 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1286 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1287 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1290 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1292 struct drm_device
*dev
= (struct drm_device
*) arg
;
1293 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1295 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1297 atomic_inc(&dev_priv
->irq_received
);
1299 /* disable master interrupt before clearing iir */
1300 de_ier
= I915_READ(DEIER
);
1301 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1302 POSTING_READ(DEIER
);
1304 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1305 * interrupts will will be stored on its back queue, and then we'll be
1306 * able to process them after we restore SDEIER (as soon as we restore
1307 * it, we'll get an interrupt if SDEIIR still has something to process
1308 * due to its back queue). */
1309 sde_ier
= I915_READ(SDEIER
);
1310 I915_WRITE(SDEIER
, 0);
1311 POSTING_READ(SDEIER
);
1313 de_iir
= I915_READ(DEIIR
);
1314 gt_iir
= I915_READ(GTIIR
);
1315 pm_iir
= I915_READ(GEN6_PMIIR
);
1317 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1323 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1325 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1327 if (de_iir
& DE_AUX_CHANNEL_A
)
1328 dp_aux_irq_handler(dev
);
1330 if (de_iir
& DE_GSE
)
1331 intel_opregion_asle_intr(dev
);
1333 if (de_iir
& DE_PIPEA_VBLANK
)
1334 drm_handle_vblank(dev
, 0);
1336 if (de_iir
& DE_PIPEB_VBLANK
)
1337 drm_handle_vblank(dev
, 1);
1339 if (de_iir
& DE_POISON
)
1340 DRM_ERROR("Poison interrupt\n");
1342 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1343 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1344 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1346 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1347 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1348 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1350 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1351 intel_prepare_page_flip(dev
, 0);
1352 intel_finish_page_flip_plane(dev
, 0);
1355 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1356 intel_prepare_page_flip(dev
, 1);
1357 intel_finish_page_flip_plane(dev
, 1);
1360 /* check event from PCH */
1361 if (de_iir
& DE_PCH_EVENT
) {
1362 u32 pch_iir
= I915_READ(SDEIIR
);
1364 if (HAS_PCH_CPT(dev
))
1365 cpt_irq_handler(dev
, pch_iir
);
1367 ibx_irq_handler(dev
, pch_iir
);
1369 /* should clear PCH hotplug event before clear CPU irq */
1370 I915_WRITE(SDEIIR
, pch_iir
);
1373 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1374 ironlake_handle_rps_change(dev
);
1376 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_RPS_EVENTS
)
1377 gen6_queue_rps_work(dev_priv
, pm_iir
);
1379 I915_WRITE(GTIIR
, gt_iir
);
1380 I915_WRITE(DEIIR
, de_iir
);
1381 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1384 I915_WRITE(DEIER
, de_ier
);
1385 POSTING_READ(DEIER
);
1386 I915_WRITE(SDEIER
, sde_ier
);
1387 POSTING_READ(SDEIER
);
1393 * i915_error_work_func - do process context error handling work
1394 * @work: work struct
1396 * Fire an error uevent so userspace can see that a hang or error
1399 static void i915_error_work_func(struct work_struct
*work
)
1401 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1403 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1405 struct drm_device
*dev
= dev_priv
->dev
;
1406 struct intel_ring_buffer
*ring
;
1407 char *error_event
[] = { "ERROR=1", NULL
};
1408 char *reset_event
[] = { "RESET=1", NULL
};
1409 char *reset_done_event
[] = { "ERROR=0", NULL
};
1412 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1415 * Note that there's only one work item which does gpu resets, so we
1416 * need not worry about concurrent gpu resets potentially incrementing
1417 * error->reset_counter twice. We only need to take care of another
1418 * racing irq/hangcheck declaring the gpu dead for a second time. A
1419 * quick check for that is good enough: schedule_work ensures the
1420 * correct ordering between hang detection and this work item, and since
1421 * the reset in-progress bit is only ever set by code outside of this
1422 * work we don't need to worry about any other races.
1424 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1425 DRM_DEBUG_DRIVER("resetting chip\n");
1426 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1429 ret
= i915_reset(dev
);
1433 * After all the gem state is reset, increment the reset
1434 * counter and wake up everyone waiting for the reset to
1437 * Since unlock operations are a one-sided barrier only,
1438 * we need to insert a barrier here to order any seqno
1440 * the counter increment.
1442 smp_mb__before_atomic_inc();
1443 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1445 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1446 KOBJ_CHANGE
, reset_done_event
);
1448 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1451 for_each_ring(ring
, dev_priv
, i
)
1452 wake_up_all(&ring
->irq_queue
);
1454 intel_display_handle_reset(dev
);
1456 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1460 /* NB: please notice the memset */
1461 static void i915_get_extra_instdone(struct drm_device
*dev
,
1464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
1467 switch(INTEL_INFO(dev
)->gen
) {
1470 instdone
[0] = I915_READ(INSTDONE
);
1475 instdone
[0] = I915_READ(INSTDONE_I965
);
1476 instdone
[1] = I915_READ(INSTDONE1
);
1479 WARN_ONCE(1, "Unsupported platform\n");
1481 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
1482 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
1483 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
1484 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
1489 #ifdef CONFIG_DEBUG_FS
1490 static struct drm_i915_error_object
*
1491 i915_error_object_create_sized(struct drm_i915_private
*dev_priv
,
1492 struct drm_i915_gem_object
*src
,
1493 const int num_pages
)
1495 struct drm_i915_error_object
*dst
;
1499 if (src
== NULL
|| src
->pages
== NULL
)
1502 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), GFP_ATOMIC
);
1506 reloc_offset
= src
->gtt_offset
;
1507 for (i
= 0; i
< num_pages
; i
++) {
1508 unsigned long flags
;
1511 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
1515 local_irq_save(flags
);
1516 if (reloc_offset
< dev_priv
->gtt
.mappable_end
&&
1517 src
->has_global_gtt_mapping
) {
1520 /* Simply ignore tiling or any overlapping fence.
1521 * It's part of the error state, and this hopefully
1522 * captures what the GPU read.
1525 s
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
1527 memcpy_fromio(d
, s
, PAGE_SIZE
);
1528 io_mapping_unmap_atomic(s
);
1529 } else if (src
->stolen
) {
1530 unsigned long offset
;
1532 offset
= dev_priv
->mm
.stolen_base
;
1533 offset
+= src
->stolen
->start
;
1534 offset
+= i
<< PAGE_SHIFT
;
1536 memcpy_fromio(d
, (void __iomem
*) offset
, PAGE_SIZE
);
1541 page
= i915_gem_object_get_page(src
, i
);
1543 drm_clflush_pages(&page
, 1);
1545 s
= kmap_atomic(page
);
1546 memcpy(d
, s
, PAGE_SIZE
);
1549 drm_clflush_pages(&page
, 1);
1551 local_irq_restore(flags
);
1555 reloc_offset
+= PAGE_SIZE
;
1557 dst
->page_count
= num_pages
;
1558 dst
->gtt_offset
= src
->gtt_offset
;
1564 kfree(dst
->pages
[i
]);
1568 #define i915_error_object_create(dev_priv, src) \
1569 i915_error_object_create_sized((dev_priv), (src), \
1570 (src)->base.size>>PAGE_SHIFT)
1573 i915_error_object_free(struct drm_i915_error_object
*obj
)
1580 for (page
= 0; page
< obj
->page_count
; page
++)
1581 kfree(obj
->pages
[page
]);
1587 i915_error_state_free(struct kref
*error_ref
)
1589 struct drm_i915_error_state
*error
= container_of(error_ref
,
1590 typeof(*error
), ref
);
1593 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
1594 i915_error_object_free(error
->ring
[i
].batchbuffer
);
1595 i915_error_object_free(error
->ring
[i
].ringbuffer
);
1596 i915_error_object_free(error
->ring
[i
].ctx
);
1597 kfree(error
->ring
[i
].requests
);
1600 kfree(error
->active_bo
);
1601 kfree(error
->overlay
);
1602 kfree(error
->display
);
1605 static void capture_bo(struct drm_i915_error_buffer
*err
,
1606 struct drm_i915_gem_object
*obj
)
1608 err
->size
= obj
->base
.size
;
1609 err
->name
= obj
->base
.name
;
1610 err
->rseqno
= obj
->last_read_seqno
;
1611 err
->wseqno
= obj
->last_write_seqno
;
1612 err
->gtt_offset
= obj
->gtt_offset
;
1613 err
->read_domains
= obj
->base
.read_domains
;
1614 err
->write_domain
= obj
->base
.write_domain
;
1615 err
->fence_reg
= obj
->fence_reg
;
1617 if (obj
->pin_count
> 0)
1619 if (obj
->user_pin_count
> 0)
1621 err
->tiling
= obj
->tiling_mode
;
1622 err
->dirty
= obj
->dirty
;
1623 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1624 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1625 err
->cache_level
= obj
->cache_level
;
1628 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1629 int count
, struct list_head
*head
)
1631 struct drm_i915_gem_object
*obj
;
1634 list_for_each_entry(obj
, head
, mm_list
) {
1635 capture_bo(err
++, obj
);
1643 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1644 int count
, struct list_head
*head
)
1646 struct drm_i915_gem_object
*obj
;
1649 list_for_each_entry(obj
, head
, global_list
) {
1650 if (obj
->pin_count
== 0)
1653 capture_bo(err
++, obj
);
1661 static void i915_gem_record_fences(struct drm_device
*dev
,
1662 struct drm_i915_error_state
*error
)
1664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1668 switch (INTEL_INFO(dev
)->gen
) {
1671 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++)
1672 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1676 for (i
= 0; i
< 16; i
++)
1677 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1680 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1681 for (i
= 0; i
< 8; i
++)
1682 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1684 for (i
= 0; i
< 8; i
++)
1685 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1693 static struct drm_i915_error_object
*
1694 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1695 struct intel_ring_buffer
*ring
)
1697 struct drm_i915_gem_object
*obj
;
1700 if (!ring
->get_seqno
)
1703 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1704 u32 acthd
= I915_READ(ACTHD
);
1706 if (WARN_ON(ring
->id
!= RCS
))
1709 obj
= ring
->private;
1710 if (acthd
>= obj
->gtt_offset
&&
1711 acthd
< obj
->gtt_offset
+ obj
->base
.size
)
1712 return i915_error_object_create(dev_priv
, obj
);
1715 seqno
= ring
->get_seqno(ring
, false);
1716 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1717 if (obj
->ring
!= ring
)
1720 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1723 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1726 /* We need to copy these to an anonymous buffer as the simplest
1727 * method to avoid being overwritten by userspace.
1729 return i915_error_object_create(dev_priv
, obj
);
1735 static void i915_record_ring_state(struct drm_device
*dev
,
1736 struct drm_i915_error_state
*error
,
1737 struct intel_ring_buffer
*ring
)
1739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1741 if (INTEL_INFO(dev
)->gen
>= 6) {
1742 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1743 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1744 error
->semaphore_mboxes
[ring
->id
][0]
1745 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1746 error
->semaphore_mboxes
[ring
->id
][1]
1747 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1748 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1749 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1752 if (INTEL_INFO(dev
)->gen
>= 4) {
1753 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1754 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1755 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1756 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1757 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1758 if (ring
->id
== RCS
)
1759 error
->bbaddr
= I915_READ64(BB_ADDR
);
1761 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1762 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1763 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1764 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1767 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1768 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1769 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1770 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1771 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1772 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1773 error
->ctl
[ring
->id
] = I915_READ_CTL(ring
);
1775 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1776 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1780 static void i915_gem_record_active_context(struct intel_ring_buffer
*ring
,
1781 struct drm_i915_error_state
*error
,
1782 struct drm_i915_error_ring
*ering
)
1784 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1785 struct drm_i915_gem_object
*obj
;
1787 /* Currently render ring is the only HW context user */
1788 if (ring
->id
!= RCS
|| !error
->ccid
)
1791 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1792 if ((error
->ccid
& PAGE_MASK
) == obj
->gtt_offset
) {
1793 ering
->ctx
= i915_error_object_create_sized(dev_priv
,
1799 static void i915_gem_record_rings(struct drm_device
*dev
,
1800 struct drm_i915_error_state
*error
)
1802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1803 struct intel_ring_buffer
*ring
;
1804 struct drm_i915_gem_request
*request
;
1807 for_each_ring(ring
, dev_priv
, i
) {
1808 i915_record_ring_state(dev
, error
, ring
);
1810 error
->ring
[i
].batchbuffer
=
1811 i915_error_first_batchbuffer(dev_priv
, ring
);
1813 error
->ring
[i
].ringbuffer
=
1814 i915_error_object_create(dev_priv
, ring
->obj
);
1817 i915_gem_record_active_context(ring
, error
, &error
->ring
[i
]);
1820 list_for_each_entry(request
, &ring
->request_list
, list
)
1823 error
->ring
[i
].num_requests
= count
;
1824 error
->ring
[i
].requests
=
1825 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1827 if (error
->ring
[i
].requests
== NULL
) {
1828 error
->ring
[i
].num_requests
= 0;
1833 list_for_each_entry(request
, &ring
->request_list
, list
) {
1834 struct drm_i915_error_request
*erq
;
1836 erq
= &error
->ring
[i
].requests
[count
++];
1837 erq
->seqno
= request
->seqno
;
1838 erq
->jiffies
= request
->emitted_jiffies
;
1839 erq
->tail
= request
->tail
;
1845 * i915_capture_error_state - capture an error record for later analysis
1848 * Should be called when an error is detected (either a hang or an error
1849 * interrupt) to capture error state from the time of the error. Fills
1850 * out a structure which becomes available in debugfs for user level tools
1853 static void i915_capture_error_state(struct drm_device
*dev
)
1855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1856 struct drm_i915_gem_object
*obj
;
1857 struct drm_i915_error_state
*error
;
1858 unsigned long flags
;
1861 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1862 error
= dev_priv
->gpu_error
.first_error
;
1863 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1867 /* Account for pipe specific data like PIPE*STAT */
1868 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1870 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1874 DRM_INFO("capturing error event; look for more information in "
1875 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1876 dev
->primary
->index
);
1878 kref_init(&error
->ref
);
1879 error
->eir
= I915_READ(EIR
);
1880 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1881 if (HAS_HW_CONTEXTS(dev
))
1882 error
->ccid
= I915_READ(CCID
);
1884 if (HAS_PCH_SPLIT(dev
))
1885 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1886 else if (IS_VALLEYVIEW(dev
))
1887 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1888 else if (IS_GEN2(dev
))
1889 error
->ier
= I915_READ16(IER
);
1891 error
->ier
= I915_READ(IER
);
1893 if (INTEL_INFO(dev
)->gen
>= 6)
1894 error
->derrmr
= I915_READ(DERRMR
);
1896 if (IS_VALLEYVIEW(dev
))
1897 error
->forcewake
= I915_READ(FORCEWAKE_VLV
);
1898 else if (INTEL_INFO(dev
)->gen
>= 7)
1899 error
->forcewake
= I915_READ(FORCEWAKE_MT
);
1900 else if (INTEL_INFO(dev
)->gen
== 6)
1901 error
->forcewake
= I915_READ(FORCEWAKE
);
1903 if (!HAS_PCH_SPLIT(dev
))
1905 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1907 if (INTEL_INFO(dev
)->gen
>= 6) {
1908 error
->error
= I915_READ(ERROR_GEN6
);
1909 error
->done_reg
= I915_READ(DONE_REG
);
1912 if (INTEL_INFO(dev
)->gen
== 7)
1913 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1915 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1917 i915_gem_record_fences(dev
, error
);
1918 i915_gem_record_rings(dev
, error
);
1920 /* Record buffers on the active and pinned lists. */
1921 error
->active_bo
= NULL
;
1922 error
->pinned_bo
= NULL
;
1925 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1927 error
->active_bo_count
= i
;
1928 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1931 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1933 error
->active_bo
= NULL
;
1934 error
->pinned_bo
= NULL
;
1936 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1938 if (error
->active_bo
)
1940 error
->active_bo
+ error
->active_bo_count
;
1943 if (error
->active_bo
)
1944 error
->active_bo_count
=
1945 capture_active_bo(error
->active_bo
,
1946 error
->active_bo_count
,
1947 &dev_priv
->mm
.active_list
);
1949 if (error
->pinned_bo
)
1950 error
->pinned_bo_count
=
1951 capture_pinned_bo(error
->pinned_bo
,
1952 error
->pinned_bo_count
,
1953 &dev_priv
->mm
.bound_list
);
1955 do_gettimeofday(&error
->time
);
1957 error
->overlay
= intel_overlay_capture_error_state(dev
);
1958 error
->display
= intel_display_capture_error_state(dev
);
1960 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1961 if (dev_priv
->gpu_error
.first_error
== NULL
) {
1962 dev_priv
->gpu_error
.first_error
= error
;
1965 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1968 i915_error_state_free(&error
->ref
);
1971 void i915_destroy_error_state(struct drm_device
*dev
)
1973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1974 struct drm_i915_error_state
*error
;
1975 unsigned long flags
;
1977 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1978 error
= dev_priv
->gpu_error
.first_error
;
1979 dev_priv
->gpu_error
.first_error
= NULL
;
1980 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1983 kref_put(&error
->ref
, i915_error_state_free
);
1986 #define i915_capture_error_state(x)
1989 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1992 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1993 u32 eir
= I915_READ(EIR
);
1999 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2001 i915_get_extra_instdone(dev
, instdone
);
2004 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2005 u32 ipeir
= I915_READ(IPEIR_I965
);
2007 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2008 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2009 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2010 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2011 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2012 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2013 I915_WRITE(IPEIR_I965
, ipeir
);
2014 POSTING_READ(IPEIR_I965
);
2016 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2017 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2018 pr_err("page table error\n");
2019 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2020 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2021 POSTING_READ(PGTBL_ER
);
2025 if (!IS_GEN2(dev
)) {
2026 if (eir
& I915_ERROR_PAGE_TABLE
) {
2027 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2028 pr_err("page table error\n");
2029 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2030 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2031 POSTING_READ(PGTBL_ER
);
2035 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2036 pr_err("memory refresh error:\n");
2038 pr_err("pipe %c stat: 0x%08x\n",
2039 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2040 /* pipestat has already been acked */
2042 if (eir
& I915_ERROR_INSTRUCTION
) {
2043 pr_err("instruction error\n");
2044 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2045 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2046 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2047 if (INTEL_INFO(dev
)->gen
< 4) {
2048 u32 ipeir
= I915_READ(IPEIR
);
2050 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2051 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2052 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2053 I915_WRITE(IPEIR
, ipeir
);
2054 POSTING_READ(IPEIR
);
2056 u32 ipeir
= I915_READ(IPEIR_I965
);
2058 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2059 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2060 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2061 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2062 I915_WRITE(IPEIR_I965
, ipeir
);
2063 POSTING_READ(IPEIR_I965
);
2067 I915_WRITE(EIR
, eir
);
2069 eir
= I915_READ(EIR
);
2072 * some errors might have become stuck,
2075 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2076 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2077 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2082 * i915_handle_error - handle an error interrupt
2085 * Do some basic checking of regsiter state at error interrupt time and
2086 * dump it to the syslog. Also call i915_capture_error_state() to make
2087 * sure we get a record and make it available in debugfs. Fire a uevent
2088 * so userspace knows something bad happened (should trigger collection
2089 * of a ring dump etc.).
2091 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
2093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2094 struct intel_ring_buffer
*ring
;
2097 i915_capture_error_state(dev
);
2098 i915_report_and_clear_eir(dev
);
2101 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2102 &dev_priv
->gpu_error
.reset_counter
);
2105 * Wakeup waiting processes so that the reset work item
2106 * doesn't deadlock trying to grab various locks.
2108 for_each_ring(ring
, dev_priv
, i
)
2109 wake_up_all(&ring
->irq_queue
);
2112 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
2115 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2118 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2120 struct drm_i915_gem_object
*obj
;
2121 struct intel_unpin_work
*work
;
2122 unsigned long flags
;
2123 bool stall_detected
;
2125 /* Ignore early vblank irqs */
2126 if (intel_crtc
== NULL
)
2129 spin_lock_irqsave(&dev
->event_lock
, flags
);
2130 work
= intel_crtc
->unpin_work
;
2133 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2134 !work
->enable_stall_check
) {
2135 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2136 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2140 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2141 obj
= work
->pending_flip_obj
;
2142 if (INTEL_INFO(dev
)->gen
>= 4) {
2143 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2144 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2147 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2148 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
2149 crtc
->y
* crtc
->fb
->pitches
[0] +
2150 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2153 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2155 if (stall_detected
) {
2156 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2157 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2161 /* Called from drm generic code, passed 'crtc' which
2162 * we use as a pipe index
2164 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2166 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2167 unsigned long irqflags
;
2169 if (!i915_pipe_enabled(dev
, pipe
))
2172 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2173 if (INTEL_INFO(dev
)->gen
>= 4)
2174 i915_enable_pipestat(dev_priv
, pipe
,
2175 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2177 i915_enable_pipestat(dev_priv
, pipe
,
2178 PIPE_VBLANK_INTERRUPT_ENABLE
);
2180 /* maintain vblank delivery even in deep C-states */
2181 if (dev_priv
->info
->gen
== 3)
2182 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2183 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2188 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2190 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2191 unsigned long irqflags
;
2193 if (!i915_pipe_enabled(dev
, pipe
))
2196 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2197 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
2198 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2199 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2204 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
2206 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2207 unsigned long irqflags
;
2209 if (!i915_pipe_enabled(dev
, pipe
))
2212 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2213 ironlake_enable_display_irq(dev_priv
,
2214 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
2215 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2220 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2222 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2223 unsigned long irqflags
;
2226 if (!i915_pipe_enabled(dev
, pipe
))
2229 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2230 imr
= I915_READ(VLV_IMR
);
2232 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2234 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2235 I915_WRITE(VLV_IMR
, imr
);
2236 i915_enable_pipestat(dev_priv
, pipe
,
2237 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2238 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2243 /* Called from drm generic code, passed 'crtc' which
2244 * we use as a pipe index
2246 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2248 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2249 unsigned long irqflags
;
2251 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2252 if (dev_priv
->info
->gen
== 3)
2253 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2255 i915_disable_pipestat(dev_priv
, pipe
,
2256 PIPE_VBLANK_INTERRUPT_ENABLE
|
2257 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2258 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2261 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2263 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2264 unsigned long irqflags
;
2266 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2267 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
2268 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2269 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2272 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
2274 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2275 unsigned long irqflags
;
2277 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2278 ironlake_disable_display_irq(dev_priv
,
2279 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
2280 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2283 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2285 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2286 unsigned long irqflags
;
2289 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2290 i915_disable_pipestat(dev_priv
, pipe
,
2291 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2292 imr
= I915_READ(VLV_IMR
);
2294 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2296 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2297 I915_WRITE(VLV_IMR
, imr
);
2298 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2302 ring_last_seqno(struct intel_ring_buffer
*ring
)
2304 return list_entry(ring
->request_list
.prev
,
2305 struct drm_i915_gem_request
, list
)->seqno
;
2309 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2311 return (list_empty(&ring
->request_list
) ||
2312 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2315 static struct intel_ring_buffer
*
2316 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2318 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2319 u32 cmd
, ipehr
, acthd
, acthd_min
;
2321 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2322 if ((ipehr
& ~(0x3 << 16)) !=
2323 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2326 /* ACTHD is likely pointing to the dword after the actual command,
2327 * so scan backwards until we find the MBOX.
2329 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2330 acthd_min
= max((int)acthd
- 3 * 4, 0);
2332 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2337 if (acthd
< acthd_min
)
2341 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2342 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2345 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2347 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2348 struct intel_ring_buffer
*signaller
;
2351 ring
->hangcheck
.deadlock
= true;
2353 signaller
= semaphore_waits_for(ring
, &seqno
);
2354 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2357 /* cursory check for an unkickable deadlock */
2358 ctl
= I915_READ_CTL(signaller
);
2359 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2362 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2365 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2367 struct intel_ring_buffer
*ring
;
2370 for_each_ring(ring
, dev_priv
, i
)
2371 ring
->hangcheck
.deadlock
= false;
2374 static enum intel_ring_hangcheck_action
2375 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2377 struct drm_device
*dev
= ring
->dev
;
2378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2381 if (ring
->hangcheck
.acthd
!= acthd
)
2387 /* Is the chip hanging on a WAIT_FOR_EVENT?
2388 * If so we can simply poke the RB_WAIT bit
2389 * and break the hang. This should work on
2390 * all but the second generation chipsets.
2392 tmp
= I915_READ_CTL(ring
);
2393 if (tmp
& RING_WAIT
) {
2394 DRM_ERROR("Kicking stuck wait on %s\n",
2396 I915_WRITE_CTL(ring
, tmp
);
2400 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2401 switch (semaphore_passed(ring
)) {
2405 DRM_ERROR("Kicking stuck semaphore on %s\n",
2407 I915_WRITE_CTL(ring
, tmp
);
2418 * This is called when the chip hasn't reported back with completed
2419 * batchbuffers in a long time. We keep track per ring seqno progress and
2420 * if there are no progress, hangcheck score for that ring is increased.
2421 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2422 * we kick the ring. If we see no progress on three subsequent calls
2423 * we assume chip is wedged and try to fix it by resetting the chip.
2425 void i915_hangcheck_elapsed(unsigned long data
)
2427 struct drm_device
*dev
= (struct drm_device
*)data
;
2428 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2429 struct intel_ring_buffer
*ring
;
2431 int busy_count
= 0, rings_hung
= 0;
2432 bool stuck
[I915_NUM_RINGS
] = { 0 };
2438 if (!i915_enable_hangcheck
)
2441 for_each_ring(ring
, dev_priv
, i
) {
2445 semaphore_clear_deadlocks(dev_priv
);
2447 seqno
= ring
->get_seqno(ring
, false);
2448 acthd
= intel_ring_get_active_head(ring
);
2450 if (ring
->hangcheck
.seqno
== seqno
) {
2451 if (ring_idle(ring
, seqno
)) {
2452 if (waitqueue_active(&ring
->irq_queue
)) {
2453 /* Issue a wake-up to catch stuck h/w. */
2454 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2456 wake_up_all(&ring
->irq_queue
);
2457 ring
->hangcheck
.score
+= HUNG
;
2463 /* We always increment the hangcheck score
2464 * if the ring is busy and still processing
2465 * the same request, so that no single request
2466 * can run indefinitely (such as a chain of
2467 * batches). The only time we do not increment
2468 * the hangcheck score on this ring, if this
2469 * ring is in a legitimate wait for another
2470 * ring. In that case the waiting ring is a
2471 * victim and we want to be sure we catch the
2472 * right culprit. Then every time we do kick
2473 * the ring, add a small increment to the
2474 * score so that we can catch a batch that is
2475 * being repeatedly kicked and so responsible
2476 * for stalling the machine.
2478 ring
->hangcheck
.action
= ring_stuck(ring
,
2481 switch (ring
->hangcheck
.action
) {
2496 ring
->hangcheck
.score
+= score
;
2499 /* Gradually reduce the count so that we catch DoS
2500 * attempts across multiple batches.
2502 if (ring
->hangcheck
.score
> 0)
2503 ring
->hangcheck
.score
--;
2506 ring
->hangcheck
.seqno
= seqno
;
2507 ring
->hangcheck
.acthd
= acthd
;
2511 for_each_ring(ring
, dev_priv
, i
) {
2512 if (ring
->hangcheck
.score
> FIRE
) {
2513 DRM_ERROR("%s on %s\n",
2514 stuck
[i
] ? "stuck" : "no progress",
2521 return i915_handle_error(dev
, true);
2524 /* Reset timer case chip hangs without another request
2526 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2527 round_jiffies_up(jiffies
+
2528 DRM_I915_HANGCHECK_JIFFIES
));
2531 static void ibx_irq_preinstall(struct drm_device
*dev
)
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2535 if (HAS_PCH_NOP(dev
))
2538 /* south display irq */
2539 I915_WRITE(SDEIMR
, 0xffffffff);
2541 * SDEIER is also touched by the interrupt handler to work around missed
2542 * PCH interrupts. Hence we can't update it after the interrupt handler
2543 * is enabled - instead we unconditionally enable all PCH interrupt
2544 * sources here, but then only unmask them as needed with SDEIMR.
2546 I915_WRITE(SDEIER
, 0xffffffff);
2547 POSTING_READ(SDEIER
);
2552 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2554 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2556 atomic_set(&dev_priv
->irq_received
, 0);
2558 I915_WRITE(HWSTAM
, 0xeffe);
2560 /* XXX hotplug from PCH */
2562 I915_WRITE(DEIMR
, 0xffffffff);
2563 I915_WRITE(DEIER
, 0x0);
2564 POSTING_READ(DEIER
);
2567 I915_WRITE(GTIMR
, 0xffffffff);
2568 I915_WRITE(GTIER
, 0x0);
2569 POSTING_READ(GTIER
);
2571 ibx_irq_preinstall(dev
);
2574 static void ivybridge_irq_preinstall(struct drm_device
*dev
)
2576 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2578 atomic_set(&dev_priv
->irq_received
, 0);
2580 I915_WRITE(HWSTAM
, 0xeffe);
2582 /* XXX hotplug from PCH */
2584 I915_WRITE(DEIMR
, 0xffffffff);
2585 I915_WRITE(DEIER
, 0x0);
2586 POSTING_READ(DEIER
);
2589 I915_WRITE(GTIMR
, 0xffffffff);
2590 I915_WRITE(GTIER
, 0x0);
2591 POSTING_READ(GTIER
);
2593 /* Power management */
2594 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2595 I915_WRITE(GEN6_PMIER
, 0x0);
2596 POSTING_READ(GEN6_PMIER
);
2598 ibx_irq_preinstall(dev
);
2601 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2603 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2606 atomic_set(&dev_priv
->irq_received
, 0);
2609 I915_WRITE(VLV_IMR
, 0);
2610 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2611 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2612 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2615 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2616 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2617 I915_WRITE(GTIMR
, 0xffffffff);
2618 I915_WRITE(GTIER
, 0x0);
2619 POSTING_READ(GTIER
);
2621 I915_WRITE(DPINVGTT
, 0xff);
2623 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2624 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2626 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2627 I915_WRITE(VLV_IIR
, 0xffffffff);
2628 I915_WRITE(VLV_IMR
, 0xffffffff);
2629 I915_WRITE(VLV_IER
, 0x0);
2630 POSTING_READ(VLV_IER
);
2633 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2635 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2636 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2637 struct intel_encoder
*intel_encoder
;
2638 u32 mask
= ~I915_READ(SDEIMR
);
2641 if (HAS_PCH_IBX(dev
)) {
2642 mask
&= ~SDE_HOTPLUG_MASK
;
2643 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2644 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2645 mask
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2647 mask
&= ~SDE_HOTPLUG_MASK_CPT
;
2648 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2649 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2650 mask
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2653 I915_WRITE(SDEIMR
, ~mask
);
2656 * Enable digital hotplug on the PCH, and configure the DP short pulse
2657 * duration to 2ms (which is the minimum in the Display Port spec)
2659 * This register is the same on all known PCH chips.
2661 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2662 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2663 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2664 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2665 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2666 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2669 static void ibx_irq_postinstall(struct drm_device
*dev
)
2671 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2674 if (HAS_PCH_NOP(dev
))
2677 if (HAS_PCH_IBX(dev
)) {
2678 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2679 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2681 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2683 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2686 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2687 I915_WRITE(SDEIMR
, ~mask
);
2690 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2692 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2693 /* enable kind of interrupts always enabled */
2694 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2695 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2696 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2697 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2700 dev_priv
->irq_mask
= ~display_mask
;
2702 /* should always can generate irq */
2703 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2704 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2705 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
2706 POSTING_READ(DEIER
);
2708 dev_priv
->gt_irq_mask
= ~0;
2710 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2711 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2713 gt_irqs
= GT_RENDER_USER_INTERRUPT
;
2716 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2718 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2719 ILK_BSD_USER_INTERRUPT
;
2721 I915_WRITE(GTIER
, gt_irqs
);
2722 POSTING_READ(GTIER
);
2724 ibx_irq_postinstall(dev
);
2726 if (IS_IRONLAKE_M(dev
)) {
2727 /* Clear & enable PCU event interrupts */
2728 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2729 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
2730 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2736 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2738 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2739 /* enable kind of interrupts always enabled */
2741 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2742 DE_PLANEC_FLIP_DONE_IVB
|
2743 DE_PLANEB_FLIP_DONE_IVB
|
2744 DE_PLANEA_FLIP_DONE_IVB
|
2745 DE_AUX_CHANNEL_A_IVB
|
2747 u32 pm_irqs
= GEN6_PM_RPS_EVENTS
;
2750 dev_priv
->irq_mask
= ~display_mask
;
2752 /* should always can generate irq */
2753 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2754 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2755 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2758 DE_PIPEC_VBLANK_IVB
|
2759 DE_PIPEB_VBLANK_IVB
|
2760 DE_PIPEA_VBLANK_IVB
);
2761 POSTING_READ(DEIER
);
2763 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2765 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2766 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2768 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2769 GT_BLT_USER_INTERRUPT
| GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2770 I915_WRITE(GTIER
, gt_irqs
);
2771 POSTING_READ(GTIER
);
2773 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2775 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
|
2776 PM_VEBOX_CS_ERROR_INTERRUPT
;
2778 /* Our enable/disable rps functions may touch these registers so
2779 * make sure to set a known state for only the non-RPS bits.
2780 * The RMW is extra paranoia since this should be called after being set
2781 * to a known state in preinstall.
2783 I915_WRITE(GEN6_PMIMR
,
2784 (I915_READ(GEN6_PMIMR
) | ~GEN6_PM_RPS_EVENTS
) & ~pm_irqs
);
2785 I915_WRITE(GEN6_PMIER
,
2786 (I915_READ(GEN6_PMIER
) & GEN6_PM_RPS_EVENTS
) | pm_irqs
);
2787 POSTING_READ(GEN6_PMIER
);
2789 ibx_irq_postinstall(dev
);
2794 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2796 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2799 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2801 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2802 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2803 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2804 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2805 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2808 *Leave vblank interrupts masked initially. enable/disable will
2809 * toggle them based on usage.
2811 dev_priv
->irq_mask
= (~enable_mask
) |
2812 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2813 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2815 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2816 POSTING_READ(PORT_HOTPLUG_EN
);
2818 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2819 I915_WRITE(VLV_IER
, enable_mask
);
2820 I915_WRITE(VLV_IIR
, 0xffffffff);
2821 I915_WRITE(PIPESTAT(0), 0xffff);
2822 I915_WRITE(PIPESTAT(1), 0xffff);
2823 POSTING_READ(VLV_IER
);
2825 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2826 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2827 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2829 I915_WRITE(VLV_IIR
, 0xffffffff);
2830 I915_WRITE(VLV_IIR
, 0xffffffff);
2832 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2833 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2835 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2836 GT_BLT_USER_INTERRUPT
;
2837 I915_WRITE(GTIER
, gt_irqs
);
2838 POSTING_READ(GTIER
);
2840 /* ack & enable invalid PTE error interrupts */
2841 #if 0 /* FIXME: add support to irq handler for checking these bits */
2842 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2843 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2846 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2851 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2853 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2859 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2862 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2864 I915_WRITE(HWSTAM
, 0xffffffff);
2865 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2866 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2868 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2869 I915_WRITE(VLV_IIR
, 0xffffffff);
2870 I915_WRITE(VLV_IMR
, 0xffffffff);
2871 I915_WRITE(VLV_IER
, 0x0);
2872 POSTING_READ(VLV_IER
);
2875 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2877 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2882 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2884 I915_WRITE(HWSTAM
, 0xffffffff);
2886 I915_WRITE(DEIMR
, 0xffffffff);
2887 I915_WRITE(DEIER
, 0x0);
2888 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2890 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2892 I915_WRITE(GTIMR
, 0xffffffff);
2893 I915_WRITE(GTIER
, 0x0);
2894 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2896 if (HAS_PCH_NOP(dev
))
2899 I915_WRITE(SDEIMR
, 0xffffffff);
2900 I915_WRITE(SDEIER
, 0x0);
2901 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2902 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2903 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2906 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2908 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2911 atomic_set(&dev_priv
->irq_received
, 0);
2914 I915_WRITE(PIPESTAT(pipe
), 0);
2915 I915_WRITE16(IMR
, 0xffff);
2916 I915_WRITE16(IER
, 0x0);
2917 POSTING_READ16(IER
);
2920 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2922 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2925 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2927 /* Unmask the interrupts that we always want on. */
2928 dev_priv
->irq_mask
=
2929 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2930 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2931 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2932 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2933 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2934 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2937 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2938 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2939 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2940 I915_USER_INTERRUPT
);
2941 POSTING_READ16(IER
);
2947 * Returns true when a page flip has completed.
2949 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2952 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2953 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2955 if (!drm_handle_vblank(dev
, pipe
))
2958 if ((iir
& flip_pending
) == 0)
2961 intel_prepare_page_flip(dev
, pipe
);
2963 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2964 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2965 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2966 * the flip is completed (no longer pending). Since this doesn't raise
2967 * an interrupt per se, we watch for the change at vblank.
2969 if (I915_READ16(ISR
) & flip_pending
)
2972 intel_finish_page_flip(dev
, pipe
);
2977 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2979 struct drm_device
*dev
= (struct drm_device
*) arg
;
2980 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2983 unsigned long irqflags
;
2987 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2988 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2990 atomic_inc(&dev_priv
->irq_received
);
2992 iir
= I915_READ16(IIR
);
2996 while (iir
& ~flip_mask
) {
2997 /* Can't rely on pipestat interrupt bit in iir as it might
2998 * have been cleared after the pipestat interrupt was received.
2999 * It doesn't set the bit in iir again, but it still produces
3000 * interrupts (for non-MSI).
3002 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3003 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3004 i915_handle_error(dev
, false);
3006 for_each_pipe(pipe
) {
3007 int reg
= PIPESTAT(pipe
);
3008 pipe_stats
[pipe
] = I915_READ(reg
);
3011 * Clear the PIPE*STAT regs before the IIR
3013 if (pipe_stats
[pipe
] & 0x8000ffff) {
3014 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3015 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3017 I915_WRITE(reg
, pipe_stats
[pipe
]);
3021 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3023 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3024 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3026 i915_update_dri1_breadcrumb(dev
);
3028 if (iir
& I915_USER_INTERRUPT
)
3029 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3031 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3032 i8xx_handle_vblank(dev
, 0, iir
))
3033 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
3035 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3036 i8xx_handle_vblank(dev
, 1, iir
))
3037 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
3045 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3047 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3050 for_each_pipe(pipe
) {
3051 /* Clear enable bits; then clear status bits */
3052 I915_WRITE(PIPESTAT(pipe
), 0);
3053 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3055 I915_WRITE16(IMR
, 0xffff);
3056 I915_WRITE16(IER
, 0x0);
3057 I915_WRITE16(IIR
, I915_READ16(IIR
));
3060 static void i915_irq_preinstall(struct drm_device
* dev
)
3062 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3065 atomic_set(&dev_priv
->irq_received
, 0);
3067 if (I915_HAS_HOTPLUG(dev
)) {
3068 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3069 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3072 I915_WRITE16(HWSTAM
, 0xeffe);
3074 I915_WRITE(PIPESTAT(pipe
), 0);
3075 I915_WRITE(IMR
, 0xffffffff);
3076 I915_WRITE(IER
, 0x0);
3080 static int i915_irq_postinstall(struct drm_device
*dev
)
3082 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3085 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3087 /* Unmask the interrupts that we always want on. */
3088 dev_priv
->irq_mask
=
3089 ~(I915_ASLE_INTERRUPT
|
3090 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3091 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3092 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3093 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3094 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3097 I915_ASLE_INTERRUPT
|
3098 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3099 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3100 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3101 I915_USER_INTERRUPT
;
3103 if (I915_HAS_HOTPLUG(dev
)) {
3104 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3105 POSTING_READ(PORT_HOTPLUG_EN
);
3107 /* Enable in IER... */
3108 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3109 /* and unmask in IMR */
3110 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3113 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3114 I915_WRITE(IER
, enable_mask
);
3117 i915_enable_asle_pipestat(dev
);
3123 * Returns true when a page flip has completed.
3125 static bool i915_handle_vblank(struct drm_device
*dev
,
3126 int plane
, int pipe
, u32 iir
)
3128 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3129 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3131 if (!drm_handle_vblank(dev
, pipe
))
3134 if ((iir
& flip_pending
) == 0)
3137 intel_prepare_page_flip(dev
, plane
);
3139 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3140 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3141 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3142 * the flip is completed (no longer pending). Since this doesn't raise
3143 * an interrupt per se, we watch for the change at vblank.
3145 if (I915_READ(ISR
) & flip_pending
)
3148 intel_finish_page_flip(dev
, pipe
);
3153 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3155 struct drm_device
*dev
= (struct drm_device
*) arg
;
3156 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3157 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3158 unsigned long irqflags
;
3160 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3161 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3162 int pipe
, ret
= IRQ_NONE
;
3164 atomic_inc(&dev_priv
->irq_received
);
3166 iir
= I915_READ(IIR
);
3168 bool irq_received
= (iir
& ~flip_mask
) != 0;
3169 bool blc_event
= false;
3171 /* Can't rely on pipestat interrupt bit in iir as it might
3172 * have been cleared after the pipestat interrupt was received.
3173 * It doesn't set the bit in iir again, but it still produces
3174 * interrupts (for non-MSI).
3176 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3177 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3178 i915_handle_error(dev
, false);
3180 for_each_pipe(pipe
) {
3181 int reg
= PIPESTAT(pipe
);
3182 pipe_stats
[pipe
] = I915_READ(reg
);
3184 /* Clear the PIPE*STAT regs before the IIR */
3185 if (pipe_stats
[pipe
] & 0x8000ffff) {
3186 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3187 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3189 I915_WRITE(reg
, pipe_stats
[pipe
]);
3190 irq_received
= true;
3193 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3198 /* Consume port. Then clear IIR or we'll miss events */
3199 if ((I915_HAS_HOTPLUG(dev
)) &&
3200 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3201 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3202 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3204 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3206 if (hotplug_trigger
) {
3207 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
, hpd_status_i915
))
3208 i915_hpd_irq_setup(dev
);
3209 queue_work(dev_priv
->wq
,
3210 &dev_priv
->hotplug_work
);
3212 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3213 POSTING_READ(PORT_HOTPLUG_STAT
);
3216 I915_WRITE(IIR
, iir
& ~flip_mask
);
3217 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3219 if (iir
& I915_USER_INTERRUPT
)
3220 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3222 for_each_pipe(pipe
) {
3227 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3228 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3229 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3231 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3235 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3236 intel_opregion_asle_intr(dev
);
3238 /* With MSI, interrupts are only generated when iir
3239 * transitions from zero to nonzero. If another bit got
3240 * set while we were handling the existing iir bits, then
3241 * we would never get another interrupt.
3243 * This is fine on non-MSI as well, as if we hit this path
3244 * we avoid exiting the interrupt handler only to generate
3247 * Note that for MSI this could cause a stray interrupt report
3248 * if an interrupt landed in the time between writing IIR and
3249 * the posting read. This should be rare enough to never
3250 * trigger the 99% of 100,000 interrupts test for disabling
3255 } while (iir
& ~flip_mask
);
3257 i915_update_dri1_breadcrumb(dev
);
3262 static void i915_irq_uninstall(struct drm_device
* dev
)
3264 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3267 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3269 if (I915_HAS_HOTPLUG(dev
)) {
3270 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3271 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3274 I915_WRITE16(HWSTAM
, 0xffff);
3275 for_each_pipe(pipe
) {
3276 /* Clear enable bits; then clear status bits */
3277 I915_WRITE(PIPESTAT(pipe
), 0);
3278 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3280 I915_WRITE(IMR
, 0xffffffff);
3281 I915_WRITE(IER
, 0x0);
3283 I915_WRITE(IIR
, I915_READ(IIR
));
3286 static void i965_irq_preinstall(struct drm_device
* dev
)
3288 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3291 atomic_set(&dev_priv
->irq_received
, 0);
3293 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3294 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3296 I915_WRITE(HWSTAM
, 0xeffe);
3298 I915_WRITE(PIPESTAT(pipe
), 0);
3299 I915_WRITE(IMR
, 0xffffffff);
3300 I915_WRITE(IER
, 0x0);
3304 static int i965_irq_postinstall(struct drm_device
*dev
)
3306 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3310 /* Unmask the interrupts that we always want on. */
3311 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3312 I915_DISPLAY_PORT_INTERRUPT
|
3313 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3314 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3315 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3316 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3317 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3319 enable_mask
= ~dev_priv
->irq_mask
;
3320 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3321 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3322 enable_mask
|= I915_USER_INTERRUPT
;
3325 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3327 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3330 * Enable some error detection, note the instruction error mask
3331 * bit is reserved, so we leave it masked.
3334 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3335 GM45_ERROR_MEM_PRIV
|
3336 GM45_ERROR_CP_PRIV
|
3337 I915_ERROR_MEMORY_REFRESH
);
3339 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3340 I915_ERROR_MEMORY_REFRESH
);
3342 I915_WRITE(EMR
, error_mask
);
3344 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3345 I915_WRITE(IER
, enable_mask
);
3348 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3349 POSTING_READ(PORT_HOTPLUG_EN
);
3351 i915_enable_asle_pipestat(dev
);
3356 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3358 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3359 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3360 struct intel_encoder
*intel_encoder
;
3363 if (I915_HAS_HOTPLUG(dev
)) {
3364 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3365 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3366 /* Note HDMI and DP share hotplug bits */
3367 /* enable bits are the same for all generations */
3368 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3369 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3370 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3371 /* Programming the CRT detection parameters tends
3372 to generate a spurious hotplug event about three
3373 seconds later. So just do it once.
3376 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3377 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3378 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3380 /* Ignore TV since it's buggy */
3381 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3385 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3387 struct drm_device
*dev
= (struct drm_device
*) arg
;
3388 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3390 u32 pipe_stats
[I915_MAX_PIPES
];
3391 unsigned long irqflags
;
3393 int ret
= IRQ_NONE
, pipe
;
3395 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3396 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3398 atomic_inc(&dev_priv
->irq_received
);
3400 iir
= I915_READ(IIR
);
3403 bool blc_event
= false;
3405 irq_received
= (iir
& ~flip_mask
) != 0;
3407 /* Can't rely on pipestat interrupt bit in iir as it might
3408 * have been cleared after the pipestat interrupt was received.
3409 * It doesn't set the bit in iir again, but it still produces
3410 * interrupts (for non-MSI).
3412 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3413 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3414 i915_handle_error(dev
, false);
3416 for_each_pipe(pipe
) {
3417 int reg
= PIPESTAT(pipe
);
3418 pipe_stats
[pipe
] = I915_READ(reg
);
3421 * Clear the PIPE*STAT regs before the IIR
3423 if (pipe_stats
[pipe
] & 0x8000ffff) {
3424 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3425 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3427 I915_WRITE(reg
, pipe_stats
[pipe
]);
3431 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3438 /* Consume port. Then clear IIR or we'll miss events */
3439 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3440 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3441 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3442 HOTPLUG_INT_STATUS_G4X
:
3443 HOTPLUG_INT_STATUS_I915
);
3445 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3447 if (hotplug_trigger
) {
3448 if (hotplug_irq_storm_detect(dev
, hotplug_trigger
,
3449 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
))
3450 i915_hpd_irq_setup(dev
);
3451 queue_work(dev_priv
->wq
,
3452 &dev_priv
->hotplug_work
);
3454 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3455 I915_READ(PORT_HOTPLUG_STAT
);
3458 I915_WRITE(IIR
, iir
& ~flip_mask
);
3459 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3461 if (iir
& I915_USER_INTERRUPT
)
3462 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3463 if (iir
& I915_BSD_USER_INTERRUPT
)
3464 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3466 for_each_pipe(pipe
) {
3467 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3468 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3469 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3471 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3476 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3477 intel_opregion_asle_intr(dev
);
3479 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3480 gmbus_irq_handler(dev
);
3482 /* With MSI, interrupts are only generated when iir
3483 * transitions from zero to nonzero. If another bit got
3484 * set while we were handling the existing iir bits, then
3485 * we would never get another interrupt.
3487 * This is fine on non-MSI as well, as if we hit this path
3488 * we avoid exiting the interrupt handler only to generate
3491 * Note that for MSI this could cause a stray interrupt report
3492 * if an interrupt landed in the time between writing IIR and
3493 * the posting read. This should be rare enough to never
3494 * trigger the 99% of 100,000 interrupts test for disabling
3500 i915_update_dri1_breadcrumb(dev
);
3505 static void i965_irq_uninstall(struct drm_device
* dev
)
3507 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3513 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3515 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3516 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3518 I915_WRITE(HWSTAM
, 0xffffffff);
3520 I915_WRITE(PIPESTAT(pipe
), 0);
3521 I915_WRITE(IMR
, 0xffffffff);
3522 I915_WRITE(IER
, 0x0);
3525 I915_WRITE(PIPESTAT(pipe
),
3526 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3527 I915_WRITE(IIR
, I915_READ(IIR
));
3530 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3532 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3533 struct drm_device
*dev
= dev_priv
->dev
;
3534 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3535 unsigned long irqflags
;
3538 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3539 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3540 struct drm_connector
*connector
;
3542 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3545 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3547 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3548 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3550 if (intel_connector
->encoder
->hpd_pin
== i
) {
3551 if (connector
->polled
!= intel_connector
->polled
)
3552 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3553 drm_get_connector_name(connector
));
3554 connector
->polled
= intel_connector
->polled
;
3555 if (!connector
->polled
)
3556 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3560 if (dev_priv
->display
.hpd_irq_setup
)
3561 dev_priv
->display
.hpd_irq_setup(dev
);
3562 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3565 void intel_irq_init(struct drm_device
*dev
)
3567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3569 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3570 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3571 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3572 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3574 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3575 i915_hangcheck_elapsed
,
3576 (unsigned long) dev
);
3577 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3578 (unsigned long) dev_priv
);
3580 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3582 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3583 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3584 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3585 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3586 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3589 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3590 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3592 dev
->driver
->get_vblank_timestamp
= NULL
;
3593 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3595 if (IS_VALLEYVIEW(dev
)) {
3596 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3597 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3598 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3599 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3600 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3601 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3602 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3603 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3604 /* Share uninstall handlers with ILK/SNB */
3605 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3606 dev
->driver
->irq_preinstall
= ivybridge_irq_preinstall
;
3607 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3608 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3609 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3610 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3611 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3612 } else if (HAS_PCH_SPLIT(dev
)) {
3613 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3614 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3615 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3616 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3617 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3618 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3619 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3621 if (INTEL_INFO(dev
)->gen
== 2) {
3622 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3623 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3624 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3625 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3626 } else if (INTEL_INFO(dev
)->gen
== 3) {
3627 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3628 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3629 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3630 dev
->driver
->irq_handler
= i915_irq_handler
;
3631 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3633 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3634 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3635 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3636 dev
->driver
->irq_handler
= i965_irq_handler
;
3637 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3639 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3640 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3644 void intel_hpd_init(struct drm_device
*dev
)
3646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3647 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3648 struct drm_connector
*connector
;
3651 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3652 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3653 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3655 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3656 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3657 connector
->polled
= intel_connector
->polled
;
3658 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3659 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3661 if (dev_priv
->display
.hpd_irq_setup
)
3662 dev_priv
->display
.hpd_irq_setup(dev
);