1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include "intel_drv.h"
35 #define MAX_NOPID ((u32)~0)
38 * Interrupts that are always left unmasked.
40 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
41 * we leave them always unmasked in IMR and then control enabling them through
44 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
45 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
46 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
48 /** Interrupts that we mask and unmask at runtime. */
49 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
51 /** These are all of the interrupts used by the driver */
52 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
53 I915_INTERRUPT_ENABLE_VAR)
55 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
56 PIPE_VBLANK_INTERRUPT_STATUS)
58 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
59 PIPE_VBLANK_INTERRUPT_ENABLE)
61 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
62 DRM_I915_VBLANK_PIPE_B)
65 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
67 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
68 dev_priv
->irq_mask_reg
&= ~mask
;
69 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
70 (void) I915_READ(IMR
);
75 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
77 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
78 dev_priv
->irq_mask_reg
|= mask
;
79 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
80 (void) I915_READ(IMR
);
85 i915_pipestat(int pipe
)
95 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
97 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
98 u32 reg
= i915_pipestat(pipe
);
100 dev_priv
->pipestat
[pipe
] |= mask
;
101 /* Enable the interrupt, clear any pending status */
102 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
103 (void) I915_READ(reg
);
108 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
110 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
111 u32 reg
= i915_pipestat(pipe
);
113 dev_priv
->pipestat
[pipe
] &= ~mask
;
114 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
115 (void) I915_READ(reg
);
120 * i915_pipe_enabled - check if a pipe is enabled
122 * @pipe: pipe to check
124 * Reading certain registers when the pipe is disabled can hang the chip.
125 * Use this routine to make sure the PLL is running and the pipe is active
126 * before reading such registers if unsure.
129 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
131 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
132 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
134 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
140 /* Called from drm generic code, passed a 'crtc', which
141 * we use as a pipe index
143 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
145 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
146 unsigned long high_frame
;
147 unsigned long low_frame
;
148 u32 high1
, high2
, low
, count
;
150 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
151 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
153 if (!i915_pipe_enabled(dev
, pipe
)) {
154 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
159 * High & low register fields aren't synchronized, so make sure
160 * we get a low value that's stable across two reads of the high
164 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
165 PIPE_FRAME_HIGH_SHIFT
);
166 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
167 PIPE_FRAME_LOW_SHIFT
);
168 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
169 PIPE_FRAME_HIGH_SHIFT
);
170 } while (high1
!= high2
);
172 count
= (high1
<< 8) | low
;
177 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
179 struct drm_device
*dev
= (struct drm_device
*) arg
;
180 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
181 struct drm_i915_master_private
*master_priv
;
183 u32 pipea_stats
, pipeb_stats
;
187 unsigned long irqflags
;
191 atomic_inc(&dev_priv
->irq_received
);
193 iir
= I915_READ(IIR
);
196 vblank_status
= I915_START_VBLANK_INTERRUPT_STATUS
;
197 vblank_enable
= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
199 vblank_status
= I915_VBLANK_INTERRUPT_STATUS
;
200 vblank_enable
= I915_VBLANK_INTERRUPT_ENABLE
;
204 irq_received
= iir
!= 0;
206 /* Can't rely on pipestat interrupt bit in iir as it might
207 * have been cleared after the pipestat interrupt was received.
208 * It doesn't set the bit in iir again, but it still produces
209 * interrupts (for non-MSI).
211 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
212 pipea_stats
= I915_READ(PIPEASTAT
);
213 pipeb_stats
= I915_READ(PIPEBSTAT
);
216 * Clear the PIPE(A|B)STAT regs before the IIR
218 if (pipea_stats
& 0x8000ffff) {
219 I915_WRITE(PIPEASTAT
, pipea_stats
);
223 if (pipeb_stats
& 0x8000ffff) {
224 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
227 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
234 I915_WRITE(IIR
, iir
);
235 new_iir
= I915_READ(IIR
); /* Flush posted writes */
237 if (dev
->primary
->master
) {
238 master_priv
= dev
->primary
->master
->driver_priv
;
239 if (master_priv
->sarea_priv
)
240 master_priv
->sarea_priv
->last_dispatch
=
241 READ_BREADCRUMB(dev_priv
);
244 if (iir
& I915_USER_INTERRUPT
) {
245 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
246 DRM_WAKEUP(&dev_priv
->irq_queue
);
249 if (pipea_stats
& vblank_status
) {
251 drm_handle_vblank(dev
, 0);
254 if (pipeb_stats
& vblank_status
) {
256 drm_handle_vblank(dev
, 1);
259 if ((pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
) ||
260 (iir
& I915_ASLE_INTERRUPT
))
261 opregion_asle_intr(dev
);
263 /* With MSI, interrupts are only generated when iir
264 * transitions from zero to nonzero. If another bit got
265 * set while we were handling the existing iir bits, then
266 * we would never get another interrupt.
268 * This is fine on non-MSI as well, as if we hit this path
269 * we avoid exiting the interrupt handler only to generate
272 * Note that for MSI this could cause a stray interrupt report
273 * if an interrupt landed in the time between writing IIR and
274 * the posting read. This should be rare enough to never
275 * trigger the 99% of 100,000 interrupts test for disabling
284 static int i915_emit_irq(struct drm_device
* dev
)
286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
287 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
290 i915_kernel_lost_context(dev
);
295 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
296 dev_priv
->counter
= 1;
297 if (master_priv
->sarea_priv
)
298 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
301 OUT_RING(MI_STORE_DWORD_INDEX
);
302 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
303 OUT_RING(dev_priv
->counter
);
304 OUT_RING(MI_USER_INTERRUPT
);
307 return dev_priv
->counter
;
310 void i915_user_irq_get(struct drm_device
*dev
)
312 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
313 unsigned long irqflags
;
315 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
316 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1))
317 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
318 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
321 void i915_user_irq_put(struct drm_device
*dev
)
323 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
324 unsigned long irqflags
;
326 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
327 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
328 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0))
329 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
330 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
333 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
335 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
336 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
339 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
340 READ_BREADCRUMB(dev_priv
));
342 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
343 if (master_priv
->sarea_priv
)
344 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
348 if (master_priv
->sarea_priv
)
349 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
351 i915_user_irq_get(dev
);
352 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
353 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
354 i915_user_irq_put(dev
);
357 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
358 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
364 /* Needs the lock as it touches the ring.
366 int i915_irq_emit(struct drm_device
*dev
, void *data
,
367 struct drm_file
*file_priv
)
369 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
370 drm_i915_irq_emit_t
*emit
= data
;
373 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
376 DRM_ERROR("called with no initialization\n");
379 mutex_lock(&dev
->struct_mutex
);
380 result
= i915_emit_irq(dev
);
381 mutex_unlock(&dev
->struct_mutex
);
383 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
384 DRM_ERROR("copy_to_user\n");
391 /* Doesn't need the hardware lock.
393 int i915_irq_wait(struct drm_device
*dev
, void *data
,
394 struct drm_file
*file_priv
)
396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
397 drm_i915_irq_wait_t
*irqwait
= data
;
400 DRM_ERROR("called with no initialization\n");
404 return i915_wait_irq(dev
, irqwait
->irq_seq
);
407 /* Called from drm generic code, passed 'crtc' which
408 * we use as a pipe index
410 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
412 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
413 unsigned long irqflags
;
415 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
417 i915_enable_pipestat(dev_priv
, pipe
,
418 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
420 i915_enable_pipestat(dev_priv
, pipe
,
421 PIPE_VBLANK_INTERRUPT_ENABLE
);
422 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
426 /* Called from drm generic code, passed 'crtc' which
427 * we use as a pipe index
429 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
431 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
432 unsigned long irqflags
;
434 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
435 i915_disable_pipestat(dev_priv
, pipe
,
436 PIPE_VBLANK_INTERRUPT_ENABLE
|
437 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
438 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
441 void i915_enable_interrupt (struct drm_device
*dev
)
443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
444 opregion_enable_asle(dev
);
445 dev_priv
->irq_enabled
= 1;
449 /* Set the vblank monitor pipe
451 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
452 struct drm_file
*file_priv
)
454 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
457 DRM_ERROR("called with no initialization\n");
464 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
465 struct drm_file
*file_priv
)
467 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
468 drm_i915_vblank_pipe_t
*pipe
= data
;
471 DRM_ERROR("called with no initialization\n");
475 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
481 * Schedule buffer swap at given vertical blank.
483 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
484 struct drm_file
*file_priv
)
486 /* The delayed swap mechanism was fundamentally racy, and has been
487 * removed. The model was that the client requested a delayed flip/swap
488 * from the kernel, then waited for vblank before continuing to perform
489 * rendering. The problem was that the kernel might wake the client
490 * up before it dispatched the vblank swap (since the lock has to be
491 * held while touching the ringbuffer), in which case the client would
492 * clear and start the next frame before the swap occurred, and
493 * flicker would occur in addition to likely missing the vblank.
495 * In the absence of this ioctl, userland falls back to a correct path
496 * of waiting for a vblank, then dispatching the swap on its own.
497 * Context switching to userland and back is plenty fast enough for
498 * meeting the requirements of vblank swapping.
505 void i915_driver_irq_preinstall(struct drm_device
* dev
)
507 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
509 atomic_set(&dev_priv
->irq_received
, 0);
511 I915_WRITE(HWSTAM
, 0xeffe);
512 I915_WRITE(PIPEASTAT
, 0);
513 I915_WRITE(PIPEBSTAT
, 0);
514 I915_WRITE(IMR
, 0xffffffff);
515 I915_WRITE(IER
, 0x0);
516 (void) I915_READ(IER
);
519 int i915_driver_irq_postinstall(struct drm_device
*dev
)
521 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
523 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
525 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
527 /* Unmask the interrupts that we always want on. */
528 dev_priv
->irq_mask_reg
= ~I915_INTERRUPT_ENABLE_FIX
;
530 dev_priv
->pipestat
[0] = 0;
531 dev_priv
->pipestat
[1] = 0;
533 /* Disable pipe interrupt enables, clear pending pipe status */
534 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
535 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
536 /* Clear pending interrupt status */
537 I915_WRITE(IIR
, I915_READ(IIR
));
539 I915_WRITE(IER
, I915_INTERRUPT_ENABLE_MASK
);
540 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
541 (void) I915_READ(IER
);
543 opregion_enable_asle(dev
);
544 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
549 void i915_driver_irq_uninstall(struct drm_device
* dev
)
551 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
556 dev_priv
->vblank_pipe
= 0;
558 I915_WRITE(HWSTAM
, 0xffffffff);
559 I915_WRITE(PIPEASTAT
, 0);
560 I915_WRITE(PIPEBSTAT
, 0);
561 I915_WRITE(IMR
, 0xffffffff);
562 I915_WRITE(IER
, 0x0);
564 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
565 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
566 I915_WRITE(IIR
, I915_READ(IIR
));