1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
67 /* For display hotplug interrupt */
69 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
71 if ((dev_priv
->irq_mask
& mask
) != 0) {
72 dev_priv
->irq_mask
&= ~mask
;
73 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
79 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
81 if ((dev_priv
->irq_mask
& mask
) != mask
) {
82 dev_priv
->irq_mask
|= mask
;
83 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
89 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
91 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
92 u32 reg
= PIPESTAT(pipe
);
94 dev_priv
->pipestat
[pipe
] |= mask
;
95 /* Enable the interrupt, clear any pending status */
96 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
102 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
104 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
105 u32 reg
= PIPESTAT(pipe
);
107 dev_priv
->pipestat
[pipe
] &= ~mask
;
108 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
114 * intel_enable_asle - enable ASLE interrupt for OpRegion
116 void intel_enable_asle(struct drm_device
*dev
)
118 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
119 unsigned long irqflags
;
121 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
123 if (HAS_PCH_SPLIT(dev
))
124 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
126 i915_enable_pipestat(dev_priv
, 1,
127 PIPE_LEGACY_BLC_EVENT_ENABLE
);
128 if (INTEL_INFO(dev
)->gen
>= 4)
129 i915_enable_pipestat(dev_priv
, 0,
130 PIPE_LEGACY_BLC_EVENT_ENABLE
);
133 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
137 * i915_pipe_enabled - check if a pipe is enabled
139 * @pipe: pipe to check
141 * Reading certain registers when the pipe is disabled can hang the chip.
142 * Use this routine to make sure the PLL is running and the pipe is active
143 * before reading such registers if unsure.
146 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
148 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
149 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
152 /* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index
155 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
157 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
158 unsigned long high_frame
;
159 unsigned long low_frame
;
160 u32 high1
, high2
, low
;
162 if (!i915_pipe_enabled(dev
, pipe
)) {
163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
164 "pipe %c\n", pipe_name(pipe
));
168 high_frame
= PIPEFRAME(pipe
);
169 low_frame
= PIPEFRAMEPIXEL(pipe
);
172 * High & low register fields aren't synchronized, so make sure
173 * we get a low value that's stable across two reads of the high
177 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
178 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
179 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
180 } while (high1
!= high2
);
182 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
183 low
>>= PIPE_FRAME_LOW_SHIFT
;
184 return (high1
<< 8) | low
;
187 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
189 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
190 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
192 if (!i915_pipe_enabled(dev
, pipe
)) {
193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
194 "pipe %c\n", pipe_name(pipe
));
198 return I915_READ(reg
);
201 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
202 int *vpos
, int *hpos
)
204 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
205 u32 vbl
= 0, position
= 0;
206 int vbl_start
, vbl_end
, htotal
, vtotal
;
210 if (!i915_pipe_enabled(dev
, pipe
)) {
211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
212 "pipe %c\n", pipe_name(pipe
));
217 vtotal
= 1 + ((I915_READ(VTOTAL(pipe
)) >> 16) & 0x1fff);
219 if (INTEL_INFO(dev
)->gen
>= 4) {
220 /* No obvious pixelcount register. Only query vertical
221 * scanout position from Display scan line register.
223 position
= I915_READ(PIPEDSL(pipe
));
225 /* Decode into vertical scanout position. Don't have
226 * horizontal scanout position.
228 *vpos
= position
& 0x1fff;
231 /* Have access to pixelcount since start of frame.
232 * We can split this into vertical and horizontal
235 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
237 htotal
= 1 + ((I915_READ(HTOTAL(pipe
)) >> 16) & 0x1fff);
238 *vpos
= position
/ htotal
;
239 *hpos
= position
- (*vpos
* htotal
);
242 /* Query vblank area. */
243 vbl
= I915_READ(VBLANK(pipe
));
245 /* Test position against vblank region. */
246 vbl_start
= vbl
& 0x1fff;
247 vbl_end
= (vbl
>> 16) & 0x1fff;
249 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
252 /* Inside "upper part" of vblank area? Apply corrective offset: */
253 if (in_vbl
&& (*vpos
>= vbl_start
))
254 *vpos
= *vpos
- vtotal
;
256 /* Readouts valid? */
258 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
262 ret
|= DRM_SCANOUTPOS_INVBL
;
267 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
269 struct timeval
*vblank_time
,
272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
273 struct drm_crtc
*crtc
;
275 if (pipe
< 0 || pipe
>= dev_priv
->num_pipe
) {
276 DRM_ERROR("Invalid crtc %d\n", pipe
);
280 /* Get drm_crtc to timestamp: */
281 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
283 DRM_ERROR("Invalid crtc %d\n", pipe
);
287 if (!crtc
->enabled
) {
288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
292 /* Helper routine in DRM core does all the work: */
293 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
299 * Handle hotplug events outside the interrupt handler proper.
301 static void i915_hotplug_work_func(struct work_struct
*work
)
303 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
305 struct drm_device
*dev
= dev_priv
->dev
;
306 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
307 struct intel_encoder
*encoder
;
309 DRM_DEBUG_KMS("running encoder hotplug functions\n");
311 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
312 if (encoder
->hot_plug
)
313 encoder
->hot_plug(encoder
);
315 /* Just fire off a uevent and let userspace tell us what to do */
316 drm_helper_hpd_irq_event(dev
);
319 static void i915_handle_rps_change(struct drm_device
*dev
)
321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
322 u32 busy_up
, busy_down
, max_avg
, min_avg
;
323 u8 new_delay
= dev_priv
->cur_delay
;
325 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
326 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
327 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
328 max_avg
= I915_READ(RCBMAXAVG
);
329 min_avg
= I915_READ(RCBMINAVG
);
331 /* Handle RCS change request from hw */
332 if (busy_up
> max_avg
) {
333 if (dev_priv
->cur_delay
!= dev_priv
->max_delay
)
334 new_delay
= dev_priv
->cur_delay
- 1;
335 if (new_delay
< dev_priv
->max_delay
)
336 new_delay
= dev_priv
->max_delay
;
337 } else if (busy_down
< min_avg
) {
338 if (dev_priv
->cur_delay
!= dev_priv
->min_delay
)
339 new_delay
= dev_priv
->cur_delay
+ 1;
340 if (new_delay
> dev_priv
->min_delay
)
341 new_delay
= dev_priv
->min_delay
;
344 if (ironlake_set_drps(dev
, new_delay
))
345 dev_priv
->cur_delay
= new_delay
;
350 static void notify_ring(struct drm_device
*dev
,
351 struct intel_ring_buffer
*ring
)
353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
356 if (ring
->obj
== NULL
)
359 seqno
= ring
->get_seqno(ring
);
360 trace_i915_gem_request_complete(ring
, seqno
);
362 ring
->irq_seqno
= seqno
;
363 wake_up_all(&ring
->irq_queue
);
364 if (i915_enable_hangcheck
) {
365 dev_priv
->hangcheck_count
= 0;
366 mod_timer(&dev_priv
->hangcheck_timer
,
368 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
372 static void gen6_pm_rps_work(struct work_struct
*work
)
374 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
376 u8 new_delay
= dev_priv
->cur_delay
;
379 spin_lock_irq(&dev_priv
->rps_lock
);
380 pm_iir
= dev_priv
->pm_iir
;
381 dev_priv
->pm_iir
= 0;
382 pm_imr
= I915_READ(GEN6_PMIMR
);
383 spin_unlock_irq(&dev_priv
->rps_lock
);
388 mutex_lock(&dev_priv
->dev
->struct_mutex
);
389 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
390 if (dev_priv
->cur_delay
!= dev_priv
->max_delay
)
391 new_delay
= dev_priv
->cur_delay
+ 1;
392 if (new_delay
> dev_priv
->max_delay
)
393 new_delay
= dev_priv
->max_delay
;
394 } else if (pm_iir
& (GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
)) {
395 gen6_gt_force_wake_get(dev_priv
);
396 if (dev_priv
->cur_delay
!= dev_priv
->min_delay
)
397 new_delay
= dev_priv
->cur_delay
- 1;
398 if (new_delay
< dev_priv
->min_delay
) {
399 new_delay
= dev_priv
->min_delay
;
400 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
401 I915_READ(GEN6_RP_INTERRUPT_LIMITS
) |
402 ((new_delay
<< 16) & 0x3f0000));
404 /* Make sure we continue to get down interrupts
405 * until we hit the minimum frequency */
406 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
407 I915_READ(GEN6_RP_INTERRUPT_LIMITS
) & ~0x3f0000);
409 gen6_gt_force_wake_put(dev_priv
);
412 gen6_set_rps(dev_priv
->dev
, new_delay
);
413 dev_priv
->cur_delay
= new_delay
;
416 * rps_lock not held here because clearing is non-destructive. There is
417 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
418 * by holding struct_mutex for the duration of the write.
420 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~pm_iir
);
421 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
424 static void pch_irq_handler(struct drm_device
*dev
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
430 pch_iir
= I915_READ(SDEIIR
);
432 if (pch_iir
& SDE_AUDIO_POWER_MASK
)
433 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
434 (pch_iir
& SDE_AUDIO_POWER_MASK
) >>
435 SDE_AUDIO_POWER_SHIFT
);
437 if (pch_iir
& SDE_GMBUS
)
438 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
440 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
441 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
443 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
444 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
446 if (pch_iir
& SDE_POISON
)
447 DRM_ERROR("PCH poison interrupt\n");
449 if (pch_iir
& SDE_FDI_MASK
)
451 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
453 I915_READ(FDI_RX_IIR(pipe
)));
455 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
456 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
458 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
459 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
461 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
462 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
463 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
464 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
467 static irqreturn_t
ivybridge_irq_handler(DRM_IRQ_ARGS
)
469 struct drm_device
*dev
= (struct drm_device
*) arg
;
470 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
472 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
473 struct drm_i915_master_private
*master_priv
;
475 atomic_inc(&dev_priv
->irq_received
);
477 /* disable master interrupt before clearing iir */
478 de_ier
= I915_READ(DEIER
);
479 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
482 de_iir
= I915_READ(DEIIR
);
483 gt_iir
= I915_READ(GTIIR
);
484 pch_iir
= I915_READ(SDEIIR
);
485 pm_iir
= I915_READ(GEN6_PMIIR
);
487 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 && pm_iir
== 0)
492 if (dev
->primary
->master
) {
493 master_priv
= dev
->primary
->master
->driver_priv
;
494 if (master_priv
->sarea_priv
)
495 master_priv
->sarea_priv
->last_dispatch
=
496 READ_BREADCRUMB(dev_priv
);
499 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
500 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
501 if (gt_iir
& GT_GEN6_BSD_USER_INTERRUPT
)
502 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
503 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
504 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
506 if (de_iir
& DE_GSE_IVB
)
507 intel_opregion_gse_intr(dev
);
509 if (de_iir
& DE_PLANEA_FLIP_DONE_IVB
) {
510 intel_prepare_page_flip(dev
, 0);
511 intel_finish_page_flip_plane(dev
, 0);
514 if (de_iir
& DE_PLANEB_FLIP_DONE_IVB
) {
515 intel_prepare_page_flip(dev
, 1);
516 intel_finish_page_flip_plane(dev
, 1);
519 if (de_iir
& DE_PIPEA_VBLANK_IVB
)
520 drm_handle_vblank(dev
, 0);
522 if (de_iir
& DE_PIPEB_VBLANK_IVB
)
523 drm_handle_vblank(dev
, 1);
525 /* check event from PCH */
526 if (de_iir
& DE_PCH_EVENT_IVB
) {
527 if (pch_iir
& SDE_HOTPLUG_MASK_CPT
)
528 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
529 pch_irq_handler(dev
);
532 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
) {
534 spin_lock_irqsave(&dev_priv
->rps_lock
, flags
);
535 WARN(dev_priv
->pm_iir
& pm_iir
, "Missed a PM interrupt\n");
536 I915_WRITE(GEN6_PMIMR
, pm_iir
);
537 dev_priv
->pm_iir
|= pm_iir
;
538 spin_unlock_irqrestore(&dev_priv
->rps_lock
, flags
);
539 queue_work(dev_priv
->wq
, &dev_priv
->rps_work
);
542 /* should clear PCH hotplug event before clear CPU irq */
543 I915_WRITE(SDEIIR
, pch_iir
);
544 I915_WRITE(GTIIR
, gt_iir
);
545 I915_WRITE(DEIIR
, de_iir
);
546 I915_WRITE(GEN6_PMIIR
, pm_iir
);
549 I915_WRITE(DEIER
, de_ier
);
555 static irqreturn_t
ironlake_irq_handler(DRM_IRQ_ARGS
)
557 struct drm_device
*dev
= (struct drm_device
*) arg
;
558 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
560 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
562 struct drm_i915_master_private
*master_priv
;
563 u32 bsd_usr_interrupt
= GT_BSD_USER_INTERRUPT
;
565 atomic_inc(&dev_priv
->irq_received
);
568 bsd_usr_interrupt
= GT_GEN6_BSD_USER_INTERRUPT
;
570 /* disable master interrupt before clearing iir */
571 de_ier
= I915_READ(DEIER
);
572 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
575 de_iir
= I915_READ(DEIIR
);
576 gt_iir
= I915_READ(GTIIR
);
577 pch_iir
= I915_READ(SDEIIR
);
578 pm_iir
= I915_READ(GEN6_PMIIR
);
580 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 &&
581 (!IS_GEN6(dev
) || pm_iir
== 0))
584 if (HAS_PCH_CPT(dev
))
585 hotplug_mask
= SDE_HOTPLUG_MASK_CPT
;
587 hotplug_mask
= SDE_HOTPLUG_MASK
;
591 if (dev
->primary
->master
) {
592 master_priv
= dev
->primary
->master
->driver_priv
;
593 if (master_priv
->sarea_priv
)
594 master_priv
->sarea_priv
->last_dispatch
=
595 READ_BREADCRUMB(dev_priv
);
598 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
599 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
600 if (gt_iir
& bsd_usr_interrupt
)
601 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
602 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
603 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
606 intel_opregion_gse_intr(dev
);
608 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
609 intel_prepare_page_flip(dev
, 0);
610 intel_finish_page_flip_plane(dev
, 0);
613 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
614 intel_prepare_page_flip(dev
, 1);
615 intel_finish_page_flip_plane(dev
, 1);
618 if (de_iir
& DE_PIPEA_VBLANK
)
619 drm_handle_vblank(dev
, 0);
621 if (de_iir
& DE_PIPEB_VBLANK
)
622 drm_handle_vblank(dev
, 1);
624 /* check event from PCH */
625 if (de_iir
& DE_PCH_EVENT
) {
626 if (pch_iir
& hotplug_mask
)
627 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
628 pch_irq_handler(dev
);
631 if (de_iir
& DE_PCU_EVENT
) {
632 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
633 i915_handle_rps_change(dev
);
636 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
) {
638 * IIR bits should never already be set because IMR should
639 * prevent an interrupt from being shown in IIR. The warning
640 * displays a case where we've unsafely cleared
641 * dev_priv->pm_iir. Although missing an interrupt of the same
642 * type is not a problem, it displays a problem in the logic.
644 * The mask bit in IMR is cleared by rps_work.
647 spin_lock_irqsave(&dev_priv
->rps_lock
, flags
);
648 WARN(dev_priv
->pm_iir
& pm_iir
, "Missed a PM interrupt\n");
649 I915_WRITE(GEN6_PMIMR
, pm_iir
);
650 dev_priv
->pm_iir
|= pm_iir
;
651 spin_unlock_irqrestore(&dev_priv
->rps_lock
, flags
);
652 queue_work(dev_priv
->wq
, &dev_priv
->rps_work
);
655 /* should clear PCH hotplug event before clear CPU irq */
656 I915_WRITE(SDEIIR
, pch_iir
);
657 I915_WRITE(GTIIR
, gt_iir
);
658 I915_WRITE(DEIIR
, de_iir
);
659 I915_WRITE(GEN6_PMIIR
, pm_iir
);
662 I915_WRITE(DEIER
, de_ier
);
669 * i915_error_work_func - do process context error handling work
672 * Fire an error uevent so userspace can see that a hang or error
675 static void i915_error_work_func(struct work_struct
*work
)
677 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
679 struct drm_device
*dev
= dev_priv
->dev
;
680 char *error_event
[] = { "ERROR=1", NULL
};
681 char *reset_event
[] = { "RESET=1", NULL
};
682 char *reset_done_event
[] = { "ERROR=0", NULL
};
684 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
686 if (atomic_read(&dev_priv
->mm
.wedged
)) {
687 DRM_DEBUG_DRIVER("resetting chip\n");
688 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_event
);
689 if (!i915_reset(dev
, GRDOM_RENDER
)) {
690 atomic_set(&dev_priv
->mm
.wedged
, 0);
691 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_done_event
);
693 complete_all(&dev_priv
->error_completion
);
697 #ifdef CONFIG_DEBUG_FS
698 static struct drm_i915_error_object
*
699 i915_error_object_create(struct drm_i915_private
*dev_priv
,
700 struct drm_i915_gem_object
*src
)
702 struct drm_i915_error_object
*dst
;
703 int page
, page_count
;
706 if (src
== NULL
|| src
->pages
== NULL
)
709 page_count
= src
->base
.size
/ PAGE_SIZE
;
711 dst
= kmalloc(sizeof(*dst
) + page_count
* sizeof (u32
*), GFP_ATOMIC
);
715 reloc_offset
= src
->gtt_offset
;
716 for (page
= 0; page
< page_count
; page
++) {
721 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
725 local_irq_save(flags
);
726 s
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
728 memcpy_fromio(d
, s
, PAGE_SIZE
);
729 io_mapping_unmap_atomic(s
);
730 local_irq_restore(flags
);
732 dst
->pages
[page
] = d
;
734 reloc_offset
+= PAGE_SIZE
;
736 dst
->page_count
= page_count
;
737 dst
->gtt_offset
= src
->gtt_offset
;
743 kfree(dst
->pages
[page
]);
749 i915_error_object_free(struct drm_i915_error_object
*obj
)
756 for (page
= 0; page
< obj
->page_count
; page
++)
757 kfree(obj
->pages
[page
]);
763 i915_error_state_free(struct drm_device
*dev
,
764 struct drm_i915_error_state
*error
)
768 for (i
= 0; i
< ARRAY_SIZE(error
->batchbuffer
); i
++)
769 i915_error_object_free(error
->batchbuffer
[i
]);
771 for (i
= 0; i
< ARRAY_SIZE(error
->ringbuffer
); i
++)
772 i915_error_object_free(error
->ringbuffer
[i
]);
774 kfree(error
->active_bo
);
775 kfree(error
->overlay
);
779 static u32
capture_bo_list(struct drm_i915_error_buffer
*err
,
781 struct list_head
*head
)
783 struct drm_i915_gem_object
*obj
;
786 list_for_each_entry(obj
, head
, mm_list
) {
787 err
->size
= obj
->base
.size
;
788 err
->name
= obj
->base
.name
;
789 err
->seqno
= obj
->last_rendering_seqno
;
790 err
->gtt_offset
= obj
->gtt_offset
;
791 err
->read_domains
= obj
->base
.read_domains
;
792 err
->write_domain
= obj
->base
.write_domain
;
793 err
->fence_reg
= obj
->fence_reg
;
795 if (obj
->pin_count
> 0)
797 if (obj
->user_pin_count
> 0)
799 err
->tiling
= obj
->tiling_mode
;
800 err
->dirty
= obj
->dirty
;
801 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
802 err
->ring
= obj
->ring
? obj
->ring
->id
: 0;
803 err
->cache_level
= obj
->cache_level
;
814 static void i915_gem_record_fences(struct drm_device
*dev
,
815 struct drm_i915_error_state
*error
)
817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
821 switch (INTEL_INFO(dev
)->gen
) {
823 for (i
= 0; i
< 16; i
++)
824 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
828 for (i
= 0; i
< 16; i
++)
829 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
832 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
833 for (i
= 0; i
< 8; i
++)
834 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
836 for (i
= 0; i
< 8; i
++)
837 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
843 static struct drm_i915_error_object
*
844 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
845 struct intel_ring_buffer
*ring
)
847 struct drm_i915_gem_object
*obj
;
850 if (!ring
->get_seqno
)
853 seqno
= ring
->get_seqno(ring
);
854 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
855 if (obj
->ring
!= ring
)
858 if (i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
861 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
864 /* We need to copy these to an anonymous buffer as the simplest
865 * method to avoid being overwritten by userspace.
867 return i915_error_object_create(dev_priv
, obj
);
874 * i915_capture_error_state - capture an error record for later analysis
877 * Should be called when an error is detected (either a hang or an error
878 * interrupt) to capture error state from the time of the error. Fills
879 * out a structure which becomes available in debugfs for user level tools
882 static void i915_capture_error_state(struct drm_device
*dev
)
884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
885 struct drm_i915_gem_object
*obj
;
886 struct drm_i915_error_state
*error
;
890 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
891 error
= dev_priv
->first_error
;
892 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
896 /* Account for pipe specific data like PIPE*STAT */
897 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
899 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
903 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
904 dev
->primary
->index
);
906 error
->seqno
= dev_priv
->ring
[RCS
].get_seqno(&dev_priv
->ring
[RCS
]);
907 error
->eir
= I915_READ(EIR
);
908 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
910 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
911 error
->instpm
= I915_READ(INSTPM
);
913 if (INTEL_INFO(dev
)->gen
>= 6) {
914 error
->error
= I915_READ(ERROR_GEN6
);
916 error
->bcs_acthd
= I915_READ(BCS_ACTHD
);
917 error
->bcs_ipehr
= I915_READ(BCS_IPEHR
);
918 error
->bcs_ipeir
= I915_READ(BCS_IPEIR
);
919 error
->bcs_instdone
= I915_READ(BCS_INSTDONE
);
920 error
->bcs_seqno
= 0;
921 if (dev_priv
->ring
[BCS
].get_seqno
)
922 error
->bcs_seqno
= dev_priv
->ring
[BCS
].get_seqno(&dev_priv
->ring
[BCS
]);
924 error
->vcs_acthd
= I915_READ(VCS_ACTHD
);
925 error
->vcs_ipehr
= I915_READ(VCS_IPEHR
);
926 error
->vcs_ipeir
= I915_READ(VCS_IPEIR
);
927 error
->vcs_instdone
= I915_READ(VCS_INSTDONE
);
928 error
->vcs_seqno
= 0;
929 if (dev_priv
->ring
[VCS
].get_seqno
)
930 error
->vcs_seqno
= dev_priv
->ring
[VCS
].get_seqno(&dev_priv
->ring
[VCS
]);
932 if (INTEL_INFO(dev
)->gen
>= 4) {
933 error
->ipeir
= I915_READ(IPEIR_I965
);
934 error
->ipehr
= I915_READ(IPEHR_I965
);
935 error
->instdone
= I915_READ(INSTDONE_I965
);
936 error
->instps
= I915_READ(INSTPS
);
937 error
->instdone1
= I915_READ(INSTDONE1
);
938 error
->acthd
= I915_READ(ACTHD_I965
);
939 error
->bbaddr
= I915_READ64(BB_ADDR
);
941 error
->ipeir
= I915_READ(IPEIR
);
942 error
->ipehr
= I915_READ(IPEHR
);
943 error
->instdone
= I915_READ(INSTDONE
);
944 error
->acthd
= I915_READ(ACTHD
);
947 i915_gem_record_fences(dev
, error
);
949 /* Record the active batch and ring buffers */
950 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
951 error
->batchbuffer
[i
] =
952 i915_error_first_batchbuffer(dev_priv
,
955 error
->ringbuffer
[i
] =
956 i915_error_object_create(dev_priv
,
957 dev_priv
->ring
[i
].obj
);
960 /* Record buffers on the active and pinned lists. */
961 error
->active_bo
= NULL
;
962 error
->pinned_bo
= NULL
;
965 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
967 error
->active_bo_count
= i
;
968 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
970 error
->pinned_bo_count
= i
- error
->active_bo_count
;
972 error
->active_bo
= NULL
;
973 error
->pinned_bo
= NULL
;
975 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
977 if (error
->active_bo
)
979 error
->active_bo
+ error
->active_bo_count
;
982 if (error
->active_bo
)
983 error
->active_bo_count
=
984 capture_bo_list(error
->active_bo
,
985 error
->active_bo_count
,
986 &dev_priv
->mm
.active_list
);
988 if (error
->pinned_bo
)
989 error
->pinned_bo_count
=
990 capture_bo_list(error
->pinned_bo
,
991 error
->pinned_bo_count
,
992 &dev_priv
->mm
.pinned_list
);
994 do_gettimeofday(&error
->time
);
996 error
->overlay
= intel_overlay_capture_error_state(dev
);
997 error
->display
= intel_display_capture_error_state(dev
);
999 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1000 if (dev_priv
->first_error
== NULL
) {
1001 dev_priv
->first_error
= error
;
1004 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1007 i915_error_state_free(dev
, error
);
1010 void i915_destroy_error_state(struct drm_device
*dev
)
1012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 struct drm_i915_error_state
*error
;
1015 spin_lock(&dev_priv
->error_lock
);
1016 error
= dev_priv
->first_error
;
1017 dev_priv
->first_error
= NULL
;
1018 spin_unlock(&dev_priv
->error_lock
);
1021 i915_error_state_free(dev
, error
);
1024 #define i915_capture_error_state(x)
1027 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1030 u32 eir
= I915_READ(EIR
);
1036 printk(KERN_ERR
"render error detected, EIR: 0x%08x\n",
1040 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1041 u32 ipeir
= I915_READ(IPEIR_I965
);
1043 printk(KERN_ERR
" IPEIR: 0x%08x\n",
1044 I915_READ(IPEIR_I965
));
1045 printk(KERN_ERR
" IPEHR: 0x%08x\n",
1046 I915_READ(IPEHR_I965
));
1047 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
1048 I915_READ(INSTDONE_I965
));
1049 printk(KERN_ERR
" INSTPS: 0x%08x\n",
1051 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
1052 I915_READ(INSTDONE1
));
1053 printk(KERN_ERR
" ACTHD: 0x%08x\n",
1054 I915_READ(ACTHD_I965
));
1055 I915_WRITE(IPEIR_I965
, ipeir
);
1056 POSTING_READ(IPEIR_I965
);
1058 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1059 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1060 printk(KERN_ERR
"page table error\n");
1061 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
1063 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1064 POSTING_READ(PGTBL_ER
);
1068 if (!IS_GEN2(dev
)) {
1069 if (eir
& I915_ERROR_PAGE_TABLE
) {
1070 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1071 printk(KERN_ERR
"page table error\n");
1072 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
1074 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1075 POSTING_READ(PGTBL_ER
);
1079 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1080 printk(KERN_ERR
"memory refresh error:\n");
1082 printk(KERN_ERR
"pipe %c stat: 0x%08x\n",
1083 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1084 /* pipestat has already been acked */
1086 if (eir
& I915_ERROR_INSTRUCTION
) {
1087 printk(KERN_ERR
"instruction error\n");
1088 printk(KERN_ERR
" INSTPM: 0x%08x\n",
1090 if (INTEL_INFO(dev
)->gen
< 4) {
1091 u32 ipeir
= I915_READ(IPEIR
);
1093 printk(KERN_ERR
" IPEIR: 0x%08x\n",
1095 printk(KERN_ERR
" IPEHR: 0x%08x\n",
1097 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
1098 I915_READ(INSTDONE
));
1099 printk(KERN_ERR
" ACTHD: 0x%08x\n",
1101 I915_WRITE(IPEIR
, ipeir
);
1102 POSTING_READ(IPEIR
);
1104 u32 ipeir
= I915_READ(IPEIR_I965
);
1106 printk(KERN_ERR
" IPEIR: 0x%08x\n",
1107 I915_READ(IPEIR_I965
));
1108 printk(KERN_ERR
" IPEHR: 0x%08x\n",
1109 I915_READ(IPEHR_I965
));
1110 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
1111 I915_READ(INSTDONE_I965
));
1112 printk(KERN_ERR
" INSTPS: 0x%08x\n",
1114 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
1115 I915_READ(INSTDONE1
));
1116 printk(KERN_ERR
" ACTHD: 0x%08x\n",
1117 I915_READ(ACTHD_I965
));
1118 I915_WRITE(IPEIR_I965
, ipeir
);
1119 POSTING_READ(IPEIR_I965
);
1123 I915_WRITE(EIR
, eir
);
1125 eir
= I915_READ(EIR
);
1128 * some errors might have become stuck,
1131 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1132 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1133 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1138 * i915_handle_error - handle an error interrupt
1141 * Do some basic checking of regsiter state at error interrupt time and
1142 * dump it to the syslog. Also call i915_capture_error_state() to make
1143 * sure we get a record and make it available in debugfs. Fire a uevent
1144 * so userspace knows something bad happened (should trigger collection
1145 * of a ring dump etc.).
1147 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1151 i915_capture_error_state(dev
);
1152 i915_report_and_clear_eir(dev
);
1155 INIT_COMPLETION(dev_priv
->error_completion
);
1156 atomic_set(&dev_priv
->mm
.wedged
, 1);
1159 * Wakeup waiting processes so they don't hang
1161 wake_up_all(&dev_priv
->ring
[RCS
].irq_queue
);
1163 wake_up_all(&dev_priv
->ring
[VCS
].irq_queue
);
1165 wake_up_all(&dev_priv
->ring
[BCS
].irq_queue
);
1168 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
1171 static void i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1173 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1174 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1176 struct drm_i915_gem_object
*obj
;
1177 struct intel_unpin_work
*work
;
1178 unsigned long flags
;
1179 bool stall_detected
;
1181 /* Ignore early vblank irqs */
1182 if (intel_crtc
== NULL
)
1185 spin_lock_irqsave(&dev
->event_lock
, flags
);
1186 work
= intel_crtc
->unpin_work
;
1188 if (work
== NULL
|| work
->pending
|| !work
->enable_stall_check
) {
1189 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1190 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1194 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1195 obj
= work
->pending_flip_obj
;
1196 if (INTEL_INFO(dev
)->gen
>= 4) {
1197 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1198 stall_detected
= I915_READ(dspsurf
) == obj
->gtt_offset
;
1200 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1201 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
1202 crtc
->y
* crtc
->fb
->pitch
+
1203 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1206 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1208 if (stall_detected
) {
1209 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1210 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1214 static irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
1216 struct drm_device
*dev
= (struct drm_device
*) arg
;
1217 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1218 struct drm_i915_master_private
*master_priv
;
1220 u32 pipe_stats
[I915_MAX_PIPES
];
1223 unsigned long irqflags
;
1225 int ret
= IRQ_NONE
, pipe
;
1226 bool blc_event
= false;
1228 atomic_inc(&dev_priv
->irq_received
);
1230 iir
= I915_READ(IIR
);
1232 if (INTEL_INFO(dev
)->gen
>= 4)
1233 vblank_status
= PIPE_START_VBLANK_INTERRUPT_STATUS
;
1235 vblank_status
= PIPE_VBLANK_INTERRUPT_STATUS
;
1238 irq_received
= iir
!= 0;
1240 /* Can't rely on pipestat interrupt bit in iir as it might
1241 * have been cleared after the pipestat interrupt was received.
1242 * It doesn't set the bit in iir again, but it still produces
1243 * interrupts (for non-MSI).
1245 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1246 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
1247 i915_handle_error(dev
, false);
1249 for_each_pipe(pipe
) {
1250 int reg
= PIPESTAT(pipe
);
1251 pipe_stats
[pipe
] = I915_READ(reg
);
1254 * Clear the PIPE*STAT regs before the IIR
1256 if (pipe_stats
[pipe
] & 0x8000ffff) {
1257 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1258 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1260 I915_WRITE(reg
, pipe_stats
[pipe
]);
1264 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1271 /* Consume port. Then clear IIR or we'll miss events */
1272 if ((I915_HAS_HOTPLUG(dev
)) &&
1273 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
1274 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1276 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1278 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
1279 queue_work(dev_priv
->wq
,
1280 &dev_priv
->hotplug_work
);
1282 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1283 I915_READ(PORT_HOTPLUG_STAT
);
1286 I915_WRITE(IIR
, iir
);
1287 new_iir
= I915_READ(IIR
); /* Flush posted writes */
1289 if (dev
->primary
->master
) {
1290 master_priv
= dev
->primary
->master
->driver_priv
;
1291 if (master_priv
->sarea_priv
)
1292 master_priv
->sarea_priv
->last_dispatch
=
1293 READ_BREADCRUMB(dev_priv
);
1296 if (iir
& I915_USER_INTERRUPT
)
1297 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1298 if (iir
& I915_BSD_USER_INTERRUPT
)
1299 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1301 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
) {
1302 intel_prepare_page_flip(dev
, 0);
1303 if (dev_priv
->flip_pending_is_done
)
1304 intel_finish_page_flip_plane(dev
, 0);
1307 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
) {
1308 intel_prepare_page_flip(dev
, 1);
1309 if (dev_priv
->flip_pending_is_done
)
1310 intel_finish_page_flip_plane(dev
, 1);
1313 for_each_pipe(pipe
) {
1314 if (pipe_stats
[pipe
] & vblank_status
&&
1315 drm_handle_vblank(dev
, pipe
)) {
1317 if (!dev_priv
->flip_pending_is_done
) {
1318 i915_pageflip_stall_check(dev
, pipe
);
1319 intel_finish_page_flip(dev
, pipe
);
1323 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
1328 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
1329 intel_opregion_asle_intr(dev
);
1331 /* With MSI, interrupts are only generated when iir
1332 * transitions from zero to nonzero. If another bit got
1333 * set while we were handling the existing iir bits, then
1334 * we would never get another interrupt.
1336 * This is fine on non-MSI as well, as if we hit this path
1337 * we avoid exiting the interrupt handler only to generate
1340 * Note that for MSI this could cause a stray interrupt report
1341 * if an interrupt landed in the time between writing IIR and
1342 * the posting read. This should be rare enough to never
1343 * trigger the 99% of 100,000 interrupts test for disabling
1352 static int i915_emit_irq(struct drm_device
* dev
)
1354 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1355 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1357 i915_kernel_lost_context(dev
);
1359 DRM_DEBUG_DRIVER("\n");
1361 dev_priv
->counter
++;
1362 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
1363 dev_priv
->counter
= 1;
1364 if (master_priv
->sarea_priv
)
1365 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
1367 if (BEGIN_LP_RING(4) == 0) {
1368 OUT_RING(MI_STORE_DWORD_INDEX
);
1369 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1370 OUT_RING(dev_priv
->counter
);
1371 OUT_RING(MI_USER_INTERRUPT
);
1375 return dev_priv
->counter
;
1378 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
1380 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1381 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1383 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
1385 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr
,
1386 READ_BREADCRUMB(dev_priv
));
1388 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
1389 if (master_priv
->sarea_priv
)
1390 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
1394 if (master_priv
->sarea_priv
)
1395 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1397 if (ring
->irq_get(ring
)) {
1398 DRM_WAIT_ON(ret
, ring
->irq_queue
, 3 * DRM_HZ
,
1399 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
1400 ring
->irq_put(ring
);
1401 } else if (wait_for(READ_BREADCRUMB(dev_priv
) >= irq_nr
, 3000))
1404 if (ret
== -EBUSY
) {
1405 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1406 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
1412 /* Needs the lock as it touches the ring.
1414 int i915_irq_emit(struct drm_device
*dev
, void *data
,
1415 struct drm_file
*file_priv
)
1417 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1418 drm_i915_irq_emit_t
*emit
= data
;
1421 if (!dev_priv
|| !LP_RING(dev_priv
)->virtual_start
) {
1422 DRM_ERROR("called with no initialization\n");
1426 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1428 mutex_lock(&dev
->struct_mutex
);
1429 result
= i915_emit_irq(dev
);
1430 mutex_unlock(&dev
->struct_mutex
);
1432 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
1433 DRM_ERROR("copy_to_user\n");
1440 /* Doesn't need the hardware lock.
1442 int i915_irq_wait(struct drm_device
*dev
, void *data
,
1443 struct drm_file
*file_priv
)
1445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1446 drm_i915_irq_wait_t
*irqwait
= data
;
1449 DRM_ERROR("called with no initialization\n");
1453 return i915_wait_irq(dev
, irqwait
->irq_seq
);
1456 /* Called from drm generic code, passed 'crtc' which
1457 * we use as a pipe index
1459 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1461 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1462 unsigned long irqflags
;
1464 if (!i915_pipe_enabled(dev
, pipe
))
1467 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1468 if (INTEL_INFO(dev
)->gen
>= 4)
1469 i915_enable_pipestat(dev_priv
, pipe
,
1470 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1472 i915_enable_pipestat(dev_priv
, pipe
,
1473 PIPE_VBLANK_INTERRUPT_ENABLE
);
1475 /* maintain vblank delivery even in deep C-states */
1476 if (dev_priv
->info
->gen
== 3)
1477 I915_WRITE(INSTPM
, INSTPM_AGPBUSY_DIS
<< 16);
1478 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1483 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1485 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1486 unsigned long irqflags
;
1488 if (!i915_pipe_enabled(dev
, pipe
))
1491 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1492 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1493 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1494 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1499 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1501 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1502 unsigned long irqflags
;
1504 if (!i915_pipe_enabled(dev
, pipe
))
1507 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1508 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1509 DE_PIPEA_VBLANK_IVB
: DE_PIPEB_VBLANK_IVB
);
1510 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1515 /* Called from drm generic code, passed 'crtc' which
1516 * we use as a pipe index
1518 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1520 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1521 unsigned long irqflags
;
1523 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1524 if (dev_priv
->info
->gen
== 3)
1526 INSTPM_AGPBUSY_DIS
<< 16 | INSTPM_AGPBUSY_DIS
);
1528 i915_disable_pipestat(dev_priv
, pipe
,
1529 PIPE_VBLANK_INTERRUPT_ENABLE
|
1530 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1531 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1534 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1536 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1537 unsigned long irqflags
;
1539 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1540 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1541 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1542 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1545 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1547 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1548 unsigned long irqflags
;
1550 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1551 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1552 DE_PIPEA_VBLANK_IVB
: DE_PIPEB_VBLANK_IVB
);
1553 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1556 /* Set the vblank monitor pipe
1558 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1559 struct drm_file
*file_priv
)
1561 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1564 DRM_ERROR("called with no initialization\n");
1571 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1572 struct drm_file
*file_priv
)
1574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 drm_i915_vblank_pipe_t
*pipe
= data
;
1578 DRM_ERROR("called with no initialization\n");
1582 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1588 * Schedule buffer swap at given vertical blank.
1590 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1591 struct drm_file
*file_priv
)
1593 /* The delayed swap mechanism was fundamentally racy, and has been
1594 * removed. The model was that the client requested a delayed flip/swap
1595 * from the kernel, then waited for vblank before continuing to perform
1596 * rendering. The problem was that the kernel might wake the client
1597 * up before it dispatched the vblank swap (since the lock has to be
1598 * held while touching the ringbuffer), in which case the client would
1599 * clear and start the next frame before the swap occurred, and
1600 * flicker would occur in addition to likely missing the vblank.
1602 * In the absence of this ioctl, userland falls back to a correct path
1603 * of waiting for a vblank, then dispatching the swap on its own.
1604 * Context switching to userland and back is plenty fast enough for
1605 * meeting the requirements of vblank swapping.
1611 ring_last_seqno(struct intel_ring_buffer
*ring
)
1613 return list_entry(ring
->request_list
.prev
,
1614 struct drm_i915_gem_request
, list
)->seqno
;
1617 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
1619 if (list_empty(&ring
->request_list
) ||
1620 i915_seqno_passed(ring
->get_seqno(ring
), ring_last_seqno(ring
))) {
1621 /* Issue a wake-up to catch stuck h/w. */
1622 if (ring
->waiting_seqno
&& waitqueue_active(&ring
->irq_queue
)) {
1623 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1625 ring
->waiting_seqno
,
1626 ring
->get_seqno(ring
));
1627 wake_up_all(&ring
->irq_queue
);
1635 static bool kick_ring(struct intel_ring_buffer
*ring
)
1637 struct drm_device
*dev
= ring
->dev
;
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 u32 tmp
= I915_READ_CTL(ring
);
1640 if (tmp
& RING_WAIT
) {
1641 DRM_ERROR("Kicking stuck wait on %s\n",
1643 I915_WRITE_CTL(ring
, tmp
);
1647 (tmp
& RING_WAIT_SEMAPHORE
)) {
1648 DRM_ERROR("Kicking stuck semaphore on %s\n",
1650 I915_WRITE_CTL(ring
, tmp
);
1657 * This is called when the chip hasn't reported back with completed
1658 * batchbuffers in a long time. The first time this is called we simply record
1659 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1660 * again, we assume the chip is wedged and try to fix it.
1662 void i915_hangcheck_elapsed(unsigned long data
)
1664 struct drm_device
*dev
= (struct drm_device
*)data
;
1665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1666 uint32_t acthd
, instdone
, instdone1
;
1669 if (!i915_enable_hangcheck
)
1672 /* If all work is done then ACTHD clearly hasn't advanced. */
1673 if (i915_hangcheck_ring_idle(&dev_priv
->ring
[RCS
], &err
) &&
1674 i915_hangcheck_ring_idle(&dev_priv
->ring
[VCS
], &err
) &&
1675 i915_hangcheck_ring_idle(&dev_priv
->ring
[BCS
], &err
)) {
1676 dev_priv
->hangcheck_count
= 0;
1682 if (INTEL_INFO(dev
)->gen
< 4) {
1683 acthd
= I915_READ(ACTHD
);
1684 instdone
= I915_READ(INSTDONE
);
1687 acthd
= I915_READ(ACTHD_I965
);
1688 instdone
= I915_READ(INSTDONE_I965
);
1689 instdone1
= I915_READ(INSTDONE1
);
1692 if (dev_priv
->last_acthd
== acthd
&&
1693 dev_priv
->last_instdone
== instdone
&&
1694 dev_priv
->last_instdone1
== instdone1
) {
1695 if (dev_priv
->hangcheck_count
++ > 1) {
1696 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1698 if (!IS_GEN2(dev
)) {
1699 /* Is the chip hanging on a WAIT_FOR_EVENT?
1700 * If so we can simply poke the RB_WAIT bit
1701 * and break the hang. This should work on
1702 * all but the second generation chipsets.
1705 if (kick_ring(&dev_priv
->ring
[RCS
]))
1709 kick_ring(&dev_priv
->ring
[VCS
]))
1713 kick_ring(&dev_priv
->ring
[BCS
]))
1717 i915_handle_error(dev
, true);
1721 dev_priv
->hangcheck_count
= 0;
1723 dev_priv
->last_acthd
= acthd
;
1724 dev_priv
->last_instdone
= instdone
;
1725 dev_priv
->last_instdone1
= instdone1
;
1729 /* Reset timer case chip hangs without another request being added */
1730 mod_timer(&dev_priv
->hangcheck_timer
,
1731 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1736 static void ironlake_irq_preinstall(struct drm_device
*dev
)
1738 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1740 atomic_set(&dev_priv
->irq_received
, 0);
1742 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
1743 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
1744 if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
1745 INIT_WORK(&dev_priv
->rps_work
, gen6_pm_rps_work
);
1747 I915_WRITE(HWSTAM
, 0xeffe);
1748 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1749 /* Workaround stalls observed on Sandy Bridge GPUs by
1750 * making the blitter command streamer generate a
1751 * write to the Hardware Status Page for
1752 * MI_USER_INTERRUPT. This appears to serialize the
1753 * previous seqno write out before the interrupt
1756 I915_WRITE(GEN6_BLITTER_HWSTAM
, ~GEN6_BLITTER_USER_INTERRUPT
);
1757 I915_WRITE(GEN6_BSD_HWSTAM
, ~GEN6_BSD_USER_INTERRUPT
);
1760 /* XXX hotplug from PCH */
1762 I915_WRITE(DEIMR
, 0xffffffff);
1763 I915_WRITE(DEIER
, 0x0);
1764 POSTING_READ(DEIER
);
1767 I915_WRITE(GTIMR
, 0xffffffff);
1768 I915_WRITE(GTIER
, 0x0);
1769 POSTING_READ(GTIER
);
1771 /* south display irq */
1772 I915_WRITE(SDEIMR
, 0xffffffff);
1773 I915_WRITE(SDEIER
, 0x0);
1774 POSTING_READ(SDEIER
);
1777 static int ironlake_irq_postinstall(struct drm_device
*dev
)
1779 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1780 /* enable kind of interrupts always enabled */
1781 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
1782 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
;
1786 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[RCS
].irq_queue
);
1788 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[VCS
].irq_queue
);
1790 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[BCS
].irq_queue
);
1792 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1793 dev_priv
->irq_mask
= ~display_mask
;
1795 /* should always can generate irq */
1796 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1797 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1798 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
1799 POSTING_READ(DEIER
);
1801 dev_priv
->gt_irq_mask
= ~0;
1803 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1804 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1809 GT_GEN6_BSD_USER_INTERRUPT
|
1810 GT_BLT_USER_INTERRUPT
;
1815 GT_BSD_USER_INTERRUPT
;
1816 I915_WRITE(GTIER
, render_irqs
);
1817 POSTING_READ(GTIER
);
1819 if (HAS_PCH_CPT(dev
)) {
1820 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1821 SDE_PORTB_HOTPLUG_CPT
|
1822 SDE_PORTC_HOTPLUG_CPT
|
1823 SDE_PORTD_HOTPLUG_CPT
);
1825 hotplug_mask
= (SDE_CRT_HOTPLUG
|
1832 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1834 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1835 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1836 I915_WRITE(SDEIER
, hotplug_mask
);
1837 POSTING_READ(SDEIER
);
1839 if (IS_IRONLAKE_M(dev
)) {
1840 /* Clear & enable PCU event interrupts */
1841 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
1842 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
1843 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
1849 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
1851 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1852 /* enable kind of interrupts always enabled */
1853 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
1854 DE_PCH_EVENT_IVB
| DE_PLANEA_FLIP_DONE_IVB
|
1855 DE_PLANEB_FLIP_DONE_IVB
;
1859 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[RCS
].irq_queue
);
1861 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[VCS
].irq_queue
);
1863 DRM_INIT_WAITQUEUE(&dev_priv
->ring
[BCS
].irq_queue
);
1865 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1866 dev_priv
->irq_mask
= ~display_mask
;
1868 /* should always can generate irq */
1869 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1870 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1871 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK_IVB
|
1872 DE_PIPEB_VBLANK_IVB
);
1873 POSTING_READ(DEIER
);
1875 dev_priv
->gt_irq_mask
= ~0;
1877 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1878 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1880 render_irqs
= GT_USER_INTERRUPT
| GT_GEN6_BSD_USER_INTERRUPT
|
1881 GT_BLT_USER_INTERRUPT
;
1882 I915_WRITE(GTIER
, render_irqs
);
1883 POSTING_READ(GTIER
);
1885 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1886 SDE_PORTB_HOTPLUG_CPT
|
1887 SDE_PORTC_HOTPLUG_CPT
|
1888 SDE_PORTD_HOTPLUG_CPT
);
1889 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1891 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1892 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1893 I915_WRITE(SDEIER
, hotplug_mask
);
1894 POSTING_READ(SDEIER
);
1899 static void i915_driver_irq_preinstall(struct drm_device
* dev
)
1901 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1904 atomic_set(&dev_priv
->irq_received
, 0);
1906 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
1907 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
1909 if (I915_HAS_HOTPLUG(dev
)) {
1910 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1911 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1914 I915_WRITE(HWSTAM
, 0xeffe);
1916 I915_WRITE(PIPESTAT(pipe
), 0);
1917 I915_WRITE(IMR
, 0xffffffff);
1918 I915_WRITE(IER
, 0x0);
1923 * Must be called after intel_modeset_init or hotplug interrupts won't be
1924 * enabled correctly.
1926 static int i915_driver_irq_postinstall(struct drm_device
*dev
)
1928 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1929 u32 enable_mask
= I915_INTERRUPT_ENABLE_FIX
| I915_INTERRUPT_ENABLE_VAR
;
1932 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1934 /* Unmask the interrupts that we always want on. */
1935 dev_priv
->irq_mask
= ~I915_INTERRUPT_ENABLE_FIX
;
1937 dev_priv
->pipestat
[0] = 0;
1938 dev_priv
->pipestat
[1] = 0;
1940 if (I915_HAS_HOTPLUG(dev
)) {
1941 /* Enable in IER... */
1942 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
1943 /* and unmask in IMR */
1944 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
1948 * Enable some error detection, note the instruction error mask
1949 * bit is reserved, so we leave it masked.
1952 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
1953 GM45_ERROR_MEM_PRIV
|
1954 GM45_ERROR_CP_PRIV
|
1955 I915_ERROR_MEMORY_REFRESH
);
1957 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
1958 I915_ERROR_MEMORY_REFRESH
);
1960 I915_WRITE(EMR
, error_mask
);
1962 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1963 I915_WRITE(IER
, enable_mask
);
1966 if (I915_HAS_HOTPLUG(dev
)) {
1967 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1969 /* Note HDMI and DP share bits */
1970 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
1971 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
1972 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
1973 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
1974 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
1975 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
1976 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
1977 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
1978 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
1979 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
1980 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
1981 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
1983 /* Programming the CRT detection parameters tends
1984 to generate a spurious hotplug event about three
1985 seconds later. So just do it once.
1988 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
1989 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
1992 /* Ignore TV since it's buggy */
1994 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
1997 intel_opregion_enable_asle(dev
);
2002 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2004 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2009 dev_priv
->vblank_pipe
= 0;
2011 I915_WRITE(HWSTAM
, 0xffffffff);
2013 I915_WRITE(DEIMR
, 0xffffffff);
2014 I915_WRITE(DEIER
, 0x0);
2015 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2017 I915_WRITE(GTIMR
, 0xffffffff);
2018 I915_WRITE(GTIER
, 0x0);
2019 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2022 static void i915_driver_irq_uninstall(struct drm_device
* dev
)
2024 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2030 dev_priv
->vblank_pipe
= 0;
2032 if (I915_HAS_HOTPLUG(dev
)) {
2033 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2034 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2037 I915_WRITE(HWSTAM
, 0xffffffff);
2039 I915_WRITE(PIPESTAT(pipe
), 0);
2040 I915_WRITE(IMR
, 0xffffffff);
2041 I915_WRITE(IER
, 0x0);
2044 I915_WRITE(PIPESTAT(pipe
),
2045 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2046 I915_WRITE(IIR
, I915_READ(IIR
));
2049 void intel_irq_init(struct drm_device
*dev
)
2051 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2052 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2053 if (IS_G4X(dev
) || IS_GEN5(dev
) || IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
2054 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2055 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2059 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
2060 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
2062 if (IS_IVYBRIDGE(dev
)) {
2063 /* Share pre & uninstall handlers with ILK/SNB */
2064 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2065 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2066 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2067 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2068 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2069 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2070 } else if (HAS_PCH_SPLIT(dev
)) {
2071 dev
->driver
->irq_handler
= ironlake_irq_handler
;
2072 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2073 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
2074 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2075 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
2076 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
2078 dev
->driver
->irq_preinstall
= i915_driver_irq_preinstall
;
2079 dev
->driver
->irq_postinstall
= i915_driver_irq_postinstall
;
2080 dev
->driver
->irq_uninstall
= i915_driver_irq_uninstall
;
2081 dev
->driver
->irq_handler
= i915_driver_irq_handler
;
2082 dev
->driver
->enable_vblank
= i915_enable_vblank
;
2083 dev
->driver
->disable_vblank
= i915_disable_vblank
;