1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
264 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
266 ilk_update_gt_irq(dev_priv
, mask
, mask
);
267 POSTING_READ_FW(GTIMR
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
)
341 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
343 spin_lock_irq(&dev_priv
->irq_lock
);
344 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
347 dev_priv
->rps
.pm_iir
= 0;
348 spin_unlock_irq(&dev_priv
->irq_lock
);
351 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
353 spin_lock_irq(&dev_priv
->irq_lock
);
354 WARN_ON_ONCE(dev_priv
->rps
.pm_iir
);
355 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
356 dev_priv
->rps
.interrupts_enabled
= true;
357 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
358 dev_priv
->pm_rps_events
);
359 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
361 spin_unlock_irq(&dev_priv
->irq_lock
);
364 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
366 return (mask
& ~dev_priv
->rps
.pm_intr_keep
);
369 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
371 spin_lock_irq(&dev_priv
->irq_lock
);
372 dev_priv
->rps
.interrupts_enabled
= false;
374 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
376 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
377 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
378 ~dev_priv
->pm_rps_events
);
380 spin_unlock_irq(&dev_priv
->irq_lock
);
381 synchronize_irq(dev_priv
->drm
.irq
);
383 /* Now that we will not be generating any more work, flush any
384 * outsanding tasks. As we are called on the RPS idle path,
385 * we will reset the GPU to minimum frequencies, so the current
386 * state of the worker can be discarded.
388 cancel_work_sync(&dev_priv
->rps
.work
);
389 gen6_reset_rps_interrupts(dev_priv
);
393 * bdw_update_port_irq - update DE port interrupt
394 * @dev_priv: driver private
395 * @interrupt_mask: mask of interrupt bits to update
396 * @enabled_irq_mask: mask of interrupt bits to enable
398 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
399 uint32_t interrupt_mask
,
400 uint32_t enabled_irq_mask
)
405 assert_spin_locked(&dev_priv
->irq_lock
);
407 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
409 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
412 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
415 new_val
&= ~interrupt_mask
;
416 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
418 if (new_val
!= old_val
) {
419 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
420 POSTING_READ(GEN8_DE_PORT_IMR
);
425 * bdw_update_pipe_irq - update DE pipe interrupt
426 * @dev_priv: driver private
427 * @pipe: pipe whose interrupt to update
428 * @interrupt_mask: mask of interrupt bits to update
429 * @enabled_irq_mask: mask of interrupt bits to enable
431 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
433 uint32_t interrupt_mask
,
434 uint32_t enabled_irq_mask
)
438 assert_spin_locked(&dev_priv
->irq_lock
);
440 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
442 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
445 new_val
= dev_priv
->de_irq_mask
[pipe
];
446 new_val
&= ~interrupt_mask
;
447 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
449 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
450 dev_priv
->de_irq_mask
[pipe
] = new_val
;
451 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
452 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
457 * ibx_display_interrupt_update - update SDEIMR
458 * @dev_priv: driver private
459 * @interrupt_mask: mask of interrupt bits to update
460 * @enabled_irq_mask: mask of interrupt bits to enable
462 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
463 uint32_t interrupt_mask
,
464 uint32_t enabled_irq_mask
)
466 uint32_t sdeimr
= I915_READ(SDEIMR
);
467 sdeimr
&= ~interrupt_mask
;
468 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
470 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
472 assert_spin_locked(&dev_priv
->irq_lock
);
474 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
477 I915_WRITE(SDEIMR
, sdeimr
);
478 POSTING_READ(SDEIMR
);
482 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
483 u32 enable_mask
, u32 status_mask
)
485 i915_reg_t reg
= PIPESTAT(pipe
);
486 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
488 assert_spin_locked(&dev_priv
->irq_lock
);
489 WARN_ON(!intel_irqs_enabled(dev_priv
));
491 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
492 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
493 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
494 pipe_name(pipe
), enable_mask
, status_mask
))
497 if ((pipestat
& enable_mask
) == enable_mask
)
500 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
502 /* Enable the interrupt, clear any pending status */
503 pipestat
|= enable_mask
| status_mask
;
504 I915_WRITE(reg
, pipestat
);
509 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
510 u32 enable_mask
, u32 status_mask
)
512 i915_reg_t reg
= PIPESTAT(pipe
);
513 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
515 assert_spin_locked(&dev_priv
->irq_lock
);
516 WARN_ON(!intel_irqs_enabled(dev_priv
));
518 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
519 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
520 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
521 pipe_name(pipe
), enable_mask
, status_mask
))
524 if ((pipestat
& enable_mask
) == 0)
527 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
529 pipestat
&= ~enable_mask
;
530 I915_WRITE(reg
, pipestat
);
534 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
536 u32 enable_mask
= status_mask
<< 16;
539 * On pipe A we don't support the PSR interrupt yet,
540 * on pipe B and C the same bit MBZ.
542 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
545 * On pipe B and C we don't support the PSR interrupt yet, on pipe
546 * A the same bit is for perf counters which we don't use either.
548 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
551 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
552 SPRITE0_FLIP_DONE_INT_EN_VLV
|
553 SPRITE1_FLIP_DONE_INT_EN_VLV
);
554 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
555 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
556 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
557 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
563 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
568 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
569 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
572 enable_mask
= status_mask
<< 16;
573 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
577 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
582 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
583 enable_mask
= vlv_get_pipestat_enable_mask(&dev_priv
->drm
,
586 enable_mask
= status_mask
<< 16;
587 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
591 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
592 * @dev_priv: i915 device private
594 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
596 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
599 spin_lock_irq(&dev_priv
->irq_lock
);
601 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
602 if (INTEL_GEN(dev_priv
) >= 4)
603 i915_enable_pipestat(dev_priv
, PIPE_A
,
604 PIPE_LEGACY_BLC_EVENT_STATUS
);
606 spin_unlock_irq(&dev_priv
->irq_lock
);
610 * This timing diagram depicts the video signal in and
611 * around the vertical blanking period.
613 * Assumptions about the fictitious mode used in this example:
615 * vsync_start = vblank_start + 1
616 * vsync_end = vblank_start + 2
617 * vtotal = vblank_start + 3
620 * latch double buffered registers
621 * increment frame counter (ctg+)
622 * generate start of vblank interrupt (gen4+)
625 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
626 * | may be shifted forward 1-3 extra lines via PIPECONF
628 * | | start of vsync:
629 * | | generate vsync interrupt
631 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
632 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
633 * ----va---> <-----------------vb--------------------> <--------va-------------
634 * | | <----vs-----> |
635 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
636 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
637 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
639 * last visible pixel first visible pixel
640 * | increment frame counter (gen3/4)
641 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
643 * x = horizontal active
644 * _ = horizontal blanking
645 * hs = horizontal sync
646 * va = vertical active
647 * vb = vertical blanking
649 * vbs = vblank_start (number)
652 * - most events happen at the start of horizontal sync
653 * - frame start happens at the start of horizontal blank, 1-4 lines
654 * (depending on PIPECONF settings) after the start of vblank
655 * - gen3/4 pixel and frame counter are synchronized with the start
656 * of horizontal active on the first line of vertical active
659 /* Called from drm generic code, passed a 'crtc', which
660 * we use as a pipe index
662 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
664 struct drm_i915_private
*dev_priv
= to_i915(dev
);
665 i915_reg_t high_frame
, low_frame
;
666 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
667 struct intel_crtc
*intel_crtc
=
668 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
669 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
671 htotal
= mode
->crtc_htotal
;
672 hsync_start
= mode
->crtc_hsync_start
;
673 vbl_start
= mode
->crtc_vblank_start
;
674 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
675 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
677 /* Convert to pixel count */
680 /* Start of vblank event occurs at start of hsync */
681 vbl_start
-= htotal
- hsync_start
;
683 high_frame
= PIPEFRAME(pipe
);
684 low_frame
= PIPEFRAMEPIXEL(pipe
);
687 * High & low register fields aren't synchronized, so make sure
688 * we get a low value that's stable across two reads of the high
692 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
693 low
= I915_READ(low_frame
);
694 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
695 } while (high1
!= high2
);
697 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
698 pixel
= low
& PIPE_PIXEL_MASK
;
699 low
>>= PIPE_FRAME_LOW_SHIFT
;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
709 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
711 struct drm_i915_private
*dev_priv
= to_i915(dev
);
713 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
716 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
717 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
719 struct drm_device
*dev
= crtc
->base
.dev
;
720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
721 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
722 enum pipe pipe
= crtc
->pipe
;
723 int position
, vtotal
;
725 vtotal
= mode
->crtc_vtotal
;
726 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
729 if (IS_GEN2(dev_priv
))
730 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
732 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
735 * On HSW, the DSL reg (0x70000) appears to return 0 if we
736 * read it just before the start of vblank. So try it again
737 * so we don't accidentally end up spanning a vblank frame
738 * increment, causing the pipe_update_end() code to squak at us.
740 * The nature of this problem means we can't simply check the ISR
741 * bit and return the vblank start value; nor can we use the scanline
742 * debug register in the transcoder as it appears to have the same
743 * problem. We may need to extend this to include other platforms,
744 * but so far testing only shows the problem on HSW.
746 if (HAS_DDI(dev_priv
) && !position
) {
749 for (i
= 0; i
< 100; i
++) {
751 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
753 if (temp
!= position
) {
761 * See update_scanline_offset() for the details on the
762 * scanline_offset adjustment.
764 return (position
+ crtc
->scanline_offset
) % vtotal
;
767 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
768 unsigned int flags
, int *vpos
, int *hpos
,
769 ktime_t
*stime
, ktime_t
*etime
,
770 const struct drm_display_mode
*mode
)
772 struct drm_i915_private
*dev_priv
= to_i915(dev
);
773 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
776 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
779 unsigned long irqflags
;
781 if (WARN_ON(!mode
->crtc_clock
)) {
782 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
783 "pipe %c\n", pipe_name(pipe
));
787 htotal
= mode
->crtc_htotal
;
788 hsync_start
= mode
->crtc_hsync_start
;
789 vtotal
= mode
->crtc_vtotal
;
790 vbl_start
= mode
->crtc_vblank_start
;
791 vbl_end
= mode
->crtc_vblank_end
;
793 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
794 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
799 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
802 * Lock uncore.lock, as we will do multiple timing critical raw
803 * register reads, potentially with preemption disabled, so the
804 * following code must not block on uncore.lock.
806 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
808 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
810 /* Get optional system timestamp before query. */
812 *stime
= ktime_get();
814 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
815 /* No obvious pixelcount register. Only query vertical
816 * scanout position from Display scan line register.
818 position
= __intel_get_crtc_scanline(intel_crtc
);
820 /* Have access to pixelcount since start of frame.
821 * We can split this into vertical and horizontal
824 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
826 /* convert to pixel counts */
832 * In interlaced modes, the pixel counter counts all pixels,
833 * so one field will have htotal more pixels. In order to avoid
834 * the reported position from jumping backwards when the pixel
835 * counter is beyond the length of the shorter field, just
836 * clamp the position the length of the shorter field. This
837 * matches how the scanline counter based position works since
838 * the scanline counter doesn't count the two half lines.
840 if (position
>= vtotal
)
841 position
= vtotal
- 1;
844 * Start of vblank interrupt is triggered at start of hsync,
845 * just prior to the first active line of vblank. However we
846 * consider lines to start at the leading edge of horizontal
847 * active. So, should we get here before we've crossed into
848 * the horizontal active of the first line in vblank, we would
849 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
850 * always add htotal-hsync_start to the current pixel position.
852 position
= (position
+ htotal
- hsync_start
) % vtotal
;
855 /* Get optional system timestamp after query. */
857 *etime
= ktime_get();
859 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
861 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
863 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
866 * While in vblank, position will be negative
867 * counting up towards 0 at vbl_end. And outside
868 * vblank, position will be positive counting
871 if (position
>= vbl_start
)
874 position
+= vtotal
- vbl_end
;
876 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
880 *vpos
= position
/ htotal
;
881 *hpos
= position
- (*vpos
* htotal
);
886 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
891 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
893 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
894 unsigned long irqflags
;
897 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
898 position
= __intel_get_crtc_scanline(crtc
);
899 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
904 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
906 struct timeval
*vblank_time
,
909 struct drm_crtc
*crtc
;
911 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
912 DRM_ERROR("Invalid crtc %u\n", pipe
);
916 /* Get drm_crtc to timestamp: */
917 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
919 DRM_ERROR("Invalid crtc %u\n", pipe
);
923 if (!crtc
->hwmode
.crtc_clock
) {
924 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
928 /* Helper routine in DRM core does all the work: */
929 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
934 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
936 u32 busy_up
, busy_down
, max_avg
, min_avg
;
939 spin_lock(&mchdev_lock
);
941 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
943 new_delay
= dev_priv
->ips
.cur_delay
;
945 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
946 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
947 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
948 max_avg
= I915_READ(RCBMAXAVG
);
949 min_avg
= I915_READ(RCBMINAVG
);
951 /* Handle RCS change request from hw */
952 if (busy_up
> max_avg
) {
953 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
954 new_delay
= dev_priv
->ips
.cur_delay
- 1;
955 if (new_delay
< dev_priv
->ips
.max_delay
)
956 new_delay
= dev_priv
->ips
.max_delay
;
957 } else if (busy_down
< min_avg
) {
958 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
959 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
960 if (new_delay
> dev_priv
->ips
.min_delay
)
961 new_delay
= dev_priv
->ips
.min_delay
;
964 if (ironlake_set_drps(dev_priv
, new_delay
))
965 dev_priv
->ips
.cur_delay
= new_delay
;
967 spin_unlock(&mchdev_lock
);
972 static void notify_ring(struct intel_engine_cs
*engine
)
974 smp_store_mb(engine
->breadcrumbs
.irq_posted
, true);
975 if (intel_engine_wakeup(engine
))
976 trace_i915_gem_request_notify(engine
);
979 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
980 struct intel_rps_ei
*ei
)
982 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
983 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
984 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
987 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
988 const struct intel_rps_ei
*old
,
989 const struct intel_rps_ei
*now
,
993 unsigned int mul
= 100;
995 if (old
->cz_clock
== 0)
998 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1001 time
= now
->cz_clock
- old
->cz_clock
;
1002 time
*= threshold
* dev_priv
->czclk_freq
;
1004 /* Workload can be split between render + media, e.g. SwapBuffers
1005 * being blitted in X after being rendered in mesa. To account for
1006 * this we need to combine both engines into our activity counter.
1008 c0
= now
->render_c0
- old
->render_c0
;
1009 c0
+= now
->media_c0
- old
->media_c0
;
1010 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1015 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1017 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1018 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1021 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1023 struct intel_rps_ei now
;
1026 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1029 vlv_c0_read(dev_priv
, &now
);
1030 if (now
.cz_clock
== 0)
1033 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1034 if (!vlv_c0_above(dev_priv
,
1035 &dev_priv
->rps
.down_ei
, &now
,
1036 dev_priv
->rps
.down_threshold
))
1037 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1038 dev_priv
->rps
.down_ei
= now
;
1041 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1042 if (vlv_c0_above(dev_priv
,
1043 &dev_priv
->rps
.up_ei
, &now
,
1044 dev_priv
->rps
.up_threshold
))
1045 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1046 dev_priv
->rps
.up_ei
= now
;
1052 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1054 struct intel_engine_cs
*engine
;
1056 for_each_engine(engine
, dev_priv
)
1057 if (intel_engine_has_waiter(engine
))
1063 static void gen6_pm_rps_work(struct work_struct
*work
)
1065 struct drm_i915_private
*dev_priv
=
1066 container_of(work
, struct drm_i915_private
, rps
.work
);
1068 int new_delay
, adj
, min
, max
;
1071 spin_lock_irq(&dev_priv
->irq_lock
);
1072 /* Speed up work cancelation during disabling rps interrupts. */
1073 if (!dev_priv
->rps
.interrupts_enabled
) {
1074 spin_unlock_irq(&dev_priv
->irq_lock
);
1078 pm_iir
= dev_priv
->rps
.pm_iir
;
1079 dev_priv
->rps
.pm_iir
= 0;
1080 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1081 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1082 client_boost
= dev_priv
->rps
.client_boost
;
1083 dev_priv
->rps
.client_boost
= false;
1084 spin_unlock_irq(&dev_priv
->irq_lock
);
1086 /* Make sure we didn't queue anything we're not going to process. */
1087 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1089 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1092 mutex_lock(&dev_priv
->rps
.hw_lock
);
1094 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1096 adj
= dev_priv
->rps
.last_adj
;
1097 new_delay
= dev_priv
->rps
.cur_freq
;
1098 min
= dev_priv
->rps
.min_freq_softlimit
;
1099 max
= dev_priv
->rps
.max_freq_softlimit
;
1100 if (client_boost
|| any_waiters(dev_priv
))
1101 max
= dev_priv
->rps
.max_freq
;
1102 if (client_boost
&& new_delay
< dev_priv
->rps
.boost_freq
) {
1103 new_delay
= dev_priv
->rps
.boost_freq
;
1105 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1108 else /* CHV needs even encode values */
1109 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1111 * For better performance, jump directly
1112 * to RPe if we're below it.
1114 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1115 new_delay
= dev_priv
->rps
.efficient_freq
;
1118 } else if (client_boost
|| any_waiters(dev_priv
)) {
1120 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1121 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1122 new_delay
= dev_priv
->rps
.efficient_freq
;
1124 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1126 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1129 else /* CHV needs even encode values */
1130 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1131 } else { /* unknown event */
1135 dev_priv
->rps
.last_adj
= adj
;
1137 /* sysfs frequency interfaces may have snuck in while servicing the
1141 new_delay
= clamp_t(int, new_delay
, min
, max
);
1143 intel_set_rps(dev_priv
, new_delay
);
1145 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1150 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1152 * @work: workqueue struct
1154 * Doesn't actually do anything except notify userspace. As a consequence of
1155 * this event, userspace should try to remap the bad rows since statistically
1156 * it is likely the same row is more likely to go bad again.
1158 static void ivybridge_parity_work(struct work_struct
*work
)
1160 struct drm_i915_private
*dev_priv
=
1161 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1162 u32 error_status
, row
, bank
, subbank
;
1163 char *parity_event
[6];
1167 /* We must turn off DOP level clock gating to access the L3 registers.
1168 * In order to prevent a get/put style interface, acquire struct mutex
1169 * any time we access those registers.
1171 mutex_lock(&dev_priv
->drm
.struct_mutex
);
1173 /* If we've screwed up tracking, just let the interrupt fire again */
1174 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1177 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1178 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1179 POSTING_READ(GEN7_MISCCPCTL
);
1181 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1185 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1188 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1190 reg
= GEN7_L3CDERRST1(slice
);
1192 error_status
= I915_READ(reg
);
1193 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1194 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1195 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1197 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1200 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1201 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1202 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1203 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1204 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1205 parity_event
[5] = NULL
;
1207 kobject_uevent_env(&dev_priv
->drm
.primary
->kdev
->kobj
,
1208 KOBJ_CHANGE
, parity_event
);
1210 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1211 slice
, row
, bank
, subbank
);
1213 kfree(parity_event
[4]);
1214 kfree(parity_event
[3]);
1215 kfree(parity_event
[2]);
1216 kfree(parity_event
[1]);
1219 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1222 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1223 spin_lock_irq(&dev_priv
->irq_lock
);
1224 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1225 spin_unlock_irq(&dev_priv
->irq_lock
);
1227 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1230 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1233 if (!HAS_L3_DPF(dev_priv
))
1236 spin_lock(&dev_priv
->irq_lock
);
1237 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1238 spin_unlock(&dev_priv
->irq_lock
);
1240 iir
&= GT_PARITY_ERROR(dev_priv
);
1241 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1242 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1244 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1245 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1247 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1250 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1253 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1254 notify_ring(&dev_priv
->engine
[RCS
]);
1255 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1256 notify_ring(&dev_priv
->engine
[VCS
]);
1259 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1262 if (gt_iir
& GT_RENDER_USER_INTERRUPT
)
1263 notify_ring(&dev_priv
->engine
[RCS
]);
1264 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1265 notify_ring(&dev_priv
->engine
[VCS
]);
1266 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1267 notify_ring(&dev_priv
->engine
[BCS
]);
1269 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1270 GT_BSD_CS_ERROR_INTERRUPT
|
1271 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1272 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1274 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1275 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1278 static __always_inline
void
1279 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1281 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1282 notify_ring(engine
);
1283 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1284 tasklet_schedule(&engine
->irq_tasklet
);
1287 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1291 irqreturn_t ret
= IRQ_NONE
;
1293 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1294 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1296 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1299 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1302 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1303 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1305 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1308 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1311 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1312 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1314 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1317 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1320 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1321 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1322 if (gt_iir
[2] & dev_priv
->pm_rps_events
) {
1323 I915_WRITE_FW(GEN8_GT_IIR(2),
1324 gt_iir
[2] & dev_priv
->pm_rps_events
);
1327 DRM_ERROR("The master control interrupt lied (PM)!\n");
1333 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1337 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1338 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1339 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1340 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1344 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1345 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1346 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1347 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1351 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1352 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1354 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1355 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1358 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1362 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1364 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1366 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1372 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1376 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1382 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1386 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1388 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1390 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1392 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1398 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1402 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1408 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1412 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1414 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1416 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1422 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1426 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1428 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1430 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1437 * Get a bit mask of pins that have triggered, and which ones may be long.
1438 * This can be called multiple times with the same masks to accumulate
1439 * hotplug detection results from several registers.
1441 * Note that the caller is expected to zero out the masks initially.
1443 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1444 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1445 const u32 hpd
[HPD_NUM_PINS
],
1446 bool long_pulse_detect(enum port port
, u32 val
))
1451 for_each_hpd_pin(i
) {
1452 if ((hpd
[i
] & hotplug_trigger
) == 0)
1455 *pin_mask
|= BIT(i
);
1457 if (!intel_hpd_pin_to_port(i
, &port
))
1460 if (long_pulse_detect(port
, dig_hotplug_reg
))
1461 *long_mask
|= BIT(i
);
1464 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1465 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1469 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1471 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1474 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1476 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1479 #if defined(CONFIG_DEBUG_FS)
1480 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1482 uint32_t crc0
, uint32_t crc1
,
1483 uint32_t crc2
, uint32_t crc3
,
1486 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1487 struct intel_pipe_crc_entry
*entry
;
1490 spin_lock(&pipe_crc
->lock
);
1492 if (!pipe_crc
->entries
) {
1493 spin_unlock(&pipe_crc
->lock
);
1494 DRM_DEBUG_KMS("spurious interrupt\n");
1498 head
= pipe_crc
->head
;
1499 tail
= pipe_crc
->tail
;
1501 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1502 spin_unlock(&pipe_crc
->lock
);
1503 DRM_ERROR("CRC buffer overflowing\n");
1507 entry
= &pipe_crc
->entries
[head
];
1509 entry
->frame
= dev_priv
->drm
.driver
->get_vblank_counter(&dev_priv
->drm
,
1511 entry
->crc
[0] = crc0
;
1512 entry
->crc
[1] = crc1
;
1513 entry
->crc
[2] = crc2
;
1514 entry
->crc
[3] = crc3
;
1515 entry
->crc
[4] = crc4
;
1517 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1518 pipe_crc
->head
= head
;
1520 spin_unlock(&pipe_crc
->lock
);
1522 wake_up_interruptible(&pipe_crc
->wq
);
1526 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1528 uint32_t crc0
, uint32_t crc1
,
1529 uint32_t crc2
, uint32_t crc3
,
1534 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1537 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1538 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1542 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1545 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1546 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1547 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1548 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1549 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1550 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1553 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1556 uint32_t res1
, res2
;
1558 if (INTEL_GEN(dev_priv
) >= 3)
1559 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1563 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1564 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1568 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1569 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1570 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1571 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1575 /* The RPS events need forcewake, so we add them to a work queue and mask their
1576 * IMR bits until the work is done. Other interrupts can be processed without
1577 * the work queue. */
1578 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1580 if (pm_iir
& dev_priv
->pm_rps_events
) {
1581 spin_lock(&dev_priv
->irq_lock
);
1582 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1583 if (dev_priv
->rps
.interrupts_enabled
) {
1584 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1585 schedule_work(&dev_priv
->rps
.work
);
1587 spin_unlock(&dev_priv
->irq_lock
);
1590 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1593 if (HAS_VEBOX(dev_priv
)) {
1594 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1595 notify_ring(&dev_priv
->engine
[VECS
]);
1597 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1598 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1602 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1607 ret
= drm_handle_vblank(&dev_priv
->drm
, pipe
);
1609 intel_finish_page_flip_mmio(dev_priv
, pipe
);
1614 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1615 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1619 spin_lock(&dev_priv
->irq_lock
);
1621 if (!dev_priv
->display_irqs_enabled
) {
1622 spin_unlock(&dev_priv
->irq_lock
);
1626 for_each_pipe(dev_priv
, pipe
) {
1628 u32 mask
, iir_bit
= 0;
1631 * PIPESTAT bits get signalled even when the interrupt is
1632 * disabled with the mask bits, and some of the status bits do
1633 * not generate interrupts at all (like the underrun bit). Hence
1634 * we need to be careful that we only handle what we want to
1638 /* fifo underruns are filterered in the underrun handler. */
1639 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1643 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1646 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1649 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1653 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1658 reg
= PIPESTAT(pipe
);
1659 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1660 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1663 * Clear the PIPE*STAT regs before the IIR
1665 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1666 PIPESTAT_INT_STATUS_MASK
))
1667 I915_WRITE(reg
, pipe_stats
[pipe
]);
1669 spin_unlock(&dev_priv
->irq_lock
);
1672 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1673 u32 pipe_stats
[I915_MAX_PIPES
])
1677 for_each_pipe(dev_priv
, pipe
) {
1678 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1679 intel_pipe_handle_vblank(dev_priv
, pipe
))
1680 intel_check_page_flip(dev_priv
, pipe
);
1682 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
)
1683 intel_finish_page_flip_cs(dev_priv
, pipe
);
1685 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1686 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1688 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1689 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1692 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1693 gmbus_irq_handler(dev_priv
);
1696 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1698 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1701 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1703 return hotplug_status
;
1706 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1709 u32 pin_mask
= 0, long_mask
= 0;
1711 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1712 IS_CHERRYVIEW(dev_priv
)) {
1713 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1715 if (hotplug_trigger
) {
1716 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1717 hotplug_trigger
, hpd_status_g4x
,
1718 i9xx_port_hotplug_long_detect
);
1720 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1723 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1724 dp_aux_irq_handler(dev_priv
);
1726 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1728 if (hotplug_trigger
) {
1729 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1730 hotplug_trigger
, hpd_status_i915
,
1731 i9xx_port_hotplug_long_detect
);
1732 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1737 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1739 struct drm_device
*dev
= arg
;
1740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1741 irqreturn_t ret
= IRQ_NONE
;
1743 if (!intel_irqs_enabled(dev_priv
))
1746 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1747 disable_rpm_wakeref_asserts(dev_priv
);
1750 u32 iir
, gt_iir
, pm_iir
;
1751 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1752 u32 hotplug_status
= 0;
1755 gt_iir
= I915_READ(GTIIR
);
1756 pm_iir
= I915_READ(GEN6_PMIIR
);
1757 iir
= I915_READ(VLV_IIR
);
1759 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1765 * Theory on interrupt generation, based on empirical evidence:
1767 * x = ((VLV_IIR & VLV_IER) ||
1768 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1769 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1771 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1772 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1773 * guarantee the CPU interrupt will be raised again even if we
1774 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1775 * bits this time around.
1777 I915_WRITE(VLV_MASTER_IER
, 0);
1778 ier
= I915_READ(VLV_IER
);
1779 I915_WRITE(VLV_IER
, 0);
1782 I915_WRITE(GTIIR
, gt_iir
);
1784 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1786 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1787 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1789 /* Call regardless, as some status bits might not be
1790 * signalled in iir */
1791 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1794 * VLV_IIR is single buffered, and reflects the level
1795 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1798 I915_WRITE(VLV_IIR
, iir
);
1800 I915_WRITE(VLV_IER
, ier
);
1801 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1802 POSTING_READ(VLV_MASTER_IER
);
1805 snb_gt_irq_handler(dev_priv
, gt_iir
);
1807 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1810 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1812 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1815 enable_rpm_wakeref_asserts(dev_priv
);
1820 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1822 struct drm_device
*dev
= arg
;
1823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1824 irqreturn_t ret
= IRQ_NONE
;
1826 if (!intel_irqs_enabled(dev_priv
))
1829 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1830 disable_rpm_wakeref_asserts(dev_priv
);
1833 u32 master_ctl
, iir
;
1835 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1836 u32 hotplug_status
= 0;
1839 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1840 iir
= I915_READ(VLV_IIR
);
1842 if (master_ctl
== 0 && iir
== 0)
1848 * Theory on interrupt generation, based on empirical evidence:
1850 * x = ((VLV_IIR & VLV_IER) ||
1851 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1852 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1854 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1855 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1856 * guarantee the CPU interrupt will be raised again even if we
1857 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1858 * bits this time around.
1860 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1861 ier
= I915_READ(VLV_IER
);
1862 I915_WRITE(VLV_IER
, 0);
1864 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1866 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1867 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1869 /* Call regardless, as some status bits might not be
1870 * signalled in iir */
1871 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1874 * VLV_IIR is single buffered, and reflects the level
1875 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1878 I915_WRITE(VLV_IIR
, iir
);
1880 I915_WRITE(VLV_IER
, ier
);
1881 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1882 POSTING_READ(GEN8_MASTER_IRQ
);
1884 gen8_gt_irq_handler(dev_priv
, gt_iir
);
1887 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1889 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1892 enable_rpm_wakeref_asserts(dev_priv
);
1897 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1898 u32 hotplug_trigger
,
1899 const u32 hpd
[HPD_NUM_PINS
])
1901 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1904 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1905 * unless we touch the hotplug register, even if hotplug_trigger is
1906 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1909 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1910 if (!hotplug_trigger
) {
1911 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1912 PORTD_HOTPLUG_STATUS_MASK
|
1913 PORTC_HOTPLUG_STATUS_MASK
|
1914 PORTB_HOTPLUG_STATUS_MASK
;
1915 dig_hotplug_reg
&= ~mask
;
1918 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1919 if (!hotplug_trigger
)
1922 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1923 dig_hotplug_reg
, hpd
,
1924 pch_port_hotplug_long_detect
);
1926 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1929 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1932 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1934 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
1936 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1937 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1938 SDE_AUDIO_POWER_SHIFT
);
1939 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1943 if (pch_iir
& SDE_AUX_MASK
)
1944 dp_aux_irq_handler(dev_priv
);
1946 if (pch_iir
& SDE_GMBUS
)
1947 gmbus_irq_handler(dev_priv
);
1949 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1950 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1952 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1953 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1955 if (pch_iir
& SDE_POISON
)
1956 DRM_ERROR("PCH poison interrupt\n");
1958 if (pch_iir
& SDE_FDI_MASK
)
1959 for_each_pipe(dev_priv
, pipe
)
1960 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1962 I915_READ(FDI_RX_IIR(pipe
)));
1964 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1965 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1967 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1968 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1970 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1971 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1973 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1974 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1977 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
1979 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1982 if (err_int
& ERR_INT_POISON
)
1983 DRM_ERROR("Poison interrupt\n");
1985 for_each_pipe(dev_priv
, pipe
) {
1986 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
1987 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1989 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1990 if (IS_IVYBRIDGE(dev_priv
))
1991 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
1993 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
1997 I915_WRITE(GEN7_ERR_INT
, err_int
);
2000 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2002 u32 serr_int
= I915_READ(SERR_INT
);
2004 if (serr_int
& SERR_INT_POISON
)
2005 DRM_ERROR("PCH poison interrupt\n");
2007 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2008 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2010 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2011 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2013 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2014 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2016 I915_WRITE(SERR_INT
, serr_int
);
2019 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2022 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2024 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2026 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2027 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2028 SDE_AUDIO_POWER_SHIFT_CPT
);
2029 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2033 if (pch_iir
& SDE_AUX_MASK_CPT
)
2034 dp_aux_irq_handler(dev_priv
);
2036 if (pch_iir
& SDE_GMBUS_CPT
)
2037 gmbus_irq_handler(dev_priv
);
2039 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2040 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2042 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2043 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2045 if (pch_iir
& SDE_FDI_MASK_CPT
)
2046 for_each_pipe(dev_priv
, pipe
)
2047 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2049 I915_READ(FDI_RX_IIR(pipe
)));
2051 if (pch_iir
& SDE_ERROR_CPT
)
2052 cpt_serr_int_handler(dev_priv
);
2055 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2057 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2058 ~SDE_PORTE_HOTPLUG_SPT
;
2059 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2060 u32 pin_mask
= 0, long_mask
= 0;
2062 if (hotplug_trigger
) {
2063 u32 dig_hotplug_reg
;
2065 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2066 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2068 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2069 dig_hotplug_reg
, hpd_spt
,
2070 spt_port_hotplug_long_detect
);
2073 if (hotplug2_trigger
) {
2074 u32 dig_hotplug_reg
;
2076 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2077 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2079 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2080 dig_hotplug_reg
, hpd_spt
,
2081 spt_port_hotplug2_long_detect
);
2085 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2087 if (pch_iir
& SDE_GMBUS_CPT
)
2088 gmbus_irq_handler(dev_priv
);
2091 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2092 u32 hotplug_trigger
,
2093 const u32 hpd
[HPD_NUM_PINS
])
2095 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2097 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2098 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2100 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2101 dig_hotplug_reg
, hpd
,
2102 ilk_port_hotplug_long_detect
);
2104 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2107 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2111 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2113 if (hotplug_trigger
)
2114 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2116 if (de_iir
& DE_AUX_CHANNEL_A
)
2117 dp_aux_irq_handler(dev_priv
);
2119 if (de_iir
& DE_GSE
)
2120 intel_opregion_asle_intr(dev_priv
);
2122 if (de_iir
& DE_POISON
)
2123 DRM_ERROR("Poison interrupt\n");
2125 for_each_pipe(dev_priv
, pipe
) {
2126 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2127 intel_pipe_handle_vblank(dev_priv
, pipe
))
2128 intel_check_page_flip(dev_priv
, pipe
);
2130 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2131 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2133 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2134 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2136 /* plane/pipes map 1:1 on ilk+ */
2137 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
))
2138 intel_finish_page_flip_cs(dev_priv
, pipe
);
2141 /* check event from PCH */
2142 if (de_iir
& DE_PCH_EVENT
) {
2143 u32 pch_iir
= I915_READ(SDEIIR
);
2145 if (HAS_PCH_CPT(dev_priv
))
2146 cpt_irq_handler(dev_priv
, pch_iir
);
2148 ibx_irq_handler(dev_priv
, pch_iir
);
2150 /* should clear PCH hotplug event before clear CPU irq */
2151 I915_WRITE(SDEIIR
, pch_iir
);
2154 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2155 ironlake_rps_change_irq_handler(dev_priv
);
2158 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2162 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2164 if (hotplug_trigger
)
2165 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2167 if (de_iir
& DE_ERR_INT_IVB
)
2168 ivb_err_int_handler(dev_priv
);
2170 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2171 dp_aux_irq_handler(dev_priv
);
2173 if (de_iir
& DE_GSE_IVB
)
2174 intel_opregion_asle_intr(dev_priv
);
2176 for_each_pipe(dev_priv
, pipe
) {
2177 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2178 intel_pipe_handle_vblank(dev_priv
, pipe
))
2179 intel_check_page_flip(dev_priv
, pipe
);
2181 /* plane/pipes map 1:1 on ilk+ */
2182 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
))
2183 intel_finish_page_flip_cs(dev_priv
, pipe
);
2186 /* check event from PCH */
2187 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2188 u32 pch_iir
= I915_READ(SDEIIR
);
2190 cpt_irq_handler(dev_priv
, pch_iir
);
2192 /* clear PCH hotplug event before clear CPU irq */
2193 I915_WRITE(SDEIIR
, pch_iir
);
2198 * To handle irqs with the minimum potential races with fresh interrupts, we:
2199 * 1 - Disable Master Interrupt Control.
2200 * 2 - Find the source(s) of the interrupt.
2201 * 3 - Clear the Interrupt Identity bits (IIR).
2202 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2203 * 5 - Re-enable Master Interrupt Control.
2205 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2207 struct drm_device
*dev
= arg
;
2208 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2209 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2210 irqreturn_t ret
= IRQ_NONE
;
2212 if (!intel_irqs_enabled(dev_priv
))
2215 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2216 disable_rpm_wakeref_asserts(dev_priv
);
2218 /* disable master interrupt before clearing iir */
2219 de_ier
= I915_READ(DEIER
);
2220 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2221 POSTING_READ(DEIER
);
2223 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2224 * interrupts will will be stored on its back queue, and then we'll be
2225 * able to process them after we restore SDEIER (as soon as we restore
2226 * it, we'll get an interrupt if SDEIIR still has something to process
2227 * due to its back queue). */
2228 if (!HAS_PCH_NOP(dev_priv
)) {
2229 sde_ier
= I915_READ(SDEIER
);
2230 I915_WRITE(SDEIER
, 0);
2231 POSTING_READ(SDEIER
);
2234 /* Find, clear, then process each source of interrupt */
2236 gt_iir
= I915_READ(GTIIR
);
2238 I915_WRITE(GTIIR
, gt_iir
);
2240 if (INTEL_GEN(dev_priv
) >= 6)
2241 snb_gt_irq_handler(dev_priv
, gt_iir
);
2243 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2246 de_iir
= I915_READ(DEIIR
);
2248 I915_WRITE(DEIIR
, de_iir
);
2250 if (INTEL_GEN(dev_priv
) >= 7)
2251 ivb_display_irq_handler(dev_priv
, de_iir
);
2253 ilk_display_irq_handler(dev_priv
, de_iir
);
2256 if (INTEL_GEN(dev_priv
) >= 6) {
2257 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2259 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2261 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2265 I915_WRITE(DEIER
, de_ier
);
2266 POSTING_READ(DEIER
);
2267 if (!HAS_PCH_NOP(dev_priv
)) {
2268 I915_WRITE(SDEIER
, sde_ier
);
2269 POSTING_READ(SDEIER
);
2272 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2273 enable_rpm_wakeref_asserts(dev_priv
);
2278 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2279 u32 hotplug_trigger
,
2280 const u32 hpd
[HPD_NUM_PINS
])
2282 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2284 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2285 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2287 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2288 dig_hotplug_reg
, hpd
,
2289 bxt_port_hotplug_long_detect
);
2291 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2295 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2297 irqreturn_t ret
= IRQ_NONE
;
2301 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2302 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2304 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2306 if (iir
& GEN8_DE_MISC_GSE
)
2307 intel_opregion_asle_intr(dev_priv
);
2309 DRM_ERROR("Unexpected DE Misc interrupt\n");
2312 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2315 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2316 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2321 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2324 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2325 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2326 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2327 GEN9_AUX_CHANNEL_C
|
2330 if (iir
& tmp_mask
) {
2331 dp_aux_irq_handler(dev_priv
);
2335 if (IS_BROXTON(dev_priv
)) {
2336 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2338 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2342 } else if (IS_BROADWELL(dev_priv
)) {
2343 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2345 ilk_hpd_irq_handler(dev_priv
,
2351 if (IS_BROXTON(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2352 gmbus_irq_handler(dev_priv
);
2357 DRM_ERROR("Unexpected DE Port interrupt\n");
2360 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2363 for_each_pipe(dev_priv
, pipe
) {
2364 u32 flip_done
, fault_errors
;
2366 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2369 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2371 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2376 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2378 if (iir
& GEN8_PIPE_VBLANK
&&
2379 intel_pipe_handle_vblank(dev_priv
, pipe
))
2380 intel_check_page_flip(dev_priv
, pipe
);
2383 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2384 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2386 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2389 intel_finish_page_flip_cs(dev_priv
, pipe
);
2391 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2392 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2394 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2395 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2398 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2399 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2401 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2404 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2409 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2410 master_ctl
& GEN8_DE_PCH_IRQ
) {
2412 * FIXME(BDW): Assume for now that the new interrupt handling
2413 * scheme also closed the SDE interrupt handling race we've seen
2414 * on older pch-split platforms. But this needs testing.
2416 iir
= I915_READ(SDEIIR
);
2418 I915_WRITE(SDEIIR
, iir
);
2421 if (HAS_PCH_SPT(dev_priv
) || HAS_PCH_KBP(dev_priv
))
2422 spt_irq_handler(dev_priv
, iir
);
2424 cpt_irq_handler(dev_priv
, iir
);
2427 * Like on previous PCH there seems to be something
2428 * fishy going on with forwarding PCH interrupts.
2430 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2437 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2439 struct drm_device
*dev
= arg
;
2440 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2445 if (!intel_irqs_enabled(dev_priv
))
2448 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2449 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2453 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2455 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2456 disable_rpm_wakeref_asserts(dev_priv
);
2458 /* Find, clear, then process each source of interrupt */
2459 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2460 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2461 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2463 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2464 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2466 enable_rpm_wakeref_asserts(dev_priv
);
2471 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
)
2474 * Notify all waiters for GPU completion events that reset state has
2475 * been changed, and that they need to restart their wait after
2476 * checking for potential errors (and bail out to drop locks if there is
2477 * a gpu reset pending so that i915_error_work_func can acquire them).
2480 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2481 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
2483 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2484 wake_up_all(&dev_priv
->pending_flip_queue
);
2488 * i915_reset_and_wakeup - do process context error handling work
2489 * @dev_priv: i915 device private
2491 * Fire an error uevent so userspace can see that a hang or error
2494 static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv
)
2496 struct kobject
*kobj
= &dev_priv
->drm
.primary
->kdev
->kobj
;
2497 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2498 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2499 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2502 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2505 * Note that there's only one work item which does gpu resets, so we
2506 * need not worry about concurrent gpu resets potentially incrementing
2507 * error->reset_counter twice. We only need to take care of another
2508 * racing irq/hangcheck declaring the gpu dead for a second time. A
2509 * quick check for that is good enough: schedule_work ensures the
2510 * correct ordering between hang detection and this work item, and since
2511 * the reset in-progress bit is only ever set by code outside of this
2512 * work we don't need to worry about any other races.
2514 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
2515 DRM_DEBUG_DRIVER("resetting chip\n");
2516 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2519 * In most cases it's guaranteed that we get here with an RPM
2520 * reference held, for example because there is a pending GPU
2521 * request that won't finish until the reset is done. This
2522 * isn't the case at least when we get here by doing a
2523 * simulated reset via debugs, so get an RPM reference.
2525 intel_runtime_pm_get(dev_priv
);
2527 intel_prepare_reset(dev_priv
);
2530 * All state reset _must_ be completed before we update the
2531 * reset counter, for otherwise waiters might miss the reset
2532 * pending state and not properly drop locks, resulting in
2533 * deadlocks with the reset work.
2535 ret
= i915_reset(dev_priv
);
2537 intel_finish_reset(dev_priv
);
2539 intel_runtime_pm_put(dev_priv
);
2542 kobject_uevent_env(kobj
,
2543 KOBJ_CHANGE
, reset_done_event
);
2546 * Note: The wake_up also serves as a memory barrier so that
2547 * waiters see the update value of the reset counter atomic_t.
2549 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2553 static void i915_report_and_clear_eir(struct drm_i915_private
*dev_priv
)
2555 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2556 u32 eir
= I915_READ(EIR
);
2562 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2564 i915_get_extra_instdone(dev_priv
, instdone
);
2566 if (IS_G4X(dev_priv
)) {
2567 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2568 u32 ipeir
= I915_READ(IPEIR_I965
);
2570 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2571 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2572 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2573 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2574 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2575 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2576 I915_WRITE(IPEIR_I965
, ipeir
);
2577 POSTING_READ(IPEIR_I965
);
2579 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2580 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2581 pr_err("page table error\n");
2582 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2583 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2584 POSTING_READ(PGTBL_ER
);
2588 if (!IS_GEN2(dev_priv
)) {
2589 if (eir
& I915_ERROR_PAGE_TABLE
) {
2590 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2591 pr_err("page table error\n");
2592 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2593 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2594 POSTING_READ(PGTBL_ER
);
2598 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2599 pr_err("memory refresh error:\n");
2600 for_each_pipe(dev_priv
, pipe
)
2601 pr_err("pipe %c stat: 0x%08x\n",
2602 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2603 /* pipestat has already been acked */
2605 if (eir
& I915_ERROR_INSTRUCTION
) {
2606 pr_err("instruction error\n");
2607 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2608 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2609 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2610 if (INTEL_GEN(dev_priv
) < 4) {
2611 u32 ipeir
= I915_READ(IPEIR
);
2613 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2614 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2615 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2616 I915_WRITE(IPEIR
, ipeir
);
2617 POSTING_READ(IPEIR
);
2619 u32 ipeir
= I915_READ(IPEIR_I965
);
2621 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2622 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2623 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2624 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2625 I915_WRITE(IPEIR_I965
, ipeir
);
2626 POSTING_READ(IPEIR_I965
);
2630 I915_WRITE(EIR
, eir
);
2632 eir
= I915_READ(EIR
);
2635 * some errors might have become stuck,
2638 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2639 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2640 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2645 * i915_handle_error - handle a gpu error
2646 * @dev_priv: i915 device private
2647 * @engine_mask: mask representing engines that are hung
2648 * Do some basic checking of register state at error time and
2649 * dump it to the syslog. Also call i915_capture_error_state() to make
2650 * sure we get a record and make it available in debugfs. Fire a uevent
2651 * so userspace knows something bad happened (should trigger collection
2652 * of a ring dump etc.).
2653 * @fmt: Error message format string
2655 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2657 const char *fmt
, ...)
2662 va_start(args
, fmt
);
2663 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2666 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2667 i915_report_and_clear_eir(dev_priv
);
2670 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2671 &dev_priv
->gpu_error
.reset_counter
);
2674 * Wakeup waiting processes so that the reset function
2675 * i915_reset_and_wakeup doesn't deadlock trying to grab
2676 * various locks. By bumping the reset counter first, the woken
2677 * processes will see a reset in progress and back off,
2678 * releasing their locks and then wait for the reset completion.
2679 * We must do this for _all_ gpu waiters that might hold locks
2680 * that the reset work needs to acquire.
2682 * Note: The wake_up serves as the required memory barrier to
2683 * ensure that the waiters see the updated value of the reset
2686 i915_error_wake_up(dev_priv
);
2689 i915_reset_and_wakeup(dev_priv
);
2692 /* Called from drm generic code, passed 'crtc' which
2693 * we use as a pipe index
2695 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2697 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2698 unsigned long irqflags
;
2700 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2701 if (INTEL_INFO(dev
)->gen
>= 4)
2702 i915_enable_pipestat(dev_priv
, pipe
,
2703 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2705 i915_enable_pipestat(dev_priv
, pipe
,
2706 PIPE_VBLANK_INTERRUPT_STATUS
);
2707 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2712 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2714 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2715 unsigned long irqflags
;
2716 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2717 DE_PIPE_VBLANK(pipe
);
2719 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2720 ilk_enable_display_irq(dev_priv
, bit
);
2721 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2726 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2728 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2729 unsigned long irqflags
;
2731 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2732 i915_enable_pipestat(dev_priv
, pipe
,
2733 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2734 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2739 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2741 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2742 unsigned long irqflags
;
2744 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2745 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2746 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2751 /* Called from drm generic code, passed 'crtc' which
2752 * we use as a pipe index
2754 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2757 unsigned long irqflags
;
2759 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2760 i915_disable_pipestat(dev_priv
, pipe
,
2761 PIPE_VBLANK_INTERRUPT_STATUS
|
2762 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2763 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2766 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2769 unsigned long irqflags
;
2770 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2771 DE_PIPE_VBLANK(pipe
);
2773 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2774 ilk_disable_display_irq(dev_priv
, bit
);
2775 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2778 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2780 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2781 unsigned long irqflags
;
2783 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2784 i915_disable_pipestat(dev_priv
, pipe
,
2785 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2786 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2789 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2791 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2792 unsigned long irqflags
;
2794 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2795 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2796 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2800 ipehr_is_semaphore_wait(struct intel_engine_cs
*engine
, u32 ipehr
)
2802 if (INTEL_GEN(engine
->i915
) >= 8) {
2803 return (ipehr
>> 23) == 0x1c;
2805 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2806 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2807 MI_SEMAPHORE_REGISTER
);
2811 static struct intel_engine_cs
*
2812 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2815 struct drm_i915_private
*dev_priv
= engine
->i915
;
2816 struct intel_engine_cs
*signaller
;
2818 if (INTEL_GEN(dev_priv
) >= 8) {
2819 for_each_engine(signaller
, dev_priv
) {
2820 if (engine
== signaller
)
2823 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2827 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2829 for_each_engine(signaller
, dev_priv
) {
2830 if(engine
== signaller
)
2833 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2838 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2839 engine
->id
, ipehr
, offset
);
2844 static struct intel_engine_cs
*
2845 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2847 struct drm_i915_private
*dev_priv
= engine
->i915
;
2848 void __iomem
*vaddr
;
2849 u32 cmd
, ipehr
, head
;
2854 * This function does not support execlist mode - any attempt to
2855 * proceed further into this function will result in a kernel panic
2856 * when dereferencing ring->buffer, which is not set up in execlist
2859 * The correct way of doing it would be to derive the currently
2860 * executing ring buffer from the current context, which is derived
2861 * from the currently running request. Unfortunately, to get the
2862 * current request we would have to grab the struct_mutex before doing
2863 * anything else, which would be ill-advised since some other thread
2864 * might have grabbed it already and managed to hang itself, causing
2865 * the hang checker to deadlock.
2867 * Therefore, this function does not support execlist mode in its
2868 * current form. Just return NULL and move on.
2870 if (engine
->buffer
== NULL
)
2873 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2874 if (!ipehr_is_semaphore_wait(engine
, ipehr
))
2878 * HEAD is likely pointing to the dword after the actual command,
2879 * so scan backwards until we find the MBOX. But limit it to just 3
2880 * or 4 dwords depending on the semaphore wait command size.
2881 * Note that we don't care about ACTHD here since that might
2882 * point at at batch, and semaphores are always emitted into the
2883 * ringbuffer itself.
2885 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2886 backwards
= (INTEL_GEN(dev_priv
) >= 8) ? 5 : 4;
2887 vaddr
= (void __iomem
*)engine
->buffer
->vaddr
;
2889 for (i
= backwards
; i
; --i
) {
2891 * Be paranoid and presume the hw has gone off into the wild -
2892 * our ring is smaller than what the hardware (and hence
2893 * HEAD_ADDR) allows. Also handles wrap-around.
2895 head
&= engine
->buffer
->size
- 1;
2897 /* This here seems to blow up */
2898 cmd
= ioread32(vaddr
+ head
);
2908 *seqno
= ioread32(vaddr
+ head
+ 4) + 1;
2909 if (INTEL_GEN(dev_priv
) >= 8) {
2910 offset
= ioread32(vaddr
+ head
+ 12);
2912 offset
|= ioread32(vaddr
+ head
+ 8);
2914 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2917 static int semaphore_passed(struct intel_engine_cs
*engine
)
2919 struct drm_i915_private
*dev_priv
= engine
->i915
;
2920 struct intel_engine_cs
*signaller
;
2923 engine
->hangcheck
.deadlock
++;
2925 signaller
= semaphore_waits_for(engine
, &seqno
);
2926 if (signaller
== NULL
)
2929 /* Prevent pathological recursion due to driver bugs */
2930 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2933 if (i915_seqno_passed(intel_engine_get_seqno(signaller
), seqno
))
2936 /* cursory check for an unkickable deadlock */
2937 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2938 semaphore_passed(signaller
) < 0)
2944 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2946 struct intel_engine_cs
*engine
;
2948 for_each_engine(engine
, dev_priv
)
2949 engine
->hangcheck
.deadlock
= 0;
2952 static bool subunits_stuck(struct intel_engine_cs
*engine
)
2954 u32 instdone
[I915_NUM_INSTDONE_REG
];
2958 if (engine
->id
!= RCS
)
2961 i915_get_extra_instdone(engine
->i915
, instdone
);
2963 /* There might be unstable subunit states even when
2964 * actual head is not moving. Filter out the unstable ones by
2965 * accumulating the undone -> done transitions and only
2966 * consider those as progress.
2969 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
2970 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
2972 if (tmp
!= engine
->hangcheck
.instdone
[i
])
2975 engine
->hangcheck
.instdone
[i
] |= tmp
;
2981 static enum intel_engine_hangcheck_action
2982 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
2984 if (acthd
!= engine
->hangcheck
.acthd
) {
2986 /* Clear subunit states on head movement */
2987 memset(engine
->hangcheck
.instdone
, 0,
2988 sizeof(engine
->hangcheck
.instdone
));
2990 return HANGCHECK_ACTIVE
;
2993 if (!subunits_stuck(engine
))
2994 return HANGCHECK_ACTIVE
;
2996 return HANGCHECK_HUNG
;
2999 static enum intel_engine_hangcheck_action
3000 engine_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3002 struct drm_i915_private
*dev_priv
= engine
->i915
;
3003 enum intel_engine_hangcheck_action ha
;
3006 ha
= head_stuck(engine
, acthd
);
3007 if (ha
!= HANGCHECK_HUNG
)
3010 if (IS_GEN2(dev_priv
))
3011 return HANGCHECK_HUNG
;
3013 /* Is the chip hanging on a WAIT_FOR_EVENT?
3014 * If so we can simply poke the RB_WAIT bit
3015 * and break the hang. This should work on
3016 * all but the second generation chipsets.
3018 tmp
= I915_READ_CTL(engine
);
3019 if (tmp
& RING_WAIT
) {
3020 i915_handle_error(dev_priv
, 0,
3021 "Kicking stuck wait on %s",
3023 I915_WRITE_CTL(engine
, tmp
);
3024 return HANGCHECK_KICK
;
3027 if (INTEL_GEN(dev_priv
) >= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3028 switch (semaphore_passed(engine
)) {
3030 return HANGCHECK_HUNG
;
3032 i915_handle_error(dev_priv
, 0,
3033 "Kicking stuck semaphore on %s",
3035 I915_WRITE_CTL(engine
, tmp
);
3036 return HANGCHECK_KICK
;
3038 return HANGCHECK_WAIT
;
3042 return HANGCHECK_HUNG
;
3046 * This is called when the chip hasn't reported back with completed
3047 * batchbuffers in a long time. We keep track per ring seqno progress and
3048 * if there are no progress, hangcheck score for that ring is increased.
3049 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3050 * we kick the ring. If we see no progress on three subsequent calls
3051 * we assume chip is wedged and try to fix it by resetting the chip.
3053 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3055 struct drm_i915_private
*dev_priv
=
3056 container_of(work
, typeof(*dev_priv
),
3057 gpu_error
.hangcheck_work
.work
);
3058 struct intel_engine_cs
*engine
;
3059 unsigned int hung
= 0, stuck
= 0;
3064 #define ACTIVE_DECAY 15
3066 if (!i915
.enable_hangcheck
)
3069 if (!READ_ONCE(dev_priv
->gt
.awake
))
3072 /* As enabling the GPU requires fairly extensive mmio access,
3073 * periodically arm the mmio checker to see if we are triggering
3074 * any invalid access.
3076 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3078 for_each_engine(engine
, dev_priv
) {
3079 bool busy
= intel_engine_has_waiter(engine
);
3084 semaphore_clear_deadlocks(dev_priv
);
3086 /* We don't strictly need an irq-barrier here, as we are not
3087 * serving an interrupt request, be paranoid in case the
3088 * barrier has side-effects (such as preventing a broken
3089 * cacheline snoop) and so be sure that we can see the seqno
3090 * advance. If the seqno should stick, due to a stale
3091 * cacheline, we would erroneously declare the GPU hung.
3093 if (engine
->irq_seqno_barrier
)
3094 engine
->irq_seqno_barrier(engine
);
3096 acthd
= intel_engine_get_active_head(engine
);
3097 seqno
= intel_engine_get_seqno(engine
);
3098 submit
= READ_ONCE(engine
->last_submitted_seqno
);
3100 if (engine
->hangcheck
.seqno
== seqno
) {
3101 if (i915_seqno_passed(seqno
, submit
)) {
3102 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3104 /* Safeguard against driver failure */
3105 engine
->hangcheck
.score
+= BUSY
;
3108 /* We always increment the hangcheck score
3109 * if the engine is busy and still processing
3110 * the same request, so that no single request
3111 * can run indefinitely (such as a chain of
3112 * batches). The only time we do not increment
3113 * the hangcheck score on this ring, if this
3114 * engine is in a legitimate wait for another
3115 * engine. In that case the waiting engine is a
3116 * victim and we want to be sure we catch the
3117 * right culprit. Then every time we do kick
3118 * the ring, add a small increment to the
3119 * score so that we can catch a batch that is
3120 * being repeatedly kicked and so responsible
3121 * for stalling the machine.
3123 engine
->hangcheck
.action
=
3124 engine_stuck(engine
, acthd
);
3126 switch (engine
->hangcheck
.action
) {
3127 case HANGCHECK_IDLE
:
3128 case HANGCHECK_WAIT
:
3130 case HANGCHECK_ACTIVE
:
3131 engine
->hangcheck
.score
+= BUSY
;
3133 case HANGCHECK_KICK
:
3134 engine
->hangcheck
.score
+= KICK
;
3136 case HANGCHECK_HUNG
:
3137 engine
->hangcheck
.score
+= HUNG
;
3142 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3143 hung
|= intel_engine_flag(engine
);
3144 if (engine
->hangcheck
.action
!= HANGCHECK_HUNG
)
3145 stuck
|= intel_engine_flag(engine
);
3148 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3150 /* Gradually reduce the count so that we catch DoS
3151 * attempts across multiple batches.
3153 if (engine
->hangcheck
.score
> 0)
3154 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3155 if (engine
->hangcheck
.score
< 0)
3156 engine
->hangcheck
.score
= 0;
3158 /* Clear head and subunit states on seqno movement */
3161 memset(engine
->hangcheck
.instdone
, 0,
3162 sizeof(engine
->hangcheck
.instdone
));
3165 engine
->hangcheck
.seqno
= seqno
;
3166 engine
->hangcheck
.acthd
= acthd
;
3175 /* If some rings hung but others were still busy, only
3176 * blame the hanging rings in the synopsis.
3180 len
= scnprintf(msg
, sizeof(msg
),
3181 "%s on ", stuck
== hung
? "No progress" : "Hang");
3182 for_each_engine_masked(engine
, dev_priv
, hung
, tmp
)
3183 len
+= scnprintf(msg
+ len
, sizeof(msg
) - len
,
3184 "%s, ", engine
->name
);
3187 return i915_handle_error(dev_priv
, hung
, msg
);
3190 /* Reset timer in case GPU hangs without another request being added */
3192 i915_queue_hangcheck(dev_priv
);
3195 static void ibx_irq_reset(struct drm_device
*dev
)
3197 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3199 if (HAS_PCH_NOP(dev
))
3202 GEN5_IRQ_RESET(SDE
);
3204 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3205 I915_WRITE(SERR_INT
, 0xffffffff);
3209 * SDEIER is also touched by the interrupt handler to work around missed PCH
3210 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3211 * instead we unconditionally enable all PCH interrupt sources here, but then
3212 * only unmask them as needed with SDEIMR.
3214 * This function needs to be called before interrupts are enabled.
3216 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3218 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3220 if (HAS_PCH_NOP(dev
))
3223 WARN_ON(I915_READ(SDEIER
) != 0);
3224 I915_WRITE(SDEIER
, 0xffffffff);
3225 POSTING_READ(SDEIER
);
3228 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3230 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3233 if (INTEL_INFO(dev
)->gen
>= 6)
3234 GEN5_IRQ_RESET(GEN6_PM
);
3237 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3241 if (IS_CHERRYVIEW(dev_priv
))
3242 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3244 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3246 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
3247 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3249 for_each_pipe(dev_priv
, pipe
) {
3250 I915_WRITE(PIPESTAT(pipe
),
3251 PIPE_FIFO_UNDERRUN_STATUS
|
3252 PIPESTAT_INT_STATUS_MASK
);
3253 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
3256 GEN5_IRQ_RESET(VLV_
);
3257 dev_priv
->irq_mask
= ~0;
3260 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3266 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3267 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3269 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3270 for_each_pipe(dev_priv
, pipe
)
3271 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3273 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3274 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3275 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3276 if (IS_CHERRYVIEW(dev_priv
))
3277 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3279 WARN_ON(dev_priv
->irq_mask
!= ~0);
3281 dev_priv
->irq_mask
= ~enable_mask
;
3283 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3288 static void ironlake_irq_reset(struct drm_device
*dev
)
3290 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3292 I915_WRITE(HWSTAM
, 0xffffffff);
3296 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3298 gen5_gt_irq_reset(dev
);
3303 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3305 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3307 I915_WRITE(VLV_MASTER_IER
, 0);
3308 POSTING_READ(VLV_MASTER_IER
);
3310 gen5_gt_irq_reset(dev
);
3312 spin_lock_irq(&dev_priv
->irq_lock
);
3313 if (dev_priv
->display_irqs_enabled
)
3314 vlv_display_irq_reset(dev_priv
);
3315 spin_unlock_irq(&dev_priv
->irq_lock
);
3318 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3320 GEN8_IRQ_RESET_NDX(GT
, 0);
3321 GEN8_IRQ_RESET_NDX(GT
, 1);
3322 GEN8_IRQ_RESET_NDX(GT
, 2);
3323 GEN8_IRQ_RESET_NDX(GT
, 3);
3326 static void gen8_irq_reset(struct drm_device
*dev
)
3328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3331 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3332 POSTING_READ(GEN8_MASTER_IRQ
);
3334 gen8_gt_irq_reset(dev_priv
);
3336 for_each_pipe(dev_priv
, pipe
)
3337 if (intel_display_power_is_enabled(dev_priv
,
3338 POWER_DOMAIN_PIPE(pipe
)))
3339 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3341 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3342 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3343 GEN5_IRQ_RESET(GEN8_PCU_
);
3345 if (HAS_PCH_SPLIT(dev
))
3349 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3350 unsigned int pipe_mask
)
3352 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3355 spin_lock_irq(&dev_priv
->irq_lock
);
3356 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3357 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3358 dev_priv
->de_irq_mask
[pipe
],
3359 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3360 spin_unlock_irq(&dev_priv
->irq_lock
);
3363 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3364 unsigned int pipe_mask
)
3368 spin_lock_irq(&dev_priv
->irq_lock
);
3369 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3370 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3371 spin_unlock_irq(&dev_priv
->irq_lock
);
3373 /* make sure we're done processing display irqs */
3374 synchronize_irq(dev_priv
->drm
.irq
);
3377 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3379 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3381 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3382 POSTING_READ(GEN8_MASTER_IRQ
);
3384 gen8_gt_irq_reset(dev_priv
);
3386 GEN5_IRQ_RESET(GEN8_PCU_
);
3388 spin_lock_irq(&dev_priv
->irq_lock
);
3389 if (dev_priv
->display_irqs_enabled
)
3390 vlv_display_irq_reset(dev_priv
);
3391 spin_unlock_irq(&dev_priv
->irq_lock
);
3394 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3395 const u32 hpd
[HPD_NUM_PINS
])
3397 struct intel_encoder
*encoder
;
3398 u32 enabled_irqs
= 0;
3400 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
3401 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3402 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3404 return enabled_irqs
;
3407 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3409 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3411 if (HAS_PCH_IBX(dev_priv
)) {
3412 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3413 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3415 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3416 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3419 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3422 * Enable digital hotplug on the PCH, and configure the DP short pulse
3423 * duration to 2ms (which is the minimum in the Display Port spec).
3424 * The pulse duration bits are reserved on LPT+.
3426 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3427 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3428 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3429 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3430 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3432 * When CPU and PCH are on the same package, port A
3433 * HPD must be enabled in both north and south.
3435 if (HAS_PCH_LPT_LP(dev_priv
))
3436 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3437 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3440 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3442 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3444 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3445 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3447 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3449 /* Enable digital hotplug on the PCH */
3450 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3451 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3452 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3453 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3455 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3456 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3457 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3460 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3462 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3464 if (INTEL_GEN(dev_priv
) >= 8) {
3465 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3466 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3468 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3469 } else if (INTEL_GEN(dev_priv
) >= 7) {
3470 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3471 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3473 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3475 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3476 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3478 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3482 * Enable digital hotplug on the CPU, and configure the DP short pulse
3483 * duration to 2ms (which is the minimum in the Display Port spec)
3484 * The pulse duration bits are reserved on HSW+.
3486 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3487 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3488 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3489 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3491 ibx_hpd_irq_setup(dev_priv
);
3494 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3496 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3498 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3499 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3501 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3503 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3504 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3505 PORTA_HOTPLUG_ENABLE
;
3507 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3508 hotplug
, enabled_irqs
);
3509 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3512 * For BXT invert bit has to be set based on AOB design
3513 * for HPD detection logic, update it based on VBT fields.
3516 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3517 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3518 hotplug
|= BXT_DDIA_HPD_INVERT
;
3519 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3520 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3521 hotplug
|= BXT_DDIB_HPD_INVERT
;
3522 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3523 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3524 hotplug
|= BXT_DDIC_HPD_INVERT
;
3526 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3529 static void ibx_irq_postinstall(struct drm_device
*dev
)
3531 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3534 if (HAS_PCH_NOP(dev
))
3537 if (HAS_PCH_IBX(dev
))
3538 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3540 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3542 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3543 I915_WRITE(SDEIMR
, ~mask
);
3546 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3548 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3549 u32 pm_irqs
, gt_irqs
;
3551 pm_irqs
= gt_irqs
= 0;
3553 dev_priv
->gt_irq_mask
= ~0;
3554 if (HAS_L3_DPF(dev
)) {
3555 /* L3 parity interrupt is always unmasked. */
3556 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3557 gt_irqs
|= GT_PARITY_ERROR(dev
);
3560 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3562 gt_irqs
|= ILK_BSD_USER_INTERRUPT
;
3564 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3567 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3569 if (INTEL_INFO(dev
)->gen
>= 6) {
3571 * RPS interrupts will get enabled/disabled on demand when RPS
3572 * itself is enabled/disabled.
3575 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3577 dev_priv
->pm_irq_mask
= 0xffffffff;
3578 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3582 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3584 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3585 u32 display_mask
, extra_mask
;
3587 if (INTEL_INFO(dev
)->gen
>= 7) {
3588 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3589 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3590 DE_PLANEB_FLIP_DONE_IVB
|
3591 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3592 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3593 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3594 DE_DP_A_HOTPLUG_IVB
);
3596 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3597 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3599 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3601 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3602 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3606 dev_priv
->irq_mask
= ~display_mask
;
3608 I915_WRITE(HWSTAM
, 0xeffe);
3610 ibx_irq_pre_postinstall(dev
);
3612 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3614 gen5_gt_irq_postinstall(dev
);
3616 ibx_irq_postinstall(dev
);
3618 if (IS_IRONLAKE_M(dev
)) {
3619 /* Enable PCU event interrupts
3621 * spinlocking not required here for correctness since interrupt
3622 * setup is guaranteed to run in single-threaded context. But we
3623 * need it to make the assert_spin_locked happy. */
3624 spin_lock_irq(&dev_priv
->irq_lock
);
3625 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3626 spin_unlock_irq(&dev_priv
->irq_lock
);
3632 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3634 assert_spin_locked(&dev_priv
->irq_lock
);
3636 if (dev_priv
->display_irqs_enabled
)
3639 dev_priv
->display_irqs_enabled
= true;
3641 if (intel_irqs_enabled(dev_priv
)) {
3642 vlv_display_irq_reset(dev_priv
);
3643 vlv_display_irq_postinstall(dev_priv
);
3647 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3649 assert_spin_locked(&dev_priv
->irq_lock
);
3651 if (!dev_priv
->display_irqs_enabled
)
3654 dev_priv
->display_irqs_enabled
= false;
3656 if (intel_irqs_enabled(dev_priv
))
3657 vlv_display_irq_reset(dev_priv
);
3661 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3663 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3665 gen5_gt_irq_postinstall(dev
);
3667 spin_lock_irq(&dev_priv
->irq_lock
);
3668 if (dev_priv
->display_irqs_enabled
)
3669 vlv_display_irq_postinstall(dev_priv
);
3670 spin_unlock_irq(&dev_priv
->irq_lock
);
3672 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3673 POSTING_READ(VLV_MASTER_IER
);
3678 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3680 /* These are interrupts we'll toggle with the ring mask register */
3681 uint32_t gt_interrupts
[] = {
3682 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3683 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3684 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3685 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3686 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3687 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3688 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3689 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3691 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3692 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3695 if (HAS_L3_DPF(dev_priv
))
3696 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3698 dev_priv
->pm_irq_mask
= 0xffffffff;
3699 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3700 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3702 * RPS interrupts will get enabled/disabled on demand when RPS itself
3703 * is enabled/disabled.
3705 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3706 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3709 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3711 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3712 uint32_t de_pipe_enables
;
3713 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3714 u32 de_port_enables
;
3715 u32 de_misc_masked
= GEN8_DE_MISC_GSE
;
3718 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3719 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3720 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3721 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3723 if (IS_BROXTON(dev_priv
))
3724 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3726 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3727 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3730 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3731 GEN8_PIPE_FIFO_UNDERRUN
;
3733 de_port_enables
= de_port_masked
;
3734 if (IS_BROXTON(dev_priv
))
3735 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3736 else if (IS_BROADWELL(dev_priv
))
3737 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3739 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3740 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3741 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3743 for_each_pipe(dev_priv
, pipe
)
3744 if (intel_display_power_is_enabled(dev_priv
,
3745 POWER_DOMAIN_PIPE(pipe
)))
3746 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3747 dev_priv
->de_irq_mask
[pipe
],
3750 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3751 GEN5_IRQ_INIT(GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3754 static int gen8_irq_postinstall(struct drm_device
*dev
)
3756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3758 if (HAS_PCH_SPLIT(dev
))
3759 ibx_irq_pre_postinstall(dev
);
3761 gen8_gt_irq_postinstall(dev_priv
);
3762 gen8_de_irq_postinstall(dev_priv
);
3764 if (HAS_PCH_SPLIT(dev
))
3765 ibx_irq_postinstall(dev
);
3767 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3768 POSTING_READ(GEN8_MASTER_IRQ
);
3773 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3775 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3777 gen8_gt_irq_postinstall(dev_priv
);
3779 spin_lock_irq(&dev_priv
->irq_lock
);
3780 if (dev_priv
->display_irqs_enabled
)
3781 vlv_display_irq_postinstall(dev_priv
);
3782 spin_unlock_irq(&dev_priv
->irq_lock
);
3784 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3785 POSTING_READ(GEN8_MASTER_IRQ
);
3790 static void gen8_irq_uninstall(struct drm_device
*dev
)
3792 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3797 gen8_irq_reset(dev
);
3800 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3802 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3807 I915_WRITE(VLV_MASTER_IER
, 0);
3808 POSTING_READ(VLV_MASTER_IER
);
3810 gen5_gt_irq_reset(dev
);
3812 I915_WRITE(HWSTAM
, 0xffffffff);
3814 spin_lock_irq(&dev_priv
->irq_lock
);
3815 if (dev_priv
->display_irqs_enabled
)
3816 vlv_display_irq_reset(dev_priv
);
3817 spin_unlock_irq(&dev_priv
->irq_lock
);
3820 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3822 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3827 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3828 POSTING_READ(GEN8_MASTER_IRQ
);
3830 gen8_gt_irq_reset(dev_priv
);
3832 GEN5_IRQ_RESET(GEN8_PCU_
);
3834 spin_lock_irq(&dev_priv
->irq_lock
);
3835 if (dev_priv
->display_irqs_enabled
)
3836 vlv_display_irq_reset(dev_priv
);
3837 spin_unlock_irq(&dev_priv
->irq_lock
);
3840 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3842 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3847 ironlake_irq_reset(dev
);
3850 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3852 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3855 for_each_pipe(dev_priv
, pipe
)
3856 I915_WRITE(PIPESTAT(pipe
), 0);
3857 I915_WRITE16(IMR
, 0xffff);
3858 I915_WRITE16(IER
, 0x0);
3859 POSTING_READ16(IER
);
3862 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3864 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3867 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3869 /* Unmask the interrupts that we always want on. */
3870 dev_priv
->irq_mask
=
3871 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3872 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3873 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3874 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3875 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3878 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3879 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3880 I915_USER_INTERRUPT
);
3881 POSTING_READ16(IER
);
3883 /* Interrupt setup is already guaranteed to be single-threaded, this is
3884 * just to make the assert_spin_locked check happy. */
3885 spin_lock_irq(&dev_priv
->irq_lock
);
3886 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3887 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3888 spin_unlock_irq(&dev_priv
->irq_lock
);
3894 * Returns true when a page flip has completed.
3896 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3897 int plane
, int pipe
, u32 iir
)
3899 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3901 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3904 if ((iir
& flip_pending
) == 0)
3905 goto check_page_flip
;
3907 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3908 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3909 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3910 * the flip is completed (no longer pending). Since this doesn't raise
3911 * an interrupt per se, we watch for the change at vblank.
3913 if (I915_READ16(ISR
) & flip_pending
)
3914 goto check_page_flip
;
3916 intel_finish_page_flip_cs(dev_priv
, pipe
);
3920 intel_check_page_flip(dev_priv
, pipe
);
3924 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3926 struct drm_device
*dev
= arg
;
3927 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3932 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3933 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3936 if (!intel_irqs_enabled(dev_priv
))
3939 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3940 disable_rpm_wakeref_asserts(dev_priv
);
3943 iir
= I915_READ16(IIR
);
3947 while (iir
& ~flip_mask
) {
3948 /* Can't rely on pipestat interrupt bit in iir as it might
3949 * have been cleared after the pipestat interrupt was received.
3950 * It doesn't set the bit in iir again, but it still produces
3951 * interrupts (for non-MSI).
3953 spin_lock(&dev_priv
->irq_lock
);
3954 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3955 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
3957 for_each_pipe(dev_priv
, pipe
) {
3958 i915_reg_t reg
= PIPESTAT(pipe
);
3959 pipe_stats
[pipe
] = I915_READ(reg
);
3962 * Clear the PIPE*STAT regs before the IIR
3964 if (pipe_stats
[pipe
] & 0x8000ffff)
3965 I915_WRITE(reg
, pipe_stats
[pipe
]);
3967 spin_unlock(&dev_priv
->irq_lock
);
3969 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3970 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3972 if (iir
& I915_USER_INTERRUPT
)
3973 notify_ring(&dev_priv
->engine
[RCS
]);
3975 for_each_pipe(dev_priv
, pipe
) {
3977 if (HAS_FBC(dev_priv
))
3980 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3981 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
3982 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3984 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3985 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
3987 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3988 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
3997 enable_rpm_wakeref_asserts(dev_priv
);
4002 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4004 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4007 for_each_pipe(dev_priv
, pipe
) {
4008 /* Clear enable bits; then clear status bits */
4009 I915_WRITE(PIPESTAT(pipe
), 0);
4010 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4012 I915_WRITE16(IMR
, 0xffff);
4013 I915_WRITE16(IER
, 0x0);
4014 I915_WRITE16(IIR
, I915_READ16(IIR
));
4017 static void i915_irq_preinstall(struct drm_device
* dev
)
4019 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4022 if (I915_HAS_HOTPLUG(dev
)) {
4023 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4024 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4027 I915_WRITE16(HWSTAM
, 0xeffe);
4028 for_each_pipe(dev_priv
, pipe
)
4029 I915_WRITE(PIPESTAT(pipe
), 0);
4030 I915_WRITE(IMR
, 0xffffffff);
4031 I915_WRITE(IER
, 0x0);
4035 static int i915_irq_postinstall(struct drm_device
*dev
)
4037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4040 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4042 /* Unmask the interrupts that we always want on. */
4043 dev_priv
->irq_mask
=
4044 ~(I915_ASLE_INTERRUPT
|
4045 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4046 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4047 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4048 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4051 I915_ASLE_INTERRUPT
|
4052 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4053 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4054 I915_USER_INTERRUPT
;
4056 if (I915_HAS_HOTPLUG(dev
)) {
4057 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4058 POSTING_READ(PORT_HOTPLUG_EN
);
4060 /* Enable in IER... */
4061 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4062 /* and unmask in IMR */
4063 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4066 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4067 I915_WRITE(IER
, enable_mask
);
4070 i915_enable_asle_pipestat(dev_priv
);
4072 /* Interrupt setup is already guaranteed to be single-threaded, this is
4073 * just to make the assert_spin_locked check happy. */
4074 spin_lock_irq(&dev_priv
->irq_lock
);
4075 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4076 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4077 spin_unlock_irq(&dev_priv
->irq_lock
);
4083 * Returns true when a page flip has completed.
4085 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
4086 int plane
, int pipe
, u32 iir
)
4088 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4090 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
4093 if ((iir
& flip_pending
) == 0)
4094 goto check_page_flip
;
4096 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4097 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4098 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4099 * the flip is completed (no longer pending). Since this doesn't raise
4100 * an interrupt per se, we watch for the change at vblank.
4102 if (I915_READ(ISR
) & flip_pending
)
4103 goto check_page_flip
;
4105 intel_finish_page_flip_cs(dev_priv
, pipe
);
4109 intel_check_page_flip(dev_priv
, pipe
);
4113 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4115 struct drm_device
*dev
= arg
;
4116 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4117 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4119 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4120 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4121 int pipe
, ret
= IRQ_NONE
;
4123 if (!intel_irqs_enabled(dev_priv
))
4126 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4127 disable_rpm_wakeref_asserts(dev_priv
);
4129 iir
= I915_READ(IIR
);
4131 bool irq_received
= (iir
& ~flip_mask
) != 0;
4132 bool blc_event
= false;
4134 /* Can't rely on pipestat interrupt bit in iir as it might
4135 * have been cleared after the pipestat interrupt was received.
4136 * It doesn't set the bit in iir again, but it still produces
4137 * interrupts (for non-MSI).
4139 spin_lock(&dev_priv
->irq_lock
);
4140 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4141 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4143 for_each_pipe(dev_priv
, pipe
) {
4144 i915_reg_t reg
= PIPESTAT(pipe
);
4145 pipe_stats
[pipe
] = I915_READ(reg
);
4147 /* Clear the PIPE*STAT regs before the IIR */
4148 if (pipe_stats
[pipe
] & 0x8000ffff) {
4149 I915_WRITE(reg
, pipe_stats
[pipe
]);
4150 irq_received
= true;
4153 spin_unlock(&dev_priv
->irq_lock
);
4158 /* Consume port. Then clear IIR or we'll miss events */
4159 if (I915_HAS_HOTPLUG(dev_priv
) &&
4160 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4161 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4163 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4166 I915_WRITE(IIR
, iir
& ~flip_mask
);
4167 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4169 if (iir
& I915_USER_INTERRUPT
)
4170 notify_ring(&dev_priv
->engine
[RCS
]);
4172 for_each_pipe(dev_priv
, pipe
) {
4174 if (HAS_FBC(dev_priv
))
4177 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4178 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4179 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4181 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4184 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4185 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4187 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4188 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4192 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4193 intel_opregion_asle_intr(dev_priv
);
4195 /* With MSI, interrupts are only generated when iir
4196 * transitions from zero to nonzero. If another bit got
4197 * set while we were handling the existing iir bits, then
4198 * we would never get another interrupt.
4200 * This is fine on non-MSI as well, as if we hit this path
4201 * we avoid exiting the interrupt handler only to generate
4204 * Note that for MSI this could cause a stray interrupt report
4205 * if an interrupt landed in the time between writing IIR and
4206 * the posting read. This should be rare enough to never
4207 * trigger the 99% of 100,000 interrupts test for disabling
4212 } while (iir
& ~flip_mask
);
4214 enable_rpm_wakeref_asserts(dev_priv
);
4219 static void i915_irq_uninstall(struct drm_device
* dev
)
4221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4224 if (I915_HAS_HOTPLUG(dev
)) {
4225 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4226 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4229 I915_WRITE16(HWSTAM
, 0xffff);
4230 for_each_pipe(dev_priv
, pipe
) {
4231 /* Clear enable bits; then clear status bits */
4232 I915_WRITE(PIPESTAT(pipe
), 0);
4233 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4235 I915_WRITE(IMR
, 0xffffffff);
4236 I915_WRITE(IER
, 0x0);
4238 I915_WRITE(IIR
, I915_READ(IIR
));
4241 static void i965_irq_preinstall(struct drm_device
* dev
)
4243 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4246 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4247 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4249 I915_WRITE(HWSTAM
, 0xeffe);
4250 for_each_pipe(dev_priv
, pipe
)
4251 I915_WRITE(PIPESTAT(pipe
), 0);
4252 I915_WRITE(IMR
, 0xffffffff);
4253 I915_WRITE(IER
, 0x0);
4257 static int i965_irq_postinstall(struct drm_device
*dev
)
4259 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4263 /* Unmask the interrupts that we always want on. */
4264 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4265 I915_DISPLAY_PORT_INTERRUPT
|
4266 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4267 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4268 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4269 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4270 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4272 enable_mask
= ~dev_priv
->irq_mask
;
4273 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4274 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4275 enable_mask
|= I915_USER_INTERRUPT
;
4277 if (IS_G4X(dev_priv
))
4278 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4280 /* Interrupt setup is already guaranteed to be single-threaded, this is
4281 * just to make the assert_spin_locked check happy. */
4282 spin_lock_irq(&dev_priv
->irq_lock
);
4283 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4284 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4285 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4286 spin_unlock_irq(&dev_priv
->irq_lock
);
4289 * Enable some error detection, note the instruction error mask
4290 * bit is reserved, so we leave it masked.
4292 if (IS_G4X(dev_priv
)) {
4293 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4294 GM45_ERROR_MEM_PRIV
|
4295 GM45_ERROR_CP_PRIV
|
4296 I915_ERROR_MEMORY_REFRESH
);
4298 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4299 I915_ERROR_MEMORY_REFRESH
);
4301 I915_WRITE(EMR
, error_mask
);
4303 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4304 I915_WRITE(IER
, enable_mask
);
4307 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4308 POSTING_READ(PORT_HOTPLUG_EN
);
4310 i915_enable_asle_pipestat(dev_priv
);
4315 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
4319 assert_spin_locked(&dev_priv
->irq_lock
);
4321 /* Note HDMI and DP share hotplug bits */
4322 /* enable bits are the same for all generations */
4323 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
4324 /* Programming the CRT detection parameters tends
4325 to generate a spurious hotplug event about three
4326 seconds later. So just do it once.
4328 if (IS_G4X(dev_priv
))
4329 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4330 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4332 /* Ignore TV since it's buggy */
4333 i915_hotplug_interrupt_update_locked(dev_priv
,
4334 HOTPLUG_INT_EN_MASK
|
4335 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4336 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4340 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4342 struct drm_device
*dev
= arg
;
4343 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4345 u32 pipe_stats
[I915_MAX_PIPES
];
4346 int ret
= IRQ_NONE
, pipe
;
4348 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4349 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4351 if (!intel_irqs_enabled(dev_priv
))
4354 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4355 disable_rpm_wakeref_asserts(dev_priv
);
4357 iir
= I915_READ(IIR
);
4360 bool irq_received
= (iir
& ~flip_mask
) != 0;
4361 bool blc_event
= false;
4363 /* Can't rely on pipestat interrupt bit in iir as it might
4364 * have been cleared after the pipestat interrupt was received.
4365 * It doesn't set the bit in iir again, but it still produces
4366 * interrupts (for non-MSI).
4368 spin_lock(&dev_priv
->irq_lock
);
4369 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4370 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4372 for_each_pipe(dev_priv
, pipe
) {
4373 i915_reg_t reg
= PIPESTAT(pipe
);
4374 pipe_stats
[pipe
] = I915_READ(reg
);
4377 * Clear the PIPE*STAT regs before the IIR
4379 if (pipe_stats
[pipe
] & 0x8000ffff) {
4380 I915_WRITE(reg
, pipe_stats
[pipe
]);
4381 irq_received
= true;
4384 spin_unlock(&dev_priv
->irq_lock
);
4391 /* Consume port. Then clear IIR or we'll miss events */
4392 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4393 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4395 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4398 I915_WRITE(IIR
, iir
& ~flip_mask
);
4399 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4401 if (iir
& I915_USER_INTERRUPT
)
4402 notify_ring(&dev_priv
->engine
[RCS
]);
4403 if (iir
& I915_BSD_USER_INTERRUPT
)
4404 notify_ring(&dev_priv
->engine
[VCS
]);
4406 for_each_pipe(dev_priv
, pipe
) {
4407 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4408 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4409 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4411 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4414 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4415 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4417 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4418 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4421 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4422 intel_opregion_asle_intr(dev_priv
);
4424 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4425 gmbus_irq_handler(dev_priv
);
4427 /* With MSI, interrupts are only generated when iir
4428 * transitions from zero to nonzero. If another bit got
4429 * set while we were handling the existing iir bits, then
4430 * we would never get another interrupt.
4432 * This is fine on non-MSI as well, as if we hit this path
4433 * we avoid exiting the interrupt handler only to generate
4436 * Note that for MSI this could cause a stray interrupt report
4437 * if an interrupt landed in the time between writing IIR and
4438 * the posting read. This should be rare enough to never
4439 * trigger the 99% of 100,000 interrupts test for disabling
4445 enable_rpm_wakeref_asserts(dev_priv
);
4450 static void i965_irq_uninstall(struct drm_device
* dev
)
4452 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4458 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4459 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4461 I915_WRITE(HWSTAM
, 0xffffffff);
4462 for_each_pipe(dev_priv
, pipe
)
4463 I915_WRITE(PIPESTAT(pipe
), 0);
4464 I915_WRITE(IMR
, 0xffffffff);
4465 I915_WRITE(IER
, 0x0);
4467 for_each_pipe(dev_priv
, pipe
)
4468 I915_WRITE(PIPESTAT(pipe
),
4469 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4470 I915_WRITE(IIR
, I915_READ(IIR
));
4474 * intel_irq_init - initializes irq support
4475 * @dev_priv: i915 device instance
4477 * This function initializes all the irq support including work items, timers
4478 * and all the vtables. It does not setup the interrupt itself though.
4480 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4482 struct drm_device
*dev
= &dev_priv
->drm
;
4484 intel_hpd_init_work(dev_priv
);
4486 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4487 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4489 /* Let's track the enabled rps events */
4490 if (IS_VALLEYVIEW(dev_priv
))
4491 /* WaGsvRC0ResidencyMethod:vlv */
4492 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4494 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4496 dev_priv
->rps
.pm_intr_keep
= 0;
4499 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4500 * if GEN6_PM_UP_EI_EXPIRED is masked.
4502 * TODO: verify if this can be reproduced on VLV,CHV.
4504 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
4505 dev_priv
->rps
.pm_intr_keep
|= GEN6_PM_RP_UP_EI_EXPIRED
;
4507 if (INTEL_INFO(dev_priv
)->gen
>= 8)
4508 dev_priv
->rps
.pm_intr_keep
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
4510 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4511 i915_hangcheck_elapsed
);
4513 if (IS_GEN2(dev_priv
)) {
4514 /* Gen2 doesn't have a hardware frame counter */
4515 dev
->max_vblank_count
= 0;
4516 dev
->driver
->get_vblank_counter
= drm_vblank_no_hw_counter
;
4517 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4518 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4519 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4521 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4522 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4526 * Opt out of the vblank disable timer on everything except gen2.
4527 * Gen2 doesn't have a hardware frame counter and so depends on
4528 * vblank interrupts to produce sane vblank seuquence numbers.
4530 if (!IS_GEN2(dev_priv
))
4531 dev
->vblank_disable_immediate
= true;
4533 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4534 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4536 if (IS_CHERRYVIEW(dev_priv
)) {
4537 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4538 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4539 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4540 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4541 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4542 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4543 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4544 } else if (IS_VALLEYVIEW(dev_priv
)) {
4545 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4546 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4547 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4548 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4549 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4550 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4551 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4552 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4553 dev
->driver
->irq_handler
= gen8_irq_handler
;
4554 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4555 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4556 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4557 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4558 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4559 if (IS_BROXTON(dev
))
4560 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4561 else if (HAS_PCH_SPT(dev
) || HAS_PCH_KBP(dev
))
4562 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4564 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4565 } else if (HAS_PCH_SPLIT(dev
)) {
4566 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4567 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4568 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4569 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4570 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4571 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4572 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4574 if (IS_GEN2(dev_priv
)) {
4575 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4576 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4577 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4578 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4579 } else if (IS_GEN3(dev_priv
)) {
4580 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4581 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4582 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4583 dev
->driver
->irq_handler
= i915_irq_handler
;
4585 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4586 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4587 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4588 dev
->driver
->irq_handler
= i965_irq_handler
;
4590 if (I915_HAS_HOTPLUG(dev_priv
))
4591 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4592 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4593 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4598 * intel_irq_install - enables the hardware interrupt
4599 * @dev_priv: i915 device instance
4601 * This function enables the hardware interrupt handling, but leaves the hotplug
4602 * handling still disabled. It is called after intel_irq_init().
4604 * In the driver load and resume code we need working interrupts in a few places
4605 * but don't want to deal with the hassle of concurrent probe and hotplug
4606 * workers. Hence the split into this two-stage approach.
4608 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4611 * We enable some interrupt sources in our postinstall hooks, so mark
4612 * interrupts as enabled _before_ actually enabling them to avoid
4613 * special cases in our ordering checks.
4615 dev_priv
->pm
.irqs_enabled
= true;
4617 return drm_irq_install(&dev_priv
->drm
, dev_priv
->drm
.pdev
->irq
);
4621 * intel_irq_uninstall - finilizes all irq handling
4622 * @dev_priv: i915 device instance
4624 * This stops interrupt and hotplug handling and unregisters and frees all
4625 * resources acquired in the init functions.
4627 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4629 drm_irq_uninstall(&dev_priv
->drm
);
4630 intel_hpd_cancel_work(dev_priv
);
4631 dev_priv
->pm
.irqs_enabled
= false;
4635 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4636 * @dev_priv: i915 device instance
4638 * This function is used to disable interrupts at runtime, both in the runtime
4639 * pm and the system suspend/resume code.
4641 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4643 dev_priv
->drm
.driver
->irq_uninstall(&dev_priv
->drm
);
4644 dev_priv
->pm
.irqs_enabled
= false;
4645 synchronize_irq(dev_priv
->drm
.irq
);
4649 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4650 * @dev_priv: i915 device instance
4652 * This function is used to enable interrupts at runtime, both in the runtime
4653 * pm and the system suspend/resume code.
4655 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4657 dev_priv
->pm
.irqs_enabled
= true;
4658 dev_priv
->drm
.driver
->irq_preinstall(&dev_priv
->drm
);
4659 dev_priv
->drm
.driver
->irq_postinstall(&dev_priv
->drm
);