1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include "intel_drv.h"
35 #define MAX_NOPID ((u32)~0)
38 * Interrupts that are always left unmasked.
40 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
41 * we leave them always unmasked in IMR and then control enabling them through
44 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
45 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
46 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
48 /** Interrupts that we mask and unmask at runtime. */
49 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
51 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
52 PIPE_VBLANK_INTERRUPT_STATUS)
54 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
55 PIPE_VBLANK_INTERRUPT_ENABLE)
57 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
58 DRM_I915_VBLANK_PIPE_B)
61 igdng_enable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
63 if ((dev_priv
->gt_irq_mask_reg
& mask
) != 0) {
64 dev_priv
->gt_irq_mask_reg
&= ~mask
;
65 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
66 (void) I915_READ(GTIMR
);
71 igdng_disable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
73 if ((dev_priv
->gt_irq_mask_reg
& mask
) != mask
) {
74 dev_priv
->gt_irq_mask_reg
|= mask
;
75 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
76 (void) I915_READ(GTIMR
);
80 /* For display hotplug interrupt */
82 igdng_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
84 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
85 dev_priv
->irq_mask_reg
&= ~mask
;
86 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
87 (void) I915_READ(DEIMR
);
92 igdng_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
94 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
95 dev_priv
->irq_mask_reg
|= mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
97 (void) I915_READ(DEIMR
);
102 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
105 dev_priv
->irq_mask_reg
&= ~mask
;
106 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
107 (void) I915_READ(IMR
);
112 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
114 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
115 dev_priv
->irq_mask_reg
|= mask
;
116 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
117 (void) I915_READ(IMR
);
122 i915_pipestat(int pipe
)
132 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
134 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
135 u32 reg
= i915_pipestat(pipe
);
137 dev_priv
->pipestat
[pipe
] |= mask
;
138 /* Enable the interrupt, clear any pending status */
139 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
140 (void) I915_READ(reg
);
145 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
147 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
148 u32 reg
= i915_pipestat(pipe
);
150 dev_priv
->pipestat
[pipe
] &= ~mask
;
151 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
152 (void) I915_READ(reg
);
157 * i915_pipe_enabled - check if a pipe is enabled
159 * @pipe: pipe to check
161 * Reading certain registers when the pipe is disabled can hang the chip.
162 * Use this routine to make sure the PLL is running and the pipe is active
163 * before reading such registers if unsure.
166 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
168 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
169 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
171 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
177 /* Called from drm generic code, passed a 'crtc', which
178 * we use as a pipe index
180 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
182 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
183 unsigned long high_frame
;
184 unsigned long low_frame
;
185 u32 high1
, high2
, low
, count
;
187 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
188 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
190 if (!i915_pipe_enabled(dev
, pipe
)) {
191 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
196 * High & low register fields aren't synchronized, so make sure
197 * we get a low value that's stable across two reads of the high
201 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
202 PIPE_FRAME_HIGH_SHIFT
);
203 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
204 PIPE_FRAME_LOW_SHIFT
);
205 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
206 PIPE_FRAME_HIGH_SHIFT
);
207 } while (high1
!= high2
);
209 count
= (high1
<< 8) | low
;
214 u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
216 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
217 int reg
= pipe
? PIPEB_FRMCOUNT_GM45
: PIPEA_FRMCOUNT_GM45
;
219 if (!i915_pipe_enabled(dev
, pipe
)) {
220 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
224 return I915_READ(reg
);
228 * Handle hotplug events outside the interrupt handler proper.
230 static void i915_hotplug_work_func(struct work_struct
*work
)
232 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
234 struct drm_device
*dev
= dev_priv
->dev
;
236 /* Just fire off a uevent and let userspace tell us what to do */
237 drm_sysfs_hotplug_event(dev
);
240 irqreturn_t
igdng_irq_handler(struct drm_device
*dev
)
242 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
245 u32 new_de_iir
, new_gt_iir
;
246 struct drm_i915_master_private
*master_priv
;
248 de_iir
= I915_READ(DEIIR
);
249 gt_iir
= I915_READ(GTIIR
);
252 if (de_iir
== 0 && gt_iir
== 0)
257 I915_WRITE(DEIIR
, de_iir
);
258 new_de_iir
= I915_READ(DEIIR
);
259 I915_WRITE(GTIIR
, gt_iir
);
260 new_gt_iir
= I915_READ(GTIIR
);
262 if (dev
->primary
->master
) {
263 master_priv
= dev
->primary
->master
->driver_priv
;
264 if (master_priv
->sarea_priv
)
265 master_priv
->sarea_priv
->last_dispatch
=
266 READ_BREADCRUMB(dev_priv
);
269 if (gt_iir
& GT_USER_INTERRUPT
) {
270 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
271 DRM_WAKEUP(&dev_priv
->irq_queue
);
281 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
283 struct drm_device
*dev
= (struct drm_device
*) arg
;
284 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
285 struct drm_i915_master_private
*master_priv
;
287 u32 pipea_stats
, pipeb_stats
;
291 unsigned long irqflags
;
295 atomic_inc(&dev_priv
->irq_received
);
298 return igdng_irq_handler(dev
);
300 iir
= I915_READ(IIR
);
303 vblank_status
= I915_START_VBLANK_INTERRUPT_STATUS
;
304 vblank_enable
= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
306 vblank_status
= I915_VBLANK_INTERRUPT_STATUS
;
307 vblank_enable
= I915_VBLANK_INTERRUPT_ENABLE
;
311 irq_received
= iir
!= 0;
313 /* Can't rely on pipestat interrupt bit in iir as it might
314 * have been cleared after the pipestat interrupt was received.
315 * It doesn't set the bit in iir again, but it still produces
316 * interrupts (for non-MSI).
318 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
319 pipea_stats
= I915_READ(PIPEASTAT
);
320 pipeb_stats
= I915_READ(PIPEBSTAT
);
323 * Clear the PIPE(A|B)STAT regs before the IIR
325 if (pipea_stats
& 0x8000ffff) {
326 I915_WRITE(PIPEASTAT
, pipea_stats
);
330 if (pipeb_stats
& 0x8000ffff) {
331 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
334 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
341 /* Consume port. Then clear IIR or we'll miss events */
342 if ((I915_HAS_HOTPLUG(dev
)) &&
343 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
344 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
346 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
348 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
349 schedule_work(&dev_priv
->hotplug_work
);
351 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
352 I915_READ(PORT_HOTPLUG_STAT
);
355 I915_WRITE(IIR
, iir
);
356 new_iir
= I915_READ(IIR
); /* Flush posted writes */
358 if (dev
->primary
->master
) {
359 master_priv
= dev
->primary
->master
->driver_priv
;
360 if (master_priv
->sarea_priv
)
361 master_priv
->sarea_priv
->last_dispatch
=
362 READ_BREADCRUMB(dev_priv
);
365 if (iir
& I915_USER_INTERRUPT
) {
366 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
367 DRM_WAKEUP(&dev_priv
->irq_queue
);
370 if (pipea_stats
& vblank_status
) {
372 drm_handle_vblank(dev
, 0);
375 if (pipeb_stats
& vblank_status
) {
377 drm_handle_vblank(dev
, 1);
380 if ((pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
) ||
381 (iir
& I915_ASLE_INTERRUPT
))
382 opregion_asle_intr(dev
);
384 /* With MSI, interrupts are only generated when iir
385 * transitions from zero to nonzero. If another bit got
386 * set while we were handling the existing iir bits, then
387 * we would never get another interrupt.
389 * This is fine on non-MSI as well, as if we hit this path
390 * we avoid exiting the interrupt handler only to generate
393 * Note that for MSI this could cause a stray interrupt report
394 * if an interrupt landed in the time between writing IIR and
395 * the posting read. This should be rare enough to never
396 * trigger the 99% of 100,000 interrupts test for disabling
405 static int i915_emit_irq(struct drm_device
* dev
)
407 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
408 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
411 i915_kernel_lost_context(dev
);
416 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
417 dev_priv
->counter
= 1;
418 if (master_priv
->sarea_priv
)
419 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
422 OUT_RING(MI_STORE_DWORD_INDEX
);
423 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
424 OUT_RING(dev_priv
->counter
);
425 OUT_RING(MI_USER_INTERRUPT
);
428 return dev_priv
->counter
;
431 void i915_user_irq_get(struct drm_device
*dev
)
433 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
434 unsigned long irqflags
;
436 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
437 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1)) {
439 igdng_enable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
441 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
443 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
446 void i915_user_irq_put(struct drm_device
*dev
)
448 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
449 unsigned long irqflags
;
451 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
452 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
453 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0)) {
455 igdng_disable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
457 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
459 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
462 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
464 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
465 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
468 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
469 READ_BREADCRUMB(dev_priv
));
471 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
472 if (master_priv
->sarea_priv
)
473 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
477 if (master_priv
->sarea_priv
)
478 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
480 i915_user_irq_get(dev
);
481 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
482 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
483 i915_user_irq_put(dev
);
486 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
487 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
493 /* Needs the lock as it touches the ring.
495 int i915_irq_emit(struct drm_device
*dev
, void *data
,
496 struct drm_file
*file_priv
)
498 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
499 drm_i915_irq_emit_t
*emit
= data
;
502 if (!dev_priv
|| !dev_priv
->ring
.virtual_start
) {
503 DRM_ERROR("called with no initialization\n");
507 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
509 mutex_lock(&dev
->struct_mutex
);
510 result
= i915_emit_irq(dev
);
511 mutex_unlock(&dev
->struct_mutex
);
513 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
514 DRM_ERROR("copy_to_user\n");
521 /* Doesn't need the hardware lock.
523 int i915_irq_wait(struct drm_device
*dev
, void *data
,
524 struct drm_file
*file_priv
)
526 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
527 drm_i915_irq_wait_t
*irqwait
= data
;
530 DRM_ERROR("called with no initialization\n");
534 return i915_wait_irq(dev
, irqwait
->irq_seq
);
537 /* Called from drm generic code, passed 'crtc' which
538 * we use as a pipe index
540 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
542 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
543 unsigned long irqflags
;
544 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
547 pipeconf
= I915_READ(pipeconf_reg
);
548 if (!(pipeconf
& PIPEACONF_ENABLE
))
554 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
556 i915_enable_pipestat(dev_priv
, pipe
,
557 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
559 i915_enable_pipestat(dev_priv
, pipe
,
560 PIPE_VBLANK_INTERRUPT_ENABLE
);
561 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
565 /* Called from drm generic code, passed 'crtc' which
566 * we use as a pipe index
568 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
570 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
571 unsigned long irqflags
;
576 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
577 i915_disable_pipestat(dev_priv
, pipe
,
578 PIPE_VBLANK_INTERRUPT_ENABLE
|
579 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
580 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
583 void i915_enable_interrupt (struct drm_device
*dev
)
585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
588 opregion_enable_asle(dev
);
589 dev_priv
->irq_enabled
= 1;
593 /* Set the vblank monitor pipe
595 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
596 struct drm_file
*file_priv
)
598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
601 DRM_ERROR("called with no initialization\n");
608 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
609 struct drm_file
*file_priv
)
611 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
612 drm_i915_vblank_pipe_t
*pipe
= data
;
615 DRM_ERROR("called with no initialization\n");
619 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
625 * Schedule buffer swap at given vertical blank.
627 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
628 struct drm_file
*file_priv
)
630 /* The delayed swap mechanism was fundamentally racy, and has been
631 * removed. The model was that the client requested a delayed flip/swap
632 * from the kernel, then waited for vblank before continuing to perform
633 * rendering. The problem was that the kernel might wake the client
634 * up before it dispatched the vblank swap (since the lock has to be
635 * held while touching the ringbuffer), in which case the client would
636 * clear and start the next frame before the swap occurred, and
637 * flicker would occur in addition to likely missing the vblank.
639 * In the absence of this ioctl, userland falls back to a correct path
640 * of waiting for a vblank, then dispatching the swap on its own.
641 * Context switching to userland and back is plenty fast enough for
642 * meeting the requirements of vblank swapping.
649 static void igdng_irq_preinstall(struct drm_device
*dev
)
651 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
653 I915_WRITE(HWSTAM
, 0xeffe);
655 /* XXX hotplug from PCH */
657 I915_WRITE(DEIMR
, 0xffffffff);
658 I915_WRITE(DEIER
, 0x0);
659 (void) I915_READ(DEIER
);
662 I915_WRITE(GTIMR
, 0xffffffff);
663 I915_WRITE(GTIER
, 0x0);
664 (void) I915_READ(GTIER
);
667 static int igdng_irq_postinstall(struct drm_device
*dev
)
669 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
670 /* enable kind of interrupts always enabled */
671 u32 display_mask
= DE_MASTER_IRQ_CONTROL
/*| DE_PCH_EVENT */;
672 u32 render_mask
= GT_USER_INTERRUPT
;
674 dev_priv
->irq_mask_reg
= ~display_mask
;
675 dev_priv
->de_irq_enable_reg
= display_mask
;
677 /* should always can generate irq */
678 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
679 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
680 I915_WRITE(DEIER
, dev_priv
->de_irq_enable_reg
);
681 (void) I915_READ(DEIER
);
683 /* user interrupt should be enabled, but masked initial */
684 dev_priv
->gt_irq_mask_reg
= 0xffffffff;
685 dev_priv
->gt_irq_enable_reg
= render_mask
;
687 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
688 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
689 I915_WRITE(GTIER
, dev_priv
->gt_irq_enable_reg
);
690 (void) I915_READ(GTIER
);
695 void i915_driver_irq_preinstall(struct drm_device
* dev
)
697 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
699 atomic_set(&dev_priv
->irq_received
, 0);
701 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
704 igdng_irq_preinstall(dev
);
708 if (I915_HAS_HOTPLUG(dev
)) {
709 I915_WRITE(PORT_HOTPLUG_EN
, 0);
710 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
713 I915_WRITE(HWSTAM
, 0xeffe);
714 I915_WRITE(PIPEASTAT
, 0);
715 I915_WRITE(PIPEBSTAT
, 0);
716 I915_WRITE(IMR
, 0xffffffff);
717 I915_WRITE(IER
, 0x0);
718 (void) I915_READ(IER
);
721 int i915_driver_irq_postinstall(struct drm_device
*dev
)
723 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
724 u32 enable_mask
= I915_INTERRUPT_ENABLE_FIX
| I915_INTERRUPT_ENABLE_VAR
;
726 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
728 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
731 return igdng_irq_postinstall(dev
);
733 /* Unmask the interrupts that we always want on. */
734 dev_priv
->irq_mask_reg
= ~I915_INTERRUPT_ENABLE_FIX
;
736 dev_priv
->pipestat
[0] = 0;
737 dev_priv
->pipestat
[1] = 0;
739 if (I915_HAS_HOTPLUG(dev
)) {
740 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
742 /* Leave other bits alone */
743 hotplug_en
|= HOTPLUG_EN_MASK
;
744 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
746 dev_priv
->hotplug_supported_mask
= CRT_HOTPLUG_INT_STATUS
|
747 TV_HOTPLUG_INT_STATUS
| SDVOC_HOTPLUG_INT_STATUS
|
748 SDVOB_HOTPLUG_INT_STATUS
;
750 dev_priv
->hotplug_supported_mask
|=
751 HDMIB_HOTPLUG_INT_STATUS
|
752 HDMIC_HOTPLUG_INT_STATUS
|
753 HDMID_HOTPLUG_INT_STATUS
;
755 /* Enable in IER... */
756 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
757 /* and unmask in IMR */
758 i915_enable_irq(dev_priv
, I915_DISPLAY_PORT_INTERRUPT
);
761 /* Disable pipe interrupt enables, clear pending pipe status */
762 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
763 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
764 /* Clear pending interrupt status */
765 I915_WRITE(IIR
, I915_READ(IIR
));
767 I915_WRITE(IER
, enable_mask
);
768 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
769 (void) I915_READ(IER
);
771 opregion_enable_asle(dev
);
776 static void igdng_irq_uninstall(struct drm_device
*dev
)
778 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
779 I915_WRITE(HWSTAM
, 0xffffffff);
781 I915_WRITE(DEIMR
, 0xffffffff);
782 I915_WRITE(DEIER
, 0x0);
783 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
785 I915_WRITE(GTIMR
, 0xffffffff);
786 I915_WRITE(GTIER
, 0x0);
787 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
790 void i915_driver_irq_uninstall(struct drm_device
* dev
)
792 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
797 dev_priv
->vblank_pipe
= 0;
800 igdng_irq_uninstall(dev
);
804 if (I915_HAS_HOTPLUG(dev
)) {
805 I915_WRITE(PORT_HOTPLUG_EN
, 0);
806 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
809 I915_WRITE(HWSTAM
, 0xffffffff);
810 I915_WRITE(PIPEASTAT
, 0);
811 I915_WRITE(PIPEBSTAT
, 0);
812 I915_WRITE(IMR
, 0xffffffff);
813 I915_WRITE(IER
, 0x0);
815 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
816 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
817 I915_WRITE(IIR
, I915_READ(IIR
));