drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define GEN_DEFAULT_PIPEOFFSETS \
  33         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  34                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  35         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  36                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  37         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  38
  39 #define GEN_CHV_PIPEOFFSETS \
  40         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  41                           CHV_PIPE_C_OFFSET }, \
  42         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  43                            CHV_TRANSCODER_C_OFFSET, }, \
  44         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  45                              CHV_PALETTE_C_OFFSET }
  46
  47 #define CURSOR_OFFSETS \
  48         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  49
  50 #define IVB_CURSOR_OFFSETS \
  51         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  52
  53 #define BDW_COLORS \
  54         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  55 #define CHV_COLORS \
  56         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  57
  58 /* Keep in gen based order, and chronological order within a gen */
  59 #define GEN2_FEATURES \
  60         .gen = 2, .num_pipes = 1, \
  61         .has_overlay = 1, .overlay_needs_physical = 1, \
  62         .has_gmch_display = 1, \
  63         .hws_needs_physical = 1, \
  64         .unfenced_needs_alignment = 1, \
  65         .ring_mask = RENDER_RING, \
  66         .has_snoop = true, \
  67         GEN_DEFAULT_PIPEOFFSETS, \
  68         CURSOR_OFFSETS
  69
  70 static const struct intel_device_info intel_i830_info __initconst = {
  71         GEN2_FEATURES,
  72         .platform = INTEL_I830,
  73         .is_mobile = 1, .cursor_needs_physical = 1,
  74         .num_pipes = 2, /* legal, last one wins */
  75 };
  76
  77 static const struct intel_device_info intel_i845g_info __initconst = {
  78         GEN2_FEATURES,
  79         .platform = INTEL_I845G,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info __initconst = {
  83         GEN2_FEATURES,
  84         .platform = INTEL_I85X, .is_mobile = 1,
  85         .num_pipes = 2, /* legal, last one wins */
  86         .cursor_needs_physical = 1,
  87         .has_fbc = 1,
  88 };
  89
  90 static const struct intel_device_info intel_i865g_info __initconst = {
  91         GEN2_FEATURES,
  92         .platform = INTEL_I865G,
  93 };
  94
  95 #define GEN3_FEATURES \
  96         .gen = 3, .num_pipes = 2, \
  97         .has_gmch_display = 1, \
  98         .ring_mask = RENDER_RING, \
  99         .has_snoop = true, \
 100         GEN_DEFAULT_PIPEOFFSETS, \
 101         CURSOR_OFFSETS
 102
 103 static const struct intel_device_info intel_i915g_info __initconst = {
 104         GEN3_FEATURES,
 105         .platform = INTEL_I915G, .cursor_needs_physical = 1,
 106         .has_overlay = 1, .overlay_needs_physical = 1,
 107         .hws_needs_physical = 1,
 108         .unfenced_needs_alignment = 1,
 109 };
 110
 111 static const struct intel_device_info intel_i915gm_info __initconst = {
 112         GEN3_FEATURES,
 113         .platform = INTEL_I915GM,
 114         .is_mobile = 1,
 115         .cursor_needs_physical = 1,
 116         .has_overlay = 1, .overlay_needs_physical = 1,
 117         .supports_tv = 1,
 118         .has_fbc = 1,
 119         .hws_needs_physical = 1,
 120         .unfenced_needs_alignment = 1,
 121 };
 122
 123 static const struct intel_device_info intel_i945g_info __initconst = {
 124         GEN3_FEATURES,
 125         .platform = INTEL_I945G,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .hws_needs_physical = 1,
 129         .unfenced_needs_alignment = 1,
 130 };
 131
 132 static const struct intel_device_info intel_i945gm_info __initconst = {
 133         GEN3_FEATURES,
 134         .platform = INTEL_I945GM, .is_mobile = 1,
 135         .has_hotplug = 1, .cursor_needs_physical = 1,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137         .supports_tv = 1,
 138         .has_fbc = 1,
 139         .hws_needs_physical = 1,
 140         .unfenced_needs_alignment = 1,
 141 };
 142
 143 static const struct intel_device_info intel_g33_info __initconst = {
 144         GEN3_FEATURES,
 145         .platform = INTEL_G33,
 146         .has_hotplug = 1,
 147         .has_overlay = 1,
 148 };
 149
 150 static const struct intel_device_info intel_pineview_info __initconst = {
 151         GEN3_FEATURES,
 152         .platform = INTEL_PINEVIEW, .is_mobile = 1,
 153         .has_hotplug = 1,
 154         .has_overlay = 1,
 155 };
 156
 157 #define GEN4_FEATURES \
 158         .gen = 4, .num_pipes = 2, \
 159         .has_hotplug = 1, \
 160         .has_gmch_display = 1, \
 161         .ring_mask = RENDER_RING, \
 162         .has_snoop = true, \
 163         GEN_DEFAULT_PIPEOFFSETS, \
 164         CURSOR_OFFSETS
 165
 166 static const struct intel_device_info intel_i965g_info __initconst = {
 167         GEN4_FEATURES,
 168         .platform = INTEL_I965G,
 169         .has_overlay = 1,
 170         .hws_needs_physical = 1,
 171         .has_snoop = false,
 172 };
 173
 174 static const struct intel_device_info intel_i965gm_info __initconst = {
 175         GEN4_FEATURES,
 176         .platform = INTEL_I965GM,
 177         .is_mobile = 1, .has_fbc = 1,
 178         .has_overlay = 1,
 179         .supports_tv = 1,
 180         .hws_needs_physical = 1,
 181         .has_snoop = false,
 182 };
 183
 184 static const struct intel_device_info intel_g45_info __initconst = {
 185         GEN4_FEATURES,
 186         .platform = INTEL_G45,
 187         .has_pipe_cxsr = 1,
 188         .ring_mask = RENDER_RING | BSD_RING,
 189 };
 190
 191 static const struct intel_device_info intel_gm45_info __initconst = {
 192         GEN4_FEATURES,
 193         .platform = INTEL_GM45,
 194         .is_mobile = 1, .has_fbc = 1,
 195         .has_pipe_cxsr = 1,
 196         .supports_tv = 1,
 197         .ring_mask = RENDER_RING | BSD_RING,
 198 };
 199
 200 #define GEN5_FEATURES \
 201         .gen = 5, .num_pipes = 2, \
 202         .has_hotplug = 1, \
 203         .ring_mask = RENDER_RING | BSD_RING, \
 204         .has_snoop = true, \
 205         GEN_DEFAULT_PIPEOFFSETS, \
 206         CURSOR_OFFSETS
 207
 208 static const struct intel_device_info intel_ironlake_d_info __initconst = {
 209         GEN5_FEATURES,
 210         .platform = INTEL_IRONLAKE,
 211 };
 212
 213 static const struct intel_device_info intel_ironlake_m_info __initconst = {
 214         GEN5_FEATURES,
 215         .platform = INTEL_IRONLAKE,
 216         .is_mobile = 1, .has_fbc = 1,
 217 };
 218
 219 #define GEN6_FEATURES \
 220         .gen = 6, .num_pipes = 2, \
 221         .has_hotplug = 1, \
 222         .has_fbc = 1, \
 223         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 224         .has_llc = 1, \
 225         .has_rc6 = 1, \
 226         .has_rc6p = 1, \
 227         .has_aliasing_ppgtt = 1, \
 228         GEN_DEFAULT_PIPEOFFSETS, \
 229         CURSOR_OFFSETS
 230
 231 #define SNB_D_PLATFORM \
 232         GEN6_FEATURES, \
 233         .platform = INTEL_SANDYBRIDGE
 234
 235 static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = {
 236         SNB_D_PLATFORM,
 237         .gt = 1,
 238 };
 239
 240 static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = {
 241         SNB_D_PLATFORM,
 242         .gt = 2,
 243 };
 244
 245 #define SNB_M_PLATFORM \
 246         GEN6_FEATURES, \
 247         .platform = INTEL_SANDYBRIDGE, \
 248         .is_mobile = 1
 249
 250
 251 static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = {
 252         SNB_M_PLATFORM,
 253         .gt = 1,
 254 };
 255
 256 static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = {
 257         SNB_M_PLATFORM,
 258         .gt = 2,
 259 };
 260
 261 #define GEN7_FEATURES  \
 262         .gen = 7, .num_pipes = 3, \
 263         .has_hotplug = 1, \
 264         .has_fbc = 1, \
 265         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 266         .has_llc = 1, \
 267         .has_rc6 = 1, \
 268         .has_rc6p = 1, \
 269         .has_aliasing_ppgtt = 1, \
 270         .has_full_ppgtt = 1, \
 271         GEN_DEFAULT_PIPEOFFSETS, \
 272         IVB_CURSOR_OFFSETS
 273
 274 #define IVB_D_PLATFORM \
 275         GEN7_FEATURES, \
 276         .platform = INTEL_IVYBRIDGE, \
 277         .has_l3_dpf = 1
 278
 279 static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = {
 280         IVB_D_PLATFORM,
 281         .gt = 1,
 282 };
 283
 284 static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = {
 285         IVB_D_PLATFORM,
 286         .gt = 2,
 287 };
 288
 289 #define IVB_M_PLATFORM \
 290         GEN7_FEATURES, \
 291         .platform = INTEL_IVYBRIDGE, \
 292         .is_mobile = 1, \
 293         .has_l3_dpf = 1
 294
 295 static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = {
 296         IVB_M_PLATFORM,
 297         .gt = 1,
 298 };
 299
 300 static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = {
 301         IVB_M_PLATFORM,
 302         .gt = 2,
 303 };
 304
 305 static const struct intel_device_info intel_ivybridge_q_info __initconst = {
 306         GEN7_FEATURES,
 307         .platform = INTEL_IVYBRIDGE,
 308         .gt = 2,
 309         .num_pipes = 0, /* legal, last one wins */
 310         .has_l3_dpf = 1,
 311 };
 312
 313 static const struct intel_device_info intel_valleyview_info __initconst = {
 314         .platform = INTEL_VALLEYVIEW,
 315         .gen = 7,
 316         .is_lp = 1,
 317         .num_pipes = 2,
 318         .has_psr = 1,
 319         .has_runtime_pm = 1,
 320         .has_rc6 = 1,
 321         .has_gmch_display = 1,
 322         .has_hotplug = 1,
 323         .has_aliasing_ppgtt = 1,
 324         .has_full_ppgtt = 1,
 325         .has_snoop = true,
 326         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 327         .display_mmio_offset = VLV_DISPLAY_BASE,
 328         GEN_DEFAULT_PIPEOFFSETS,
 329         CURSOR_OFFSETS
 330 };
 331
 332 #define HSW_FEATURES  \
 333         GEN7_FEATURES, \
 334         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 335         .has_ddi = 1, \
 336         .has_fpga_dbg = 1, \
 337         .has_psr = 1, \
 338         .has_resource_streamer = 1, \
 339         .has_dp_mst = 1, \
 340         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 341         .has_runtime_pm = 1
 342
 343 #define HSW_PLATFORM \
 344         HSW_FEATURES, \
 345         .platform = INTEL_HASWELL, \
 346         .has_l3_dpf = 1
 347
 348 static const struct intel_device_info intel_haswell_gt1_info __initconst = {
 349         HSW_PLATFORM,
 350         .gt = 1,
 351 };
 352
 353 static const struct intel_device_info intel_haswell_gt2_info __initconst = {
 354         HSW_PLATFORM,
 355         .gt = 2,
 356 };
 357
 358 static const struct intel_device_info intel_haswell_gt3_info __initconst = {
 359         HSW_PLATFORM,
 360         .gt = 3,
 361 };
 362
 363 #define BDW_FEATURES \
 364         HSW_FEATURES, \
 365         BDW_COLORS, \
 366         .has_logical_ring_contexts = 1, \
 367         .has_full_48bit_ppgtt = 1, \
 368         .has_64bit_reloc = 1, \
 369         .has_reset_engine = 1
 370
 371 #define BDW_PLATFORM \
 372         BDW_FEATURES, \
 373         .gen = 8, \
 374         .platform = INTEL_BROADWELL
 375
 376 static const struct intel_device_info intel_broadwell_gt1_info __initconst = {
 377         BDW_PLATFORM,
 378         .gt = 1,
 379 };
 380
 381 static const struct intel_device_info intel_broadwell_gt2_info __initconst = {
 382         BDW_PLATFORM,
 383         .gt = 2,
 384 };
 385
 386 static const struct intel_device_info intel_broadwell_rsvd_info __initconst = {
 387         BDW_PLATFORM,
 388         .gt = 3,
 389         /* According to the device ID those devices are GT3, they were
 390          * previously treated as not GT3, keep it like that.
 391          */
 392 };
 393
 394 static const struct intel_device_info intel_broadwell_gt3_info __initconst = {
 395         BDW_PLATFORM,
 396         .gt = 3,
 397         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 398 };
 399
 400 static const struct intel_device_info intel_cherryview_info __initconst = {
 401         .gen = 8, .num_pipes = 3,
 402         .has_hotplug = 1,
 403         .is_lp = 1,
 404         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 405         .platform = INTEL_CHERRYVIEW,
 406         .has_64bit_reloc = 1,
 407         .has_psr = 1,
 408         .has_runtime_pm = 1,
 409         .has_resource_streamer = 1,
 410         .has_rc6 = 1,
 411         .has_logical_ring_contexts = 1,
 412         .has_gmch_display = 1,
 413         .has_aliasing_ppgtt = 1,
 414         .has_full_ppgtt = 1,
 415         .has_reset_engine = 1,
 416         .has_snoop = true,
 417         .display_mmio_offset = VLV_DISPLAY_BASE,
 418         GEN_CHV_PIPEOFFSETS,
 419         CURSOR_OFFSETS,
 420         CHV_COLORS,
 421 };
 422
 423 #define SKL_PLATFORM \
 424         BDW_FEATURES, \
 425         .gen = 9, \
 426         .platform = INTEL_SKYLAKE, \
 427         .has_csr = 1, \
 428         .has_guc = 1, \
 429         .ddb_size = 896
 430
 431 static const struct intel_device_info intel_skylake_gt1_info __initconst = {
 432         SKL_PLATFORM,
 433         .gt = 1,
 434 };
 435
 436 static const struct intel_device_info intel_skylake_gt2_info __initconst = {
 437         SKL_PLATFORM,
 438         .gt = 2,
 439 };
 440
 441 #define SKL_GT3_PLUS_PLATFORM \
 442         SKL_PLATFORM, \
 443         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 444
 445
 446 static const struct intel_device_info intel_skylake_gt3_info __initconst = {
 447         SKL_GT3_PLUS_PLATFORM,
 448         .gt = 3,
 449 };
 450
 451 static const struct intel_device_info intel_skylake_gt4_info __initconst = {
 452         SKL_GT3_PLUS_PLATFORM,
 453         .gt = 4,
 454 };
 455
 456 #define GEN9_LP_FEATURES \
 457         .gen = 9, \
 458         .is_lp = 1, \
 459         .has_hotplug = 1, \
 460         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 461         .num_pipes = 3, \
 462         .has_64bit_reloc = 1, \
 463         .has_ddi = 1, \
 464         .has_fpga_dbg = 1, \
 465         .has_fbc = 1, \
 466         .has_runtime_pm = 1, \
 467         .has_pooled_eu = 0, \
 468         .has_csr = 1, \
 469         .has_resource_streamer = 1, \
 470         .has_rc6 = 1, \
 471         .has_dp_mst = 1, \
 472         .has_logical_ring_contexts = 1, \
 473         .has_guc = 1, \
 474         .has_aliasing_ppgtt = 1, \
 475         .has_full_ppgtt = 1, \
 476         .has_full_48bit_ppgtt = 1, \
 477         .has_reset_engine = 1, \
 478         .has_snoop = true, \
 479         .has_ipc = 1, \
 480         GEN_DEFAULT_PIPEOFFSETS, \
 481         IVB_CURSOR_OFFSETS, \
 482         BDW_COLORS
 483
 484 static const struct intel_device_info intel_broxton_info __initconst = {
 485         GEN9_LP_FEATURES,
 486         .platform = INTEL_BROXTON,
 487         .ddb_size = 512,
 488 };
 489
 490 static const struct intel_device_info intel_geminilake_info __initconst = {
 491         GEN9_LP_FEATURES,
 492         .platform = INTEL_GEMINILAKE,
 493         .ddb_size = 1024,
 494         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 495 };
 496
 497 #define KBL_PLATFORM \
 498         BDW_FEATURES, \
 499         .gen = 9, \
 500         .platform = INTEL_KABYLAKE, \
 501         .has_csr = 1, \
 502         .has_guc = 1, \
 503         .has_ipc = 1, \
 504         .ddb_size = 896
 505
 506 static const struct intel_device_info intel_kabylake_gt1_info __initconst = {
 507         KBL_PLATFORM,
 508         .gt = 1,
 509 };
 510
 511 static const struct intel_device_info intel_kabylake_gt2_info __initconst = {
 512         KBL_PLATFORM,
 513         .gt = 2,
 514 };
 515
 516 static const struct intel_device_info intel_kabylake_gt3_info __initconst = {
 517         KBL_PLATFORM,
 518         .gt = 3,
 519         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 520 };
 521
 522 #define CFL_PLATFORM \
 523         BDW_FEATURES, \
 524         .gen = 9, \
 525         .platform = INTEL_COFFEELAKE, \
 526         .has_csr = 1, \
 527         .has_guc = 1, \
 528         .has_ipc = 1, \
 529         .ddb_size = 896
 530
 531 static const struct intel_device_info intel_coffeelake_gt1_info __initconst = {
 532         CFL_PLATFORM,
 533         .gt = 1,
 534 };
 535
 536 static const struct intel_device_info intel_coffeelake_gt2_info __initconst = {
 537         CFL_PLATFORM,
 538         .gt = 2,
 539 };
 540
 541 static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
 542         CFL_PLATFORM,
 543         .gt = 3,
 544         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 545 };
 546
 547 static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
 548         BDW_FEATURES,
 549         .is_alpha_support = 1,
 550         .platform = INTEL_CANNONLAKE,
 551         .gen = 10,
 552         .gt = 2,
 553         .ddb_size = 1024,
 554         .has_csr = 1,
 555         .has_ipc = 1,
 556         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 557 };
 558
 559 /*
 560  * Make sure any device matches here are from most specific to most
 561  * general.  For example, since the Quanta match is based on the subsystem
 562  * and subvendor IDs, we need it to come before the more general IVB
 563  * PCI ID matches, otherwise we'll use the wrong info struct above.
 564  */
 565 static const struct pci_device_id pciidlist[] = {
 566         INTEL_I830_IDS(&intel_i830_info),
 567         INTEL_I845G_IDS(&intel_i845g_info),
 568         INTEL_I85X_IDS(&intel_i85x_info),
 569         INTEL_I865G_IDS(&intel_i865g_info),
 570         INTEL_I915G_IDS(&intel_i915g_info),
 571         INTEL_I915GM_IDS(&intel_i915gm_info),
 572         INTEL_I945G_IDS(&intel_i945g_info),
 573         INTEL_I945GM_IDS(&intel_i945gm_info),
 574         INTEL_I965G_IDS(&intel_i965g_info),
 575         INTEL_G33_IDS(&intel_g33_info),
 576         INTEL_I965GM_IDS(&intel_i965gm_info),
 577         INTEL_GM45_IDS(&intel_gm45_info),
 578         INTEL_G45_IDS(&intel_g45_info),
 579         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 580         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 581         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 582         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 583         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 584         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 585         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 586         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 587         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 588         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 589         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 590         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 591         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 592         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 593         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 594         INTEL_VLV_IDS(&intel_valleyview_info),
 595         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 596         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 597         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 598         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 599         INTEL_CHV_IDS(&intel_cherryview_info),
 600         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 601         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 602         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 603         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 604         INTEL_BXT_IDS(&intel_broxton_info),
 605         INTEL_GLK_IDS(&intel_geminilake_info),
 606         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 607         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 608         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 609         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 610         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 611         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 612         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 613         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 614         INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
 615         INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
 616         {0, 0, 0}
 617 };
 618 MODULE_DEVICE_TABLE(pci, pciidlist);
 619
 620 static void i915_pci_remove(struct pci_dev *pdev)
 621 {
 622         struct drm_device *dev = pci_get_drvdata(pdev);
 623
 624         i915_driver_unload(dev);
 625         drm_dev_unref(dev);
 626 }
 627
 628 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 629 {
 630         struct intel_device_info *intel_info =
 631                 (struct intel_device_info *) ent->driver_data;
 632         int err;
 633
 634         if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
 635                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 636                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 637                          "to enable support in this kernel version, or check for kernel updates.\n");
 638                 return -ENODEV;
 639         }
 640
 641         /* Only bind to function 0 of the device. Early generations
 642          * used function 1 as a placeholder for multi-head. This causes
 643          * us confusion instead, especially on the systems where both
 644          * functions have the same PCI-ID!
 645          */
 646         if (PCI_FUNC(pdev->devfn))
 647                 return -ENODEV;
 648
 649         /*
 650          * apple-gmux is needed on dual GPU MacBook Pro
 651          * to probe the panel if we're the inactive GPU.
 652          */
 653         if (vga_switcheroo_client_probe_defer(pdev))
 654                 return -EPROBE_DEFER;
 655
 656         err = i915_driver_load(pdev, ent);
 657         if (err)
 658                 return err;
 659
 660         err = i915_live_selftests(pdev);
 661         if (err) {
 662                 i915_pci_remove(pdev);
 663                 return err > 0 ? -ENOTTY : err;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static struct pci_driver i915_pci_driver = {
 670         .name = DRIVER_NAME,
 671         .id_table = pciidlist,
 672         .probe = i915_pci_probe,
 673         .remove = i915_pci_remove,
 674         .driver.pm = &i915_pm_ops,
 675 };
 676
 677 static int __init i915_init(void)
 678 {
 679         bool use_kms = true;
 680         int err;
 681
 682         err = i915_mock_selftests();
 683         if (err)
 684                 return err > 0 ? 0 : err;
 685
 686         /*
 687          * Enable KMS by default, unless explicitly overriden by
 688          * either the i915.modeset prarameter or by the
 689          * vga_text_mode_force boot option.
 690          */
 691
 692         if (i915.modeset == 0)
 693                 use_kms = false;
 694
 695         if (vgacon_text_force() && i915.modeset == -1)
 696                 use_kms = false;
 697
 698         if (!use_kms) {
 699                 /* Silently fail loading to not upset userspace. */
 700                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 701                 return 0;
 702         }
 703
 704         return pci_register_driver(&i915_pci_driver);
 705 }
 706
 707 static void __exit i915_exit(void)
 708 {
 709         if (!i915_pci_driver.driver.owner)
 710                 return;
 711
 712         pci_unregister_driver(&i915_pci_driver);
 713 }
 714
 715 module_init(i915_init);
 716 module_exit(i915_exit);
 717
 718 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 719 MODULE_AUTHOR("Intel Corporation");
 720
 721 MODULE_DESCRIPTION(DRIVER_DESC);
 722 MODULE_LICENSE("GPL and additional rights");