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1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
30
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32
33 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
35
36 /*
37 * The Bridge device's PCI config space has information about the
38 * fb aperture size and the amount of pre-reserved memory.
39 * This is all handled in the intel-gtt.ko module. i915.ko only
40 * cares about the vga bit for the vga rbiter.
41 */
42 #define INTEL_GMCH_CTRL 0x52
43 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
44 #define SNB_GMCH_CTRL 0x50
45 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
46 #define SNB_GMCH_GGMS_MASK 0x3
47 #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
48 #define SNB_GMCH_GMS_MASK 0x1f
49
50
51 /* PCI config space */
52
53 #define HPLLCC 0xc0 /* 855 only */
54 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
55 #define GC_CLOCK_133_200 (0 << 0)
56 #define GC_CLOCK_100_200 (1 << 0)
57 #define GC_CLOCK_100_133 (2 << 0)
58 #define GC_CLOCK_166_250 (3 << 0)
59 #define GCFGC2 0xda
60 #define GCFGC 0xf0 /* 915+ only */
61 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
62 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
63 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
64 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
65 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
66 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
67 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
68 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
69 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
70 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
71 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
72 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
73 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
74 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
75 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
76 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
77 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
78 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
79 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
80 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
81 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
82 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
83 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
84 #define LBB 0xf4
85
86 /* Graphics reset regs */
87 #define I965_GDRST 0xc0 /* PCI config register */
88 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
89 #define GRDOM_FULL (0<<2)
90 #define GRDOM_RENDER (1<<2)
91 #define GRDOM_MEDIA (3<<2)
92 #define GRDOM_RESET_ENABLE (1<<0)
93
94 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
95 #define GEN6_MBC_SNPCR_SHIFT 21
96 #define GEN6_MBC_SNPCR_MASK (3<<21)
97 #define GEN6_MBC_SNPCR_MAX (0<<21)
98 #define GEN6_MBC_SNPCR_MED (1<<21)
99 #define GEN6_MBC_SNPCR_LOW (2<<21)
100 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
101
102 #define GEN6_MBCTL 0x0907c
103 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
104 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
105 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
106 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
107 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
108
109 #define GEN6_GDRST 0x941c
110 #define GEN6_GRDOM_FULL (1 << 0)
111 #define GEN6_GRDOM_RENDER (1 << 1)
112 #define GEN6_GRDOM_MEDIA (1 << 2)
113 #define GEN6_GRDOM_BLT (1 << 3)
114
115 /* PPGTT stuff */
116 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
117
118 #define GEN6_PDE_VALID (1 << 0)
119 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
120 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
121 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
122
123 #define GEN6_PTE_VALID (1 << 0)
124 #define GEN6_PTE_UNCACHED (1 << 1)
125 #define HSW_PTE_UNCACHED (0)
126 #define GEN6_PTE_CACHE_LLC (2 << 1)
127 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
128 #define GEN6_PTE_CACHE_BITS (3 << 1)
129 #define GEN6_PTE_GFDT (1 << 3)
130 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
131
132 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
133 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
134 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
135 #define PP_DIR_DCLV_2G 0xffffffff
136
137 #define GAM_ECOCHK 0x4090
138 #define ECOCHK_SNB_BIT (1<<10)
139 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
140 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
141
142 #define GAC_ECO_BITS 0x14090
143 #define ECOBITS_PPGTT_CACHE64B (3<<8)
144 #define ECOBITS_PPGTT_CACHE4B (0<<8)
145
146 #define GAB_CTL 0x24000
147 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
148
149 /* VGA stuff */
150
151 #define VGA_ST01_MDA 0x3ba
152 #define VGA_ST01_CGA 0x3da
153
154 #define VGA_MSR_WRITE 0x3c2
155 #define VGA_MSR_READ 0x3cc
156 #define VGA_MSR_MEM_EN (1<<1)
157 #define VGA_MSR_CGA_MODE (1<<0)
158
159 #define VGA_SR_INDEX 0x3c4
160 #define VGA_SR_DATA 0x3c5
161
162 #define VGA_AR_INDEX 0x3c0
163 #define VGA_AR_VID_EN (1<<5)
164 #define VGA_AR_DATA_WRITE 0x3c0
165 #define VGA_AR_DATA_READ 0x3c1
166
167 #define VGA_GR_INDEX 0x3ce
168 #define VGA_GR_DATA 0x3cf
169 /* GR05 */
170 #define VGA_GR_MEM_READ_MODE_SHIFT 3
171 #define VGA_GR_MEM_READ_MODE_PLANE 1
172 /* GR06 */
173 #define VGA_GR_MEM_MODE_MASK 0xc
174 #define VGA_GR_MEM_MODE_SHIFT 2
175 #define VGA_GR_MEM_A0000_AFFFF 0
176 #define VGA_GR_MEM_A0000_BFFFF 1
177 #define VGA_GR_MEM_B0000_B7FFF 2
178 #define VGA_GR_MEM_B0000_BFFFF 3
179
180 #define VGA_DACMASK 0x3c6
181 #define VGA_DACRX 0x3c7
182 #define VGA_DACWX 0x3c8
183 #define VGA_DACDATA 0x3c9
184
185 #define VGA_CR_INDEX_MDA 0x3b4
186 #define VGA_CR_DATA_MDA 0x3b5
187 #define VGA_CR_INDEX_CGA 0x3d4
188 #define VGA_CR_DATA_CGA 0x3d5
189
190 /*
191 * Memory interface instructions used by the kernel
192 */
193 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
194
195 #define MI_NOOP MI_INSTR(0, 0)
196 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
197 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
198 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
199 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
200 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
201 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
202 #define MI_FLUSH MI_INSTR(0x04, 0)
203 #define MI_READ_FLUSH (1 << 0)
204 #define MI_EXE_FLUSH (1 << 1)
205 #define MI_NO_WRITE_FLUSH (1 << 2)
206 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
207 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
208 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
209 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
210 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
211 #define MI_SUSPEND_FLUSH_EN (1<<0)
212 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
213 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
214 #define MI_OVERLAY_CONTINUE (0x0<<21)
215 #define MI_OVERLAY_ON (0x1<<21)
216 #define MI_OVERLAY_OFF (0x2<<21)
217 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
218 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
219 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
220 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
221 /* IVB has funny definitions for which plane to flip. */
222 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
223 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
224 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
225 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
226 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
227 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
228 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
229 #define MI_ARB_ENABLE (1<<0)
230 #define MI_ARB_DISABLE (0<<0)
231
232 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
233 #define MI_MM_SPACE_GTT (1<<8)
234 #define MI_MM_SPACE_PHYSICAL (0<<8)
235 #define MI_SAVE_EXT_STATE_EN (1<<3)
236 #define MI_RESTORE_EXT_STATE_EN (1<<2)
237 #define MI_FORCE_RESTORE (1<<1)
238 #define MI_RESTORE_INHIBIT (1<<0)
239 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
240 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
241 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
242 #define MI_STORE_DWORD_INDEX_SHIFT 2
243 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
244 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
245 * simply ignores the register load under certain conditions.
246 * - One can actually load arbitrary many arbitrary registers: Simply issue x
247 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
248 */
249 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
250 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
251 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
252 #define MI_INVALIDATE_TLB (1<<18)
253 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
254 #define MI_INVALIDATE_BSD (1<<7)
255 #define MI_FLUSH_DW_USE_GTT (1<<2)
256 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
257 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
258 #define MI_BATCH_NON_SECURE (1)
259 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
260 #define MI_BATCH_NON_SECURE_I965 (1<<8)
261 #define MI_BATCH_PPGTT_HSW (1<<8)
262 #define MI_BATCH_NON_SECURE_HSW (1<<13)
263 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
264 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
265 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
266 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
267 #define MI_SEMAPHORE_UPDATE (1<<21)
268 #define MI_SEMAPHORE_COMPARE (1<<20)
269 #define MI_SEMAPHORE_REGISTER (1<<18)
270 #define MI_SEMAPHORE_SYNC_RV (2<<16)
271 #define MI_SEMAPHORE_SYNC_RB (0<<16)
272 #define MI_SEMAPHORE_SYNC_VR (0<<16)
273 #define MI_SEMAPHORE_SYNC_VB (2<<16)
274 #define MI_SEMAPHORE_SYNC_BR (2<<16)
275 #define MI_SEMAPHORE_SYNC_BV (0<<16)
276 #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
277 /*
278 * 3D instructions used by the kernel
279 */
280 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
281
282 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
283 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
284 #define SC_UPDATE_SCISSOR (0x1<<1)
285 #define SC_ENABLE_MASK (0x1<<0)
286 #define SC_ENABLE (0x1<<0)
287 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
288 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
289 #define SCI_YMIN_MASK (0xffff<<16)
290 #define SCI_XMIN_MASK (0xffff<<0)
291 #define SCI_YMAX_MASK (0xffff<<16)
292 #define SCI_XMAX_MASK (0xffff<<0)
293 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
294 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
295 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
296 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
297 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
298 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
299 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
300 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
301 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
302 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
303 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
304 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
305 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
306 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
307 #define BLT_DEPTH_8 (0<<24)
308 #define BLT_DEPTH_16_565 (1<<24)
309 #define BLT_DEPTH_16_1555 (2<<24)
310 #define BLT_DEPTH_32 (3<<24)
311 #define BLT_ROP_GXCOPY (0xcc<<16)
312 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
313 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
314 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
315 #define ASYNC_FLIP (1<<22)
316 #define DISPLAY_PLANE_A (0<<20)
317 #define DISPLAY_PLANE_B (1<<20)
318 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
319 #define PIPE_CONTROL_CS_STALL (1<<20)
320 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
321 #define PIPE_CONTROL_QW_WRITE (1<<14)
322 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
323 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
324 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
325 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
326 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
327 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
328 #define PIPE_CONTROL_NOTIFY (1<<8)
329 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
330 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
331 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
332 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
333 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
334 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
335
336
337 /*
338 * Reset registers
339 */
340 #define DEBUG_RESET_I830 0x6070
341 #define DEBUG_RESET_FULL (1<<7)
342 #define DEBUG_RESET_RENDER (1<<8)
343 #define DEBUG_RESET_DISPLAY (1<<9)
344
345 /*
346 * DPIO - a special bus for various display related registers to hide behind:
347 * 0x800c: m1, m2, n, p1, p2, k dividers
348 * 0x8014: REF and SFR select
349 * 0x8014: N divider, VCO select
350 * 0x801c/3c: core clock bits
351 * 0x8048/68: low pass filter coefficients
352 * 0x8100: fast clock controls
353 */
354 #define DPIO_PKT 0x2100
355 #define DPIO_RID (0<<24)
356 #define DPIO_OP_WRITE (1<<16)
357 #define DPIO_OP_READ (0<<16)
358 #define DPIO_PORTID (0x12<<8)
359 #define DPIO_BYTE (0xf<<4)
360 #define DPIO_BUSY (1<<0) /* status only */
361 #define DPIO_DATA 0x2104
362 #define DPIO_REG 0x2108
363 #define DPIO_CTL 0x2110
364 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
365 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
366 #define DPIO_SFR_BYPASS (1<<1)
367 #define DPIO_RESET (1<<0)
368
369 #define _DPIO_DIV_A 0x800c
370 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
371 #define DPIO_K_SHIFT (24) /* 4 bits */
372 #define DPIO_P1_SHIFT (21) /* 3 bits */
373 #define DPIO_P2_SHIFT (16) /* 5 bits */
374 #define DPIO_N_SHIFT (12) /* 4 bits */
375 #define DPIO_ENABLE_CALIBRATION (1<<11)
376 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
377 #define DPIO_M2DIV_MASK 0xff
378 #define _DPIO_DIV_B 0x802c
379 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
380
381 #define _DPIO_REFSFR_A 0x8014
382 #define DPIO_REFSEL_OVERRIDE 27
383 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
384 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
385 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
386 #define DPIO_PLL_REFCLK_SEL_MASK 3
387 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
388 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
389 #define _DPIO_REFSFR_B 0x8034
390 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
391
392 #define _DPIO_CORE_CLK_A 0x801c
393 #define _DPIO_CORE_CLK_B 0x803c
394 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
395
396 #define _DPIO_LFP_COEFF_A 0x8048
397 #define _DPIO_LFP_COEFF_B 0x8068
398 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
399
400 #define DPIO_FASTCLK_DISABLE 0x8100
401
402 #define DPIO_DATA_CHANNEL1 0x8220
403 #define DPIO_DATA_CHANNEL2 0x8420
404
405 /*
406 * Fence registers
407 */
408 #define FENCE_REG_830_0 0x2000
409 #define FENCE_REG_945_8 0x3000
410 #define I830_FENCE_START_MASK 0x07f80000
411 #define I830_FENCE_TILING_Y_SHIFT 12
412 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
413 #define I830_FENCE_PITCH_SHIFT 4
414 #define I830_FENCE_REG_VALID (1<<0)
415 #define I915_FENCE_MAX_PITCH_VAL 4
416 #define I830_FENCE_MAX_PITCH_VAL 6
417 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
418
419 #define I915_FENCE_START_MASK 0x0ff00000
420 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
421
422 #define FENCE_REG_965_0 0x03000
423 #define I965_FENCE_PITCH_SHIFT 2
424 #define I965_FENCE_TILING_Y_SHIFT 1
425 #define I965_FENCE_REG_VALID (1<<0)
426 #define I965_FENCE_MAX_PITCH_VAL 0x0400
427
428 #define FENCE_REG_SANDYBRIDGE_0 0x100000
429 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
430
431 /* control register for cpu gtt access */
432 #define TILECTL 0x101000
433 #define TILECTL_SWZCTL (1 << 0)
434 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
435 #define TILECTL_BACKSNOOP_DIS (1 << 3)
436
437 /*
438 * Instruction and interrupt control regs
439 */
440 #define PGTBL_ER 0x02024
441 #define RENDER_RING_BASE 0x02000
442 #define BSD_RING_BASE 0x04000
443 #define GEN6_BSD_RING_BASE 0x12000
444 #define BLT_RING_BASE 0x22000
445 #define RING_TAIL(base) ((base)+0x30)
446 #define RING_HEAD(base) ((base)+0x34)
447 #define RING_START(base) ((base)+0x38)
448 #define RING_CTL(base) ((base)+0x3c)
449 #define RING_SYNC_0(base) ((base)+0x40)
450 #define RING_SYNC_1(base) ((base)+0x44)
451 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
452 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
453 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
454 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
455 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
456 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
457 #define RING_MAX_IDLE(base) ((base)+0x54)
458 #define RING_HWS_PGA(base) ((base)+0x80)
459 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
460 #define ARB_MODE 0x04030
461 #define ARB_MODE_SWIZZLE_SNB (1<<4)
462 #define ARB_MODE_SWIZZLE_IVB (1<<5)
463 #define RENDER_HWS_PGA_GEN7 (0x04080)
464 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
465 #define DONE_REG 0x40b0
466 #define BSD_HWS_PGA_GEN7 (0x04180)
467 #define BLT_HWS_PGA_GEN7 (0x04280)
468 #define RING_ACTHD(base) ((base)+0x74)
469 #define RING_NOPID(base) ((base)+0x94)
470 #define RING_IMR(base) ((base)+0xa8)
471 #define RING_TIMESTAMP(base) ((base)+0x358)
472 #define TAIL_ADDR 0x001FFFF8
473 #define HEAD_WRAP_COUNT 0xFFE00000
474 #define HEAD_WRAP_ONE 0x00200000
475 #define HEAD_ADDR 0x001FFFFC
476 #define RING_NR_PAGES 0x001FF000
477 #define RING_REPORT_MASK 0x00000006
478 #define RING_REPORT_64K 0x00000002
479 #define RING_REPORT_128K 0x00000004
480 #define RING_NO_REPORT 0x00000000
481 #define RING_VALID_MASK 0x00000001
482 #define RING_VALID 0x00000001
483 #define RING_INVALID 0x00000000
484 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
485 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
486 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
487 #if 0
488 #define PRB0_TAIL 0x02030
489 #define PRB0_HEAD 0x02034
490 #define PRB0_START 0x02038
491 #define PRB0_CTL 0x0203c
492 #define PRB1_TAIL 0x02040 /* 915+ only */
493 #define PRB1_HEAD 0x02044 /* 915+ only */
494 #define PRB1_START 0x02048 /* 915+ only */
495 #define PRB1_CTL 0x0204c /* 915+ only */
496 #endif
497 #define IPEIR_I965 0x02064
498 #define IPEHR_I965 0x02068
499 #define INSTDONE_I965 0x0206c
500 #define GEN7_INSTDONE_1 0x0206c
501 #define GEN7_SC_INSTDONE 0x07100
502 #define GEN7_SAMPLER_INSTDONE 0x0e160
503 #define GEN7_ROW_INSTDONE 0x0e164
504 #define I915_NUM_INSTDONE_REG 4
505 #define RING_IPEIR(base) ((base)+0x64)
506 #define RING_IPEHR(base) ((base)+0x68)
507 #define RING_INSTDONE(base) ((base)+0x6c)
508 #define RING_INSTPS(base) ((base)+0x70)
509 #define RING_DMA_FADD(base) ((base)+0x78)
510 #define RING_INSTPM(base) ((base)+0xc0)
511 #define INSTPS 0x02070 /* 965+ only */
512 #define INSTDONE1 0x0207c /* 965+ only */
513 #define ACTHD_I965 0x02074
514 #define HWS_PGA 0x02080
515 #define HWS_ADDRESS_MASK 0xfffff000
516 #define HWS_START_ADDRESS_SHIFT 4
517 #define PWRCTXA 0x2088 /* 965GM+ only */
518 #define PWRCTX_EN (1<<0)
519 #define IPEIR 0x02088
520 #define IPEHR 0x0208c
521 #define INSTDONE 0x02090
522 #define NOPID 0x02094
523 #define HWSTAM 0x02098
524 #define DMA_FADD_I8XX 0x020d0
525
526 #define ERROR_GEN6 0x040a0
527 #define GEN7_ERR_INT 0x44040
528 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
529
530 /* GM45+ chicken bits -- debug workaround bits that may be required
531 * for various sorts of correct behavior. The top 16 bits of each are
532 * the enables for writing to the corresponding low bit.
533 */
534 #define _3D_CHICKEN 0x02084
535 #define _3D_CHICKEN2 0x0208c
536 /* Disables pipelining of read flushes past the SF-WIZ interface.
537 * Required on all Ironlake steppings according to the B-Spec, but the
538 * particular danger of not doing so is not specified.
539 */
540 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
541 #define _3D_CHICKEN3 0x02090
542 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
543 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
544
545 #define MI_MODE 0x0209c
546 # define VS_TIMER_DISPATCH (1 << 6)
547 # define MI_FLUSH_ENABLE (1 << 12)
548
549 #define GEN6_GT_MODE 0x20d0
550 #define GEN6_GT_MODE_HI (1 << 9)
551
552 #define GFX_MODE 0x02520
553 #define GFX_MODE_GEN7 0x0229c
554 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
555 #define GFX_RUN_LIST_ENABLE (1<<15)
556 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
557 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
558 #define GFX_REPLAY_MODE (1<<11)
559 #define GFX_PSMI_GRANULARITY (1<<10)
560 #define GFX_PPGTT_ENABLE (1<<9)
561
562 #define VLV_DISPLAY_BASE 0x180000
563
564 #define SCPD0 0x0209c /* 915+ only */
565 #define IER 0x020a0
566 #define IIR 0x020a4
567 #define IMR 0x020a8
568 #define ISR 0x020ac
569 #define VLV_GUNIT_CLOCK_GATE 0x182060
570 #define GCFG_DIS (1<<8)
571 #define VLV_IIR_RW 0x182084
572 #define VLV_IER 0x1820a0
573 #define VLV_IIR 0x1820a4
574 #define VLV_IMR 0x1820a8
575 #define VLV_ISR 0x1820ac
576 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
577 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
578 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
579 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
580 #define I915_HWB_OOM_INTERRUPT (1<<13)
581 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
582 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
583 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
584 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
585 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
586 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
587 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
588 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
589 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
590 #define I915_DEBUG_INTERRUPT (1<<2)
591 #define I915_USER_INTERRUPT (1<<1)
592 #define I915_ASLE_INTERRUPT (1<<0)
593 #define I915_BSD_USER_INTERRUPT (1<<25)
594 #define EIR 0x020b0
595 #define EMR 0x020b4
596 #define ESR 0x020b8
597 #define GM45_ERROR_PAGE_TABLE (1<<5)
598 #define GM45_ERROR_MEM_PRIV (1<<4)
599 #define I915_ERROR_PAGE_TABLE (1<<4)
600 #define GM45_ERROR_CP_PRIV (1<<3)
601 #define I915_ERROR_MEMORY_REFRESH (1<<1)
602 #define I915_ERROR_INSTRUCTION (1<<0)
603 #define INSTPM 0x020c0
604 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
605 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
606 will not assert AGPBUSY# and will only
607 be delivered when out of C3. */
608 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
609 #define ACTHD 0x020c8
610 #define FW_BLC 0x020d8
611 #define FW_BLC2 0x020dc
612 #define FW_BLC_SELF 0x020e0 /* 915+ only */
613 #define FW_BLC_SELF_EN_MASK (1<<31)
614 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
615 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
616 #define MM_BURST_LENGTH 0x00700000
617 #define MM_FIFO_WATERMARK 0x0001F000
618 #define LM_BURST_LENGTH 0x00000700
619 #define LM_FIFO_WATERMARK 0x0000001F
620 #define MI_ARB_STATE 0x020e4 /* 915+ only */
621
622 /* Make render/texture TLB fetches lower priorty than associated data
623 * fetches. This is not turned on by default
624 */
625 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
626
627 /* Isoch request wait on GTT enable (Display A/B/C streams).
628 * Make isoch requests stall on the TLB update. May cause
629 * display underruns (test mode only)
630 */
631 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
632
633 /* Block grant count for isoch requests when block count is
634 * set to a finite value.
635 */
636 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
637 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
638 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
639 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
640 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
641
642 /* Enable render writes to complete in C2/C3/C4 power states.
643 * If this isn't enabled, render writes are prevented in low
644 * power states. That seems bad to me.
645 */
646 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
647
648 /* This acknowledges an async flip immediately instead
649 * of waiting for 2TLB fetches.
650 */
651 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
652
653 /* Enables non-sequential data reads through arbiter
654 */
655 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
656
657 /* Disable FSB snooping of cacheable write cycles from binner/render
658 * command stream
659 */
660 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
661
662 /* Arbiter time slice for non-isoch streams */
663 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
664 #define MI_ARB_TIME_SLICE_1 (0 << 5)
665 #define MI_ARB_TIME_SLICE_2 (1 << 5)
666 #define MI_ARB_TIME_SLICE_4 (2 << 5)
667 #define MI_ARB_TIME_SLICE_6 (3 << 5)
668 #define MI_ARB_TIME_SLICE_8 (4 << 5)
669 #define MI_ARB_TIME_SLICE_10 (5 << 5)
670 #define MI_ARB_TIME_SLICE_14 (6 << 5)
671 #define MI_ARB_TIME_SLICE_16 (7 << 5)
672
673 /* Low priority grace period page size */
674 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
675 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
676
677 /* Disable display A/B trickle feed */
678 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
679
680 /* Set display plane priority */
681 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
682 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
683
684 #define CACHE_MODE_0 0x02120 /* 915+ only */
685 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
686 #define CM0_IZ_OPT_DISABLE (1<<6)
687 #define CM0_ZR_OPT_DISABLE (1<<5)
688 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
689 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
690 #define CM0_COLOR_EVICT_DISABLE (1<<3)
691 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
692 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
693 #define BB_ADDR 0x02140 /* 8 bytes */
694 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
695 #define ECOSKPD 0x021d0
696 #define ECO_GATING_CX_ONLY (1<<3)
697 #define ECO_FLIP_DONE (1<<0)
698
699 #define CACHE_MODE_1 0x7004 /* IVB+ */
700 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
701
702 /* GEN6 interrupt control
703 * Note that the per-ring interrupt bits do alias with the global interrupt bits
704 * in GTIMR. */
705 #define GEN6_RENDER_HWSTAM 0x2098
706 #define GEN6_RENDER_IMR 0x20a8
707 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
708 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
709 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
710 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
711 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
712 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
713 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
714 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
715 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
716
717 #define GEN6_BLITTER_HWSTAM 0x22098
718 #define GEN6_BLITTER_IMR 0x220a8
719 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
720 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
721 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
722 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
723
724 #define GEN6_BLITTER_ECOSKPD 0x221d0
725 #define GEN6_BLITTER_LOCK_SHIFT 16
726 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
727
728 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
729 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
730 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
731 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
732 #define GEN6_BSD_GO_INDICATOR (1 << 4)
733
734 #define GEN6_BSD_HWSTAM 0x12098
735 #define GEN6_BSD_IMR 0x120a8
736 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
737
738 #define GEN6_BSD_RNCID 0x12198
739
740 #define GEN7_FF_THREAD_MODE 0x20a0
741 #define GEN7_FF_SCHED_MASK 0x0077070
742 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
743 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
744 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
745 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
746 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
747 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
748 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
749 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
750 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
751 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
752 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
753 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
754
755 /*
756 * Framebuffer compression (915+ only)
757 */
758
759 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
760 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
761 #define FBC_CONTROL 0x03208
762 #define FBC_CTL_EN (1<<31)
763 #define FBC_CTL_PERIODIC (1<<30)
764 #define FBC_CTL_INTERVAL_SHIFT (16)
765 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
766 #define FBC_CTL_C3_IDLE (1<<13)
767 #define FBC_CTL_STRIDE_SHIFT (5)
768 #define FBC_CTL_FENCENO (1<<0)
769 #define FBC_COMMAND 0x0320c
770 #define FBC_CMD_COMPRESS (1<<0)
771 #define FBC_STATUS 0x03210
772 #define FBC_STAT_COMPRESSING (1<<31)
773 #define FBC_STAT_COMPRESSED (1<<30)
774 #define FBC_STAT_MODIFIED (1<<29)
775 #define FBC_STAT_CURRENT_LINE (1<<0)
776 #define FBC_CONTROL2 0x03214
777 #define FBC_CTL_FENCE_DBL (0<<4)
778 #define FBC_CTL_IDLE_IMM (0<<2)
779 #define FBC_CTL_IDLE_FULL (1<<2)
780 #define FBC_CTL_IDLE_LINE (2<<2)
781 #define FBC_CTL_IDLE_DEBUG (3<<2)
782 #define FBC_CTL_CPU_FENCE (1<<1)
783 #define FBC_CTL_PLANEA (0<<0)
784 #define FBC_CTL_PLANEB (1<<0)
785 #define FBC_FENCE_OFF 0x0321b
786 #define FBC_TAG 0x03300
787
788 #define FBC_LL_SIZE (1536)
789
790 /* Framebuffer compression for GM45+ */
791 #define DPFC_CB_BASE 0x3200
792 #define DPFC_CONTROL 0x3208
793 #define DPFC_CTL_EN (1<<31)
794 #define DPFC_CTL_PLANEA (0<<30)
795 #define DPFC_CTL_PLANEB (1<<30)
796 #define DPFC_CTL_FENCE_EN (1<<29)
797 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
798 #define DPFC_SR_EN (1<<10)
799 #define DPFC_CTL_LIMIT_1X (0<<6)
800 #define DPFC_CTL_LIMIT_2X (1<<6)
801 #define DPFC_CTL_LIMIT_4X (2<<6)
802 #define DPFC_RECOMP_CTL 0x320c
803 #define DPFC_RECOMP_STALL_EN (1<<27)
804 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
805 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
806 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
807 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
808 #define DPFC_STATUS 0x3210
809 #define DPFC_INVAL_SEG_SHIFT (16)
810 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
811 #define DPFC_COMP_SEG_SHIFT (0)
812 #define DPFC_COMP_SEG_MASK (0x000003ff)
813 #define DPFC_STATUS2 0x3214
814 #define DPFC_FENCE_YOFF 0x3218
815 #define DPFC_CHICKEN 0x3224
816 #define DPFC_HT_MODIFY (1<<31)
817
818 /* Framebuffer compression for Ironlake */
819 #define ILK_DPFC_CB_BASE 0x43200
820 #define ILK_DPFC_CONTROL 0x43208
821 /* The bit 28-8 is reserved */
822 #define DPFC_RESERVED (0x1FFFFF00)
823 #define ILK_DPFC_RECOMP_CTL 0x4320c
824 #define ILK_DPFC_STATUS 0x43210
825 #define ILK_DPFC_FENCE_YOFF 0x43218
826 #define ILK_DPFC_CHICKEN 0x43224
827 #define ILK_FBC_RT_BASE 0x2128
828 #define ILK_FBC_RT_VALID (1<<0)
829
830 #define ILK_DISPLAY_CHICKEN1 0x42000
831 #define ILK_FBCQ_DIS (1<<22)
832 #define ILK_PABSTRETCH_DIS (1<<21)
833
834
835 /*
836 * Framebuffer compression for Sandybridge
837 *
838 * The following two registers are of type GTTMMADR
839 */
840 #define SNB_DPFC_CTL_SA 0x100100
841 #define SNB_CPU_FENCE_ENABLE (1<<29)
842 #define DPFC_CPU_FENCE_OFFSET 0x100104
843
844
845 /*
846 * GPIO regs
847 */
848 #define GPIOA 0x5010
849 #define GPIOB 0x5014
850 #define GPIOC 0x5018
851 #define GPIOD 0x501c
852 #define GPIOE 0x5020
853 #define GPIOF 0x5024
854 #define GPIOG 0x5028
855 #define GPIOH 0x502c
856 # define GPIO_CLOCK_DIR_MASK (1 << 0)
857 # define GPIO_CLOCK_DIR_IN (0 << 1)
858 # define GPIO_CLOCK_DIR_OUT (1 << 1)
859 # define GPIO_CLOCK_VAL_MASK (1 << 2)
860 # define GPIO_CLOCK_VAL_OUT (1 << 3)
861 # define GPIO_CLOCK_VAL_IN (1 << 4)
862 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
863 # define GPIO_DATA_DIR_MASK (1 << 8)
864 # define GPIO_DATA_DIR_IN (0 << 9)
865 # define GPIO_DATA_DIR_OUT (1 << 9)
866 # define GPIO_DATA_VAL_MASK (1 << 10)
867 # define GPIO_DATA_VAL_OUT (1 << 11)
868 # define GPIO_DATA_VAL_IN (1 << 12)
869 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
870
871 #define GMBUS0 0x5100 /* clock/port select */
872 #define GMBUS_RATE_100KHZ (0<<8)
873 #define GMBUS_RATE_50KHZ (1<<8)
874 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
875 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
876 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
877 #define GMBUS_PORT_DISABLED 0
878 #define GMBUS_PORT_SSC 1
879 #define GMBUS_PORT_VGADDC 2
880 #define GMBUS_PORT_PANEL 3
881 #define GMBUS_PORT_DPC 4 /* HDMIC */
882 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
883 #define GMBUS_PORT_DPD 6 /* HDMID */
884 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
885 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
886 #define GMBUS1 0x5104 /* command/status */
887 #define GMBUS_SW_CLR_INT (1<<31)
888 #define GMBUS_SW_RDY (1<<30)
889 #define GMBUS_ENT (1<<29) /* enable timeout */
890 #define GMBUS_CYCLE_NONE (0<<25)
891 #define GMBUS_CYCLE_WAIT (1<<25)
892 #define GMBUS_CYCLE_INDEX (2<<25)
893 #define GMBUS_CYCLE_STOP (4<<25)
894 #define GMBUS_BYTE_COUNT_SHIFT 16
895 #define GMBUS_SLAVE_INDEX_SHIFT 8
896 #define GMBUS_SLAVE_ADDR_SHIFT 1
897 #define GMBUS_SLAVE_READ (1<<0)
898 #define GMBUS_SLAVE_WRITE (0<<0)
899 #define GMBUS2 0x5108 /* status */
900 #define GMBUS_INUSE (1<<15)
901 #define GMBUS_HW_WAIT_PHASE (1<<14)
902 #define GMBUS_STALL_TIMEOUT (1<<13)
903 #define GMBUS_INT (1<<12)
904 #define GMBUS_HW_RDY (1<<11)
905 #define GMBUS_SATOER (1<<10)
906 #define GMBUS_ACTIVE (1<<9)
907 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
908 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
909 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
910 #define GMBUS_NAK_EN (1<<3)
911 #define GMBUS_IDLE_EN (1<<2)
912 #define GMBUS_HW_WAIT_EN (1<<1)
913 #define GMBUS_HW_RDY_EN (1<<0)
914 #define GMBUS5 0x5120 /* byte index */
915 #define GMBUS_2BYTE_INDEX_EN (1<<31)
916
917 /*
918 * Clock control & power management
919 */
920
921 #define VGA0 0x6000
922 #define VGA1 0x6004
923 #define VGA_PD 0x6010
924 #define VGA0_PD_P2_DIV_4 (1 << 7)
925 #define VGA0_PD_P1_DIV_2 (1 << 5)
926 #define VGA0_PD_P1_SHIFT 0
927 #define VGA0_PD_P1_MASK (0x1f << 0)
928 #define VGA1_PD_P2_DIV_4 (1 << 15)
929 #define VGA1_PD_P1_DIV_2 (1 << 13)
930 #define VGA1_PD_P1_SHIFT 8
931 #define VGA1_PD_P1_MASK (0x1f << 8)
932 #define _DPLL_A 0x06014
933 #define _DPLL_B 0x06018
934 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
935 #define DPLL_VCO_ENABLE (1 << 31)
936 #define DPLL_DVO_HIGH_SPEED (1 << 30)
937 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
938 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
939 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
940 #define DPLL_VGA_MODE_DIS (1 << 28)
941 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
942 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
943 #define DPLL_MODE_MASK (3 << 26)
944 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
945 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
946 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
947 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
948 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
949 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
950 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
951 #define DPLL_LOCK_VLV (1<<15)
952 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
953
954 #define SRX_INDEX 0x3c4
955 #define SRX_DATA 0x3c5
956 #define SR01 1
957 #define SR01_SCREEN_OFF (1<<5)
958
959 #define PPCR 0x61204
960 #define PPCR_ON (1<<0)
961
962 #define DVOB 0x61140
963 #define DVOB_ON (1<<31)
964 #define DVOC 0x61160
965 #define DVOC_ON (1<<31)
966 #define LVDS 0x61180
967 #define LVDS_ON (1<<31)
968
969 /* Scratch pad debug 0 reg:
970 */
971 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
972 /*
973 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
974 * this field (only one bit may be set).
975 */
976 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
977 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
978 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
979 /* i830, required in DVO non-gang */
980 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
981 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
982 #define PLL_REF_INPUT_DREFCLK (0 << 13)
983 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
984 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
985 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
986 #define PLL_REF_INPUT_MASK (3 << 13)
987 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
988 /* Ironlake */
989 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
990 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
991 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
992 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
993 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
994
995 /*
996 * Parallel to Serial Load Pulse phase selection.
997 * Selects the phase for the 10X DPLL clock for the PCIe
998 * digital display port. The range is 4 to 13; 10 or more
999 * is just a flip delay. The default is 6
1000 */
1001 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1002 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1003 /*
1004 * SDVO multiplier for 945G/GM. Not used on 965.
1005 */
1006 #define SDVO_MULTIPLIER_MASK 0x000000ff
1007 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1008 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1009 #define _DPLL_A_MD 0x0601c /* 965+ only */
1010 /*
1011 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1012 *
1013 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1014 */
1015 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1016 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1017 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1018 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1019 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1020 /*
1021 * SDVO/UDI pixel multiplier.
1022 *
1023 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1024 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1025 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1026 * dummy bytes in the datastream at an increased clock rate, with both sides of
1027 * the link knowing how many bytes are fill.
1028 *
1029 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1030 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1031 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1032 * through an SDVO command.
1033 *
1034 * This register field has values of multiplication factor minus 1, with
1035 * a maximum multiplier of 5 for SDVO.
1036 */
1037 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1038 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1039 /*
1040 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1041 * This best be set to the default value (3) or the CRT won't work. No,
1042 * I don't entirely understand what this does...
1043 */
1044 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1045 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1046 #define _DPLL_B_MD 0x06020 /* 965+ only */
1047 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1048
1049 #define _FPA0 0x06040
1050 #define _FPA1 0x06044
1051 #define _FPB0 0x06048
1052 #define _FPB1 0x0604c
1053 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1054 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1055 #define FP_N_DIV_MASK 0x003f0000
1056 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1057 #define FP_N_DIV_SHIFT 16
1058 #define FP_M1_DIV_MASK 0x00003f00
1059 #define FP_M1_DIV_SHIFT 8
1060 #define FP_M2_DIV_MASK 0x0000003f
1061 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1062 #define FP_M2_DIV_SHIFT 0
1063 #define DPLL_TEST 0x606c
1064 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1065 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1066 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1067 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1068 #define DPLLB_TEST_N_BYPASS (1 << 19)
1069 #define DPLLB_TEST_M_BYPASS (1 << 18)
1070 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1071 #define DPLLA_TEST_N_BYPASS (1 << 3)
1072 #define DPLLA_TEST_M_BYPASS (1 << 2)
1073 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1074 #define D_STATE 0x6104
1075 #define DSTATE_GFX_RESET_I830 (1<<6)
1076 #define DSTATE_PLL_D3_OFF (1<<3)
1077 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1078 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1079 #define DSPCLK_GATE_D 0x6200
1080 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1081 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1082 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1083 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1084 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1085 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1086 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1087 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1088 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1089 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1090 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1091 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1092 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1093 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1094 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1095 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1096 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1097 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1098 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1099 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1100 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1101 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1102 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1103 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1104 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1105 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1106 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1107 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1108 /**
1109 * This bit must be set on the 830 to prevent hangs when turning off the
1110 * overlay scaler.
1111 */
1112 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1113 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1114 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1115 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1116 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1117
1118 #define RENCLK_GATE_D1 0x6204
1119 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1120 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1121 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1122 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1123 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1124 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1125 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1126 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1127 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1128 /** This bit must be unset on 855,865 */
1129 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1130 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1131 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1132 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1133 /** This bit must be set on 855,865. */
1134 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1135 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1136 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1137 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1138 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1139 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1140 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1141 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1142 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1143 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1144 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1145 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1146 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1147 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1148 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1149 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1150 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1151 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1152
1153 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1154 /** This bit must always be set on 965G/965GM */
1155 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1156 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1157 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1158 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1159 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1160 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1161 /** This bit must always be set on 965G */
1162 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1163 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1164 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1165 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1166 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1167 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1168 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1169 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1170 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1171 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1172 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1173 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1174 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1175 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1176 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1177 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1178 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1179 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1180 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1181
1182 #define RENCLK_GATE_D2 0x6208
1183 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1184 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1185 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1186 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1187 #define DEUC 0x6214 /* CRL only */
1188
1189 #define FW_BLC_SELF_VLV 0x6500
1190 #define FW_CSPWRDWNEN (1<<15)
1191
1192 /*
1193 * Palette regs
1194 */
1195
1196 #define _PALETTE_A 0x0a000
1197 #define _PALETTE_B 0x0a800
1198 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1199
1200 /* MCH MMIO space */
1201
1202 /*
1203 * MCHBAR mirror.
1204 *
1205 * This mirrors the MCHBAR MMIO space whose location is determined by
1206 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1207 * every way. It is not accessible from the CP register read instructions.
1208 *
1209 */
1210 #define MCHBAR_MIRROR_BASE 0x10000
1211
1212 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1213
1214 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1215 #define DCC 0x10200
1216 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1217 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1218 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1219 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1220 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1221 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1222
1223 /** Pineview MCH register contains DDR3 setting */
1224 #define CSHRDDR3CTL 0x101a8
1225 #define CSHRDDR3CTL_DDR3 (1 << 2)
1226
1227 /** 965 MCH register controlling DRAM channel configuration */
1228 #define C0DRB3 0x10206
1229 #define C1DRB3 0x10606
1230
1231 /** snb MCH registers for reading the DRAM channel configuration */
1232 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1233 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1234 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1235 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1236 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1237 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1238 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1239 #define MAD_DIMM_ECC_ON (0x3 << 24)
1240 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1241 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1242 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1243 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1244 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1245 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1246 #define MAD_DIMM_A_SELECT (0x1 << 16)
1247 /* DIMM sizes are in multiples of 256mb. */
1248 #define MAD_DIMM_B_SIZE_SHIFT 8
1249 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1250 #define MAD_DIMM_A_SIZE_SHIFT 0
1251 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1252
1253
1254 /* Clocking configuration register */
1255 #define CLKCFG 0x10c00
1256 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1257 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1258 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1259 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1260 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1261 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1262 /* Note, below two are guess */
1263 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1264 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1265 #define CLKCFG_FSB_MASK (7 << 0)
1266 #define CLKCFG_MEM_533 (1 << 4)
1267 #define CLKCFG_MEM_667 (2 << 4)
1268 #define CLKCFG_MEM_800 (3 << 4)
1269 #define CLKCFG_MEM_MASK (7 << 4)
1270
1271 #define TSC1 0x11001
1272 #define TSE (1<<0)
1273 #define TR1 0x11006
1274 #define TSFS 0x11020
1275 #define TSFS_SLOPE_MASK 0x0000ff00
1276 #define TSFS_SLOPE_SHIFT 8
1277 #define TSFS_INTR_MASK 0x000000ff
1278
1279 #define CRSTANDVID 0x11100
1280 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1281 #define PXVFREQ_PX_MASK 0x7f000000
1282 #define PXVFREQ_PX_SHIFT 24
1283 #define VIDFREQ_BASE 0x11110
1284 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1285 #define VIDFREQ2 0x11114
1286 #define VIDFREQ3 0x11118
1287 #define VIDFREQ4 0x1111c
1288 #define VIDFREQ_P0_MASK 0x1f000000
1289 #define VIDFREQ_P0_SHIFT 24
1290 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1291 #define VIDFREQ_P0_CSCLK_SHIFT 20
1292 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1293 #define VIDFREQ_P0_CRCLK_SHIFT 16
1294 #define VIDFREQ_P1_MASK 0x00001f00
1295 #define VIDFREQ_P1_SHIFT 8
1296 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1297 #define VIDFREQ_P1_CSCLK_SHIFT 4
1298 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1299 #define INTTOEXT_BASE_ILK 0x11300
1300 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1301 #define INTTOEXT_MAP3_SHIFT 24
1302 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1303 #define INTTOEXT_MAP2_SHIFT 16
1304 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1305 #define INTTOEXT_MAP1_SHIFT 8
1306 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1307 #define INTTOEXT_MAP0_SHIFT 0
1308 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1309 #define MEMSWCTL 0x11170 /* Ironlake only */
1310 #define MEMCTL_CMD_MASK 0xe000
1311 #define MEMCTL_CMD_SHIFT 13
1312 #define MEMCTL_CMD_RCLK_OFF 0
1313 #define MEMCTL_CMD_RCLK_ON 1
1314 #define MEMCTL_CMD_CHFREQ 2
1315 #define MEMCTL_CMD_CHVID 3
1316 #define MEMCTL_CMD_VMMOFF 4
1317 #define MEMCTL_CMD_VMMON 5
1318 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1319 when command complete */
1320 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1321 #define MEMCTL_FREQ_SHIFT 8
1322 #define MEMCTL_SFCAVM (1<<7)
1323 #define MEMCTL_TGT_VID_MASK 0x007f
1324 #define MEMIHYST 0x1117c
1325 #define MEMINTREN 0x11180 /* 16 bits */
1326 #define MEMINT_RSEXIT_EN (1<<8)
1327 #define MEMINT_CX_SUPR_EN (1<<7)
1328 #define MEMINT_CONT_BUSY_EN (1<<6)
1329 #define MEMINT_AVG_BUSY_EN (1<<5)
1330 #define MEMINT_EVAL_CHG_EN (1<<4)
1331 #define MEMINT_MON_IDLE_EN (1<<3)
1332 #define MEMINT_UP_EVAL_EN (1<<2)
1333 #define MEMINT_DOWN_EVAL_EN (1<<1)
1334 #define MEMINT_SW_CMD_EN (1<<0)
1335 #define MEMINTRSTR 0x11182 /* 16 bits */
1336 #define MEM_RSEXIT_MASK 0xc000
1337 #define MEM_RSEXIT_SHIFT 14
1338 #define MEM_CONT_BUSY_MASK 0x3000
1339 #define MEM_CONT_BUSY_SHIFT 12
1340 #define MEM_AVG_BUSY_MASK 0x0c00
1341 #define MEM_AVG_BUSY_SHIFT 10
1342 #define MEM_EVAL_CHG_MASK 0x0300
1343 #define MEM_EVAL_BUSY_SHIFT 8
1344 #define MEM_MON_IDLE_MASK 0x00c0
1345 #define MEM_MON_IDLE_SHIFT 6
1346 #define MEM_UP_EVAL_MASK 0x0030
1347 #define MEM_UP_EVAL_SHIFT 4
1348 #define MEM_DOWN_EVAL_MASK 0x000c
1349 #define MEM_DOWN_EVAL_SHIFT 2
1350 #define MEM_SW_CMD_MASK 0x0003
1351 #define MEM_INT_STEER_GFX 0
1352 #define MEM_INT_STEER_CMR 1
1353 #define MEM_INT_STEER_SMI 2
1354 #define MEM_INT_STEER_SCI 3
1355 #define MEMINTRSTS 0x11184
1356 #define MEMINT_RSEXIT (1<<7)
1357 #define MEMINT_CONT_BUSY (1<<6)
1358 #define MEMINT_AVG_BUSY (1<<5)
1359 #define MEMINT_EVAL_CHG (1<<4)
1360 #define MEMINT_MON_IDLE (1<<3)
1361 #define MEMINT_UP_EVAL (1<<2)
1362 #define MEMINT_DOWN_EVAL (1<<1)
1363 #define MEMINT_SW_CMD (1<<0)
1364 #define MEMMODECTL 0x11190
1365 #define MEMMODE_BOOST_EN (1<<31)
1366 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1367 #define MEMMODE_BOOST_FREQ_SHIFT 24
1368 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1369 #define MEMMODE_IDLE_MODE_SHIFT 16
1370 #define MEMMODE_IDLE_MODE_EVAL 0
1371 #define MEMMODE_IDLE_MODE_CONT 1
1372 #define MEMMODE_HWIDLE_EN (1<<15)
1373 #define MEMMODE_SWMODE_EN (1<<14)
1374 #define MEMMODE_RCLK_GATE (1<<13)
1375 #define MEMMODE_HW_UPDATE (1<<12)
1376 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1377 #define MEMMODE_FSTART_SHIFT 8
1378 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1379 #define MEMMODE_FMAX_SHIFT 4
1380 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1381 #define RCBMAXAVG 0x1119c
1382 #define MEMSWCTL2 0x1119e /* Cantiga only */
1383 #define SWMEMCMD_RENDER_OFF (0 << 13)
1384 #define SWMEMCMD_RENDER_ON (1 << 13)
1385 #define SWMEMCMD_SWFREQ (2 << 13)
1386 #define SWMEMCMD_TARVID (3 << 13)
1387 #define SWMEMCMD_VRM_OFF (4 << 13)
1388 #define SWMEMCMD_VRM_ON (5 << 13)
1389 #define CMDSTS (1<<12)
1390 #define SFCAVM (1<<11)
1391 #define SWFREQ_MASK 0x0380 /* P0-7 */
1392 #define SWFREQ_SHIFT 7
1393 #define TARVID_MASK 0x001f
1394 #define MEMSTAT_CTG 0x111a0
1395 #define RCBMINAVG 0x111a0
1396 #define RCUPEI 0x111b0
1397 #define RCDNEI 0x111b4
1398 #define RSTDBYCTL 0x111b8
1399 #define RS1EN (1<<31)
1400 #define RS2EN (1<<30)
1401 #define RS3EN (1<<29)
1402 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1403 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1404 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1405 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1406 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1407 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1408 #define RSX_STATUS_MASK (7<<20)
1409 #define RSX_STATUS_ON (0<<20)
1410 #define RSX_STATUS_RC1 (1<<20)
1411 #define RSX_STATUS_RC1E (2<<20)
1412 #define RSX_STATUS_RS1 (3<<20)
1413 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1414 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1415 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1416 #define RSX_STATUS_RSVD2 (7<<20)
1417 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1418 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1419 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1420 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1421 #define RS1CONTSAV_MASK (3<<14)
1422 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1423 #define RS1CONTSAV_RSVD (1<<14)
1424 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1425 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1426 #define NORMSLEXLAT_MASK (3<<12)
1427 #define SLOW_RS123 (0<<12)
1428 #define SLOW_RS23 (1<<12)
1429 #define SLOW_RS3 (2<<12)
1430 #define NORMAL_RS123 (3<<12)
1431 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1432 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1433 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1434 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1435 #define RS_CSTATE_MASK (3<<4)
1436 #define RS_CSTATE_C367_RS1 (0<<4)
1437 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1438 #define RS_CSTATE_RSVD (2<<4)
1439 #define RS_CSTATE_C367_RS2 (3<<4)
1440 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1441 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1442 #define VIDCTL 0x111c0
1443 #define VIDSTS 0x111c8
1444 #define VIDSTART 0x111cc /* 8 bits */
1445 #define MEMSTAT_ILK 0x111f8
1446 #define MEMSTAT_VID_MASK 0x7f00
1447 #define MEMSTAT_VID_SHIFT 8
1448 #define MEMSTAT_PSTATE_MASK 0x00f8
1449 #define MEMSTAT_PSTATE_SHIFT 3
1450 #define MEMSTAT_MON_ACTV (1<<2)
1451 #define MEMSTAT_SRC_CTL_MASK 0x0003
1452 #define MEMSTAT_SRC_CTL_CORE 0
1453 #define MEMSTAT_SRC_CTL_TRB 1
1454 #define MEMSTAT_SRC_CTL_THM 2
1455 #define MEMSTAT_SRC_CTL_STDBY 3
1456 #define RCPREVBSYTUPAVG 0x113b8
1457 #define RCPREVBSYTDNAVG 0x113bc
1458 #define PMMISC 0x11214
1459 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1460 #define SDEW 0x1124c
1461 #define CSIEW0 0x11250
1462 #define CSIEW1 0x11254
1463 #define CSIEW2 0x11258
1464 #define PEW 0x1125c
1465 #define DEW 0x11270
1466 #define MCHAFE 0x112c0
1467 #define CSIEC 0x112e0
1468 #define DMIEC 0x112e4
1469 #define DDREC 0x112e8
1470 #define PEG0EC 0x112ec
1471 #define PEG1EC 0x112f0
1472 #define GFXEC 0x112f4
1473 #define RPPREVBSYTUPAVG 0x113b8
1474 #define RPPREVBSYTDNAVG 0x113bc
1475 #define ECR 0x11600
1476 #define ECR_GPFE (1<<31)
1477 #define ECR_IMONE (1<<30)
1478 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1479 #define OGW0 0x11608
1480 #define OGW1 0x1160c
1481 #define EG0 0x11610
1482 #define EG1 0x11614
1483 #define EG2 0x11618
1484 #define EG3 0x1161c
1485 #define EG4 0x11620
1486 #define EG5 0x11624
1487 #define EG6 0x11628
1488 #define EG7 0x1162c
1489 #define PXW 0x11664
1490 #define PXWL 0x11680
1491 #define LCFUSE02 0x116c0
1492 #define LCFUSE_HIV_MASK 0x000000ff
1493 #define CSIPLL0 0x12c10
1494 #define DDRMPLL1 0X12c20
1495 #define PEG_BAND_GAP_DATA 0x14d68
1496
1497 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1498 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1499 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1500
1501 #define GEN6_GT_PERF_STATUS 0x145948
1502 #define GEN6_RP_STATE_LIMITS 0x145994
1503 #define GEN6_RP_STATE_CAP 0x145998
1504
1505 /*
1506 * Logical Context regs
1507 */
1508 #define CCID 0x2180
1509 #define CCID_EN (1<<0)
1510 #define CXT_SIZE 0x21a0
1511 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1512 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1513 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1514 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1515 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1516 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
1517 GEN6_CXT_RING_SIZE(cxt_reg) + \
1518 GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1519 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1520 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1521 #define GEN7_CXT_SIZE 0x21a8
1522 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1523 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1524 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1525 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1526 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1527 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1528 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \
1529 GEN7_CXT_RING_SIZE(ctx_reg) + \
1530 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1531 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1532 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1533 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1534 #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f)
1535 #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7)
1536 #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff)
1537 #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \
1538 HSW_CXT_RING_SIZE(ctx_reg) + \
1539 HSW_CXT_RENDER_SIZE(ctx_reg) + \
1540 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1541
1542
1543 /*
1544 * Overlay regs
1545 */
1546
1547 #define OVADD 0x30000
1548 #define DOVSTA 0x30008
1549 #define OC_BUF (0x3<<20)
1550 #define OGAMC5 0x30010
1551 #define OGAMC4 0x30014
1552 #define OGAMC3 0x30018
1553 #define OGAMC2 0x3001c
1554 #define OGAMC1 0x30020
1555 #define OGAMC0 0x30024
1556
1557 /*
1558 * Display engine regs
1559 */
1560
1561 /* Pipe A timing regs */
1562 #define _HTOTAL_A 0x60000
1563 #define _HBLANK_A 0x60004
1564 #define _HSYNC_A 0x60008
1565 #define _VTOTAL_A 0x6000c
1566 #define _VBLANK_A 0x60010
1567 #define _VSYNC_A 0x60014
1568 #define _PIPEASRC 0x6001c
1569 #define _BCLRPAT_A 0x60020
1570 #define _VSYNCSHIFT_A 0x60028
1571
1572 /* Pipe B timing regs */
1573 #define _HTOTAL_B 0x61000
1574 #define _HBLANK_B 0x61004
1575 #define _HSYNC_B 0x61008
1576 #define _VTOTAL_B 0x6100c
1577 #define _VBLANK_B 0x61010
1578 #define _VSYNC_B 0x61014
1579 #define _PIPEBSRC 0x6101c
1580 #define _BCLRPAT_B 0x61020
1581 #define _VSYNCSHIFT_B 0x61028
1582
1583
1584 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1585 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1586 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1587 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1588 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1589 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1590 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1591 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1592
1593 /* VGA port control */
1594 #define ADPA 0x61100
1595 #define PCH_ADPA 0xe1100
1596 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
1597
1598 #define ADPA_DAC_ENABLE (1<<31)
1599 #define ADPA_DAC_DISABLE 0
1600 #define ADPA_PIPE_SELECT_MASK (1<<30)
1601 #define ADPA_PIPE_A_SELECT 0
1602 #define ADPA_PIPE_B_SELECT (1<<30)
1603 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1604 /* CPT uses bits 29:30 for pch transcoder select */
1605 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1606 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
1607 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
1608 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1609 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
1610 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
1611 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
1612 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
1613 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
1614 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
1615 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
1616 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
1617 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
1618 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
1619 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
1620 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
1621 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
1622 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
1623 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1624 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1625 #define ADPA_SETS_HVPOLARITY 0
1626 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1627 #define ADPA_VSYNC_CNTL_ENABLE 0
1628 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1629 #define ADPA_HSYNC_CNTL_ENABLE 0
1630 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1631 #define ADPA_VSYNC_ACTIVE_LOW 0
1632 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1633 #define ADPA_HSYNC_ACTIVE_LOW 0
1634 #define ADPA_DPMS_MASK (~(3<<10))
1635 #define ADPA_DPMS_ON (0<<10)
1636 #define ADPA_DPMS_SUSPEND (1<<10)
1637 #define ADPA_DPMS_STANDBY (2<<10)
1638 #define ADPA_DPMS_OFF (3<<10)
1639
1640
1641 /* Hotplug control (945+ only) */
1642 #define PORT_HOTPLUG_EN 0x61110
1643 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1644 #define DPB_HOTPLUG_INT_EN (1 << 29)
1645 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1646 #define DPC_HOTPLUG_INT_EN (1 << 28)
1647 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1648 #define DPD_HOTPLUG_INT_EN (1 << 27)
1649 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1650 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1651 #define TV_HOTPLUG_INT_EN (1 << 18)
1652 #define CRT_HOTPLUG_INT_EN (1 << 9)
1653 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1654 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1655 /* must use period 64 on GM45 according to docs */
1656 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1657 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1658 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1659 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1660 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1661 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1662 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1663 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1664 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1665 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1666 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1667 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1668
1669 #define PORT_HOTPLUG_STAT 0x61114
1670 /* HDMI/DP bits are gen4+ */
1671 #define DPB_HOTPLUG_LIVE_STATUS (1 << 29)
1672 #define DPC_HOTPLUG_LIVE_STATUS (1 << 28)
1673 #define DPD_HOTPLUG_LIVE_STATUS (1 << 27)
1674 #define DPD_HOTPLUG_INT_STATUS (3 << 21)
1675 #define DPC_HOTPLUG_INT_STATUS (3 << 19)
1676 #define DPB_HOTPLUG_INT_STATUS (3 << 17)
1677 /* HDMI bits are shared with the DP bits */
1678 #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29)
1679 #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28)
1680 #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27)
1681 #define HDMID_HOTPLUG_INT_STATUS (3 << 21)
1682 #define HDMIC_HOTPLUG_INT_STATUS (3 << 19)
1683 #define HDMIB_HOTPLUG_INT_STATUS (3 << 17)
1684 /* CRT/TV common between gen3+ */
1685 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1686 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1687 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1688 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1689 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1690 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1691 /* SDVO is different across gen3/4 */
1692 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1693 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1694 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1695 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1696 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1697 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1698
1699 /* SDVO port control */
1700 #define SDVOB 0x61140
1701 #define SDVOC 0x61160
1702 #define SDVO_ENABLE (1 << 31)
1703 #define SDVO_PIPE_B_SELECT (1 << 30)
1704 #define SDVO_STALL_SELECT (1 << 29)
1705 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1706 /**
1707 * 915G/GM SDVO pixel multiplier.
1708 *
1709 * Programmed value is multiplier - 1, up to 5x.
1710 *
1711 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1712 */
1713 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1714 #define SDVO_PORT_MULTIPLY_SHIFT 23
1715 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1716 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1717 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1718 #define SDVOC_GANG_MODE (1 << 16)
1719 #define SDVO_ENCODING_SDVO (0x0 << 10)
1720 #define SDVO_ENCODING_HDMI (0x2 << 10)
1721 /** Requird for HDMI operation */
1722 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1723 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
1724 #define SDVO_BORDER_ENABLE (1 << 7)
1725 #define SDVO_AUDIO_ENABLE (1 << 6)
1726 /** New with 965, default is to be set */
1727 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1728 /** New with 965, default is to be set */
1729 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1730 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1731 #define SDVO_DETECTED (1 << 2)
1732 /* Bits to be preserved when writing */
1733 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1734 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1735
1736 /* DVO port control */
1737 #define DVOA 0x61120
1738 #define DVOB 0x61140
1739 #define DVOC 0x61160
1740 #define DVO_ENABLE (1 << 31)
1741 #define DVO_PIPE_B_SELECT (1 << 30)
1742 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1743 #define DVO_PIPE_STALL (1 << 28)
1744 #define DVO_PIPE_STALL_TV (2 << 28)
1745 #define DVO_PIPE_STALL_MASK (3 << 28)
1746 #define DVO_USE_VGA_SYNC (1 << 15)
1747 #define DVO_DATA_ORDER_I740 (0 << 14)
1748 #define DVO_DATA_ORDER_FP (1 << 14)
1749 #define DVO_VSYNC_DISABLE (1 << 11)
1750 #define DVO_HSYNC_DISABLE (1 << 10)
1751 #define DVO_VSYNC_TRISTATE (1 << 9)
1752 #define DVO_HSYNC_TRISTATE (1 << 8)
1753 #define DVO_BORDER_ENABLE (1 << 7)
1754 #define DVO_DATA_ORDER_GBRG (1 << 6)
1755 #define DVO_DATA_ORDER_RGGB (0 << 6)
1756 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1757 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1758 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1759 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1760 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1761 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1762 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1763 #define DVO_PRESERVE_MASK (0x7<<24)
1764 #define DVOA_SRCDIM 0x61124
1765 #define DVOB_SRCDIM 0x61144
1766 #define DVOC_SRCDIM 0x61164
1767 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1768 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1769
1770 /* LVDS port control */
1771 #define LVDS 0x61180
1772 /*
1773 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1774 * the DPLL semantics change when the LVDS is assigned to that pipe.
1775 */
1776 #define LVDS_PORT_EN (1 << 31)
1777 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1778 #define LVDS_PIPEB_SELECT (1 << 30)
1779 #define LVDS_PIPE_MASK (1 << 30)
1780 #define LVDS_PIPE(pipe) ((pipe) << 30)
1781 /* LVDS dithering flag on 965/g4x platform */
1782 #define LVDS_ENABLE_DITHER (1 << 25)
1783 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1784 #define LVDS_VSYNC_POLARITY (1 << 21)
1785 #define LVDS_HSYNC_POLARITY (1 << 20)
1786
1787 /* Enable border for unscaled (or aspect-scaled) display */
1788 #define LVDS_BORDER_ENABLE (1 << 15)
1789 /*
1790 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1791 * pixel.
1792 */
1793 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1794 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1795 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1796 /*
1797 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1798 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1799 * on.
1800 */
1801 #define LVDS_A3_POWER_MASK (3 << 6)
1802 #define LVDS_A3_POWER_DOWN (0 << 6)
1803 #define LVDS_A3_POWER_UP (3 << 6)
1804 /*
1805 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1806 * is set.
1807 */
1808 #define LVDS_CLKB_POWER_MASK (3 << 4)
1809 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1810 #define LVDS_CLKB_POWER_UP (3 << 4)
1811 /*
1812 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1813 * setting for whether we are in dual-channel mode. The B3 pair will
1814 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1815 */
1816 #define LVDS_B0B3_POWER_MASK (3 << 2)
1817 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1818 #define LVDS_B0B3_POWER_UP (3 << 2)
1819
1820 /* Video Data Island Packet control */
1821 #define VIDEO_DIP_DATA 0x61178
1822 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
1823 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1824 * of the infoframe structure specified by CEA-861. */
1825 #define VIDEO_DIP_DATA_SIZE 32
1826 #define VIDEO_DIP_CTL 0x61170
1827 /* Pre HSW: */
1828 #define VIDEO_DIP_ENABLE (1 << 31)
1829 #define VIDEO_DIP_PORT_B (1 << 29)
1830 #define VIDEO_DIP_PORT_C (2 << 29)
1831 #define VIDEO_DIP_PORT_D (3 << 29)
1832 #define VIDEO_DIP_PORT_MASK (3 << 29)
1833 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
1834 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1835 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1836 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
1837 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1838 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1839 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1840 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1841 #define VIDEO_DIP_SELECT_MASK (3 << 19)
1842 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1843 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1844 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1845 #define VIDEO_DIP_FREQ_MASK (3 << 16)
1846 /* HSW and later: */
1847 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
1848 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
1849 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
1850 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
1851 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
1852 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1853
1854 /* Panel power sequencing */
1855 #define PP_STATUS 0x61200
1856 #define PP_ON (1 << 31)
1857 /*
1858 * Indicates that all dependencies of the panel are on:
1859 *
1860 * - PLL enabled
1861 * - pipe enabled
1862 * - LVDS/DVOB/DVOC on
1863 */
1864 #define PP_READY (1 << 30)
1865 #define PP_SEQUENCE_NONE (0 << 28)
1866 #define PP_SEQUENCE_POWER_UP (1 << 28)
1867 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
1868 #define PP_SEQUENCE_MASK (3 << 28)
1869 #define PP_SEQUENCE_SHIFT 28
1870 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1871 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1872 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
1873 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
1874 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
1875 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
1876 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
1877 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
1878 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
1879 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
1880 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
1881 #define PP_CONTROL 0x61204
1882 #define POWER_TARGET_ON (1 << 0)
1883 #define PP_ON_DELAYS 0x61208
1884 #define PP_OFF_DELAYS 0x6120c
1885 #define PP_DIVISOR 0x61210
1886
1887 /* Panel fitting */
1888 #define PFIT_CONTROL 0x61230
1889 #define PFIT_ENABLE (1 << 31)
1890 #define PFIT_PIPE_MASK (3 << 29)
1891 #define PFIT_PIPE_SHIFT 29
1892 #define VERT_INTERP_DISABLE (0 << 10)
1893 #define VERT_INTERP_BILINEAR (1 << 10)
1894 #define VERT_INTERP_MASK (3 << 10)
1895 #define VERT_AUTO_SCALE (1 << 9)
1896 #define HORIZ_INTERP_DISABLE (0 << 6)
1897 #define HORIZ_INTERP_BILINEAR (1 << 6)
1898 #define HORIZ_INTERP_MASK (3 << 6)
1899 #define HORIZ_AUTO_SCALE (1 << 5)
1900 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1901 #define PFIT_FILTER_FUZZY (0 << 24)
1902 #define PFIT_SCALING_AUTO (0 << 26)
1903 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1904 #define PFIT_SCALING_PILLAR (2 << 26)
1905 #define PFIT_SCALING_LETTER (3 << 26)
1906 #define PFIT_PGM_RATIOS 0x61234
1907 #define PFIT_VERT_SCALE_MASK 0xfff00000
1908 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1909 /* Pre-965 */
1910 #define PFIT_VERT_SCALE_SHIFT 20
1911 #define PFIT_VERT_SCALE_MASK 0xfff00000
1912 #define PFIT_HORIZ_SCALE_SHIFT 4
1913 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1914 /* 965+ */
1915 #define PFIT_VERT_SCALE_SHIFT_965 16
1916 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1917 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1918 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1919
1920 #define PFIT_AUTO_RATIOS 0x61238
1921
1922 /* Backlight control */
1923 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1924 #define BLM_PWM_ENABLE (1 << 31)
1925 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
1926 #define BLM_PIPE_SELECT (1 << 29)
1927 #define BLM_PIPE_SELECT_IVB (3 << 29)
1928 #define BLM_PIPE_A (0 << 29)
1929 #define BLM_PIPE_B (1 << 29)
1930 #define BLM_PIPE_C (2 << 29) /* ivb + */
1931 #define BLM_PIPE(pipe) ((pipe) << 29)
1932 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
1933 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
1934 #define BLM_PHASE_IN_ENABLE (1 << 25)
1935 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
1936 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
1937 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
1938 #define BLM_PHASE_IN_COUNT_SHIFT (8)
1939 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
1940 #define BLM_PHASE_IN_INCR_SHIFT (0)
1941 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
1942 #define BLC_PWM_CTL 0x61254
1943 /*
1944 * This is the most significant 15 bits of the number of backlight cycles in a
1945 * complete cycle of the modulated backlight control.
1946 *
1947 * The actual value is this field multiplied by two.
1948 */
1949 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1950 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1951 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
1952 /*
1953 * This is the number of cycles out of the backlight modulation cycle for which
1954 * the backlight is on.
1955 *
1956 * This field must be no greater than the number of cycles in the complete
1957 * backlight modulation cycle.
1958 */
1959 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1960 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1961 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
1962 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
1963
1964 #define BLC_HIST_CTL 0x61260
1965
1966 /* New registers for PCH-split platforms. Safe where new bits show up, the
1967 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
1968 #define BLC_PWM_CPU_CTL2 0x48250
1969 #define BLC_PWM_CPU_CTL 0x48254
1970
1971 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
1972 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
1973 #define BLC_PWM_PCH_CTL1 0xc8250
1974 #define BLM_PCH_PWM_ENABLE (1 << 31)
1975 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
1976 #define BLM_PCH_POLARITY (1 << 29)
1977 #define BLC_PWM_PCH_CTL2 0xc8254
1978
1979 /* TV port control */
1980 #define TV_CTL 0x68000
1981 /** Enables the TV encoder */
1982 # define TV_ENC_ENABLE (1 << 31)
1983 /** Sources the TV encoder input from pipe B instead of A. */
1984 # define TV_ENC_PIPEB_SELECT (1 << 30)
1985 /** Outputs composite video (DAC A only) */
1986 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1987 /** Outputs SVideo video (DAC B/C) */
1988 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1989 /** Outputs Component video (DAC A/B/C) */
1990 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1991 /** Outputs Composite and SVideo (DAC A/B/C) */
1992 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1993 # define TV_TRILEVEL_SYNC (1 << 21)
1994 /** Enables slow sync generation (945GM only) */
1995 # define TV_SLOW_SYNC (1 << 20)
1996 /** Selects 4x oversampling for 480i and 576p */
1997 # define TV_OVERSAMPLE_4X (0 << 18)
1998 /** Selects 2x oversampling for 720p and 1080i */
1999 # define TV_OVERSAMPLE_2X (1 << 18)
2000 /** Selects no oversampling for 1080p */
2001 # define TV_OVERSAMPLE_NONE (2 << 18)
2002 /** Selects 8x oversampling */
2003 # define TV_OVERSAMPLE_8X (3 << 18)
2004 /** Selects progressive mode rather than interlaced */
2005 # define TV_PROGRESSIVE (1 << 17)
2006 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2007 # define TV_PAL_BURST (1 << 16)
2008 /** Field for setting delay of Y compared to C */
2009 # define TV_YC_SKEW_MASK (7 << 12)
2010 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2011 # define TV_ENC_SDP_FIX (1 << 11)
2012 /**
2013 * Enables a fix for the 915GM only.
2014 *
2015 * Not sure what it does.
2016 */
2017 # define TV_ENC_C0_FIX (1 << 10)
2018 /** Bits that must be preserved by software */
2019 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2020 # define TV_FUSE_STATE_MASK (3 << 4)
2021 /** Read-only state that reports all features enabled */
2022 # define TV_FUSE_STATE_ENABLED (0 << 4)
2023 /** Read-only state that reports that Macrovision is disabled in hardware*/
2024 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2025 /** Read-only state that reports that TV-out is disabled in hardware. */
2026 # define TV_FUSE_STATE_DISABLED (2 << 4)
2027 /** Normal operation */
2028 # define TV_TEST_MODE_NORMAL (0 << 0)
2029 /** Encoder test pattern 1 - combo pattern */
2030 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2031 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2032 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2033 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2034 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2035 /** Encoder test pattern 4 - random noise */
2036 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2037 /** Encoder test pattern 5 - linear color ramps */
2038 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2039 /**
2040 * This test mode forces the DACs to 50% of full output.
2041 *
2042 * This is used for load detection in combination with TVDAC_SENSE_MASK
2043 */
2044 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2045 # define TV_TEST_MODE_MASK (7 << 0)
2046
2047 #define TV_DAC 0x68004
2048 # define TV_DAC_SAVE 0x00ffff00
2049 /**
2050 * Reports that DAC state change logic has reported change (RO).
2051 *
2052 * This gets cleared when TV_DAC_STATE_EN is cleared
2053 */
2054 # define TVDAC_STATE_CHG (1 << 31)
2055 # define TVDAC_SENSE_MASK (7 << 28)
2056 /** Reports that DAC A voltage is above the detect threshold */
2057 # define TVDAC_A_SENSE (1 << 30)
2058 /** Reports that DAC B voltage is above the detect threshold */
2059 # define TVDAC_B_SENSE (1 << 29)
2060 /** Reports that DAC C voltage is above the detect threshold */
2061 # define TVDAC_C_SENSE (1 << 28)
2062 /**
2063 * Enables DAC state detection logic, for load-based TV detection.
2064 *
2065 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2066 * to off, for load detection to work.
2067 */
2068 # define TVDAC_STATE_CHG_EN (1 << 27)
2069 /** Sets the DAC A sense value to high */
2070 # define TVDAC_A_SENSE_CTL (1 << 26)
2071 /** Sets the DAC B sense value to high */
2072 # define TVDAC_B_SENSE_CTL (1 << 25)
2073 /** Sets the DAC C sense value to high */
2074 # define TVDAC_C_SENSE_CTL (1 << 24)
2075 /** Overrides the ENC_ENABLE and DAC voltage levels */
2076 # define DAC_CTL_OVERRIDE (1 << 7)
2077 /** Sets the slew rate. Must be preserved in software */
2078 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2079 # define DAC_A_1_3_V (0 << 4)
2080 # define DAC_A_1_1_V (1 << 4)
2081 # define DAC_A_0_7_V (2 << 4)
2082 # define DAC_A_MASK (3 << 4)
2083 # define DAC_B_1_3_V (0 << 2)
2084 # define DAC_B_1_1_V (1 << 2)
2085 # define DAC_B_0_7_V (2 << 2)
2086 # define DAC_B_MASK (3 << 2)
2087 # define DAC_C_1_3_V (0 << 0)
2088 # define DAC_C_1_1_V (1 << 0)
2089 # define DAC_C_0_7_V (2 << 0)
2090 # define DAC_C_MASK (3 << 0)
2091
2092 /**
2093 * CSC coefficients are stored in a floating point format with 9 bits of
2094 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2095 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2096 * -1 (0x3) being the only legal negative value.
2097 */
2098 #define TV_CSC_Y 0x68010
2099 # define TV_RY_MASK 0x07ff0000
2100 # define TV_RY_SHIFT 16
2101 # define TV_GY_MASK 0x00000fff
2102 # define TV_GY_SHIFT 0
2103
2104 #define TV_CSC_Y2 0x68014
2105 # define TV_BY_MASK 0x07ff0000
2106 # define TV_BY_SHIFT 16
2107 /**
2108 * Y attenuation for component video.
2109 *
2110 * Stored in 1.9 fixed point.
2111 */
2112 # define TV_AY_MASK 0x000003ff
2113 # define TV_AY_SHIFT 0
2114
2115 #define TV_CSC_U 0x68018
2116 # define TV_RU_MASK 0x07ff0000
2117 # define TV_RU_SHIFT 16
2118 # define TV_GU_MASK 0x000007ff
2119 # define TV_GU_SHIFT 0
2120
2121 #define TV_CSC_U2 0x6801c
2122 # define TV_BU_MASK 0x07ff0000
2123 # define TV_BU_SHIFT 16
2124 /**
2125 * U attenuation for component video.
2126 *
2127 * Stored in 1.9 fixed point.
2128 */
2129 # define TV_AU_MASK 0x000003ff
2130 # define TV_AU_SHIFT 0
2131
2132 #define TV_CSC_V 0x68020
2133 # define TV_RV_MASK 0x0fff0000
2134 # define TV_RV_SHIFT 16
2135 # define TV_GV_MASK 0x000007ff
2136 # define TV_GV_SHIFT 0
2137
2138 #define TV_CSC_V2 0x68024
2139 # define TV_BV_MASK 0x07ff0000
2140 # define TV_BV_SHIFT 16
2141 /**
2142 * V attenuation for component video.
2143 *
2144 * Stored in 1.9 fixed point.
2145 */
2146 # define TV_AV_MASK 0x000007ff
2147 # define TV_AV_SHIFT 0
2148
2149 #define TV_CLR_KNOBS 0x68028
2150 /** 2s-complement brightness adjustment */
2151 # define TV_BRIGHTNESS_MASK 0xff000000
2152 # define TV_BRIGHTNESS_SHIFT 24
2153 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2154 # define TV_CONTRAST_MASK 0x00ff0000
2155 # define TV_CONTRAST_SHIFT 16
2156 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2157 # define TV_SATURATION_MASK 0x0000ff00
2158 # define TV_SATURATION_SHIFT 8
2159 /** Hue adjustment, as an integer phase angle in degrees */
2160 # define TV_HUE_MASK 0x000000ff
2161 # define TV_HUE_SHIFT 0
2162
2163 #define TV_CLR_LEVEL 0x6802c
2164 /** Controls the DAC level for black */
2165 # define TV_BLACK_LEVEL_MASK 0x01ff0000
2166 # define TV_BLACK_LEVEL_SHIFT 16
2167 /** Controls the DAC level for blanking */
2168 # define TV_BLANK_LEVEL_MASK 0x000001ff
2169 # define TV_BLANK_LEVEL_SHIFT 0
2170
2171 #define TV_H_CTL_1 0x68030
2172 /** Number of pixels in the hsync. */
2173 # define TV_HSYNC_END_MASK 0x1fff0000
2174 # define TV_HSYNC_END_SHIFT 16
2175 /** Total number of pixels minus one in the line (display and blanking). */
2176 # define TV_HTOTAL_MASK 0x00001fff
2177 # define TV_HTOTAL_SHIFT 0
2178
2179 #define TV_H_CTL_2 0x68034
2180 /** Enables the colorburst (needed for non-component color) */
2181 # define TV_BURST_ENA (1 << 31)
2182 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2183 # define TV_HBURST_START_SHIFT 16
2184 # define TV_HBURST_START_MASK 0x1fff0000
2185 /** Length of the colorburst */
2186 # define TV_HBURST_LEN_SHIFT 0
2187 # define TV_HBURST_LEN_MASK 0x0001fff
2188
2189 #define TV_H_CTL_3 0x68038
2190 /** End of hblank, measured in pixels minus one from start of hsync */
2191 # define TV_HBLANK_END_SHIFT 16
2192 # define TV_HBLANK_END_MASK 0x1fff0000
2193 /** Start of hblank, measured in pixels minus one from start of hsync */
2194 # define TV_HBLANK_START_SHIFT 0
2195 # define TV_HBLANK_START_MASK 0x0001fff
2196
2197 #define TV_V_CTL_1 0x6803c
2198 /** XXX */
2199 # define TV_NBR_END_SHIFT 16
2200 # define TV_NBR_END_MASK 0x07ff0000
2201 /** XXX */
2202 # define TV_VI_END_F1_SHIFT 8
2203 # define TV_VI_END_F1_MASK 0x00003f00
2204 /** XXX */
2205 # define TV_VI_END_F2_SHIFT 0
2206 # define TV_VI_END_F2_MASK 0x0000003f
2207
2208 #define TV_V_CTL_2 0x68040
2209 /** Length of vsync, in half lines */
2210 # define TV_VSYNC_LEN_MASK 0x07ff0000
2211 # define TV_VSYNC_LEN_SHIFT 16
2212 /** Offset of the start of vsync in field 1, measured in one less than the
2213 * number of half lines.
2214 */
2215 # define TV_VSYNC_START_F1_MASK 0x00007f00
2216 # define TV_VSYNC_START_F1_SHIFT 8
2217 /**
2218 * Offset of the start of vsync in field 2, measured in one less than the
2219 * number of half lines.
2220 */
2221 # define TV_VSYNC_START_F2_MASK 0x0000007f
2222 # define TV_VSYNC_START_F2_SHIFT 0
2223
2224 #define TV_V_CTL_3 0x68044
2225 /** Enables generation of the equalization signal */
2226 # define TV_EQUAL_ENA (1 << 31)
2227 /** Length of vsync, in half lines */
2228 # define TV_VEQ_LEN_MASK 0x007f0000
2229 # define TV_VEQ_LEN_SHIFT 16
2230 /** Offset of the start of equalization in field 1, measured in one less than
2231 * the number of half lines.
2232 */
2233 # define TV_VEQ_START_F1_MASK 0x0007f00
2234 # define TV_VEQ_START_F1_SHIFT 8
2235 /**
2236 * Offset of the start of equalization in field 2, measured in one less than
2237 * the number of half lines.
2238 */
2239 # define TV_VEQ_START_F2_MASK 0x000007f
2240 # define TV_VEQ_START_F2_SHIFT 0
2241
2242 #define TV_V_CTL_4 0x68048
2243 /**
2244 * Offset to start of vertical colorburst, measured in one less than the
2245 * number of lines from vertical start.
2246 */
2247 # define TV_VBURST_START_F1_MASK 0x003f0000
2248 # define TV_VBURST_START_F1_SHIFT 16
2249 /**
2250 * Offset to the end of vertical colorburst, measured in one less than the
2251 * number of lines from the start of NBR.
2252 */
2253 # define TV_VBURST_END_F1_MASK 0x000000ff
2254 # define TV_VBURST_END_F1_SHIFT 0
2255
2256 #define TV_V_CTL_5 0x6804c
2257 /**
2258 * Offset to start of vertical colorburst, measured in one less than the
2259 * number of lines from vertical start.
2260 */
2261 # define TV_VBURST_START_F2_MASK 0x003f0000
2262 # define TV_VBURST_START_F2_SHIFT 16
2263 /**
2264 * Offset to the end of vertical colorburst, measured in one less than the
2265 * number of lines from the start of NBR.
2266 */
2267 # define TV_VBURST_END_F2_MASK 0x000000ff
2268 # define TV_VBURST_END_F2_SHIFT 0
2269
2270 #define TV_V_CTL_6 0x68050
2271 /**
2272 * Offset to start of vertical colorburst, measured in one less than the
2273 * number of lines from vertical start.
2274 */
2275 # define TV_VBURST_START_F3_MASK 0x003f0000
2276 # define TV_VBURST_START_F3_SHIFT 16
2277 /**
2278 * Offset to the end of vertical colorburst, measured in one less than the
2279 * number of lines from the start of NBR.
2280 */
2281 # define TV_VBURST_END_F3_MASK 0x000000ff
2282 # define TV_VBURST_END_F3_SHIFT 0
2283
2284 #define TV_V_CTL_7 0x68054
2285 /**
2286 * Offset to start of vertical colorburst, measured in one less than the
2287 * number of lines from vertical start.
2288 */
2289 # define TV_VBURST_START_F4_MASK 0x003f0000
2290 # define TV_VBURST_START_F4_SHIFT 16
2291 /**
2292 * Offset to the end of vertical colorburst, measured in one less than the
2293 * number of lines from the start of NBR.
2294 */
2295 # define TV_VBURST_END_F4_MASK 0x000000ff
2296 # define TV_VBURST_END_F4_SHIFT 0
2297
2298 #define TV_SC_CTL_1 0x68060
2299 /** Turns on the first subcarrier phase generation DDA */
2300 # define TV_SC_DDA1_EN (1 << 31)
2301 /** Turns on the first subcarrier phase generation DDA */
2302 # define TV_SC_DDA2_EN (1 << 30)
2303 /** Turns on the first subcarrier phase generation DDA */
2304 # define TV_SC_DDA3_EN (1 << 29)
2305 /** Sets the subcarrier DDA to reset frequency every other field */
2306 # define TV_SC_RESET_EVERY_2 (0 << 24)
2307 /** Sets the subcarrier DDA to reset frequency every fourth field */
2308 # define TV_SC_RESET_EVERY_4 (1 << 24)
2309 /** Sets the subcarrier DDA to reset frequency every eighth field */
2310 # define TV_SC_RESET_EVERY_8 (2 << 24)
2311 /** Sets the subcarrier DDA to never reset the frequency */
2312 # define TV_SC_RESET_NEVER (3 << 24)
2313 /** Sets the peak amplitude of the colorburst.*/
2314 # define TV_BURST_LEVEL_MASK 0x00ff0000
2315 # define TV_BURST_LEVEL_SHIFT 16
2316 /** Sets the increment of the first subcarrier phase generation DDA */
2317 # define TV_SCDDA1_INC_MASK 0x00000fff
2318 # define TV_SCDDA1_INC_SHIFT 0
2319
2320 #define TV_SC_CTL_2 0x68064
2321 /** Sets the rollover for the second subcarrier phase generation DDA */
2322 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2323 # define TV_SCDDA2_SIZE_SHIFT 16
2324 /** Sets the increent of the second subcarrier phase generation DDA */
2325 # define TV_SCDDA2_INC_MASK 0x00007fff
2326 # define TV_SCDDA2_INC_SHIFT 0
2327
2328 #define TV_SC_CTL_3 0x68068
2329 /** Sets the rollover for the third subcarrier phase generation DDA */
2330 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2331 # define TV_SCDDA3_SIZE_SHIFT 16
2332 /** Sets the increent of the third subcarrier phase generation DDA */
2333 # define TV_SCDDA3_INC_MASK 0x00007fff
2334 # define TV_SCDDA3_INC_SHIFT 0
2335
2336 #define TV_WIN_POS 0x68070
2337 /** X coordinate of the display from the start of horizontal active */
2338 # define TV_XPOS_MASK 0x1fff0000
2339 # define TV_XPOS_SHIFT 16
2340 /** Y coordinate of the display from the start of vertical active (NBR) */
2341 # define TV_YPOS_MASK 0x00000fff
2342 # define TV_YPOS_SHIFT 0
2343
2344 #define TV_WIN_SIZE 0x68074
2345 /** Horizontal size of the display window, measured in pixels*/
2346 # define TV_XSIZE_MASK 0x1fff0000
2347 # define TV_XSIZE_SHIFT 16
2348 /**
2349 * Vertical size of the display window, measured in pixels.
2350 *
2351 * Must be even for interlaced modes.
2352 */
2353 # define TV_YSIZE_MASK 0x00000fff
2354 # define TV_YSIZE_SHIFT 0
2355
2356 #define TV_FILTER_CTL_1 0x68080
2357 /**
2358 * Enables automatic scaling calculation.
2359 *
2360 * If set, the rest of the registers are ignored, and the calculated values can
2361 * be read back from the register.
2362 */
2363 # define TV_AUTO_SCALE (1 << 31)
2364 /**
2365 * Disables the vertical filter.
2366 *
2367 * This is required on modes more than 1024 pixels wide */
2368 # define TV_V_FILTER_BYPASS (1 << 29)
2369 /** Enables adaptive vertical filtering */
2370 # define TV_VADAPT (1 << 28)
2371 # define TV_VADAPT_MODE_MASK (3 << 26)
2372 /** Selects the least adaptive vertical filtering mode */
2373 # define TV_VADAPT_MODE_LEAST (0 << 26)
2374 /** Selects the moderately adaptive vertical filtering mode */
2375 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2376 /** Selects the most adaptive vertical filtering mode */
2377 # define TV_VADAPT_MODE_MOST (3 << 26)
2378 /**
2379 * Sets the horizontal scaling factor.
2380 *
2381 * This should be the fractional part of the horizontal scaling factor divided
2382 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2383 *
2384 * (src width - 1) / ((oversample * dest width) - 1)
2385 */
2386 # define TV_HSCALE_FRAC_MASK 0x00003fff
2387 # define TV_HSCALE_FRAC_SHIFT 0
2388
2389 #define TV_FILTER_CTL_2 0x68084
2390 /**
2391 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2392 *
2393 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2394 */
2395 # define TV_VSCALE_INT_MASK 0x00038000
2396 # define TV_VSCALE_INT_SHIFT 15
2397 /**
2398 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2399 *
2400 * \sa TV_VSCALE_INT_MASK
2401 */
2402 # define TV_VSCALE_FRAC_MASK 0x00007fff
2403 # define TV_VSCALE_FRAC_SHIFT 0
2404
2405 #define TV_FILTER_CTL_3 0x68088
2406 /**
2407 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2408 *
2409 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2410 *
2411 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2412 */
2413 # define TV_VSCALE_IP_INT_MASK 0x00038000
2414 # define TV_VSCALE_IP_INT_SHIFT 15
2415 /**
2416 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2417 *
2418 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2419 *
2420 * \sa TV_VSCALE_IP_INT_MASK
2421 */
2422 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2423 # define TV_VSCALE_IP_FRAC_SHIFT 0
2424
2425 #define TV_CC_CONTROL 0x68090
2426 # define TV_CC_ENABLE (1 << 31)
2427 /**
2428 * Specifies which field to send the CC data in.
2429 *
2430 * CC data is usually sent in field 0.
2431 */
2432 # define TV_CC_FID_MASK (1 << 27)
2433 # define TV_CC_FID_SHIFT 27
2434 /** Sets the horizontal position of the CC data. Usually 135. */
2435 # define TV_CC_HOFF_MASK 0x03ff0000
2436 # define TV_CC_HOFF_SHIFT 16
2437 /** Sets the vertical position of the CC data. Usually 21 */
2438 # define TV_CC_LINE_MASK 0x0000003f
2439 # define TV_CC_LINE_SHIFT 0
2440
2441 #define TV_CC_DATA 0x68094
2442 # define TV_CC_RDY (1 << 31)
2443 /** Second word of CC data to be transmitted. */
2444 # define TV_CC_DATA_2_MASK 0x007f0000
2445 # define TV_CC_DATA_2_SHIFT 16
2446 /** First word of CC data to be transmitted. */
2447 # define TV_CC_DATA_1_MASK 0x0000007f
2448 # define TV_CC_DATA_1_SHIFT 0
2449
2450 #define TV_H_LUMA_0 0x68100
2451 #define TV_H_LUMA_59 0x681ec
2452 #define TV_H_CHROMA_0 0x68200
2453 #define TV_H_CHROMA_59 0x682ec
2454 #define TV_V_LUMA_0 0x68300
2455 #define TV_V_LUMA_42 0x683a8
2456 #define TV_V_CHROMA_0 0x68400
2457 #define TV_V_CHROMA_42 0x684a8
2458
2459 /* Display Port */
2460 #define DP_A 0x64000 /* eDP */
2461 #define DP_B 0x64100
2462 #define DP_C 0x64200
2463 #define DP_D 0x64300
2464
2465 #define DP_PORT_EN (1 << 31)
2466 #define DP_PIPEB_SELECT (1 << 30)
2467 #define DP_PIPE_MASK (1 << 30)
2468
2469 /* Link training mode - select a suitable mode for each stage */
2470 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2471 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2472 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2473 #define DP_LINK_TRAIN_OFF (3 << 28)
2474 #define DP_LINK_TRAIN_MASK (3 << 28)
2475 #define DP_LINK_TRAIN_SHIFT 28
2476
2477 /* CPT Link training mode */
2478 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2479 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2480 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2481 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2482 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2483 #define DP_LINK_TRAIN_SHIFT_CPT 8
2484
2485 /* Signal voltages. These are mostly controlled by the other end */
2486 #define DP_VOLTAGE_0_4 (0 << 25)
2487 #define DP_VOLTAGE_0_6 (1 << 25)
2488 #define DP_VOLTAGE_0_8 (2 << 25)
2489 #define DP_VOLTAGE_1_2 (3 << 25)
2490 #define DP_VOLTAGE_MASK (7 << 25)
2491 #define DP_VOLTAGE_SHIFT 25
2492
2493 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2494 * they want
2495 */
2496 #define DP_PRE_EMPHASIS_0 (0 << 22)
2497 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2498 #define DP_PRE_EMPHASIS_6 (2 << 22)
2499 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2500 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2501 #define DP_PRE_EMPHASIS_SHIFT 22
2502
2503 /* How many wires to use. I guess 3 was too hard */
2504 #define DP_PORT_WIDTH_1 (0 << 19)
2505 #define DP_PORT_WIDTH_2 (1 << 19)
2506 #define DP_PORT_WIDTH_4 (3 << 19)
2507 #define DP_PORT_WIDTH_MASK (7 << 19)
2508
2509 /* Mystic DPCD version 1.1 special mode */
2510 #define DP_ENHANCED_FRAMING (1 << 18)
2511
2512 /* eDP */
2513 #define DP_PLL_FREQ_270MHZ (0 << 16)
2514 #define DP_PLL_FREQ_160MHZ (1 << 16)
2515 #define DP_PLL_FREQ_MASK (3 << 16)
2516
2517 /** locked once port is enabled */
2518 #define DP_PORT_REVERSAL (1 << 15)
2519
2520 /* eDP */
2521 #define DP_PLL_ENABLE (1 << 14)
2522
2523 /** sends the clock on lane 15 of the PEG for debug */
2524 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2525
2526 #define DP_SCRAMBLING_DISABLE (1 << 12)
2527 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2528
2529 /** limit RGB values to avoid confusing TVs */
2530 #define DP_COLOR_RANGE_16_235 (1 << 8)
2531
2532 /** Turn on the audio link */
2533 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2534
2535 /** vs and hs sync polarity */
2536 #define DP_SYNC_VS_HIGH (1 << 4)
2537 #define DP_SYNC_HS_HIGH (1 << 3)
2538
2539 /** A fantasy */
2540 #define DP_DETECTED (1 << 2)
2541
2542 /** The aux channel provides a way to talk to the
2543 * signal sink for DDC etc. Max packet size supported
2544 * is 20 bytes in each direction, hence the 5 fixed
2545 * data registers
2546 */
2547 #define DPA_AUX_CH_CTL 0x64010
2548 #define DPA_AUX_CH_DATA1 0x64014
2549 #define DPA_AUX_CH_DATA2 0x64018
2550 #define DPA_AUX_CH_DATA3 0x6401c
2551 #define DPA_AUX_CH_DATA4 0x64020
2552 #define DPA_AUX_CH_DATA5 0x64024
2553
2554 #define DPB_AUX_CH_CTL 0x64110
2555 #define DPB_AUX_CH_DATA1 0x64114
2556 #define DPB_AUX_CH_DATA2 0x64118
2557 #define DPB_AUX_CH_DATA3 0x6411c
2558 #define DPB_AUX_CH_DATA4 0x64120
2559 #define DPB_AUX_CH_DATA5 0x64124
2560
2561 #define DPC_AUX_CH_CTL 0x64210
2562 #define DPC_AUX_CH_DATA1 0x64214
2563 #define DPC_AUX_CH_DATA2 0x64218
2564 #define DPC_AUX_CH_DATA3 0x6421c
2565 #define DPC_AUX_CH_DATA4 0x64220
2566 #define DPC_AUX_CH_DATA5 0x64224
2567
2568 #define DPD_AUX_CH_CTL 0x64310
2569 #define DPD_AUX_CH_DATA1 0x64314
2570 #define DPD_AUX_CH_DATA2 0x64318
2571 #define DPD_AUX_CH_DATA3 0x6431c
2572 #define DPD_AUX_CH_DATA4 0x64320
2573 #define DPD_AUX_CH_DATA5 0x64324
2574
2575 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2576 #define DP_AUX_CH_CTL_DONE (1 << 30)
2577 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2578 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2579 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2580 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2581 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2582 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2583 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2584 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2585 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2586 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2587 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2588 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2589 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2590 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2591 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2592 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2593 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2594 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2595 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2596
2597 /*
2598 * Computing GMCH M and N values for the Display Port link
2599 *
2600 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2601 *
2602 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2603 *
2604 * The GMCH value is used internally
2605 *
2606 * bytes_per_pixel is the number of bytes coming out of the plane,
2607 * which is after the LUTs, so we want the bytes for our color format.
2608 * For our current usage, this is always 3, one byte for R, G and B.
2609 */
2610 #define _PIPEA_GMCH_DATA_M 0x70050
2611 #define _PIPEB_GMCH_DATA_M 0x71050
2612
2613 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2614 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2615 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2616
2617 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2618
2619 #define _PIPEA_GMCH_DATA_N 0x70054
2620 #define _PIPEB_GMCH_DATA_N 0x71054
2621 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2622
2623 /*
2624 * Computing Link M and N values for the Display Port link
2625 *
2626 * Link M / N = pixel_clock / ls_clk
2627 *
2628 * (the DP spec calls pixel_clock the 'strm_clk')
2629 *
2630 * The Link value is transmitted in the Main Stream
2631 * Attributes and VB-ID.
2632 */
2633
2634 #define _PIPEA_DP_LINK_M 0x70060
2635 #define _PIPEB_DP_LINK_M 0x71060
2636 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2637
2638 #define _PIPEA_DP_LINK_N 0x70064
2639 #define _PIPEB_DP_LINK_N 0x71064
2640 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2641
2642 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2643 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2644 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2645 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2646
2647 /* Display & cursor control */
2648
2649 /* Pipe A */
2650 #define _PIPEADSL 0x70000
2651 #define DSL_LINEMASK_GEN2 0x00000fff
2652 #define DSL_LINEMASK_GEN3 0x00001fff
2653 #define _PIPEACONF 0x70008
2654 #define PIPECONF_ENABLE (1<<31)
2655 #define PIPECONF_DISABLE 0
2656 #define PIPECONF_DOUBLE_WIDE (1<<30)
2657 #define I965_PIPECONF_ACTIVE (1<<30)
2658 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2659 #define PIPECONF_SINGLE_WIDE 0
2660 #define PIPECONF_PIPE_UNLOCKED 0
2661 #define PIPECONF_PIPE_LOCKED (1<<25)
2662 #define PIPECONF_PALETTE 0
2663 #define PIPECONF_GAMMA (1<<24)
2664 #define PIPECONF_FORCE_BORDER (1<<25)
2665 #define PIPECONF_INTERLACE_MASK (7 << 21)
2666 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
2667 /* Note that pre-gen3 does not support interlaced display directly. Panel
2668 * fitting must be disabled on pre-ilk for interlaced. */
2669 #define PIPECONF_PROGRESSIVE (0 << 21)
2670 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2671 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2672 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2673 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2674 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2675 * means panel fitter required, PF means progressive fetch, DBL means power
2676 * saving pixel doubling. */
2677 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2678 #define PIPECONF_INTERLACED_ILK (3 << 21)
2679 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2680 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2681 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2682 #define PIPECONF_BPP_MASK (0x000000e0)
2683 #define PIPECONF_BPP_8 (0<<5)
2684 #define PIPECONF_BPP_10 (1<<5)
2685 #define PIPECONF_BPP_6 (2<<5)
2686 #define PIPECONF_BPP_12 (3<<5)
2687 #define PIPECONF_DITHER_EN (1<<4)
2688 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2689 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2690 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2691 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2692 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2693 #define _PIPEASTAT 0x70024
2694 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2695 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
2696 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2697 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2698 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2699 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
2700 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2701 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2702 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2703 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2704 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26)
2705 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2706 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2707 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2708 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2709 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2710 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2711 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
2712 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2713 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2714 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2715 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2716 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2717 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2718 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
2719 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2720 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2721 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2722 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2723 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2724 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2725 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2726 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2727 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2728 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2729 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2730 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2731 #define PIPE_8BPC (0 << 5)
2732 #define PIPE_10BPC (1 << 5)
2733 #define PIPE_6BPC (2 << 5)
2734 #define PIPE_12BPC (3 << 5)
2735
2736 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2737 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
2738 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2739 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2740 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2741 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2742
2743 #define VLV_DPFLIPSTAT 0x70028
2744 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
2745 #define PIPEB_HLINE_INT_EN (1<<28)
2746 #define PIPEB_VBLANK_INT_EN (1<<27)
2747 #define SPRITED_FLIPDONE_INT_EN (1<<26)
2748 #define SPRITEC_FLIPDONE_INT_EN (1<<25)
2749 #define PLANEB_FLIPDONE_INT_EN (1<<24)
2750 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
2751 #define PIPEA_HLINE_INT_EN (1<<20)
2752 #define PIPEA_VBLANK_INT_EN (1<<19)
2753 #define SPRITEB_FLIPDONE_INT_EN (1<<18)
2754 #define SPRITEA_FLIPDONE_INT_EN (1<<17)
2755 #define PLANEA_FLIPDONE_INT_EN (1<<16)
2756
2757 #define DPINVGTT 0x7002c /* VLV only */
2758 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
2759 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
2760 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
2761 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
2762 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
2763 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
2764 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
2765 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
2766 #define DPINVGTT_EN_MASK 0xff0000
2767 #define CURSORB_INVALID_GTT_STATUS (1<<7)
2768 #define CURSORA_INVALID_GTT_STATUS (1<<6)
2769 #define SPRITED_INVALID_GTT_STATUS (1<<5)
2770 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
2771 #define PLANEB_INVALID_GTT_STATUS (1<<3)
2772 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
2773 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
2774 #define PLANEA_INVALID_GTT_STATUS (1<<0)
2775 #define DPINVGTT_STATUS_MASK 0xff
2776
2777 #define DSPARB 0x70030
2778 #define DSPARB_CSTART_MASK (0x7f << 7)
2779 #define DSPARB_CSTART_SHIFT 7
2780 #define DSPARB_BSTART_MASK (0x7f)
2781 #define DSPARB_BSTART_SHIFT 0
2782 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2783 #define DSPARB_AEND_SHIFT 0
2784
2785 #define DSPFW1 0x70034
2786 #define DSPFW_SR_SHIFT 23
2787 #define DSPFW_SR_MASK (0x1ff<<23)
2788 #define DSPFW_CURSORB_SHIFT 16
2789 #define DSPFW_CURSORB_MASK (0x3f<<16)
2790 #define DSPFW_PLANEB_SHIFT 8
2791 #define DSPFW_PLANEB_MASK (0x7f<<8)
2792 #define DSPFW_PLANEA_MASK (0x7f)
2793 #define DSPFW2 0x70038
2794 #define DSPFW_CURSORA_MASK 0x00003f00
2795 #define DSPFW_CURSORA_SHIFT 8
2796 #define DSPFW_PLANEC_MASK (0x7f)
2797 #define DSPFW3 0x7003c
2798 #define DSPFW_HPLL_SR_EN (1<<31)
2799 #define DSPFW_CURSOR_SR_SHIFT 24
2800 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2801 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2802 #define DSPFW_HPLL_CURSOR_SHIFT 16
2803 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2804 #define DSPFW_HPLL_SR_MASK (0x1ff)
2805
2806 /* drain latency register values*/
2807 #define DRAIN_LATENCY_PRECISION_32 32
2808 #define DRAIN_LATENCY_PRECISION_16 16
2809 #define VLV_DDL1 0x70050
2810 #define DDL_CURSORA_PRECISION_32 (1<<31)
2811 #define DDL_CURSORA_PRECISION_16 (0<<31)
2812 #define DDL_CURSORA_SHIFT 24
2813 #define DDL_PLANEA_PRECISION_32 (1<<7)
2814 #define DDL_PLANEA_PRECISION_16 (0<<7)
2815 #define VLV_DDL2 0x70054
2816 #define DDL_CURSORB_PRECISION_32 (1<<31)
2817 #define DDL_CURSORB_PRECISION_16 (0<<31)
2818 #define DDL_CURSORB_SHIFT 24
2819 #define DDL_PLANEB_PRECISION_32 (1<<7)
2820 #define DDL_PLANEB_PRECISION_16 (0<<7)
2821
2822 /* FIFO watermark sizes etc */
2823 #define G4X_FIFO_LINE_SIZE 64
2824 #define I915_FIFO_LINE_SIZE 64
2825 #define I830_FIFO_LINE_SIZE 32
2826
2827 #define VALLEYVIEW_FIFO_SIZE 255
2828 #define G4X_FIFO_SIZE 127
2829 #define I965_FIFO_SIZE 512
2830 #define I945_FIFO_SIZE 127
2831 #define I915_FIFO_SIZE 95
2832 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2833 #define I830_FIFO_SIZE 95
2834
2835 #define VALLEYVIEW_MAX_WM 0xff
2836 #define G4X_MAX_WM 0x3f
2837 #define I915_MAX_WM 0x3f
2838
2839 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2840 #define PINEVIEW_FIFO_LINE_SIZE 64
2841 #define PINEVIEW_MAX_WM 0x1ff
2842 #define PINEVIEW_DFT_WM 0x3f
2843 #define PINEVIEW_DFT_HPLLOFF_WM 0
2844 #define PINEVIEW_GUARD_WM 10
2845 #define PINEVIEW_CURSOR_FIFO 64
2846 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2847 #define PINEVIEW_CURSOR_DFT_WM 0
2848 #define PINEVIEW_CURSOR_GUARD_WM 5
2849
2850 #define VALLEYVIEW_CURSOR_MAX_WM 64
2851 #define I965_CURSOR_FIFO 64
2852 #define I965_CURSOR_MAX_WM 32
2853 #define I965_CURSOR_DFT_WM 8
2854
2855 /* define the Watermark register on Ironlake */
2856 #define WM0_PIPEA_ILK 0x45100
2857 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2858 #define WM0_PIPE_PLANE_SHIFT 16
2859 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2860 #define WM0_PIPE_SPRITE_SHIFT 8
2861 #define WM0_PIPE_CURSOR_MASK (0x1f)
2862
2863 #define WM0_PIPEB_ILK 0x45104
2864 #define WM0_PIPEC_IVB 0x45200
2865 #define WM1_LP_ILK 0x45108
2866 #define WM1_LP_SR_EN (1<<31)
2867 #define WM1_LP_LATENCY_SHIFT 24
2868 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2869 #define WM1_LP_FBC_MASK (0xf<<20)
2870 #define WM1_LP_FBC_SHIFT 20
2871 #define WM1_LP_SR_MASK (0x1ff<<8)
2872 #define WM1_LP_SR_SHIFT 8
2873 #define WM1_LP_CURSOR_MASK (0x3f)
2874 #define WM2_LP_ILK 0x4510c
2875 #define WM2_LP_EN (1<<31)
2876 #define WM3_LP_ILK 0x45110
2877 #define WM3_LP_EN (1<<31)
2878 #define WM1S_LP_ILK 0x45120
2879 #define WM2S_LP_IVB 0x45124
2880 #define WM3S_LP_IVB 0x45128
2881 #define WM1S_LP_EN (1<<31)
2882
2883 /* Memory latency timer register */
2884 #define MLTR_ILK 0x11222
2885 #define MLTR_WM1_SHIFT 0
2886 #define MLTR_WM2_SHIFT 8
2887 /* the unit of memory self-refresh latency time is 0.5us */
2888 #define ILK_SRLT_MASK 0x3f
2889 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2890 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2891 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2892
2893 /* define the fifo size on Ironlake */
2894 #define ILK_DISPLAY_FIFO 128
2895 #define ILK_DISPLAY_MAXWM 64
2896 #define ILK_DISPLAY_DFTWM 8
2897 #define ILK_CURSOR_FIFO 32
2898 #define ILK_CURSOR_MAXWM 16
2899 #define ILK_CURSOR_DFTWM 8
2900
2901 #define ILK_DISPLAY_SR_FIFO 512
2902 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2903 #define ILK_DISPLAY_DFT_SRWM 0x3f
2904 #define ILK_CURSOR_SR_FIFO 64
2905 #define ILK_CURSOR_MAX_SRWM 0x3f
2906 #define ILK_CURSOR_DFT_SRWM 8
2907
2908 #define ILK_FIFO_LINE_SIZE 64
2909
2910 /* define the WM info on Sandybridge */
2911 #define SNB_DISPLAY_FIFO 128
2912 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2913 #define SNB_DISPLAY_DFTWM 8
2914 #define SNB_CURSOR_FIFO 32
2915 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2916 #define SNB_CURSOR_DFTWM 8
2917
2918 #define SNB_DISPLAY_SR_FIFO 512
2919 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2920 #define SNB_DISPLAY_DFT_SRWM 0x3f
2921 #define SNB_CURSOR_SR_FIFO 64
2922 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2923 #define SNB_CURSOR_DFT_SRWM 8
2924
2925 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2926
2927 #define SNB_FIFO_LINE_SIZE 64
2928
2929
2930 /* the address where we get all kinds of latency value */
2931 #define SSKPD 0x5d10
2932 #define SSKPD_WM_MASK 0x3f
2933 #define SSKPD_WM0_SHIFT 0
2934 #define SSKPD_WM1_SHIFT 8
2935 #define SSKPD_WM2_SHIFT 16
2936 #define SSKPD_WM3_SHIFT 24
2937
2938 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2939 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2940 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2941 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2942 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2943
2944 /*
2945 * The two pipe frame counter registers are not synchronized, so
2946 * reading a stable value is somewhat tricky. The following code
2947 * should work:
2948 *
2949 * do {
2950 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2951 * PIPE_FRAME_HIGH_SHIFT;
2952 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2953 * PIPE_FRAME_LOW_SHIFT);
2954 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2955 * PIPE_FRAME_HIGH_SHIFT);
2956 * } while (high1 != high2);
2957 * frame = (high1 << 8) | low1;
2958 */
2959 #define _PIPEAFRAMEHIGH 0x70040
2960 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2961 #define PIPE_FRAME_HIGH_SHIFT 0
2962 #define _PIPEAFRAMEPIXEL 0x70044
2963 #define PIPE_FRAME_LOW_MASK 0xff000000
2964 #define PIPE_FRAME_LOW_SHIFT 24
2965 #define PIPE_PIXEL_MASK 0x00ffffff
2966 #define PIPE_PIXEL_SHIFT 0
2967 /* GM45+ just has to be different */
2968 #define _PIPEA_FRMCOUNT_GM45 0x70040
2969 #define _PIPEA_FLIPCOUNT_GM45 0x70044
2970 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2971
2972 /* Cursor A & B regs */
2973 #define _CURACNTR 0x70080
2974 /* Old style CUR*CNTR flags (desktop 8xx) */
2975 #define CURSOR_ENABLE 0x80000000
2976 #define CURSOR_GAMMA_ENABLE 0x40000000
2977 #define CURSOR_STRIDE_MASK 0x30000000
2978 #define CURSOR_FORMAT_SHIFT 24
2979 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2980 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2981 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2982 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2983 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2984 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2985 /* New style CUR*CNTR flags */
2986 #define CURSOR_MODE 0x27
2987 #define CURSOR_MODE_DISABLE 0x00
2988 #define CURSOR_MODE_64_32B_AX 0x07
2989 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2990 #define MCURSOR_PIPE_SELECT (1 << 28)
2991 #define MCURSOR_PIPE_A 0x00
2992 #define MCURSOR_PIPE_B (1 << 28)
2993 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2994 #define _CURABASE 0x70084
2995 #define _CURAPOS 0x70088
2996 #define CURSOR_POS_MASK 0x007FF
2997 #define CURSOR_POS_SIGN 0x8000
2998 #define CURSOR_X_SHIFT 0
2999 #define CURSOR_Y_SHIFT 16
3000 #define CURSIZE 0x700a0
3001 #define _CURBCNTR 0x700c0
3002 #define _CURBBASE 0x700c4
3003 #define _CURBPOS 0x700c8
3004
3005 #define _CURBCNTR_IVB 0x71080
3006 #define _CURBBASE_IVB 0x71084
3007 #define _CURBPOS_IVB 0x71088
3008
3009 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3010 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3011 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3012
3013 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3014 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3015 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3016
3017 /* Display A control */
3018 #define _DSPACNTR 0x70180
3019 #define DISPLAY_PLANE_ENABLE (1<<31)
3020 #define DISPLAY_PLANE_DISABLE 0
3021 #define DISPPLANE_GAMMA_ENABLE (1<<30)
3022 #define DISPPLANE_GAMMA_DISABLE 0
3023 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3024 #define DISPPLANE_YUV422 (0x0<<26)
3025 #define DISPPLANE_8BPP (0x2<<26)
3026 #define DISPPLANE_BGRA555 (0x3<<26)
3027 #define DISPPLANE_BGRX555 (0x4<<26)
3028 #define DISPPLANE_BGRX565 (0x5<<26)
3029 #define DISPPLANE_BGRX888 (0x6<<26)
3030 #define DISPPLANE_BGRA888 (0x7<<26)
3031 #define DISPPLANE_RGBX101010 (0x8<<26)
3032 #define DISPPLANE_RGBA101010 (0x9<<26)
3033 #define DISPPLANE_BGRX101010 (0xa<<26)
3034 #define DISPPLANE_RGBX161616 (0xc<<26)
3035 #define DISPPLANE_RGBX888 (0xe<<26)
3036 #define DISPPLANE_RGBA888 (0xf<<26)
3037 #define DISPPLANE_STEREO_ENABLE (1<<25)
3038 #define DISPPLANE_STEREO_DISABLE 0
3039 #define DISPPLANE_SEL_PIPE_SHIFT 24
3040 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3041 #define DISPPLANE_SEL_PIPE_A 0
3042 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3043 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3044 #define DISPPLANE_SRC_KEY_DISABLE 0
3045 #define DISPPLANE_LINE_DOUBLE (1<<20)
3046 #define DISPPLANE_NO_LINE_DOUBLE 0
3047 #define DISPPLANE_STEREO_POLARITY_FIRST 0
3048 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3049 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3050 #define DISPPLANE_TILED (1<<10)
3051 #define _DSPAADDR 0x70184
3052 #define _DSPASTRIDE 0x70188
3053 #define _DSPAPOS 0x7018C /* reserved */
3054 #define _DSPASIZE 0x70190
3055 #define _DSPASURF 0x7019C /* 965+ only */
3056 #define _DSPATILEOFF 0x701A4 /* 965+ only */
3057 #define _DSPAOFFSET 0x701A4 /* HSW */
3058 #define _DSPASURFLIVE 0x701AC
3059
3060 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3061 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3062 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3063 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3064 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3065 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3066 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3067 #define DSPLINOFF(plane) DSPADDR(plane)
3068 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3069 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3070
3071 /* Display/Sprite base address macros */
3072 #define DISP_BASEADDR_MASK (0xfffff000)
3073 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3074 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3075 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3076 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3077
3078 /* VBIOS flags */
3079 #define SWF00 0x71410
3080 #define SWF01 0x71414
3081 #define SWF02 0x71418
3082 #define SWF03 0x7141c
3083 #define SWF04 0x71420
3084 #define SWF05 0x71424
3085 #define SWF06 0x71428
3086 #define SWF10 0x70410
3087 #define SWF11 0x70414
3088 #define SWF14 0x71420
3089 #define SWF30 0x72414
3090 #define SWF31 0x72418
3091 #define SWF32 0x7241c
3092
3093 /* Pipe B */
3094 #define _PIPEBDSL 0x71000
3095 #define _PIPEBCONF 0x71008
3096 #define _PIPEBSTAT 0x71024
3097 #define _PIPEBFRAMEHIGH 0x71040
3098 #define _PIPEBFRAMEPIXEL 0x71044
3099 #define _PIPEB_FRMCOUNT_GM45 0x71040
3100 #define _PIPEB_FLIPCOUNT_GM45 0x71044
3101
3102
3103 /* Display B control */
3104 #define _DSPBCNTR 0x71180
3105 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3106 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
3107 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3108 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3109 #define _DSPBADDR 0x71184
3110 #define _DSPBSTRIDE 0x71188
3111 #define _DSPBPOS 0x7118C
3112 #define _DSPBSIZE 0x71190
3113 #define _DSPBSURF 0x7119C
3114 #define _DSPBTILEOFF 0x711A4
3115 #define _DSPBOFFSET 0x711A4
3116 #define _DSPBSURFLIVE 0x711AC
3117
3118 /* Sprite A control */
3119 #define _DVSACNTR 0x72180
3120 #define DVS_ENABLE (1<<31)
3121 #define DVS_GAMMA_ENABLE (1<<30)
3122 #define DVS_PIXFORMAT_MASK (3<<25)
3123 #define DVS_FORMAT_YUV422 (0<<25)
3124 #define DVS_FORMAT_RGBX101010 (1<<25)
3125 #define DVS_FORMAT_RGBX888 (2<<25)
3126 #define DVS_FORMAT_RGBX161616 (3<<25)
3127 #define DVS_SOURCE_KEY (1<<22)
3128 #define DVS_RGB_ORDER_XBGR (1<<20)
3129 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3130 #define DVS_YUV_ORDER_YUYV (0<<16)
3131 #define DVS_YUV_ORDER_UYVY (1<<16)
3132 #define DVS_YUV_ORDER_YVYU (2<<16)
3133 #define DVS_YUV_ORDER_VYUY (3<<16)
3134 #define DVS_DEST_KEY (1<<2)
3135 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
3136 #define DVS_TILED (1<<10)
3137 #define _DVSALINOFF 0x72184
3138 #define _DVSASTRIDE 0x72188
3139 #define _DVSAPOS 0x7218c
3140 #define _DVSASIZE 0x72190
3141 #define _DVSAKEYVAL 0x72194
3142 #define _DVSAKEYMSK 0x72198
3143 #define _DVSASURF 0x7219c
3144 #define _DVSAKEYMAXVAL 0x721a0
3145 #define _DVSATILEOFF 0x721a4
3146 #define _DVSASURFLIVE 0x721ac
3147 #define _DVSASCALE 0x72204
3148 #define DVS_SCALE_ENABLE (1<<31)
3149 #define DVS_FILTER_MASK (3<<29)
3150 #define DVS_FILTER_MEDIUM (0<<29)
3151 #define DVS_FILTER_ENHANCING (1<<29)
3152 #define DVS_FILTER_SOFTENING (2<<29)
3153 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3154 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3155 #define _DVSAGAMC 0x72300
3156
3157 #define _DVSBCNTR 0x73180
3158 #define _DVSBLINOFF 0x73184
3159 #define _DVSBSTRIDE 0x73188
3160 #define _DVSBPOS 0x7318c
3161 #define _DVSBSIZE 0x73190
3162 #define _DVSBKEYVAL 0x73194
3163 #define _DVSBKEYMSK 0x73198
3164 #define _DVSBSURF 0x7319c
3165 #define _DVSBKEYMAXVAL 0x731a0
3166 #define _DVSBTILEOFF 0x731a4
3167 #define _DVSBSURFLIVE 0x731ac
3168 #define _DVSBSCALE 0x73204
3169 #define _DVSBGAMC 0x73300
3170
3171 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3172 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3173 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3174 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3175 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3176 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3177 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3178 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3179 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3180 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3181 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3182 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3183
3184 #define _SPRA_CTL 0x70280
3185 #define SPRITE_ENABLE (1<<31)
3186 #define SPRITE_GAMMA_ENABLE (1<<30)
3187 #define SPRITE_PIXFORMAT_MASK (7<<25)
3188 #define SPRITE_FORMAT_YUV422 (0<<25)
3189 #define SPRITE_FORMAT_RGBX101010 (1<<25)
3190 #define SPRITE_FORMAT_RGBX888 (2<<25)
3191 #define SPRITE_FORMAT_RGBX161616 (3<<25)
3192 #define SPRITE_FORMAT_YUV444 (4<<25)
3193 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3194 #define SPRITE_CSC_ENABLE (1<<24)
3195 #define SPRITE_SOURCE_KEY (1<<22)
3196 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3197 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3198 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3199 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3200 #define SPRITE_YUV_ORDER_YUYV (0<<16)
3201 #define SPRITE_YUV_ORDER_UYVY (1<<16)
3202 #define SPRITE_YUV_ORDER_YVYU (2<<16)
3203 #define SPRITE_YUV_ORDER_VYUY (3<<16)
3204 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3205 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
3206 #define SPRITE_TILED (1<<10)
3207 #define SPRITE_DEST_KEY (1<<2)
3208 #define _SPRA_LINOFF 0x70284
3209 #define _SPRA_STRIDE 0x70288
3210 #define _SPRA_POS 0x7028c
3211 #define _SPRA_SIZE 0x70290
3212 #define _SPRA_KEYVAL 0x70294
3213 #define _SPRA_KEYMSK 0x70298
3214 #define _SPRA_SURF 0x7029c
3215 #define _SPRA_KEYMAX 0x702a0
3216 #define _SPRA_TILEOFF 0x702a4
3217 #define _SPRA_OFFSET 0x702a4
3218 #define _SPRA_SURFLIVE 0x702ac
3219 #define _SPRA_SCALE 0x70304
3220 #define SPRITE_SCALE_ENABLE (1<<31)
3221 #define SPRITE_FILTER_MASK (3<<29)
3222 #define SPRITE_FILTER_MEDIUM (0<<29)
3223 #define SPRITE_FILTER_ENHANCING (1<<29)
3224 #define SPRITE_FILTER_SOFTENING (2<<29)
3225 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3226 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3227 #define _SPRA_GAMC 0x70400
3228
3229 #define _SPRB_CTL 0x71280
3230 #define _SPRB_LINOFF 0x71284
3231 #define _SPRB_STRIDE 0x71288
3232 #define _SPRB_POS 0x7128c
3233 #define _SPRB_SIZE 0x71290
3234 #define _SPRB_KEYVAL 0x71294
3235 #define _SPRB_KEYMSK 0x71298
3236 #define _SPRB_SURF 0x7129c
3237 #define _SPRB_KEYMAX 0x712a0
3238 #define _SPRB_TILEOFF 0x712a4
3239 #define _SPRB_OFFSET 0x712a4
3240 #define _SPRB_SURFLIVE 0x712ac
3241 #define _SPRB_SCALE 0x71304
3242 #define _SPRB_GAMC 0x71400
3243
3244 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3245 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3246 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3247 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3248 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3249 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3250 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3251 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3252 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3253 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3254 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3255 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3256 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3257 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3258
3259 /* VBIOS regs */
3260 #define VGACNTRL 0x71400
3261 # define VGA_DISP_DISABLE (1 << 31)
3262 # define VGA_2X_MODE (1 << 30)
3263 # define VGA_PIPE_B_SELECT (1 << 29)
3264
3265 /* Ironlake */
3266
3267 #define CPU_VGACNTRL 0x41000
3268
3269 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3270 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3271 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3272 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3273 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3274 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3275 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
3276 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3277 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3278
3279 /* refresh rate hardware control */
3280 #define RR_HW_CTL 0x45300
3281 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3282 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3283
3284 #define FDI_PLL_BIOS_0 0x46000
3285 #define FDI_PLL_FB_CLOCK_MASK 0xff
3286 #define FDI_PLL_BIOS_1 0x46004
3287 #define FDI_PLL_BIOS_2 0x46008
3288 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3289 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
3290 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
3291
3292 #define PCH_3DCGDIS0 0x46020
3293 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3294 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3295
3296 #define PCH_3DCGDIS1 0x46024
3297 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3298
3299 #define FDI_PLL_FREQ_CTL 0x46030
3300 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3301 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3302 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3303
3304
3305 #define _PIPEA_DATA_M1 0x60030
3306 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3307 #define TU_SIZE_MASK 0x7e000000
3308 #define PIPE_DATA_M1_OFFSET 0
3309 #define _PIPEA_DATA_N1 0x60034
3310 #define PIPE_DATA_N1_OFFSET 0
3311
3312 #define _PIPEA_DATA_M2 0x60038
3313 #define PIPE_DATA_M2_OFFSET 0
3314 #define _PIPEA_DATA_N2 0x6003c
3315 #define PIPE_DATA_N2_OFFSET 0
3316
3317 #define _PIPEA_LINK_M1 0x60040
3318 #define PIPE_LINK_M1_OFFSET 0
3319 #define _PIPEA_LINK_N1 0x60044
3320 #define PIPE_LINK_N1_OFFSET 0
3321
3322 #define _PIPEA_LINK_M2 0x60048
3323 #define PIPE_LINK_M2_OFFSET 0
3324 #define _PIPEA_LINK_N2 0x6004c
3325 #define PIPE_LINK_N2_OFFSET 0
3326
3327 /* PIPEB timing regs are same start from 0x61000 */
3328
3329 #define _PIPEB_DATA_M1 0x61030
3330 #define _PIPEB_DATA_N1 0x61034
3331
3332 #define _PIPEB_DATA_M2 0x61038
3333 #define _PIPEB_DATA_N2 0x6103c
3334
3335 #define _PIPEB_LINK_M1 0x61040
3336 #define _PIPEB_LINK_N1 0x61044
3337
3338 #define _PIPEB_LINK_M2 0x61048
3339 #define _PIPEB_LINK_N2 0x6104c
3340
3341 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3342 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3343 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3344 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3345 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3346 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3347 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3348 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3349
3350 /* CPU panel fitter */
3351 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3352 #define _PFA_CTL_1 0x68080
3353 #define _PFB_CTL_1 0x68880
3354 #define PF_ENABLE (1<<31)
3355 #define PF_FILTER_MASK (3<<23)
3356 #define PF_FILTER_PROGRAMMED (0<<23)
3357 #define PF_FILTER_MED_3x3 (1<<23)
3358 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3359 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3360 #define _PFA_WIN_SZ 0x68074
3361 #define _PFB_WIN_SZ 0x68874
3362 #define _PFA_WIN_POS 0x68070
3363 #define _PFB_WIN_POS 0x68870
3364 #define _PFA_VSCALE 0x68084
3365 #define _PFB_VSCALE 0x68884
3366 #define _PFA_HSCALE 0x68090
3367 #define _PFB_HSCALE 0x68890
3368
3369 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3370 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3371 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3372 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3373 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3374
3375 /* legacy palette */
3376 #define _LGC_PALETTE_A 0x4a000
3377 #define _LGC_PALETTE_B 0x4a800
3378 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3379
3380 /* interrupts */
3381 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3382 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3383 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3384 #define DE_PLANEB_FLIP_DONE (1 << 27)
3385 #define DE_PLANEA_FLIP_DONE (1 << 26)
3386 #define DE_PCU_EVENT (1 << 25)
3387 #define DE_GTT_FAULT (1 << 24)
3388 #define DE_POISON (1 << 23)
3389 #define DE_PERFORM_COUNTER (1 << 22)
3390 #define DE_PCH_EVENT (1 << 21)
3391 #define DE_AUX_CHANNEL_A (1 << 20)
3392 #define DE_DP_A_HOTPLUG (1 << 19)
3393 #define DE_GSE (1 << 18)
3394 #define DE_PIPEB_VBLANK (1 << 15)
3395 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3396 #define DE_PIPEB_ODD_FIELD (1 << 13)
3397 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3398 #define DE_PIPEB_VSYNC (1 << 11)
3399 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3400 #define DE_PIPEA_VBLANK (1 << 7)
3401 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3402 #define DE_PIPEA_ODD_FIELD (1 << 5)
3403 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3404 #define DE_PIPEA_VSYNC (1 << 3)
3405 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3406
3407 /* More Ivybridge lolz */
3408 #define DE_ERR_DEBUG_IVB (1<<30)
3409 #define DE_GSE_IVB (1<<29)
3410 #define DE_PCH_EVENT_IVB (1<<28)
3411 #define DE_DP_A_HOTPLUG_IVB (1<<27)
3412 #define DE_AUX_CHANNEL_A_IVB (1<<26)
3413 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3414 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3415 #define DE_PIPEC_VBLANK_IVB (1<<10)
3416 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3417 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3418 #define DE_PIPEB_VBLANK_IVB (1<<5)
3419 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3420 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3421 #define DE_PIPEA_VBLANK_IVB (1<<0)
3422
3423 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
3424 #define MASTER_INTERRUPT_ENABLE (1<<31)
3425
3426 #define DEISR 0x44000
3427 #define DEIMR 0x44004
3428 #define DEIIR 0x44008
3429 #define DEIER 0x4400c
3430
3431 /* GT interrupt.
3432 * Note that for gen6+ the ring-specific interrupt bits do alias with the
3433 * corresponding bits in the per-ring interrupt control registers. */
3434 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3435 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
3436 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
3437 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
3438 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
3439 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
3440 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
3441 #define GT_PIPE_NOTIFY (1 << 4)
3442 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
3443 #define GT_SYNC_STATUS (1 << 2)
3444 #define GT_USER_INTERRUPT (1 << 0)
3445
3446 #define GTISR 0x44010
3447 #define GTIMR 0x44014
3448 #define GTIIR 0x44018
3449 #define GTIER 0x4401c
3450
3451 #define ILK_DISPLAY_CHICKEN2 0x42004
3452 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3453 #define ILK_ELPIN_409_SELECT (1 << 25)
3454 #define ILK_DPARB_GATE (1<<22)
3455 #define ILK_VSDPFD_FULL (1<<21)
3456 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3457 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3458 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3459 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3460 #define ILK_HDCP_DISABLE (1<<25)
3461 #define ILK_eDP_A_DISABLE (1<<24)
3462 #define ILK_DESKTOP (1<<23)
3463
3464 #define ILK_DSPCLK_GATE_D 0x42020
3465 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
3466 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3467 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
3468 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
3469 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
3470
3471 #define IVB_CHICKEN3 0x4200c
3472 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3473 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3474
3475 #define DISP_ARB_CTL 0x45000
3476 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
3477 #define DISP_FBC_WM_DIS (1<<15)
3478
3479 /* GEN7 chicken */
3480 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3481 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3482
3483 #define GEN7_L3CNTLREG1 0xB01C
3484 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3485 #define GEN7_L3AGDIS (1<<19)
3486
3487 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3488 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3489
3490 #define GEN7_L3SQCREG4 0xb034
3491 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
3492
3493 /* WaCatErrorRejectionIssue */
3494 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3495 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3496
3497 #define HSW_FUSE_STRAP 0x42014
3498 #define HSW_CDCLK_LIMIT (1 << 24)
3499
3500 /* PCH */
3501
3502 /* south display engine interrupt: IBX */
3503 #define SDE_AUDIO_POWER_D (1 << 27)
3504 #define SDE_AUDIO_POWER_C (1 << 26)
3505 #define SDE_AUDIO_POWER_B (1 << 25)
3506 #define SDE_AUDIO_POWER_SHIFT (25)
3507 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3508 #define SDE_GMBUS (1 << 24)
3509 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3510 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3511 #define SDE_AUDIO_HDCP_MASK (3 << 22)
3512 #define SDE_AUDIO_TRANSB (1 << 21)
3513 #define SDE_AUDIO_TRANSA (1 << 20)
3514 #define SDE_AUDIO_TRANS_MASK (3 << 20)
3515 #define SDE_POISON (1 << 19)
3516 /* 18 reserved */
3517 #define SDE_FDI_RXB (1 << 17)
3518 #define SDE_FDI_RXA (1 << 16)
3519 #define SDE_FDI_MASK (3 << 16)
3520 #define SDE_AUXD (1 << 15)
3521 #define SDE_AUXC (1 << 14)
3522 #define SDE_AUXB (1 << 13)
3523 #define SDE_AUX_MASK (7 << 13)
3524 /* 12 reserved */
3525 #define SDE_CRT_HOTPLUG (1 << 11)
3526 #define SDE_PORTD_HOTPLUG (1 << 10)
3527 #define SDE_PORTC_HOTPLUG (1 << 9)
3528 #define SDE_PORTB_HOTPLUG (1 << 8)
3529 #define SDE_SDVOB_HOTPLUG (1 << 6)
3530 #define SDE_HOTPLUG_MASK (0xf << 8)
3531 #define SDE_TRANSB_CRC_DONE (1 << 5)
3532 #define SDE_TRANSB_CRC_ERR (1 << 4)
3533 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
3534 #define SDE_TRANSA_CRC_DONE (1 << 2)
3535 #define SDE_TRANSA_CRC_ERR (1 << 1)
3536 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
3537 #define SDE_TRANS_MASK (0x3f)
3538
3539 /* south display engine interrupt: CPT/PPT */
3540 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
3541 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
3542 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
3543 #define SDE_AUDIO_POWER_SHIFT_CPT 29
3544 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3545 #define SDE_AUXD_CPT (1 << 27)
3546 #define SDE_AUXC_CPT (1 << 26)
3547 #define SDE_AUXB_CPT (1 << 25)
3548 #define SDE_AUX_MASK_CPT (7 << 25)
3549 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3550 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3551 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3552 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
3553 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3554 SDE_PORTD_HOTPLUG_CPT | \
3555 SDE_PORTC_HOTPLUG_CPT | \
3556 SDE_PORTB_HOTPLUG_CPT)
3557 #define SDE_GMBUS_CPT (1 << 17)
3558 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3559 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3560 #define SDE_FDI_RXC_CPT (1 << 8)
3561 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3562 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3563 #define SDE_FDI_RXB_CPT (1 << 4)
3564 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3565 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3566 #define SDE_FDI_RXA_CPT (1 << 0)
3567 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3568 SDE_AUDIO_CP_REQ_B_CPT | \
3569 SDE_AUDIO_CP_REQ_A_CPT)
3570 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3571 SDE_AUDIO_CP_CHG_B_CPT | \
3572 SDE_AUDIO_CP_CHG_A_CPT)
3573 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3574 SDE_FDI_RXB_CPT | \
3575 SDE_FDI_RXA_CPT)
3576
3577 #define SDEISR 0xc4000
3578 #define SDEIMR 0xc4004
3579 #define SDEIIR 0xc4008
3580 #define SDEIER 0xc400c
3581
3582 /* digital port hotplug */
3583 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
3584 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3585 #define PORTD_PULSE_DURATION_2ms (0)
3586 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3587 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3588 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3589 #define PORTD_PULSE_DURATION_MASK (3 << 18)
3590 #define PORTD_HOTPLUG_NO_DETECT (0)
3591 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3592 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3593 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3594 #define PORTC_PULSE_DURATION_2ms (0)
3595 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3596 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3597 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3598 #define PORTC_PULSE_DURATION_MASK (3 << 10)
3599 #define PORTC_HOTPLUG_NO_DETECT (0)
3600 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3601 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3602 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3603 #define PORTB_PULSE_DURATION_2ms (0)
3604 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3605 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3606 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3607 #define PORTB_PULSE_DURATION_MASK (3 << 2)
3608 #define PORTB_HOTPLUG_NO_DETECT (0)
3609 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3610 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3611
3612 #define PCH_GPIOA 0xc5010
3613 #define PCH_GPIOB 0xc5014
3614 #define PCH_GPIOC 0xc5018
3615 #define PCH_GPIOD 0xc501c
3616 #define PCH_GPIOE 0xc5020
3617 #define PCH_GPIOF 0xc5024
3618
3619 #define PCH_GMBUS0 0xc5100
3620 #define PCH_GMBUS1 0xc5104
3621 #define PCH_GMBUS2 0xc5108
3622 #define PCH_GMBUS3 0xc510c
3623 #define PCH_GMBUS4 0xc5110
3624 #define PCH_GMBUS5 0xc5120
3625
3626 #define _PCH_DPLL_A 0xc6014
3627 #define _PCH_DPLL_B 0xc6018
3628 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3629
3630 #define _PCH_FPA0 0xc6040
3631 #define FP_CB_TUNE (0x3<<22)
3632 #define _PCH_FPA1 0xc6044
3633 #define _PCH_FPB0 0xc6048
3634 #define _PCH_FPB1 0xc604c
3635 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3636 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
3637
3638 #define PCH_DPLL_TEST 0xc606c
3639
3640 #define PCH_DREF_CONTROL 0xC6200
3641 #define DREF_CONTROL_MASK 0x7fc3
3642 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3643 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3644 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3645 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
3646 #define DREF_SSC_SOURCE_DISABLE (0<<11)
3647 #define DREF_SSC_SOURCE_ENABLE (2<<11)
3648 #define DREF_SSC_SOURCE_MASK (3<<11)
3649 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3650 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
3651 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3652 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
3653 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3654 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3655 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
3656 #define DREF_SSC4_DOWNSPREAD (0<<6)
3657 #define DREF_SSC4_CENTERSPREAD (1<<6)
3658 #define DREF_SSC1_DISABLE (0<<1)
3659 #define DREF_SSC1_ENABLE (1<<1)
3660 #define DREF_SSC4_DISABLE (0)
3661 #define DREF_SSC4_ENABLE (1)
3662
3663 #define PCH_RAWCLK_FREQ 0xc6204
3664 #define FDL_TP1_TIMER_SHIFT 12
3665 #define FDL_TP1_TIMER_MASK (3<<12)
3666 #define FDL_TP2_TIMER_SHIFT 10
3667 #define FDL_TP2_TIMER_MASK (3<<10)
3668 #define RAWCLK_FREQ_MASK 0x3ff
3669
3670 #define PCH_DPLL_TMR_CFG 0xc6208
3671
3672 #define PCH_SSC4_PARMS 0xc6210
3673 #define PCH_SSC4_AUX_PARMS 0xc6214
3674
3675 #define PCH_DPLL_SEL 0xc7000
3676 #define TRANSA_DPLL_ENABLE (1<<3)
3677 #define TRANSA_DPLLB_SEL (1<<0)
3678 #define TRANSA_DPLLA_SEL 0
3679 #define TRANSB_DPLL_ENABLE (1<<7)
3680 #define TRANSB_DPLLB_SEL (1<<4)
3681 #define TRANSB_DPLLA_SEL (0)
3682 #define TRANSC_DPLL_ENABLE (1<<11)
3683 #define TRANSC_DPLLB_SEL (1<<8)
3684 #define TRANSC_DPLLA_SEL (0)
3685
3686 /* transcoder */
3687
3688 #define _TRANS_HTOTAL_A 0xe0000
3689 #define TRANS_HTOTAL_SHIFT 16
3690 #define TRANS_HACTIVE_SHIFT 0
3691 #define _TRANS_HBLANK_A 0xe0004
3692 #define TRANS_HBLANK_END_SHIFT 16
3693 #define TRANS_HBLANK_START_SHIFT 0
3694 #define _TRANS_HSYNC_A 0xe0008
3695 #define TRANS_HSYNC_END_SHIFT 16
3696 #define TRANS_HSYNC_START_SHIFT 0
3697 #define _TRANS_VTOTAL_A 0xe000c
3698 #define TRANS_VTOTAL_SHIFT 16
3699 #define TRANS_VACTIVE_SHIFT 0
3700 #define _TRANS_VBLANK_A 0xe0010
3701 #define TRANS_VBLANK_END_SHIFT 16
3702 #define TRANS_VBLANK_START_SHIFT 0
3703 #define _TRANS_VSYNC_A 0xe0014
3704 #define TRANS_VSYNC_END_SHIFT 16
3705 #define TRANS_VSYNC_START_SHIFT 0
3706 #define _TRANS_VSYNCSHIFT_A 0xe0028
3707
3708 #define _TRANSA_DATA_M1 0xe0030
3709 #define _TRANSA_DATA_N1 0xe0034
3710 #define _TRANSA_DATA_M2 0xe0038
3711 #define _TRANSA_DATA_N2 0xe003c
3712 #define _TRANSA_DP_LINK_M1 0xe0040
3713 #define _TRANSA_DP_LINK_N1 0xe0044
3714 #define _TRANSA_DP_LINK_M2 0xe0048
3715 #define _TRANSA_DP_LINK_N2 0xe004c
3716
3717 /* Per-transcoder DIP controls */
3718
3719 #define _VIDEO_DIP_CTL_A 0xe0200
3720 #define _VIDEO_DIP_DATA_A 0xe0208
3721 #define _VIDEO_DIP_GCP_A 0xe0210
3722
3723 #define _VIDEO_DIP_CTL_B 0xe1200
3724 #define _VIDEO_DIP_DATA_B 0xe1208
3725 #define _VIDEO_DIP_GCP_B 0xe1210
3726
3727 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3728 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3729 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3730
3731 #define VLV_VIDEO_DIP_CTL_A 0x60200
3732 #define VLV_VIDEO_DIP_DATA_A 0x60208
3733 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3734
3735 #define VLV_VIDEO_DIP_CTL_B 0x61170
3736 #define VLV_VIDEO_DIP_DATA_B 0x61174
3737 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3738
3739 #define VLV_TVIDEO_DIP_CTL(pipe) \
3740 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
3741 #define VLV_TVIDEO_DIP_DATA(pipe) \
3742 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
3743 #define VLV_TVIDEO_DIP_GCP(pipe) \
3744 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3745
3746 /* Haswell DIP controls */
3747 #define HSW_VIDEO_DIP_CTL_A 0x60200
3748 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3749 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
3750 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3751 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3752 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3753 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3754 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
3755 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3756 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3757 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3758 #define HSW_VIDEO_DIP_GCP_A 0x60210
3759
3760 #define HSW_VIDEO_DIP_CTL_B 0x61200
3761 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3762 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
3763 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3764 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3765 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3766 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3767 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
3768 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3769 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3770 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3771 #define HSW_VIDEO_DIP_GCP_B 0x61210
3772
3773 #define HSW_TVIDEO_DIP_CTL(pipe) \
3774 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3775 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
3776 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3777 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
3778 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3779 #define HSW_TVIDEO_DIP_GCP(pipe) \
3780 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3781
3782 #define _TRANS_HTOTAL_B 0xe1000
3783 #define _TRANS_HBLANK_B 0xe1004
3784 #define _TRANS_HSYNC_B 0xe1008
3785 #define _TRANS_VTOTAL_B 0xe100c
3786 #define _TRANS_VBLANK_B 0xe1010
3787 #define _TRANS_VSYNC_B 0xe1014
3788 #define _TRANS_VSYNCSHIFT_B 0xe1028
3789
3790 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3791 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3792 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3793 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3794 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3795 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3796 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3797 _TRANS_VSYNCSHIFT_B)
3798
3799 #define _TRANSB_DATA_M1 0xe1030
3800 #define _TRANSB_DATA_N1 0xe1034
3801 #define _TRANSB_DATA_M2 0xe1038
3802 #define _TRANSB_DATA_N2 0xe103c
3803 #define _TRANSB_DP_LINK_M1 0xe1040
3804 #define _TRANSB_DP_LINK_N1 0xe1044
3805 #define _TRANSB_DP_LINK_M2 0xe1048
3806 #define _TRANSB_DP_LINK_N2 0xe104c
3807
3808 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3809 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3810 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3811 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3812 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3813 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3814 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3815 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3816
3817 #define _TRANSACONF 0xf0008
3818 #define _TRANSBCONF 0xf1008
3819 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3820 #define TRANS_DISABLE (0<<31)
3821 #define TRANS_ENABLE (1<<31)
3822 #define TRANS_STATE_MASK (1<<30)
3823 #define TRANS_STATE_DISABLE (0<<30)
3824 #define TRANS_STATE_ENABLE (1<<30)
3825 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3826 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3827 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3828 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3829 #define TRANS_DP_AUDIO_ONLY (1<<26)
3830 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3831 #define TRANS_INTERLACE_MASK (7<<21)
3832 #define TRANS_PROGRESSIVE (0<<21)
3833 #define TRANS_INTERLACED (3<<21)
3834 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
3835 #define TRANS_8BPC (0<<5)
3836 #define TRANS_10BPC (1<<5)
3837 #define TRANS_6BPC (2<<5)
3838 #define TRANS_12BPC (3<<5)
3839
3840 #define _TRANSA_CHICKEN1 0xf0060
3841 #define _TRANSB_CHICKEN1 0xf1060
3842 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3843 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
3844 #define _TRANSA_CHICKEN2 0xf0064
3845 #define _TRANSB_CHICKEN2 0xf1064
3846 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3847 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
3848
3849
3850 #define SOUTH_CHICKEN1 0xc2000
3851 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
3852 #define FDIA_PHASE_SYNC_SHIFT_EN 18
3853 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3854 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3855 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
3856 #define SOUTH_CHICKEN2 0xc2004
3857 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
3858
3859 #define _FDI_RXA_CHICKEN 0xc200c
3860 #define _FDI_RXB_CHICKEN 0xc2010
3861 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3862 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3863 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3864
3865 #define SOUTH_DSPCLK_GATE_D 0xc2020
3866 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3867
3868 /* CPU: FDI_TX */
3869 #define _FDI_TXA_CTL 0x60100
3870 #define _FDI_TXB_CTL 0x61100
3871 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3872 #define FDI_TX_DISABLE (0<<31)
3873 #define FDI_TX_ENABLE (1<<31)
3874 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3875 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3876 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3877 #define FDI_LINK_TRAIN_NONE (3<<28)
3878 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3879 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3880 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3881 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3882 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3883 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3884 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3885 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3886 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3887 SNB has different settings. */
3888 /* SNB A-stepping */
3889 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3890 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3891 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3892 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3893 /* SNB B-stepping */
3894 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3895 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3896 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3897 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3898 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3899 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3900 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3901 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3902 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3903 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3904 /* Ironlake: hardwired to 1 */
3905 #define FDI_TX_PLL_ENABLE (1<<14)
3906
3907 /* Ivybridge has different bits for lolz */
3908 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3909 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3910 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3911 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3912
3913 /* both Tx and Rx */
3914 #define FDI_COMPOSITE_SYNC (1<<11)
3915 #define FDI_LINK_TRAIN_AUTO (1<<10)
3916 #define FDI_SCRAMBLING_ENABLE (0<<7)
3917 #define FDI_SCRAMBLING_DISABLE (1<<7)
3918
3919 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3920 #define _FDI_RXA_CTL 0xf000c
3921 #define _FDI_RXB_CTL 0xf100c
3922 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3923 #define FDI_RX_ENABLE (1<<31)
3924 /* train, dp width same as FDI_TX */
3925 #define FDI_FS_ERRC_ENABLE (1<<27)
3926 #define FDI_FE_ERRC_ENABLE (1<<26)
3927 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3928 #define FDI_8BPC (0<<16)
3929 #define FDI_10BPC (1<<16)
3930 #define FDI_6BPC (2<<16)
3931 #define FDI_12BPC (3<<16)
3932 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3933 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3934 #define FDI_RX_PLL_ENABLE (1<<13)
3935 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3936 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3937 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3938 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3939 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3940 #define FDI_PCDCLK (1<<4)
3941 /* CPT */
3942 #define FDI_AUTO_TRAINING (1<<10)
3943 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3944 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3945 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3946 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3947 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3948 /* LPT */
3949 #define FDI_PORT_WIDTH_2X_LPT (1<<19)
3950 #define FDI_PORT_WIDTH_1X_LPT (0<<19)
3951
3952 #define _FDI_RXA_MISC 0xf0010
3953 #define _FDI_RXB_MISC 0xf1010
3954 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
3955 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
3956 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
3957 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
3958 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
3959 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
3960 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
3961 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3962
3963 #define _FDI_RXA_TUSIZE1 0xf0030
3964 #define _FDI_RXA_TUSIZE2 0xf0038
3965 #define _FDI_RXB_TUSIZE1 0xf1030
3966 #define _FDI_RXB_TUSIZE2 0xf1038
3967 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3968 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3969
3970 /* FDI_RX interrupt register format */
3971 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3972 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3973 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3974 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3975 #define FDI_RX_FS_CODE_ERR (1<<6)
3976 #define FDI_RX_FE_CODE_ERR (1<<5)
3977 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3978 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3979 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3980 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3981 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3982
3983 #define _FDI_RXA_IIR 0xf0014
3984 #define _FDI_RXA_IMR 0xf0018
3985 #define _FDI_RXB_IIR 0xf1014
3986 #define _FDI_RXB_IMR 0xf1018
3987 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3988 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3989
3990 #define FDI_PLL_CTL_1 0xfe000
3991 #define FDI_PLL_CTL_2 0xfe004
3992
3993 /* or SDVOB */
3994 #define HDMIB 0xe1140
3995 #define PORT_ENABLE (1 << 31)
3996 #define TRANSCODER(pipe) ((pipe) << 30)
3997 #define TRANSCODER_CPT(pipe) ((pipe) << 29)
3998 #define TRANSCODER_MASK (1 << 30)
3999 #define TRANSCODER_MASK_CPT (3 << 29)
4000 #define COLOR_FORMAT_8bpc (0)
4001 #define COLOR_FORMAT_12bpc (3 << 26)
4002 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
4003 #define SDVO_ENCODING (0)
4004 #define TMDS_ENCODING (2 << 10)
4005 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
4006 /* CPT */
4007 #define HDMI_MODE_SELECT (1 << 9)
4008 #define DVI_MODE_SELECT (0)
4009 #define SDVOB_BORDER_ENABLE (1 << 7)
4010 #define AUDIO_ENABLE (1 << 6)
4011 #define VSYNC_ACTIVE_HIGH (1 << 4)
4012 #define HSYNC_ACTIVE_HIGH (1 << 3)
4013 #define PORT_DETECTED (1 << 2)
4014
4015 /* PCH SDVOB multiplex with HDMIB */
4016 #define PCH_SDVOB HDMIB
4017
4018 #define HDMIC 0xe1150
4019 #define HDMID 0xe1160
4020
4021 #define PCH_LVDS 0xe1180
4022 #define LVDS_DETECTED (1 << 1)
4023
4024 /* vlv has 2 sets of panel control regs. */
4025 #define PIPEA_PP_STATUS 0x61200
4026 #define PIPEA_PP_CONTROL 0x61204
4027 #define PIPEA_PP_ON_DELAYS 0x61208
4028 #define PIPEA_PP_OFF_DELAYS 0x6120c
4029 #define PIPEA_PP_DIVISOR 0x61210
4030
4031 #define PIPEB_PP_STATUS 0x61300
4032 #define PIPEB_PP_CONTROL 0x61304
4033 #define PIPEB_PP_ON_DELAYS 0x61308
4034 #define PIPEB_PP_OFF_DELAYS 0x6130c
4035 #define PIPEB_PP_DIVISOR 0x61310
4036
4037 #define PCH_PP_STATUS 0xc7200
4038 #define PCH_PP_CONTROL 0xc7204
4039 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4040 #define PANEL_UNLOCK_MASK (0xffff << 16)
4041 #define EDP_FORCE_VDD (1 << 3)
4042 #define EDP_BLC_ENABLE (1 << 2)
4043 #define PANEL_POWER_RESET (1 << 1)
4044 #define PANEL_POWER_OFF (0 << 0)
4045 #define PANEL_POWER_ON (1 << 0)
4046 #define PCH_PP_ON_DELAYS 0xc7208
4047 #define PANEL_PORT_SELECT_MASK (3 << 30)
4048 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4049 #define PANEL_PORT_SELECT_DPA (1 << 30)
4050 #define EDP_PANEL (1 << 30)
4051 #define PANEL_PORT_SELECT_DPC (2 << 30)
4052 #define PANEL_PORT_SELECT_DPD (3 << 30)
4053 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4054 #define PANEL_POWER_UP_DELAY_SHIFT 16
4055 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4056 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4057
4058 #define PCH_PP_OFF_DELAYS 0xc720c
4059 #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
4060 #define PANEL_POWER_PORT_LVDS (0 << 30)
4061 #define PANEL_POWER_PORT_DP_A (1 << 30)
4062 #define PANEL_POWER_PORT_DP_C (2 << 30)
4063 #define PANEL_POWER_PORT_DP_D (3 << 30)
4064 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4065 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4066 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4067 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4068
4069 #define PCH_PP_DIVISOR 0xc7210
4070 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4071 #define PP_REFERENCE_DIVIDER_SHIFT 8
4072 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4073 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4074
4075 #define PCH_DP_B 0xe4100
4076 #define PCH_DPB_AUX_CH_CTL 0xe4110
4077 #define PCH_DPB_AUX_CH_DATA1 0xe4114
4078 #define PCH_DPB_AUX_CH_DATA2 0xe4118
4079 #define PCH_DPB_AUX_CH_DATA3 0xe411c
4080 #define PCH_DPB_AUX_CH_DATA4 0xe4120
4081 #define PCH_DPB_AUX_CH_DATA5 0xe4124
4082
4083 #define PCH_DP_C 0xe4200
4084 #define PCH_DPC_AUX_CH_CTL 0xe4210
4085 #define PCH_DPC_AUX_CH_DATA1 0xe4214
4086 #define PCH_DPC_AUX_CH_DATA2 0xe4218
4087 #define PCH_DPC_AUX_CH_DATA3 0xe421c
4088 #define PCH_DPC_AUX_CH_DATA4 0xe4220
4089 #define PCH_DPC_AUX_CH_DATA5 0xe4224
4090
4091 #define PCH_DP_D 0xe4300
4092 #define PCH_DPD_AUX_CH_CTL 0xe4310
4093 #define PCH_DPD_AUX_CH_DATA1 0xe4314
4094 #define PCH_DPD_AUX_CH_DATA2 0xe4318
4095 #define PCH_DPD_AUX_CH_DATA3 0xe431c
4096 #define PCH_DPD_AUX_CH_DATA4 0xe4320
4097 #define PCH_DPD_AUX_CH_DATA5 0xe4324
4098
4099 /* CPT */
4100 #define PORT_TRANS_A_SEL_CPT 0
4101 #define PORT_TRANS_B_SEL_CPT (1<<29)
4102 #define PORT_TRANS_C_SEL_CPT (2<<29)
4103 #define PORT_TRANS_SEL_MASK (3<<29)
4104 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4105 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4106 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4107
4108 #define TRANS_DP_CTL_A 0xe0300
4109 #define TRANS_DP_CTL_B 0xe1300
4110 #define TRANS_DP_CTL_C 0xe2300
4111 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4112 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
4113 #define TRANS_DP_PORT_SEL_B (0<<29)
4114 #define TRANS_DP_PORT_SEL_C (1<<29)
4115 #define TRANS_DP_PORT_SEL_D (2<<29)
4116 #define TRANS_DP_PORT_SEL_NONE (3<<29)
4117 #define TRANS_DP_PORT_SEL_MASK (3<<29)
4118 #define TRANS_DP_AUDIO_ONLY (1<<26)
4119 #define TRANS_DP_ENH_FRAMING (1<<18)
4120 #define TRANS_DP_8BPC (0<<9)
4121 #define TRANS_DP_10BPC (1<<9)
4122 #define TRANS_DP_6BPC (2<<9)
4123 #define TRANS_DP_12BPC (3<<9)
4124 #define TRANS_DP_BPC_MASK (3<<9)
4125 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4126 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
4127 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4128 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
4129 #define TRANS_DP_SYNC_MASK (3<<3)
4130
4131 /* SNB eDP training params */
4132 /* SNB A-stepping */
4133 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4134 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4135 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4136 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4137 /* SNB B-stepping */
4138 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4139 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4140 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4141 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4142 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4143 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4144
4145 /* IVB */
4146 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4147 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4148 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4149 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4150 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4151 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4152 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
4153
4154 /* legacy values */
4155 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4156 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4157 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4158 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4159 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4160
4161 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4162
4163 #define FORCEWAKE 0xA18C
4164 #define FORCEWAKE_VLV 0x1300b0
4165 #define FORCEWAKE_ACK_VLV 0x1300b4
4166 #define FORCEWAKE_ACK_HSW 0x130044
4167 #define FORCEWAKE_ACK 0x130090
4168 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
4169 #define FORCEWAKE_KERNEL 0x1
4170 #define FORCEWAKE_USER 0x2
4171 #define FORCEWAKE_MT_ACK 0x130040
4172 #define ECOBUS 0xa180
4173 #define FORCEWAKE_MT_ENABLE (1<<5)
4174
4175 #define GTFIFODBG 0x120000
4176 #define GT_FIFO_CPU_ERROR_MASK 7
4177 #define GT_FIFO_OVFERR (1<<2)
4178 #define GT_FIFO_IAWRERR (1<<1)
4179 #define GT_FIFO_IARDERR (1<<0)
4180
4181 #define GT_FIFO_FREE_ENTRIES 0x120008
4182 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
4183
4184 #define GEN6_UCGCTL1 0x9400
4185 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4186 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4187
4188 #define GEN6_UCGCTL2 0x9404
4189 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4190 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4191 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4192 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4193 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4194
4195 #define GEN7_UCGCTL4 0x940c
4196 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4197
4198 #define GEN6_RPNSWREQ 0xA008
4199 #define GEN6_TURBO_DISABLE (1<<31)
4200 #define GEN6_FREQUENCY(x) ((x)<<25)
4201 #define GEN6_OFFSET(x) ((x)<<19)
4202 #define GEN6_AGGRESSIVE_TURBO (0<<15)
4203 #define GEN6_RC_VIDEO_FREQ 0xA00C
4204 #define GEN6_RC_CONTROL 0xA090
4205 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4206 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4207 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4208 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4209 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4210 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4211 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
4212 #define GEN6_RP_DOWN_TIMEOUT 0xA010
4213 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
4214 #define GEN6_RPSTAT1 0xA01C
4215 #define GEN6_CAGF_SHIFT 8
4216 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4217 #define GEN6_RP_CONTROL 0xA024
4218 #define GEN6_RP_MEDIA_TURBO (1<<11)
4219 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4220 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4221 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4222 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
4223 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
4224 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
4225 #define GEN6_RP_ENABLE (1<<7)
4226 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4227 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4228 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4229 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)
4230 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4231 #define GEN6_RP_UP_THRESHOLD 0xA02C
4232 #define GEN6_RP_DOWN_THRESHOLD 0xA030
4233 #define GEN6_RP_CUR_UP_EI 0xA050
4234 #define GEN6_CURICONT_MASK 0xffffff
4235 #define GEN6_RP_CUR_UP 0xA054
4236 #define GEN6_CURBSYTAVG_MASK 0xffffff
4237 #define GEN6_RP_PREV_UP 0xA058
4238 #define GEN6_RP_CUR_DOWN_EI 0xA05C
4239 #define GEN6_CURIAVG_MASK 0xffffff
4240 #define GEN6_RP_CUR_DOWN 0xA060
4241 #define GEN6_RP_PREV_DOWN 0xA064
4242 #define GEN6_RP_UP_EI 0xA068
4243 #define GEN6_RP_DOWN_EI 0xA06C
4244 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
4245 #define GEN6_RC_STATE 0xA094
4246 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4247 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4248 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4249 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4250 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4251 #define GEN6_RC_SLEEP 0xA0B0
4252 #define GEN6_RC1e_THRESHOLD 0xA0B4
4253 #define GEN6_RC6_THRESHOLD 0xA0B8
4254 #define GEN6_RC6p_THRESHOLD 0xA0BC
4255 #define GEN6_RC6pp_THRESHOLD 0xA0C0
4256 #define GEN6_PMINTRMSK 0xA168
4257
4258 #define GEN6_PMISR 0x44020
4259 #define GEN6_PMIMR 0x44024 /* rps_lock */
4260 #define GEN6_PMIIR 0x44028
4261 #define GEN6_PMIER 0x4402C
4262 #define GEN6_PM_MBOX_EVENT (1<<25)
4263 #define GEN6_PM_THERMAL_EVENT (1<<24)
4264 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4265 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4266 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4267 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4268 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4269 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4270 GEN6_PM_RP_DOWN_THRESHOLD | \
4271 GEN6_PM_RP_DOWN_TIMEOUT)
4272
4273 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
4274 #define GEN6_GT_GFX_RC6 0x138108
4275 #define GEN6_GT_GFX_RC6p 0x13810C
4276 #define GEN6_GT_GFX_RC6pp 0x138110
4277
4278 #define GEN6_PCODE_MAILBOX 0x138124
4279 #define GEN6_PCODE_READY (1<<31)
4280 #define GEN6_READ_OC_PARAMS 0xc
4281 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4282 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
4283 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
4284 #define GEN6_PCODE_READ_RC6VIDS 0x5
4285 #define GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0
4286 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0)
4287 #define GEN6_PCODE_DATA 0x138128
4288 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4289
4290 #define GEN6_GT_CORE_STATUS 0x138060
4291 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
4292 #define GEN6_RCn_MASK 7
4293 #define GEN6_RC0 0
4294 #define GEN6_RC3 2
4295 #define GEN6_RC6 3
4296 #define GEN6_RC7 4
4297
4298 #define GEN7_MISCCPCTL (0x9424)
4299 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4300
4301 /* IVYBRIDGE DPF */
4302 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
4303 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4304 #define GEN7_PARITY_ERROR_VALID (1<<13)
4305 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4306 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4307 #define GEN7_PARITY_ERROR_ROW(reg) \
4308 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4309 #define GEN7_PARITY_ERROR_BANK(reg) \
4310 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4311 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4312 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4313 #define GEN7_L3CDERRST1_ENABLE (1<<7)
4314
4315 #define GEN7_L3LOG_BASE 0xB070
4316 #define GEN7_L3LOG_SIZE 0x80
4317
4318 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
4319 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
4320 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
4321 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
4322
4323 #define GEN7_ROW_CHICKEN2 0xe4f4
4324 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4325 #define DOP_CLOCK_GATING_DISABLE (1<<0)
4326
4327 #define G4X_AUD_VID_DID 0x62020
4328 #define INTEL_AUDIO_DEVCL 0x808629FB
4329 #define INTEL_AUDIO_DEVBLC 0x80862801
4330 #define INTEL_AUDIO_DEVCTG 0x80862802
4331
4332 #define G4X_AUD_CNTL_ST 0x620B4
4333 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
4334 #define G4X_ELDV_DEVCTG (1 << 14)
4335 #define G4X_ELD_ADDR (0xf << 5)
4336 #define G4X_ELD_ACK (1 << 4)
4337 #define G4X_HDMIW_HDMIEDID 0x6210C
4338
4339 #define IBX_HDMIW_HDMIEDID_A 0xE2050
4340 #define IBX_HDMIW_HDMIEDID_B 0xE2150
4341 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4342 IBX_HDMIW_HDMIEDID_A, \
4343 IBX_HDMIW_HDMIEDID_B)
4344 #define IBX_AUD_CNTL_ST_A 0xE20B4
4345 #define IBX_AUD_CNTL_ST_B 0xE21B4
4346 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4347 IBX_AUD_CNTL_ST_A, \
4348 IBX_AUD_CNTL_ST_B)
4349 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
4350 #define IBX_ELD_ADDRESS (0x1f << 5)
4351 #define IBX_ELD_ACK (1 << 4)
4352 #define IBX_AUD_CNTL_ST2 0xE20C0
4353 #define IBX_ELD_VALIDB (1 << 0)
4354 #define IBX_CP_READYB (1 << 1)
4355
4356 #define CPT_HDMIW_HDMIEDID_A 0xE5050
4357 #define CPT_HDMIW_HDMIEDID_B 0xE5150
4358 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4359 CPT_HDMIW_HDMIEDID_A, \
4360 CPT_HDMIW_HDMIEDID_B)
4361 #define CPT_AUD_CNTL_ST_A 0xE50B4
4362 #define CPT_AUD_CNTL_ST_B 0xE51B4
4363 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4364 CPT_AUD_CNTL_ST_A, \
4365 CPT_AUD_CNTL_ST_B)
4366 #define CPT_AUD_CNTRL_ST2 0xE50C0
4367
4368 /* These are the 4 32-bit write offset registers for each stream
4369 * output buffer. It determines the offset from the
4370 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4371 */
4372 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
4373
4374 #define IBX_AUD_CONFIG_A 0xe2000
4375 #define IBX_AUD_CONFIG_B 0xe2100
4376 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4377 IBX_AUD_CONFIG_A, \
4378 IBX_AUD_CONFIG_B)
4379 #define CPT_AUD_CONFIG_A 0xe5000
4380 #define CPT_AUD_CONFIG_B 0xe5100
4381 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4382 CPT_AUD_CONFIG_A, \
4383 CPT_AUD_CONFIG_B)
4384 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
4385 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
4386 #define AUD_CONFIG_UPPER_N_SHIFT 20
4387 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
4388 #define AUD_CONFIG_LOWER_N_SHIFT 4
4389 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
4390 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
4391 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
4392 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
4393
4394 /* HSW Audio */
4395 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
4396 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
4397 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
4398 HSW_AUD_CONFIG_A, \
4399 HSW_AUD_CONFIG_B)
4400
4401 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
4402 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
4403 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4404 HSW_AUD_MISC_CTRL_A, \
4405 HSW_AUD_MISC_CTRL_B)
4406
4407 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4408 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4409 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4410 HSW_AUD_DIP_ELD_CTRL_ST_A, \
4411 HSW_AUD_DIP_ELD_CTRL_ST_B)
4412
4413 /* Audio Digital Converter */
4414 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
4415 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
4416 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4417 HSW_AUD_DIG_CNVT_1, \
4418 HSW_AUD_DIG_CNVT_2)
4419 #define DIP_PORT_SEL_MASK 0x3
4420
4421 #define HSW_AUD_EDID_DATA_A 0x65050
4422 #define HSW_AUD_EDID_DATA_B 0x65150
4423 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4424 HSW_AUD_EDID_DATA_A, \
4425 HSW_AUD_EDID_DATA_B)
4426
4427 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
4428 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
4429 #define AUDIO_INACTIVE_C (1<<11)
4430 #define AUDIO_INACTIVE_B (1<<7)
4431 #define AUDIO_INACTIVE_A (1<<3)
4432 #define AUDIO_OUTPUT_ENABLE_A (1<<2)
4433 #define AUDIO_OUTPUT_ENABLE_B (1<<6)
4434 #define AUDIO_OUTPUT_ENABLE_C (1<<10)
4435 #define AUDIO_ELD_VALID_A (1<<0)
4436 #define AUDIO_ELD_VALID_B (1<<4)
4437 #define AUDIO_ELD_VALID_C (1<<8)
4438 #define AUDIO_CP_READY_A (1<<1)
4439 #define AUDIO_CP_READY_B (1<<5)
4440 #define AUDIO_CP_READY_C (1<<9)
4441
4442 /* HSW Power Wells */
4443 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
4444 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
4445 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
4446 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
4447 #define HSW_PWR_WELL_ENABLE (1<<31)
4448 #define HSW_PWR_WELL_STATE (1<<30)
4449 #define HSW_PWR_WELL_CTL5 0x45410
4450 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
4451 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
4452 #define HSW_PWR_WELL_FORCE_ON (1<<19)
4453 #define HSW_PWR_WELL_CTL6 0x45414
4454
4455 /* Per-pipe DDI Function Control */
4456 #define TRANS_DDI_FUNC_CTL_A 0x60400
4457 #define TRANS_DDI_FUNC_CTL_B 0x61400
4458 #define TRANS_DDI_FUNC_CTL_C 0x62400
4459 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
4460 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4461 TRANS_DDI_FUNC_CTL_B)
4462 #define TRANS_DDI_FUNC_ENABLE (1<<31)
4463 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4464 #define TRANS_DDI_PORT_MASK (7<<28)
4465 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
4466 #define TRANS_DDI_PORT_NONE (0<<28)
4467 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
4468 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
4469 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
4470 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
4471 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
4472 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
4473 #define TRANS_DDI_BPC_MASK (7<<20)
4474 #define TRANS_DDI_BPC_8 (0<<20)
4475 #define TRANS_DDI_BPC_10 (1<<20)
4476 #define TRANS_DDI_BPC_6 (2<<20)
4477 #define TRANS_DDI_BPC_12 (3<<20)
4478 #define TRANS_DDI_PVSYNC (1<<17)
4479 #define TRANS_DDI_PHSYNC (1<<16)
4480 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
4481 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
4482 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
4483 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
4484 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
4485 #define TRANS_DDI_BFI_ENABLE (1<<4)
4486 #define TRANS_DDI_PORT_WIDTH_X1 (0<<1)
4487 #define TRANS_DDI_PORT_WIDTH_X2 (1<<1)
4488 #define TRANS_DDI_PORT_WIDTH_X4 (3<<1)
4489
4490 /* DisplayPort Transport Control */
4491 #define DP_TP_CTL_A 0x64040
4492 #define DP_TP_CTL_B 0x64140
4493 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4494 #define DP_TP_CTL_ENABLE (1<<31)
4495 #define DP_TP_CTL_MODE_SST (0<<27)
4496 #define DP_TP_CTL_MODE_MST (1<<27)
4497 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
4498 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
4499 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
4500 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
4501 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
4502 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
4503 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
4504 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
4505 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
4506
4507 /* DisplayPort Transport Status */
4508 #define DP_TP_STATUS_A 0x64044
4509 #define DP_TP_STATUS_B 0x64144
4510 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4511 #define DP_TP_STATUS_IDLE_DONE (1<<25)
4512 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
4513
4514 /* DDI Buffer Control */
4515 #define DDI_BUF_CTL_A 0x64000
4516 #define DDI_BUF_CTL_B 0x64100
4517 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4518 #define DDI_BUF_CTL_ENABLE (1<<31)
4519 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
4520 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
4521 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
4522 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
4523 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
4524 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
4525 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
4526 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
4527 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
4528 #define DDI_BUF_EMP_MASK (0xf<<24)
4529 #define DDI_BUF_IS_IDLE (1<<7)
4530 #define DDI_PORT_WIDTH_X1 (0<<1)
4531 #define DDI_PORT_WIDTH_X2 (1<<1)
4532 #define DDI_PORT_WIDTH_X4 (3<<1)
4533 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
4534
4535 /* DDI Buffer Translations */
4536 #define DDI_BUF_TRANS_A 0x64E00
4537 #define DDI_BUF_TRANS_B 0x64E60
4538 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4539
4540 /* Sideband Interface (SBI) is programmed indirectly, via
4541 * SBI_ADDR, which contains the register offset; and SBI_DATA,
4542 * which contains the payload */
4543 #define SBI_ADDR 0xC6000
4544 #define SBI_DATA 0xC6004
4545 #define SBI_CTL_STAT 0xC6008
4546 #define SBI_CTL_OP_CRRD (0x6<<8)
4547 #define SBI_CTL_OP_CRWR (0x7<<8)
4548 #define SBI_RESPONSE_FAIL (0x1<<1)
4549 #define SBI_RESPONSE_SUCCESS (0x0<<1)
4550 #define SBI_BUSY (0x1<<0)
4551 #define SBI_READY (0x0<<0)
4552
4553 /* SBI offsets */
4554 #define SBI_SSCDIVINTPHASE6 0x0600
4555 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
4556 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
4557 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
4558 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
4559 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
4560 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
4561 #define SBI_SSCCTL 0x020c
4562 #define SBI_SSCCTL6 0x060C
4563 #define SBI_SSCCTL_DISABLE (1<<0)
4564 #define SBI_SSCAUXDIV6 0x0610
4565 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
4566 #define SBI_DBUFF0 0x2a00
4567
4568 /* LPT PIXCLK_GATE */
4569 #define PIXCLK_GATE 0xC6020
4570 #define PIXCLK_GATE_UNGATE (1<<0)
4571 #define PIXCLK_GATE_GATE (0<<0)
4572
4573 /* SPLL */
4574 #define SPLL_CTL 0x46020
4575 #define SPLL_PLL_ENABLE (1<<31)
4576 #define SPLL_PLL_SSC (1<<28)
4577 #define SPLL_PLL_NON_SSC (2<<28)
4578 #define SPLL_PLL_FREQ_810MHz (0<<26)
4579 #define SPLL_PLL_FREQ_1350MHz (1<<26)
4580
4581 /* WRPLL */
4582 #define WRPLL_CTL1 0x46040
4583 #define WRPLL_CTL2 0x46060
4584 #define WRPLL_PLL_ENABLE (1<<31)
4585 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
4586 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
4587 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
4588 /* WRPLL divider programming */
4589 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
4590 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
4591 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
4592
4593 /* Port clock selection */
4594 #define PORT_CLK_SEL_A 0x46100
4595 #define PORT_CLK_SEL_B 0x46104
4596 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4597 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
4598 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
4599 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
4600 #define PORT_CLK_SEL_SPLL (3<<29)
4601 #define PORT_CLK_SEL_WRPLL1 (4<<29)
4602 #define PORT_CLK_SEL_WRPLL2 (5<<29)
4603 #define PORT_CLK_SEL_NONE (7<<29)
4604
4605 /* Transcoder clock selection */
4606 #define TRANS_CLK_SEL_A 0x46140
4607 #define TRANS_CLK_SEL_B 0x46144
4608 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4609 /* For each transcoder, we need to select the corresponding port clock */
4610 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
4611 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
4612
4613 #define _TRANSA_MSA_MISC 0x60410
4614 #define _TRANSB_MSA_MISC 0x61410
4615 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
4616 _TRANSB_MSA_MISC)
4617 #define TRANS_MSA_SYNC_CLK (1<<0)
4618 #define TRANS_MSA_6_BPC (0<<5)
4619 #define TRANS_MSA_8_BPC (1<<5)
4620 #define TRANS_MSA_10_BPC (2<<5)
4621 #define TRANS_MSA_12_BPC (3<<5)
4622 #define TRANS_MSA_16_BPC (4<<5)
4623
4624 /* LCPLL Control */
4625 #define LCPLL_CTL 0x130040
4626 #define LCPLL_PLL_DISABLE (1<<31)
4627 #define LCPLL_PLL_LOCK (1<<30)
4628 #define LCPLL_CLK_FREQ_MASK (3<<26)
4629 #define LCPLL_CLK_FREQ_450 (0<<26)
4630 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
4631 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
4632 #define LCPLL_CD_SOURCE_FCLK (1<<21)
4633
4634 /* Pipe WM_LINETIME - watermark line time */
4635 #define PIPE_WM_LINETIME_A 0x45270
4636 #define PIPE_WM_LINETIME_B 0x45274
4637 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
4638 PIPE_WM_LINETIME_B)
4639 #define PIPE_WM_LINETIME_MASK (0x1ff)
4640 #define PIPE_WM_LINETIME_TIME(x) ((x))
4641 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
4642 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
4643
4644 /* SFUSE_STRAP */
4645 #define SFUSE_STRAP 0xc2014
4646 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
4647 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
4648 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
4649
4650 #define WM_DBG 0x45280
4651 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
4652 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
4653 #define WM_DBG_DISALLOW_SPRITE (1<<2)
4654
4655 #endif /* _I915_REG_H_ */